1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-pm.h>
3 #include <dt-bindings/pinctrl/rockchip.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/sensor-dev.h>
6 #include <dt-bindings/clock/rk_system_status.h>
8 #include "rk3368-clocks.dtsi"
11 compatible = "rockchip,rk3368";
13 rockchip,sram = <&sram>;
14 interrupt-parent = <&gic>;
41 entry-method = "arm,psci";
42 CPU_SLEEP_0: cpu-sleep-0 {
43 compatible = "arm,idle-state";
44 arm,psci-suspend-param = <0x1010000>;
45 entry-latency-us = <0x3fffffff>;
46 exit-latency-us = <0x40000000>;
47 min-residency-us = <0xffffffff>;
53 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
56 cpu-idle-states = <&CPU_SLEEP_0>;
60 compatible = "arm,cortex-a53", "arm,armv8";
62 enable-method = "psci";
63 cpu-idle-states = <&CPU_SLEEP_0>;
67 compatible = "arm,cortex-a53", "arm,armv8";
69 enable-method = "psci";
70 cpu-idle-states = <&CPU_SLEEP_0>;
74 compatible = "arm,cortex-a53", "arm,armv8";
76 enable-method = "psci";
77 cpu-idle-states = <&CPU_SLEEP_0>;
81 compatible = "arm,cortex-a53", "arm,armv8";
83 enable-method = "psci";
84 cpu-idle-states = <&CPU_SLEEP_0>;
88 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
91 cpu-idle-states = <&CPU_SLEEP_0>;
95 compatible = "arm,cortex-a53", "arm,armv8";
97 enable-method = "psci";
98 cpu-idle-states = <&CPU_SLEEP_0>;
102 compatible = "arm,cortex-a53", "arm,armv8";
104 enable-method = "psci";
105 cpu-idle-states = <&CPU_SLEEP_0>;
141 compatible = "arm,psci-0.2";
145 gic: interrupt-controller@ffb70000 {
146 compatible = "arm,cortex-a15-gic";
147 #interrupt-cells = <3>;
148 #address-cells = <0>;
149 interrupt-controller;
150 reg = <0x0 0xffb71000 0 0x1000>,
151 <0x0 0xffb72000 0 0x1000>;
154 pmu: syscon@ff730000 {
155 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
156 reg = <0x0 0xff730000 0x0 0x1000>;
159 pmugrf: syscon@ff738000 {
160 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
161 reg = <0x0 0xff738000 0x0 0x1000>;
164 sgrf: syscon@ff740000 {
165 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
166 reg = <0x0 0xff740000 0x0 0x1000>;
170 cru: syscon@ff760000 {
171 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
172 reg = <0x0 0xff760000 0x0 0x1000>;
175 grf: syscon@ff770000 {
176 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
177 reg = <0x0 0xff770000 0x0 0x1000>;
181 compatible = "arm,armv8-pmuv3";
182 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
192 cpu_axi_bus: cpu_axi_bus {
193 compatible = "rockchip,cpu_axi_bus";
194 #address-cells = <2>;
199 #address-cells = <2>;
204 reg = <0x0 0xffa80000 0x0 0x20>;
207 reg = <0x0 0xffa80080 0x0 0x20>;
210 reg = <0x0 0xffa80280 0x0 0x20>;
213 reg = <0x0 0xffa90000 0x0 0x20>;
216 reg = <0x0 0xffaa0000 0x0 0x20>;
219 reg = <0x0 0xffaa0080 0x0 0x20>;
222 reg = <0x0 0xffab0000 0x0 0x20>;
223 rockchip,priority = <2 2>;
226 reg = <0x0 0xffad0000 0x0 0x20>;
229 reg = <0x0 0xffad0080 0x0 0x20>;
232 reg = <0x0 0xffad0100 0x0 0x20>;
235 reg = <0x0 0xffad0180 0x0 0x20>;
236 rockchip,priority = <2 2>;
239 reg = <0x0 0xffad0200 0x0 0x20>;
240 rockchip,priority = <2 2>;
243 reg = <0x0 0xffad0280 0x0 0x20>;
246 reg = <0x0 0xffad0300 0x0 0x20>;
247 rockchip,priority = <2 2>;
250 reg = <0x0 0xffad0380 0x0 0x20>;
253 reg = <0x0 0xffad0400 0x0 0x20>;
256 reg = <0x0 0xffae0000 0x0 0x20>;
259 reg = <0x0 0xffae0100 0x0 0x20>;
262 reg = <0x0 0xffae0180 0x0 0x20>;
265 reg = <0x0 0xffaf0000 0x0 0x20>;
270 #address-cells = <2>;
275 reg = <0x0 0xffac0000 0x0 0x3c>;
276 rockchip,read-latency = <0x34>;
282 compatible = "arm,armv8-timer";
283 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
284 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
285 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
286 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
287 clock-frequency = <24000000>;
291 compatible = "rockchip,timer";
292 reg = <0x0 0xff810000 0x0 0x20>;
293 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
294 rockchip,broadcast = <1>;
297 sram: sram@ff8c0000 {
298 compatible = "mmio-sram";
299 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
303 watchdog: wdt@ff800000 {
304 compatible = "rockchip,watch dog";
305 reg = <0x0 0xff800000 0x0 0x100>;
306 clocks = <&pclk_alive_pre>;
307 clock-names = "pclk_wdt";
308 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
310 rockchip,timeout = <60>;
311 rockchip,atboot = <1>;
312 rockchip,debug = <0>;
317 #address-cells = <2>;
319 compatible = "arm,amba-bus";
320 interrupt-parent = <&gic>;
323 pdma0: pdma@ff600000 {
324 compatible = "arm,pl330", "arm,primecell";
325 reg = <0x0 0xff600000 0x0 0x4000>;
326 clocks = <&clk_gates12 11>;
327 clock-names = "apb_pclk";
328 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
334 pdma1: pdma@ff250000 {
335 compatible = "arm,pl330", "arm,primecell";
336 reg = <0x0 0xff250000 0x0 0x4000>;
337 clocks = <&clk_gates19 3>;
338 clock-names = "apb_pclk";
339 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
345 reset: reset@ff760300{
346 compatible = "rockchip,reset";
347 reg = <0x0 0xff760300 0x0 0x38>;
348 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
352 nandc0: nandc@ff400000 {
353 compatible = "rockchip,rk-nandc";
354 reg = <0x0 0xff400000 0x0 0x4000>;
355 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
358 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
361 nandc0reg: nandc0@ff400000 {
362 compatible = "rockchip,rk-nandc";
363 reg = <0x0 0xff400000 0x0 0x4000>;
366 emmc: rksdmmc@ff0f0000 {
367 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
368 reg = <0x0 0xff0f0000 0x0 0x4000>;
369 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
370 #address-cells = <1>;
372 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
373 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
374 rockchip,grf = <&grf>;
376 fifo-depth = <0x100>;
380 sdmmc: rksdmmc@ff0c0000 {
381 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
382 reg = <0x0 0xff0c0000 0x0 0x4000>;
383 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
384 #address-cells = <1>;
386 pinctrl-names = "default", "idle", "udbg";
387 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
388 pinctrl-1 = <&sdmmc_gpio>;
389 pinctrl-2 = <&uart2_xfer &cpu_jtag &sdmmc_dectn>;
390 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
391 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
392 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
393 rockchip,grf = <&grf>;
395 fifo-depth = <0x100>;
399 sdio: rksdmmc@ff0d0000 {
400 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
401 reg = <0x0 0xff0d0000 0x0 0x4000>;
402 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
403 #address-cells = <1>;
405 pinctrl-names = "default","idle";
406 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
407 pinctrl-1 = <&sdio0_gpio>;
408 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
409 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
410 rockchip,grf = <&grf>;
412 fifo-depth = <0x100>;
417 compatible = "rockchip,rockchip-spi";
418 reg = <0x0 0xff110000 0x0 0x1000>;
419 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
420 #address-cells = <1>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
424 rockchip,spi-src-clk = <0>;
426 clocks =<&clk_spi0>, <&clk_gates19 4>;
427 clock-names = "spi", "pclk_spi0";
428 //dmas = <&pdma1 11>, <&pdma1 12>;
430 //dma-names = "tx", "rx";
435 compatible = "rockchip,rockchip-spi";
436 reg = <0x0 0xff120000 0x0 0x1000>;
437 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
438 #address-cells = <1>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
442 rockchip,spi-src-clk = <1>;
444 clocks = <&clk_spi1>, <&clk_gates19 5>;
445 clock-names = "spi", "pclk_spi1";
446 //dmas = <&pdma1 13>, <&pdma1 14>;
448 //dma-names = "tx", "rx";
453 compatible = "rockchip,rockchip-spi";
454 reg = <0x0 0xff130000 0x0 0x1000>;
455 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
456 #address-cells = <1>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
460 rockchip,spi-src-clk = <2>;
462 clocks = <&clk_spi2>, <&clk_gates19 6>;
463 clock-names = "spi", "pclk_spi2";
464 //dmas = <&pdma1 15>, <&pdma1 16>;
466 //dma-names = "tx", "rx";
470 uart_bt: serial@ff180000 {
471 compatible = "rockchip,serial";
472 reg = <0x0 0xff180000 0x0 0x100>;
473 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
474 clock-frequency = <24000000>;
475 clocks = <&clk_uart0>, <&clk_gates19 7>;
476 clock-names = "sclk_uart", "pclk_uart";
479 //dmas = <&pdma1 1>, <&pdma1 2>;
481 pinctrl-names = "default";
482 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
486 uart_bb: serial@ff190000 {
487 compatible = "rockchip,serial";
488 reg = <0x0 0xff190000 0x0 0x100>;
489 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
490 clock-frequency = <24000000>;
491 clocks = <&clk_uart1>, <&clk_gates19 8>;
492 clock-names = "sclk_uart", "pclk_uart";
495 //dmas = <&pdma1 3>, <&pdma1 4>;
497 pinctrl-names = "default";
498 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
502 uart_dbg: serial@ff690000 {
503 compatible = "rockchip,serial";
504 reg = <0x0 0xff690000 0x0 0x100>;
505 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
506 clock-frequency = <24000000>;
507 clocks = <&clk_uart2>, <&clk_gates13 5>;
508 clock-names = "sclk_uart", "pclk_uart";
511 //dmas = <&pdma0 4>, <&pdma0 5>;
513 //pinctrl-names = "default";
514 //pinctrl-0 = <&uart2_xfer>;
518 uart_gps: serial@ff1b0000 {
519 compatible = "rockchip,serial";
520 reg = <0x0 0xff1b0000 0x0 0x100>;
521 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
522 clock-frequency = <24000000>;
523 clocks = <&clk_uart3>, <&clk_gates19 9>;
524 clock-names = "sclk_uart", "pclk_uart";
525 current-speed = <115200>;
528 //dmas = <&pdma1 7>, <&pdma1 8>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
535 uart_exp: serial@ff1c0000 {
536 compatible = "rockchip,serial";
537 reg = <0x0 0xff1c0000 0x0 0x100>;
538 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
539 clock-frequency = <24000000>;
540 clocks = <&clk_uart4>, <&clk_gates19 10>;
541 clock-names = "sclk_uart", "pclk_uart";
544 //dmas = <&pdma1 9>, <&pdma1 10>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
551 rockchip_clocks_init: clocks-init{
552 compatible = "rockchip,clocks-init";
553 rockchip,clocks-init-parent =
554 <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
555 <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
556 <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
557 <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
558 rockchip,clocks-init-rate =
559 <&clk_gpll 576000000>, <&clk_core_b 792000000>,
560 <&clk_core_l 600000000>, <&clk_cpll 400000000>,
561 /*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
562 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
563 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
564 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
565 <&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
566 <&clk_cs 300000000>, <&clkin_trace 300000000>,
567 <&aclk_cci 600000000>, <&clk_mac 125000000>,
568 <&aclk_vio0 400000000>, <&hclk_vio 100000000>,
569 <&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
570 <&clk_isp 400000000>, <&clk_edp 200000000>,
571 <&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
572 <&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
573 <&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
574 <&clk_hevc_cabac 300000000>;
576 rockchip,clocks-uboot-has-init =
581 rockchip_clocks_enable: clocks-enable {
582 compatible = "rockchip,clocks-enable";
605 <&clk_gates12 12>,/*aclk_strc_sys*/
606 <&clk_gates12 6>,/*aclk_intmem1*/
607 <&clk_gates12 5>,/*aclk_intmem0*/
608 <&clk_gates12 4>,/*aclk_intmem*/
609 <&clk_gates13 9>,/*aclk_gic400*/
610 <&clk_gates12 9>,/*hclk_rom*/
613 <&clk_gates22 13>,/*pclk_timer1*/
614 <&clk_gates22 12>,/*pclk_timer0*/
615 <&clk_gates22 9>,/*pclk_alive_niu*/
616 <&clk_gates22 8>,/*pclk_grf*/
619 <&clk_gates23 5>,/*pclk_pmugrf*/
620 <&clk_gates23 3>,/*pclk_sgrf*/
621 <&clk_gates23 2>,/*pclk_pmu_noc*/
622 <&clk_gates23 1>,/*pclk_intmem1*/
623 <&clk_gates23 0>,/*pclk_pmu*/
626 <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
627 <&clk_gates20 8>,/*aclk_peri_niu*/
628 <&clk_gates21 4>,/*aclk_peri_mmu*/
629 <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
630 <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
631 <&clk_gates19 1>,/*pclk_peri_axi_matrix*/
635 <&clk_gates7 0>;/*clk_jtag*/
640 compatible = "rockchip,rk30-i2c";
641 reg = <0x0 0xff650000 0x0 0x1000>;
642 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
643 #address-cells = <1>;
645 pinctrl-names = "default", "gpio";
646 pinctrl-0 = <&i2c0_xfer>;
647 pinctrl-1 = <&i2c0_gpio>;
648 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
649 clocks = <&clk_gates12 2>;
650 rockchip,check-idle = <1>;
656 compatible = "rockchip,rk30-i2c";
657 reg = <0x0 0xff660000 0x0 0x1000>;
658 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
659 #address-cells = <1>;
661 pinctrl-names = "default", "gpio";
662 pinctrl-0 = <&i2c1_xfer>;
663 pinctrl-1 = <&i2c1_gpio>;
664 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
665 clocks = <&clk_gates12 3>;
666 rockchip,check-idle = <1>;
672 compatible = "rockchip,rk30-i2c";
673 reg = <0x0 0xff140000 0x0 0x1000>;
674 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
675 #address-cells = <1>;
677 pinctrl-names = "default", "gpio";
678 pinctrl-0 = <&i2c2_xfer>;
679 pinctrl-1 = <&i2c2_gpio>;
680 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
681 clocks = <&clk_gates19 11>;
682 rockchip,check-idle = <1>;
688 compatible = "rockchip,rk30-i2c";
689 reg = <0x0 0xff150000 0x0 0x1000>;
690 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
691 #address-cells = <1>;
693 pinctrl-names = "default", "gpio";
694 pinctrl-0 = <&i2c3_xfer>;
695 pinctrl-1 = <&i2c3_gpio>;
696 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
697 clocks = <&clk_gates19 12>;
698 rockchip,check-idle = <1>;
704 compatible = "rockchip,rk30-i2c";
705 reg = <0x0 0xff160000 0x0 0x1000>;
706 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
707 #address-cells = <1>;
709 pinctrl-names = "default", "gpio";
710 pinctrl-0 = <&i2c4_xfer>;
711 pinctrl-1 = <&i2c4_gpio>;
712 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
713 clocks = <&clk_gates19 13>;
714 rockchip,check-idle = <1>;
720 compatible = "rockchip,rk30-i2c";
721 reg = <0x0 0xff170000 0x0 0x1000>;
722 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
723 #address-cells = <1>;
725 pinctrl-names = "default", "gpio";
726 pinctrl-0 = <&i2c5_xfer>;
727 pinctrl-1 = <&i2c5_gpio>;
728 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
729 clocks = <&clk_gates19 14>;
730 rockchip,check-idle = <1>;
735 compatible = "rockchip,rk-fb";
736 rockchip,disp-mode = <NO_DUAL>;
740 rk_screen: rk_screen {
741 compatible = "rockchip,screen";
744 dsihost0: mipi@ff960000{
745 compatible = "rockchip,rk3368-dsi";
747 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
748 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
749 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>;
751 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
755 lvds: lvds@ff968000 {
756 compatible = "rockchip,rk3368-lvds";
757 rockchip,grf = <&grf>;
758 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
759 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
760 clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
761 clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
766 compatible = "rockchip,rk32-edp";
767 reg = <0x0 0xff970000 0x0 0x4000>;
768 rockchip,grf = <&grf>;
769 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
771 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
772 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
773 reset-names = "edp_24m", "edp_apb";
776 hdmi: hdmi@ff980000 {
777 compatible = "rockchip,rk3368-hdmi";
778 reg = <0x0 0xff980000 0x0 0x20000>;
779 rockchip,grf = <&grf>;
780 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
781 pinctrl-names = "default", "gpio";
782 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
783 pinctrl-1 = <&i2c5_gpio>;
784 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
785 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
789 hdmi_hdcp2: hdmi_hdcp2@ff978000 {
790 compatible = "rockchip,rk3368-hdmi-hdcp2";
791 reg = <0x0 0xff978000 0x0 0x2000>;
792 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
794 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
798 lcdc: lcdc@ff930000 {
799 compatible = "rockchip,rk3368-lcdc";
800 rockchip,grf = <&grf>;
801 rockchip,pmugrf = <&pmugrf>;
802 rockchip,prop = <PRMRY>;
803 rockchip,pwr18 = <0>;
804 rockchip,iommu-enabled = <0>;
805 reg = <0x0 0xff930000 0x0 0x10000>;
806 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
807 /*pinctrl-names = "default", "gpio";
808 *pinctrl-0 = <&lcdc_lcdc>;
809 *pinctrl-1 = <&lcdc_gpio>;
812 clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
813 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
817 compatible = "rockchip,saradc";
818 reg = <0x0 0xff100000 0x0 0x100>;
819 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
820 #io-channel-cells = <1>;
822 rockchip,adc-vref = <1800>;
823 clock-frequency = <1000000>;
824 clocks = <&clk_saradc>, <&clk_gates19 15>;
825 clock-names = "saradc", "pclk_saradc";
830 compatible = "rockchip,rk3368-rga2";
831 reg = <0x0 0xff920000 0x0 0x1000>;
832 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
834 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
837 i2s0: i2s0@ff898000 {
838 compatible = "rockchip-i2s";
839 reg = <0x0 0xff898000 0x0 0x1000>;
841 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
842 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
843 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
844 dmas = <&pdma0 0>, <&pdma0 1>;
846 dma-names = "tx", "rx";
847 pinctrl-names = "default", "sleep";
848 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
849 pinctrl-1 = <&i2s_gpio>;
852 i2s1: i2s1@ff890000 {
853 compatible = "rockchip-i2s";
854 reg = <0x0 0xff890000 0x0 0x1000>;
856 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
857 clock-names = "i2s_clk", "i2s_hclk";
858 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
859 dmas = <&pdma0 6>, <&pdma0 7>;
861 dma-names = "tx", "rx";
864 spdif: spdif@ff880000 {
865 compatible = "rockchip-spdif";
866 reg = <0x0 0xff880000 0x0 0x1000>;
867 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
868 clock-names = "spdif_mclk", "spdif_hclk";
869 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
873 pinctrl-names = "default";
874 pinctrl-0 = <&spdif_tx>;
878 compatible = "rockchip,rk-pwm";
879 reg = <0x0 0xff680000 0x0 0x10>;
881 pinctrl-names = "default";
882 pinctrl-0 = <&pwm0_pin>;
883 clocks = <&clk_gates13 6>;
884 clock-names = "pclk_pwm";
889 compatible = "rockchip,rk-pwm";
890 reg = <0x0 0xff680010 0x0 0x10>;
892 pinctrl-names = "default";
893 pinctrl-0 = <&pwm1_pin>;
894 clocks = <&clk_gates13 6>;
895 clock-names = "pclk_pwm";
900 compatible = "rockchip,rk-pwm";
901 reg = <0x0 0xff680020 0x0 0x10>;
903 //pinctrl-names = "default";
904 //pinctrl-0 = <&pwm1_pin>;
905 clocks = <&clk_gates13 6>;
906 clock-names = "pclk_pwm";
911 compatible = "rockchip,rk-pwm";
912 reg = <0x0 0xff680030 0x0 0x10>;
914 pinctrl-names = "default";
915 pinctrl-0 = <&pwm3_pin>;
916 clocks = <&clk_gates13 6>;
917 clock-names = "pclk_pwm";
921 remotectl: pwm@ff680030 {
922 compatible = "rockchip,remotectl-pwm";
923 reg = <0x0 0xff680030 0x0 0x50>;
925 pinctrl-names = "default";
926 pinctrl-0 = <&pwm3_pin>;
927 clocks = <&clk_gates13 6>;
928 clock-names = "pclk_pwm";
933 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
937 voppwm: pwm@ff9301a0 {
938 compatible = "rockchip,vop-pwm";
939 reg = <0x0 0xff9301a0 0x0 0x10>;
941 pinctrl-names = "default";
942 pinctrl-0 = <&vop_pwm_pin>;
943 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
944 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
949 compatible = "rockchip,rk3368-pvtm";
950 rockchip,grf = <&grf>;
951 rockchip,pmugrf = <&pmugrf>;
952 rockchip,pvtm-clk-out = <1>;
956 compatible = "rockchip,rk3368-cpufreq";
957 rockchip,grf = <&grf>;
963 regulator_name = "vdd_arm";
964 suspend_volt = <1000>; //mV
966 clk_core_b_dvfs_table: clk_core_b {
976 clk_core_l_dvfs_table: clk_core_l {
990 regulator_name = "vdd_logic";
991 suspend_volt = <1000>; //mV
993 clk_ddr_dvfs_table: clk_ddr {
1001 status = "disabled";
1006 clk_gpu_dvfs_table: clk_gpu {
1007 operating-points = <
1027 compatible = "rockchip,ion";
1028 #address-cells = <1>;
1031 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1032 compatible = "rockchip,ion-heap";
1033 rockchip,ion_heap = <4>;
1034 reg = <0x00000000 0x08000000>; /* 512MB */
1036 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1037 compatible = "rockchip,ion-heap";
1038 rockchip,ion_heap = <0>;
1043 compatible = "rockchip,vpu_sub";
1044 iommu_enabled = <0>;
1045 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1046 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1047 interrupt-names = "irq_enc", "irq_dec";
1049 name = "vpu_service";
1052 hevc: hevc_service {
1053 compatible = "rockchip,hevc_sub";
1054 iommu_enabled = <0>;
1055 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1056 interrupt-names = "irq_dec";
1058 name = "hevc_service";
1061 vpu_combo: vpu_combo@ff9a0000 {
1062 compatible = "rockchip,vpu_combo";
1063 reg = <0x0 0xff9a0000 0x0 0x800>;
1064 rockchip,grf = <&grf>;
1066 rockchip,sub = <&vpu>, <&hevc>;
1067 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1068 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1070 mode_ctrl = <0x418>;
1076 compatible = "rockchip,iep";
1077 iommu_enabled = <0>;
1078 reg = <0x0 0xff900000 0x0 0x800>;
1079 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1081 clock-names = "aclk_iep", "hclk_iep";
1085 gmac: eth@ff290000 {
1086 compatible = "rockchip,rk3368-gmac";
1087 reg = <0x0 0xff290000 0x0 0x10000>;
1088 rockchip,grf = <&grf>;
1089 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1090 interrupt-names = "macirq";
1092 clocks = <&clk_mac>, <&clk_gates7 4>,
1093 <&clk_gates7 5>, <&clk_gates7 6>,
1094 <&clk_gates7 7>, <&clk_gates20 13>,
1096 clock-names = "clk_mac", "mac_clk_rx",
1097 "mac_clk_tx", "clk_mac_ref",
1098 "clk_mac_refout", "aclk_mac",
1102 pinctrl-names = "default";
1103 pinctrl-0 = <&rgmii_pins>;
1104 status = "disabled";
1108 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1109 reg = <0x0 0xffa30000 0x0 0x10000>;
1110 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1111 interrupt-names = "GPU";
1116 compatible = "rockchip,iep_mmu";
1117 reg = <0x0 0xff900800 0x0 0x100>;
1118 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1119 interrupt-names = "iep_mmu";
1124 compatible = "rockchip,vip_mmu";
1125 reg = <0x0 0xff950800 0x0 0x100>;
1126 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1127 interrupt-names = "vip_mmu";
1132 compatible = "rockchip,vopb_mmu";
1133 reg = <0x0 0xff930300 0x0 0x100>;
1134 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1135 interrupt-names = "vop_mmu";
1139 dbgname = "isp_mmu";
1140 compatible = "rockchip,isp_mmu";
1141 reg = <0x0 0xff914000 0x0 0x100>,
1142 <0x0 0xff915000 0x0 0x100>;
1143 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1144 interrupt-names = "isp_mmu";
1148 dbgname = "hdcp_mmu";
1149 compatible = "rockchip,hdcp_mmu";
1150 reg = <0x0 0xff940000 0x0 0x100>;
1151 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1152 interrupt-names = "hdcp_mmu";
1157 compatible = "rockchip,hevc_mmu";
1158 reg = <0x0 0xff9c0440 0x0 0x40>, /*need to fix*/
1159 <0x0 0xff9c0480 0x0 0x40>;
1160 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1161 interrupt-names = "hevc_mmu";
1166 compatible = "rockchip,vpu_mmu";
1167 reg = <0x0 0xff9a0800 0x0 0x100>; /*need to fix*/
1168 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1169 interrupt-names = "vpu_mmu";
1173 rockchip,ctrbits = <
1180 |RKPM_CTR_SYSCLK_DIV
1181 |RKPM_CTR_IDLEAUTO_MD
1182 |RKPM_CTR_ARMOFF_LPMD
1184 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1187 rockchip,pmic-suspend_gpios = <
1188 /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1190 rockchip,pmic-resume_gpios = <
1191 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1196 compatible = "rockchip,isp";
1197 reg = <0x0 0xff910000 0x0 0x10000>;
1198 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1199 clocks = <&clk_gates16 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>, <&pd_isp>;
1200 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "pd_isp";
1201 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1202 pinctrl-0 = <&cif_clkout>;
1203 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1204 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1205 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1206 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1207 pinctrl-5 = <&cif_clkout>;
1208 pinctrl-6 = <&cif_clkout &isp_prelight>;
1209 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1210 pinctrl-8 = <&isp_flash_trigger>;
1211 rockchip,isp,mipiphy = <2>;
1212 rockchip,isp,cifphy = <1>;
1213 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1214 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1215 rockchip,grf = <&grf>;
1216 rockchip,cru = <&cru>;
1217 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1218 rockchip,isp,iommu_enable = <0>;
1223 compatible = "rockchip,cif";
1224 reg = <0x0 0xff950000 0x0 0x10000>;
1225 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1226 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1227 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1228 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1229 pinctrl-names = "cif_pin_all";
1230 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1231 rockchip,grf = <&grf>;
1232 rockchip,cru = <&cru>;
1238 #include "rk3368-thermal.dtsi"
1242 tsadc: tsadc@ff280000 {
1243 compatible = "rockchip,rk3368-tsadc";
1244 reg = <0x0 0xff280000 0x0 0x100>;
1245 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1246 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1247 rockchip,grf = <&grf>;
1248 rockchip,cru = <&cru>;
1249 rockchip,pmu = <&pmu>;
1250 clock-names = "tsadc", "apb_pclk";
1251 clock-frequency = <32000>;
1252 resets = <&reset RK3368_SRST_TSADC_P>;
1253 reset-names = "tsadc-apb";
1254 //pinctrl-names = "default";
1255 //pinctrl-0 = <&tsadc_int>;
1256 #thermal-sensor-cells = <1>;
1257 hw-shut-temp = <120000>;
1258 status = "disabled";
1262 compatible = "rockchip,rk3368-tsp";
1263 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1264 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1265 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1266 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1267 interrupt-names = "irq_tsp";
1268 // pinctrl-names = "default";
1269 // pinctrl-0 = <&isp_hsadc>;
1273 crypto: crypto@FF8A0000{
1274 compatible = "rockchip,rk3368-crypto";
1275 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1276 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1277 interrupt-names = "irq_crypto";
1278 clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1279 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1283 dwc_control_usb: dwc-control-usb {
1284 compatible = "rockchip,rk3368-dwc-control-usb";
1285 rockchip,grf = <&grf>;
1286 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1287 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1288 interrupt-names = "otg_id", "otg_bvalid",
1289 "otg_linestate", "host0_linestate";
1290 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1291 clock-names = "hclk_usb_peri", "usbphy_480m";
1292 //resets = <&reset RK3128_RST_USBPOR>;
1293 //reset-names = "usbphy_por";
1295 compatible = "inno,phy";
1296 regbase = &dwc_control_usb;
1297 rk_usb,bvalid = <0x4bc 23 1>;
1298 rk_usb,iddig = <0x4bc 26 1>;
1299 rk_usb,vdmsrcen = <0x718 12 1>;
1300 rk_usb,vdpsrcen = <0x718 11 1>;
1301 rk_usb,rdmpden = <0x718 10 1>;
1302 rk_usb,idpsrcen = <0x718 9 1>;
1303 rk_usb,idmsinken = <0x718 8 1>;
1304 rk_usb,idpsinken = <0x718 7 1>;
1305 rk_usb,dpattach = <0x4b8 31 1>;
1306 rk_usb,cpdet = <0x4b8 30 1>;
1307 rk_usb,dcpattach = <0x4b8 29 1>;
1311 usb0: usb@ff580000 {
1312 compatible = "rockchip,rk3368_usb20_otg";
1313 reg = <0x0 0xff580000 0x0 0x40000>;
1314 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1315 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1316 clock-names = "clk_usbphy0", "hclk_otg";
1317 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1318 <&reset RK3368_SRST_USBOTGC0>;
1319 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1320 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1321 rockchip,usb-mode = <0>;
1324 usb_ehci: usb@ff500000 {
1325 compatible = "generic-ehci";
1326 reg = <0x0 0xff500000 0x0 0x20000>;
1327 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1328 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1329 clock-names = "clk_usbphy0", "hclk_ehci";
1330 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1331 // <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1332 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1335 usb_ohci: usb@ff520000 {
1336 compatible = "generic-ohci";
1337 reg = <0x0 0xff520000 0x0 0x20000>;
1338 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1339 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1340 clock-names = "clk_usbphy0", "hclk_ohci";
1343 usb_hsic: usb@ff5c0000 {
1344 compatible = "rockchip,rk3288_rk_hsic_host";
1345 reg = <0x0 0xff5c0000 0x0 0x40000>;
1346 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1348 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1349 <&hsicphy_12m>, <&usbphy_480m>,
1350 <&otgphy1_480m>, <&otgphy2_480m>;
1351 clock-names = "hsicphy_480m", "hclk_hsic",
1352 "hsicphy_12m", "usbphy_480m",
1353 "hsic_usbphy1", "hsic_usbphy2";
1354 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1355 <&reset RK3288_SOFT_RST_HSICPHY>;
1356 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1358 status = "disabled";
1362 compatible = "rockchip,rk3368-pinctrl";
1363 rockchip,grf = <&grf>;
1364 rockchip,pmugrf = <&pmugrf>;
1365 #address-cells = <2>;
1369 gpio0: gpio0@ff750000 {
1370 compatible = "rockchip,gpio-bank";
1371 reg = <0x0 0xff750000 0x0 0x100>;
1372 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1373 clocks = <&clk_gates23 4>;
1378 interrupt-controller;
1379 #interrupt-cells = <2>;
1382 gpio1: gpio1@ff780000 {
1383 compatible = "rockchip,gpio-bank";
1384 reg = <0x0 0xff780000 0x0 0x100>;
1385 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1386 clocks = <&clk_gates22 1>;
1391 interrupt-controller;
1392 #interrupt-cells = <2>;
1395 gpio2: gpio2@ff790000 {
1396 compatible = "rockchip,gpio-bank";
1397 reg = <0x0 0xff790000 0x0 0x100>;
1398 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1399 clocks = <&clk_gates22 2>;
1404 interrupt-controller;
1405 #interrupt-cells = <2>;
1408 gpio3: gpio3@ff7a0000 {
1409 compatible = "rockchip,gpio-bank";
1410 reg = <0x0 0xff7a0000 0x0 0x100>;
1411 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1412 clocks = <&clk_gates22 3>;
1417 interrupt-controller;
1418 #interrupt-cells = <2>;
1421 pcfg_pull_up: pcfg-pull-up {
1425 pcfg_pull_down: pcfg-pull-down {
1429 pcfg_pull_none: pcfg-pull-none {
1433 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1434 drive-strength = <8>;
1437 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1438 drive-strength = <12>;
1441 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1443 drive-strength = <8>;
1446 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1447 drive-strength = <4>;
1450 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1452 drive-strength = <4>;
1455 pcfg_output_high: pcfg-output-high {
1459 pcfg_output_low: pcfg-output-low {
1464 i2c0_xfer: i2c0-xfer {
1465 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1466 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1468 i2c0_gpio: i2c0-gpio {
1469 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1470 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1475 i2c1_xfer: i2c1-xfer {
1476 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1477 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1479 i2c1_gpio: i2c1-gpio {
1480 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1481 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1486 i2c2_xfer: i2c2-xfer {
1487 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1488 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1490 i2c2_gpio: i2c2-gpio {
1491 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1492 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1497 i2c3_xfer: i2c3-xfer {
1498 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1499 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1501 i2c3_gpio: i2c3-gpio {
1502 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1503 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1508 i2c4_xfer: i2c4-xfer {
1509 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1510 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1512 i2c4_gpio: i2c4-gpio {
1513 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1514 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1519 i2c5_xfer: i2c5-xfer {
1520 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1521 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1523 i2c5_gpio: i2c5-gpio {
1524 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1525 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1530 uart0_xfer: uart0-xfer {
1531 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1532 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1535 uart0_cts: uart0-cts {
1536 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1539 uart0_rts: uart0-rts {
1540 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1543 uart0_rts_gpio: uart0-rts-gpio {
1544 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1549 uart1_xfer: uart1-xfer {
1550 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1551 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1554 uart1_cts: uart1-cts {
1555 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1558 uart1_rts: uart1-rts {
1559 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1564 uart2_xfer: uart2-xfer {
1565 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1566 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1571 uart3_xfer: uart3-xfer {
1572 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1573 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1576 uart3_cts: uart3-cts {
1577 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1580 uart3_rts: uart3-rts {
1581 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1586 uart4_xfer: uart4-xfer {
1587 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1588 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1591 uart4_cts: uart4-cts {
1592 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1595 uart4_rts: uart4-rts {
1596 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1601 spi0_clk: spi0-clk {
1602 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1604 spi0_cs0: spi0-cs0 {
1605 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1608 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1611 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1613 spi0_cs1: spi0-cs1 {
1614 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1619 spi1_clk: spi1-clk {
1620 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1622 spi1_cs0: spi1-cs0 {
1623 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1626 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1629 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1631 spi1_cs1: spi1-cs1 {
1632 rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
1637 spi2_clk: spi2-clk {
1638 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1640 spi2_cs0: spi2-cs0 {
1641 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1644 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1647 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1652 i2s_mclk: i2s-mclk {
1653 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1657 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1660 i2s_lrckrx:i2s-lrckrx {
1661 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1664 i2s_lrcktx:i2s-lrcktx {
1665 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1669 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1673 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1677 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1681 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1685 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1688 i2s_gpio: i2s-gpio {
1689 rockchip,pins = <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,
1690 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1691 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1692 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1693 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1694 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1695 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1696 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1697 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1702 spdif_tx: spdif-tx {
1703 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1708 sdmmc_clk: sdmmc-clk {
1709 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1712 sdmmc_cmd: sdmmc-cmd {
1713 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1716 sdmmc_dectn: sdmmc-dectn {
1717 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1720 sdmmc_bus1: sdmmc-bus1 {
1721 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1724 sdmmc_bus4: sdmmc-bus4 {
1725 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1726 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1727 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1728 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1731 sdmmc_gpio: sdmmc-gpio {
1732 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1733 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1734 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1735 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1736 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1737 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1738 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1743 sdio0_bus1: sdio0-bus1 {
1744 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1747 sdio0_bus4: sdio0-bus4 {
1748 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1749 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1750 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1751 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1754 sdio0_cmd: sdio0-cmd {
1755 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1758 sdio0_clk: sdio0-clk {
1759 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1762 sdio0_dectn: sdio0-dectn {
1763 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1766 sdio0_wrprt: sdio0-wrprt {
1767 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1770 sdio0_pwren: sdio0-pwren {
1771 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1774 sdio0_bkpwr: sdio0-bkpwr {
1775 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1778 sdio0_int: sdio0-int {
1779 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1782 sdio0_gpio: sdio0-gpio {
1783 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1784 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1785 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1786 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1787 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1788 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1789 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1790 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1791 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1792 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1793 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1798 emmc_clk: emmc-clk {
1799 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1802 emmc_cmd: emmc-cmd {
1803 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1806 emmc_pwren: emmc-pwren {
1807 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1810 emmc_rstnout: emmc_rstnout {
1811 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1814 emmc_bus1: emmc-bus1 {
1815 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1818 emmc_bus4: emmc-bus4 {
1819 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1820 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1821 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1822 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1827 pwm0_pin: pwm0-pin {
1828 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1831 vop_pwm_pin:vop-pwm {
1832 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1837 pwm1_pin: pwm1-pin {
1838 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1843 pwm3_pin: pwm3-pin {
1844 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1849 lcdc_lcdc: lcdc-lcdc {
1851 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1852 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1853 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1854 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1855 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1856 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1857 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1858 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1859 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1860 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1861 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1862 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1863 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1864 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1865 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1866 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1867 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1868 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1871 lcdc_gpio: lcdc-gpio {
1873 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1874 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1875 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1876 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1877 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1878 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1879 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1880 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1881 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1882 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1883 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1884 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1885 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1886 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1887 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1888 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1889 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1890 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1895 cif_clkout: cif-clkout {
1896 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1899 isp_dvp_d2d9: isp-dvp-d2d9 {
1900 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1901 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1902 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1903 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1904 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1905 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1906 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1907 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1908 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1909 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1910 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1911 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1914 isp_dvp_d0d1: isp-dvp-d0d1 {
1915 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1916 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1919 isp_dvp_d10d11:isp_d10d11 {
1920 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1921 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1924 isp_dvp_d0d7: isp-dvp-d0d7 {
1925 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1926 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1927 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1928 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1929 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1930 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1931 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1932 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1935 isp_shutter: isp-shutter {
1936 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1937 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1940 isp_flash_trigger: isp-flash-trigger {
1941 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1944 isp_prelight: isp-prelight {
1945 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1948 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1949 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1955 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1959 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1963 gps_rfclk: gps-rfclk {
1964 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1969 rgmii_pins: rgmii-pins {
1970 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1971 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1972 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1973 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1974 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1975 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
1976 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
1977 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
1978 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1979 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1980 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1981 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1982 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1983 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1984 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
1987 rmii_pins: rmii-pins {
1988 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1989 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1990 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1991 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1992 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1993 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1994 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1995 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1996 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1997 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
2002 tsadc_int: tsadc-int {
2003 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
2005 tsadc_gpio: tsadc-gpio {
2006 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
2011 hdmi_cec: hdmi-cec {
2012 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2017 hdmii2c_xfer: hdmii2c-xfer {
2018 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2019 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2024 cpu_jtag: cpu-jtag {
2025 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2026 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2032 compatible = "rockchip,rk3368-reboot";
2033 rockchip,cru = <&cru>;
2034 rockchip,pmugrf = <&pmugrf>;