1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-pm.h>
3 #include <dt-bindings/pinctrl/rockchip.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/sensor-dev.h>
6 #include <dt-bindings/clock/rk_system_status.h>
8 #include "rk3368-clocks.dtsi"
11 compatible = "rockchip,rk3368";
13 rockchip,sram = <&sram>;
14 interrupt-parent = <&gic>;
41 entry-method = "arm,psci";
42 CPU_SLEEP_0: cpu-sleep-0 {
43 compatible = "arm,idle-state";
44 arm,psci-suspend-param = <0x1010000>;
45 entry-latency-us = <0x3fffffff>;
46 exit-latency-us = <0x40000000>;
47 min-residency-us = <0xffffffff>;
53 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
56 cpu-idle-states = <&CPU_SLEEP_0>;
60 compatible = "arm,cortex-a53", "arm,armv8";
62 enable-method = "psci";
63 cpu-idle-states = <&CPU_SLEEP_0>;
67 compatible = "arm,cortex-a53", "arm,armv8";
69 enable-method = "psci";
70 cpu-idle-states = <&CPU_SLEEP_0>;
74 compatible = "arm,cortex-a53", "arm,armv8";
76 enable-method = "psci";
77 cpu-idle-states = <&CPU_SLEEP_0>;
81 compatible = "arm,cortex-a53", "arm,armv8";
83 enable-method = "psci";
84 cpu-idle-states = <&CPU_SLEEP_0>;
88 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
91 cpu-idle-states = <&CPU_SLEEP_0>;
95 compatible = "arm,cortex-a53", "arm,armv8";
97 enable-method = "psci";
98 cpu-idle-states = <&CPU_SLEEP_0>;
102 compatible = "arm,cortex-a53", "arm,armv8";
104 enable-method = "psci";
105 cpu-idle-states = <&CPU_SLEEP_0>;
141 compatible = "arm,psci-0.2";
145 gic: interrupt-controller@ffb70000 {
146 compatible = "arm,cortex-a15-gic";
147 #interrupt-cells = <3>;
148 #address-cells = <0>;
149 interrupt-controller;
150 reg = <0x0 0xffb71000 0 0x1000>,
151 <0x0 0xffb72000 0 0x1000>;
154 ddrpctl: syscon@ff610000 {
155 compatible = "rockchip,rk3368-ddrpctl", "syscon";
156 reg = <0x0 0xff610000 0x0 0x400>;
159 pmu: syscon@ff730000 {
160 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
161 reg = <0x0 0xff730000 0x0 0x1000>;
164 pmugrf: syscon@ff738000 {
165 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
166 reg = <0x0 0xff738000 0x0 0x1000>;
169 sgrf: syscon@ff740000 {
170 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
171 reg = <0x0 0xff740000 0x0 0x1000>;
175 cru: syscon@ff760000 {
176 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
177 reg = <0x0 0xff760000 0x0 0x1000>;
180 grf: syscon@ff770000 {
181 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
182 reg = <0x0 0xff770000 0x0 0x1000>;
185 msch: syscon@ffac0000 {
186 compatible = "rockchip,rk3368-msch", "rockchip,msch", "syscon";
187 reg = <0x0 0xffac0000 0x0 0x3000>;
191 compatible = "arm,armv8-pmuv3";
192 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
202 cpu_axi_bus: cpu_axi_bus {
203 compatible = "rockchip,cpu_axi_bus";
204 #address-cells = <2>;
209 #address-cells = <2>;
214 reg = <0x0 0xffa80000 0x0 0x20>;
217 reg = <0x0 0xffa80080 0x0 0x20>;
220 reg = <0x0 0xffa80280 0x0 0x20>;
223 reg = <0x0 0xffa90000 0x0 0x20>;
226 reg = <0x0 0xffaa0000 0x0 0x20>;
229 reg = <0x0 0xffaa0080 0x0 0x20>;
232 reg = <0x0 0xffab0000 0x0 0x20>;
233 rockchip,priority = <2 2>;
236 reg = <0x0 0xffad0000 0x0 0x20>;
239 reg = <0x0 0xffad0080 0x0 0x20>;
242 reg = <0x0 0xffad0100 0x0 0x20>;
245 reg = <0x0 0xffad0180 0x0 0x20>;
246 rockchip,priority = <2 2>;
249 reg = <0x0 0xffad0200 0x0 0x20>;
250 rockchip,priority = <2 2>;
253 reg = <0x0 0xffad0280 0x0 0x20>;
256 reg = <0x0 0xffad0300 0x0 0x20>;
257 rockchip,priority = <2 2>;
260 reg = <0x0 0xffad0380 0x0 0x20>;
263 reg = <0x0 0xffad0400 0x0 0x20>;
266 reg = <0x0 0xffae0000 0x0 0x20>;
269 reg = <0x0 0xffae0100 0x0 0x20>;
272 reg = <0x0 0xffae0180 0x0 0x20>;
275 reg = <0x0 0xffaf0000 0x0 0x20>;
280 #address-cells = <2>;
285 reg = <0x0 0xffac0000 0x0 0x3c>;
286 rockchip,read-latency = <0x34>;
292 compatible = "arm,armv8-timer";
293 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
294 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
295 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
296 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
297 clock-frequency = <24000000>;
301 compatible = "rockchip,timer";
302 reg = <0x0 0xff810000 0x0 0x20>;
303 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
304 rockchip,broadcast = <1>;
307 sram: sram@ff8c0000 {
308 compatible = "mmio-sram";
309 reg = <0x0 0xff8c0000 0x0 0xf000>; /* 60K (reserved 4K for mailbox)*/
313 watchdog: wdt@ff800000 {
314 compatible = "rockchip,watch dog";
315 reg = <0x0 0xff800000 0x0 0x100>;
316 clocks = <&pclk_alive_pre>;
317 clock-names = "pclk_wdt";
318 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
320 rockchip,timeout = <60>;
321 rockchip,atboot = <1>;
322 rockchip,debug = <0>;
327 #address-cells = <2>;
329 compatible = "arm,amba-bus";
330 interrupt-parent = <&gic>;
333 pdma0: pdma@ff600000 {
334 compatible = "arm,pl330", "arm,primecell";
335 reg = <0x0 0xff600000 0x0 0x4000>;
336 clocks = <&clk_gates12 11>;
337 clock-names = "apb_pclk";
338 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
344 pdma1: pdma@ff250000 {
345 compatible = "arm,pl330", "arm,primecell";
346 reg = <0x0 0xff250000 0x0 0x4000>;
347 clocks = <&clk_gates19 3>;
348 clock-names = "apb_pclk";
349 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
355 reset: reset@ff760300{
356 compatible = "rockchip,reset";
357 reg = <0x0 0xff760300 0x0 0x38>;
358 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
362 nandc0: nandc@ff400000 {
363 compatible = "rockchip,rk-nandc";
364 reg = <0x0 0xff400000 0x0 0x4000>;
365 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
368 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
371 nandc0reg: nandc0@ff400000 {
372 compatible = "rockchip,rk-nandc";
373 reg = <0x0 0xff400000 0x0 0x4000>;
376 emmc: rksdmmc@ff0f0000 {
377 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
378 reg = <0x0 0xff0f0000 0x0 0x4000>;
379 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
380 #address-cells = <1>;
382 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
383 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
384 rockchip,grf = <&grf>;
386 fifo-depth = <0x100>;
390 sdmmc: rksdmmc@ff0c0000 {
391 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
392 reg = <0x0 0xff0c0000 0x0 0x4000>;
393 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
394 #address-cells = <1>;
396 pinctrl-names = "default", "idle", "udbg";
397 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
398 pinctrl-1 = <&sdmmc_gpio>;
399 pinctrl-2 = <&uart2_xfer &cpu_jtag &sdmmc_dectn>;
400 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
401 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
402 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
403 rockchip,grf = <&grf>;
405 fifo-depth = <0x100>;
409 sdio: rksdmmc@ff0d0000 {
410 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
411 reg = <0x0 0xff0d0000 0x0 0x4000>;
412 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
413 #address-cells = <1>;
415 pinctrl-names = "default","idle";
416 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
417 pinctrl-1 = <&sdio0_gpio>;
418 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
419 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
420 rockchip,grf = <&grf>;
422 fifo-depth = <0x100>;
427 compatible = "rockchip,rockchip-spi";
428 reg = <0x0 0xff110000 0x0 0x1000>;
429 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
434 rockchip,spi-src-clk = <0>;
436 clocks =<&clk_spi0>, <&clk_gates19 4>;
437 clock-names = "spi", "pclk_spi0";
438 //dmas = <&pdma1 11>, <&pdma1 12>;
440 //dma-names = "tx", "rx";
445 compatible = "rockchip,rockchip-spi";
446 reg = <0x0 0xff120000 0x0 0x1000>;
447 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
448 #address-cells = <1>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
452 rockchip,spi-src-clk = <1>;
454 clocks = <&clk_spi1>, <&clk_gates19 5>;
455 clock-names = "spi", "pclk_spi1";
456 //dmas = <&pdma1 13>, <&pdma1 14>;
458 //dma-names = "tx", "rx";
463 compatible = "rockchip,rockchip-spi";
464 reg = <0x0 0xff130000 0x0 0x1000>;
465 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
466 #address-cells = <1>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
470 rockchip,spi-src-clk = <2>;
472 clocks = <&clk_spi2>, <&clk_gates19 6>;
473 clock-names = "spi", "pclk_spi2";
474 //dmas = <&pdma1 15>, <&pdma1 16>;
476 //dma-names = "tx", "rx";
480 uart_bt: serial@ff180000 {
481 compatible = "rockchip,serial";
482 reg = <0x0 0xff180000 0x0 0x100>;
483 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
484 clock-frequency = <24000000>;
485 clocks = <&clk_uart0>, <&clk_gates19 7>;
486 clock-names = "sclk_uart", "pclk_uart";
489 //dmas = <&pdma1 1>, <&pdma1 2>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
496 uart_bb: serial@ff190000 {
497 compatible = "rockchip,serial";
498 reg = <0x0 0xff190000 0x0 0x100>;
499 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
500 clock-frequency = <24000000>;
501 clocks = <&clk_uart1>, <&clk_gates19 8>;
502 clock-names = "sclk_uart", "pclk_uart";
505 //dmas = <&pdma1 3>, <&pdma1 4>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
512 uart_dbg: serial@ff690000 {
513 compatible = "rockchip,serial";
514 reg = <0x0 0xff690000 0x0 0x100>;
515 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
516 clock-frequency = <24000000>;
517 clocks = <&clk_uart2>, <&clk_gates13 5>;
518 clock-names = "sclk_uart", "pclk_uart";
521 //dmas = <&pdma0 4>, <&pdma0 5>;
523 //pinctrl-names = "default";
524 //pinctrl-0 = <&uart2_xfer>;
528 uart_gps: serial@ff1b0000 {
529 compatible = "rockchip,serial";
530 reg = <0x0 0xff1b0000 0x0 0x100>;
531 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
532 clock-frequency = <24000000>;
533 clocks = <&clk_uart3>, <&clk_gates19 9>;
534 clock-names = "sclk_uart", "pclk_uart";
535 current-speed = <115200>;
538 //dmas = <&pdma1 7>, <&pdma1 8>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
545 uart_exp: serial@ff1c0000 {
546 compatible = "rockchip,serial";
547 reg = <0x0 0xff1c0000 0x0 0x100>;
548 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
549 clock-frequency = <24000000>;
550 clocks = <&clk_uart4>, <&clk_gates19 10>;
551 clock-names = "sclk_uart", "pclk_uart";
554 //dmas = <&pdma1 9>, <&pdma1 10>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
561 mbox: mbox@ff6b0000 {
562 compatible = "rockchip,rk3368-mailbox";
563 reg = <0x0 0xff6b0000 0x0 0x1000>,
564 <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
565 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&clk_gates12 1>;
570 clock-names = "pclk_mailbox";
574 mbox_scpi: mbox-scpi {
575 compatible = "rockchip,mbox-scpi";
576 mboxes = <&mbox 0 &mbox 1>;
580 compatible = "rockchip,rk3368-ddr";
582 rockchip,ddrpctl = <&ddrpctl>;
583 rockchip,grf = <&grf>;
584 rockchip,msch = <&msch>;
587 rockchip_clocks_init: clocks-init{
588 compatible = "rockchip,clocks-init";
589 rockchip,clocks-init-parent =
590 <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
591 <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
592 <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
593 <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
594 rockchip,clocks-init-rate =
595 <&clk_gpll 576000000>, <&clk_core_b 792000000>,
596 <&clk_core_l 600000000>, <&clk_cpll 400000000>,
597 /*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
598 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
599 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
600 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
601 <&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
602 <&clk_cs 300000000>, <&clkin_trace 300000000>,
603 <&aclk_cci 600000000>, <&clk_mac 125000000>,
604 <&aclk_vio0 400000000>, <&hclk_vio 100000000>,
605 <&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
606 <&clk_isp 400000000>, <&clk_edp 200000000>,
607 <&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
608 <&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
609 <&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
610 <&clk_hevc_cabac 300000000>;
612 rockchip,clocks-uboot-has-init =
617 rockchip_clocks_enable: clocks-enable {
618 compatible = "rockchip,clocks-enable";
641 <&clk_gates12 12>,/*aclk_strc_sys*/
642 <&clk_gates12 6>,/*aclk_intmem1*/
643 <&clk_gates12 5>,/*aclk_intmem0*/
644 <&clk_gates12 4>,/*aclk_intmem*/
645 <&clk_gates13 9>,/*aclk_gic400*/
646 <&clk_gates12 9>,/*hclk_rom*/
649 <&clk_gates22 13>,/*pclk_timer1*/
650 <&clk_gates22 12>,/*pclk_timer0*/
651 <&clk_gates22 9>,/*pclk_alive_niu*/
652 <&clk_gates22 8>,/*pclk_grf*/
655 <&clk_gates23 5>,/*pclk_pmugrf*/
656 <&clk_gates23 3>,/*pclk_sgrf*/
657 <&clk_gates23 2>,/*pclk_pmu_noc*/
658 <&clk_gates23 1>,/*pclk_intmem1*/
659 <&clk_gates23 0>,/*pclk_pmu*/
662 <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
663 <&clk_gates20 8>,/*aclk_peri_niu*/
664 <&clk_gates21 4>,/*aclk_peri_mmu*/
665 <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
666 <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
667 <&clk_gates19 1>,/*pclk_peri_axi_matrix*/
671 <&clk_gates7 0>;/*clk_jtag*/
676 compatible = "rockchip,rk30-i2c";
677 reg = <0x0 0xff650000 0x0 0x1000>;
678 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
679 #address-cells = <1>;
681 pinctrl-names = "default", "gpio";
682 pinctrl-0 = <&i2c0_xfer>;
683 pinctrl-1 = <&i2c0_gpio>;
684 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
685 clocks = <&clk_gates12 2>;
686 rockchip,check-idle = <1>;
692 compatible = "rockchip,rk30-i2c";
693 reg = <0x0 0xff660000 0x0 0x1000>;
694 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
695 #address-cells = <1>;
697 pinctrl-names = "default", "gpio";
698 pinctrl-0 = <&i2c1_xfer>;
699 pinctrl-1 = <&i2c1_gpio>;
700 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
701 clocks = <&clk_gates12 3>;
702 rockchip,check-idle = <1>;
708 compatible = "rockchip,rk30-i2c";
709 reg = <0x0 0xff140000 0x0 0x1000>;
710 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
711 #address-cells = <1>;
713 pinctrl-names = "default", "gpio";
714 pinctrl-0 = <&i2c2_xfer>;
715 pinctrl-1 = <&i2c2_gpio>;
716 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
717 clocks = <&clk_gates19 11>;
718 rockchip,check-idle = <1>;
724 compatible = "rockchip,rk30-i2c";
725 reg = <0x0 0xff150000 0x0 0x1000>;
726 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
727 #address-cells = <1>;
729 pinctrl-names = "default", "gpio";
730 pinctrl-0 = <&i2c3_xfer>;
731 pinctrl-1 = <&i2c3_gpio>;
732 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
733 clocks = <&clk_gates19 12>;
734 rockchip,check-idle = <1>;
740 compatible = "rockchip,rk30-i2c";
741 reg = <0x0 0xff160000 0x0 0x1000>;
742 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
743 #address-cells = <1>;
745 pinctrl-names = "default", "gpio";
746 pinctrl-0 = <&i2c4_xfer>;
747 pinctrl-1 = <&i2c4_gpio>;
748 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
749 clocks = <&clk_gates19 13>;
750 rockchip,check-idle = <1>;
756 compatible = "rockchip,rk30-i2c";
757 reg = <0x0 0xff170000 0x0 0x1000>;
758 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
759 #address-cells = <1>;
761 pinctrl-names = "default", "gpio";
762 pinctrl-0 = <&i2c5_xfer>;
763 pinctrl-1 = <&i2c5_gpio>;
764 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
765 clocks = <&clk_gates19 14>;
766 rockchip,check-idle = <1>;
771 compatible = "rockchip,rk-fb";
772 rockchip,disp-mode = <NO_DUAL>;
776 rk_screen: rk_screen {
777 compatible = "rockchip,screen";
780 dsihost0: mipi@ff960000{
781 compatible = "rockchip,rk3368-dsi";
783 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
784 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
785 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>, <&pd_mipidsi>;
787 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "pd_mipi_dsi";
791 lvds: lvds@ff968000 {
792 compatible = "rockchip,rk3368-lvds";
793 rockchip,grf = <&grf>;
794 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
795 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
796 clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
797 clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
802 compatible = "rockchip,rk32-edp";
803 reg = <0x0 0xff970000 0x0 0x4000>;
804 rockchip,grf = <&grf>;
805 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
807 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
808 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
809 reset-names = "edp_24m", "edp_apb";
812 hdmi: hdmi@ff980000 {
813 compatible = "rockchip,rk3368-hdmi";
814 reg = <0x0 0xff980000 0x0 0x20000>;
815 rockchip,grf = <&grf>;
816 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
817 pinctrl-names = "default", "gpio";
818 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
819 pinctrl-1 = <&i2c5_gpio>;
820 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
821 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
825 hdmi_hdcp2: hdmi_hdcp2@ff978000 {
826 compatible = "rockchip,rk3368-hdmi-hdcp2";
827 reg = <0x0 0xff978000 0x0 0x2000>;
828 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
830 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
834 lcdc: lcdc@ff930000 {
835 compatible = "rockchip,rk3368-lcdc";
836 rockchip,grf = <&grf>;
837 rockchip,pmugrf = <&pmugrf>;
838 rockchip,cru = <&cru>;
839 rockchip,prop = <PRMRY>;
840 rockchip,pwr18 = <0>;
841 rockchip,iommu-enabled = <0>;
842 reg = <0x0 0xff930000 0x0 0x10000>;
843 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
844 /*pinctrl-names = "default", "gpio";
845 *pinctrl-0 = <&lcdc_lcdc>;
846 *pinctrl-1 = <&lcdc_gpio>;
849 clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
850 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
854 compatible = "rockchip,saradc";
855 reg = <0x0 0xff100000 0x0 0x100>;
856 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
857 #io-channel-cells = <1>;
859 rockchip,adc-vref = <1800>;
860 clock-frequency = <1000000>;
861 clocks = <&clk_saradc>, <&clk_gates19 15>;
862 clock-names = "saradc", "pclk_saradc";
867 compatible = "rockchip,rk3368-rga2";
868 reg = <0x0 0xff920000 0x0 0x1000>;
869 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
871 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
874 i2s0: i2s0@ff898000 {
875 compatible = "rockchip-i2s";
876 reg = <0x0 0xff898000 0x0 0x1000>;
878 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
879 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
880 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
881 dmas = <&pdma0 0>, <&pdma0 1>;
883 dma-names = "tx", "rx";
884 pinctrl-names = "default", "sleep";
885 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
886 pinctrl-1 = <&i2s_gpio>;
889 i2s1: i2s1@ff890000 {
890 compatible = "rockchip-i2s";
891 reg = <0x0 0xff890000 0x0 0x1000>;
893 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
894 clock-names = "i2s_clk", "i2s_hclk";
895 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
896 dmas = <&pdma0 6>, <&pdma0 7>;
898 dma-names = "tx", "rx";
901 spdif: spdif@ff880000 {
902 compatible = "rockchip-spdif";
903 reg = <0x0 0xff880000 0x0 0x1000>;
904 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
905 clock-names = "spdif_mclk", "spdif_hclk";
906 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
910 pinctrl-names = "default";
911 pinctrl-0 = <&spdif_tx>;
915 compatible = "rockchip,rk-pwm";
916 reg = <0x0 0xff680000 0x0 0x10>;
918 pinctrl-names = "default";
919 pinctrl-0 = <&pwm0_pin>;
920 clocks = <&clk_gates13 6>;
921 clock-names = "pclk_pwm";
926 compatible = "rockchip,rk-pwm";
927 reg = <0x0 0xff680010 0x0 0x10>;
929 pinctrl-names = "default";
930 pinctrl-0 = <&pwm1_pin>;
931 clocks = <&clk_gates13 6>;
932 clock-names = "pclk_pwm";
937 compatible = "rockchip,rk-pwm";
938 reg = <0x0 0xff680020 0x0 0x10>;
940 //pinctrl-names = "default";
941 //pinctrl-0 = <&pwm1_pin>;
942 clocks = <&clk_gates13 6>;
943 clock-names = "pclk_pwm";
948 compatible = "rockchip,rk-pwm";
949 reg = <0x0 0xff680030 0x0 0x10>;
951 pinctrl-names = "default";
952 pinctrl-0 = <&pwm3_pin>;
953 clocks = <&clk_gates13 6>;
954 clock-names = "pclk_pwm";
958 remotectl: pwm@ff680030 {
959 compatible = "rockchip,remotectl-pwm";
960 reg = <0x0 0xff680030 0x0 0x50>;
962 pinctrl-names = "default";
963 pinctrl-0 = <&pwm3_pin>;
964 clocks = <&clk_gates13 6>;
965 clock-names = "pclk_pwm";
970 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
974 voppwm: pwm@ff9301a0 {
975 compatible = "rockchip,vop-pwm";
976 reg = <0x0 0xff9301a0 0x0 0x10>;
978 pinctrl-names = "default";
979 pinctrl-0 = <&vop_pwm_pin>;
980 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
981 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
986 compatible = "rockchip,rk3368-pvtm";
987 rockchip,grf = <&grf>;
988 rockchip,pmugrf = <&pmugrf>;
989 rockchip,pvtm-clk-out = <1>;
993 compatible = "rockchip,rk3368-cpufreq";
994 rockchip,grf = <&grf>;
1000 regulator_name = "vdd_arm";
1001 suspend_volt = <1000>; //mV
1003 clk_core_b_dvfs_table: clk_core_b {
1004 operating-points = <
1012 temp-limit-enable = <1>;
1014 min_temp_limit = <216>;
1015 normal-temp-limit = <
1016 /*delta-temp delta-freq*/
1022 performance-temp-limit = <
1027 clk_core_l_dvfs_table: clk_core_l {
1028 operating-points = <
1036 temp-limit-enable = <1>;
1038 min_temp_limit = <216>;
1039 normal-temp-limit = <
1040 /*delta-temp delta-freq*/
1046 performance-temp-limit = <
1054 vd_logic: vd_logic {
1055 regulator_name = "vdd_logic";
1056 suspend_volt = <1000>; //mV
1058 clk_ddr_dvfs_table: clk_ddr {
1059 operating-points = <
1066 status = "disabled";
1071 clk_gpu_dvfs_table: clk_gpu {
1072 operating-points = <
1092 compatible = "rockchip,ion";
1093 #address-cells = <1>;
1096 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1097 compatible = "rockchip,ion-heap";
1098 rockchip,ion_heap = <4>;
1099 reg = <0x00000000 0x08000000>; /* 512MB */
1101 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1102 compatible = "rockchip,ion-heap";
1103 rockchip,ion_heap = <0>;
1108 compatible = "rockchip,vpu_sub";
1109 iommu_enabled = <0>;
1110 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1112 interrupt-names = "irq_enc", "irq_dec";
1114 name = "vpu_service";
1117 hevc: hevc_service {
1118 compatible = "rockchip,hevc_sub";
1119 iommu_enabled = <0>;
1120 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1121 interrupt-names = "irq_dec";
1123 name = "hevc_service";
1126 vpu_combo: vpu_combo@ff9a0000 {
1127 compatible = "rockchip,vpu_combo";
1128 reg = <0x0 0xff9a0000 0x0 0x800>;
1129 rockchip,grf = <&grf>;
1131 rockchip,sub = <&vpu>, <&hevc>;
1132 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1133 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1135 mode_ctrl = <0x418>;
1141 compatible = "rockchip,iep";
1142 iommu_enabled = <0>;
1143 reg = <0x0 0xff900000 0x0 0x800>;
1144 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1146 clock-names = "aclk_iep", "hclk_iep";
1150 gmac: eth@ff290000 {
1151 compatible = "rockchip,rk3368-gmac";
1152 reg = <0x0 0xff290000 0x0 0x10000>;
1153 rockchip,grf = <&grf>;
1154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1155 interrupt-names = "macirq";
1157 clocks = <&clk_mac>, <&clk_gates7 4>,
1158 <&clk_gates7 5>, <&clk_gates7 6>,
1159 <&clk_gates7 7>, <&clk_gates20 13>,
1161 clock-names = "clk_mac", "mac_clk_rx",
1162 "mac_clk_tx", "clk_mac_ref",
1163 "clk_mac_refout", "aclk_mac",
1167 pinctrl-names = "default";
1168 pinctrl-0 = <&rgmii_pins>;
1169 status = "disabled";
1173 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1174 reg = <0x0 0xffa30000 0x0 0x10000>;
1175 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1176 interrupt-names = "GPU";
1181 compatible = "rockchip,iep_mmu";
1182 reg = <0x0 0xff900800 0x0 0x100>;
1183 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1184 interrupt-names = "iep_mmu";
1189 compatible = "rockchip,vip_mmu";
1190 reg = <0x0 0xff950800 0x0 0x100>;
1191 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1192 interrupt-names = "vip_mmu";
1197 compatible = "rockchip,vopb_mmu";
1198 reg = <0x0 0xff930300 0x0 0x100>;
1199 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1200 interrupt-names = "vop_mmu";
1204 dbgname = "isp_mmu";
1205 compatible = "rockchip,isp_mmu";
1206 reg = <0x0 0xff914000 0x0 0x100>,
1207 <0x0 0xff915000 0x0 0x100>;
1208 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1209 interrupt-names = "isp_mmu";
1213 dbgname = "hdcp_mmu";
1214 compatible = "rockchip,hdcp_mmu";
1215 reg = <0x0 0xff940000 0x0 0x100>;
1216 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1217 interrupt-names = "hdcp_mmu";
1222 compatible = "rockchip,hevc_mmu";
1223 reg = <0x0 0xff9a0440 0x0 0x40>, /*need to fix*/
1224 <0x0 0xff9a0480 0x0 0x40>;
1225 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1226 interrupt-names = "hevc_mmu";
1231 compatible = "rockchip,vpu_mmu";
1232 reg = <0x0 0xff9a0800 0x0 0x100>; /*need to fix*/
1233 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1234 interrupt-names = "vpu_mmu";
1238 rockchip,ctrbits = <
1245 |RKPM_CTR_SYSCLK_DIV
1246 |RKPM_CTR_IDLEAUTO_MD
1247 |RKPM_CTR_ARMOFF_LPMD
1249 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1252 rockchip,pmic-suspend_gpios = <
1253 /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1255 rockchip,pmic-resume_gpios = <
1256 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1261 compatible = "rockchip,isp";
1262 reg = <0x0 0xff910000 0x0 0x10000>;
1263 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1264 clocks = <&clk_gates16 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>, <&pd_isp>;
1265 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "pd_isp";
1266 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1267 pinctrl-0 = <&cif_clkout>;
1268 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1269 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1270 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1271 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1272 pinctrl-5 = <&cif_clkout>;
1273 pinctrl-6 = <&cif_clkout &isp_prelight>;
1274 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1275 pinctrl-8 = <&isp_flash_trigger>;
1276 rockchip,isp,mipiphy = <2>;
1277 rockchip,isp,cifphy = <1>;
1278 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1279 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1280 rockchip,grf = <&grf>;
1281 rockchip,cru = <&cru>;
1282 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1283 rockchip,isp,iommu_enable = <0>;
1288 compatible = "rockchip,cif";
1289 reg = <0x0 0xff950000 0x0 0x10000>;
1290 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1291 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1292 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1293 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1294 pinctrl-names = "cif_pin_all";
1295 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1296 rockchip,grf = <&grf>;
1297 rockchip,cru = <&cru>;
1303 #include "rk3368-thermal.dtsi"
1307 tsadc: tsadc@ff280000 {
1308 compatible = "rockchip,rk3368-tsadc";
1309 reg = <0x0 0xff280000 0x0 0x100>;
1310 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1311 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1312 rockchip,grf = <&grf>;
1313 rockchip,cru = <&cru>;
1314 rockchip,pmu = <&pmu>;
1315 clock-names = "tsadc", "apb_pclk";
1316 clock-frequency = <32000>;
1317 resets = <&reset RK3368_SRST_TSADC_P>;
1318 reset-names = "tsadc-apb";
1319 //pinctrl-names = "default";
1320 //pinctrl-0 = <&tsadc_int>;
1321 #thermal-sensor-cells = <1>;
1322 hw-shut-temp = <120000>;
1323 status = "disabled";
1327 compatible = "rockchip,rk3368-tsp";
1328 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1329 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1330 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1331 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1332 interrupt-names = "irq_tsp";
1333 // pinctrl-names = "default";
1334 // pinctrl-0 = <&isp_hsadc>;
1338 crypto: crypto@FF8A0000{
1339 compatible = "rockchip,rk3368-crypto";
1340 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1341 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1342 interrupt-names = "irq_crypto";
1343 clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1344 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1348 dwc_control_usb: dwc-control-usb {
1349 compatible = "rockchip,rk3368-dwc-control-usb";
1350 rockchip,grf = <&grf>;
1351 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1353 interrupt-names = "otg_id", "otg_bvalid",
1354 "otg_linestate", "host0_linestate";
1355 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1356 clock-names = "hclk_usb_peri", "usbphy_480m";
1357 //resets = <&reset RK3128_RST_USBPOR>;
1358 //reset-names = "usbphy_por";
1360 compatible = "inno,phy";
1361 regbase = &dwc_control_usb;
1362 rk_usb,bvalid = <0x4bc 23 1>;
1363 rk_usb,iddig = <0x4bc 26 1>;
1364 rk_usb,vdmsrcen = <0x718 12 1>;
1365 rk_usb,vdpsrcen = <0x718 11 1>;
1366 rk_usb,rdmpden = <0x718 10 1>;
1367 rk_usb,idpsrcen = <0x718 9 1>;
1368 rk_usb,idmsinken = <0x718 8 1>;
1369 rk_usb,idpsinken = <0x718 7 1>;
1370 rk_usb,dpattach = <0x4b8 31 1>;
1371 rk_usb,cpdet = <0x4b8 30 1>;
1372 rk_usb,dcpattach = <0x4b8 29 1>;
1376 usb0: usb@ff580000 {
1377 compatible = "rockchip,rk3368_usb20_otg";
1378 reg = <0x0 0xff580000 0x0 0x40000>;
1379 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1380 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1381 clock-names = "clk_usbphy0", "hclk_otg";
1382 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1383 <&reset RK3368_SRST_USBOTGC0>;
1384 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1385 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1386 rockchip,usb-mode = <0>;
1389 usb_ehci: usb@ff500000 {
1390 compatible = "generic-ehci";
1391 reg = <0x0 0xff500000 0x0 0x20000>;
1392 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1393 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1394 clock-names = "clk_usbphy0", "hclk_ehci";
1395 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1396 // <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1397 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1400 usb_ohci: usb@ff520000 {
1401 compatible = "generic-ohci";
1402 reg = <0x0 0xff520000 0x0 0x20000>;
1403 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1404 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1405 clock-names = "clk_usbphy0", "hclk_ohci";
1408 usb_hsic: usb@ff5c0000 {
1409 compatible = "rockchip,rk3288_rk_hsic_host";
1410 reg = <0x0 0xff5c0000 0x0 0x40000>;
1411 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1413 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1414 <&hsicphy_12m>, <&usbphy_480m>,
1415 <&otgphy1_480m>, <&otgphy2_480m>;
1416 clock-names = "hsicphy_480m", "hclk_hsic",
1417 "hsicphy_12m", "usbphy_480m",
1418 "hsic_usbphy1", "hsic_usbphy2";
1419 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1420 <&reset RK3288_SOFT_RST_HSICPHY>;
1421 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1423 status = "disabled";
1427 compatible = "rockchip,rk3368-pinctrl";
1428 rockchip,grf = <&grf>;
1429 rockchip,pmugrf = <&pmugrf>;
1430 #address-cells = <2>;
1434 gpio0: gpio0@ff750000 {
1435 compatible = "rockchip,gpio-bank";
1436 reg = <0x0 0xff750000 0x0 0x100>;
1437 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1438 clocks = <&clk_gates23 4>;
1443 interrupt-controller;
1444 #interrupt-cells = <2>;
1447 gpio1: gpio1@ff780000 {
1448 compatible = "rockchip,gpio-bank";
1449 reg = <0x0 0xff780000 0x0 0x100>;
1450 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1451 clocks = <&clk_gates22 1>;
1456 interrupt-controller;
1457 #interrupt-cells = <2>;
1460 gpio2: gpio2@ff790000 {
1461 compatible = "rockchip,gpio-bank";
1462 reg = <0x0 0xff790000 0x0 0x100>;
1463 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1464 clocks = <&clk_gates22 2>;
1469 interrupt-controller;
1470 #interrupt-cells = <2>;
1473 gpio3: gpio3@ff7a0000 {
1474 compatible = "rockchip,gpio-bank";
1475 reg = <0x0 0xff7a0000 0x0 0x100>;
1476 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1477 clocks = <&clk_gates22 3>;
1482 interrupt-controller;
1483 #interrupt-cells = <2>;
1486 pcfg_pull_up: pcfg-pull-up {
1490 pcfg_pull_down: pcfg-pull-down {
1494 pcfg_pull_none: pcfg-pull-none {
1498 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1499 drive-strength = <8>;
1502 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1503 drive-strength = <12>;
1506 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1508 drive-strength = <8>;
1511 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1512 drive-strength = <4>;
1515 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1517 drive-strength = <4>;
1520 pcfg_output_high: pcfg-output-high {
1524 pcfg_output_low: pcfg-output-low {
1529 i2c0_xfer: i2c0-xfer {
1530 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1531 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1533 i2c0_gpio: i2c0-gpio {
1534 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1535 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1540 i2c1_xfer: i2c1-xfer {
1541 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1542 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1544 i2c1_gpio: i2c1-gpio {
1545 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1546 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1551 i2c2_xfer: i2c2-xfer {
1552 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1553 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1555 i2c2_gpio: i2c2-gpio {
1556 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1557 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1562 i2c3_xfer: i2c3-xfer {
1563 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1564 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1566 i2c3_gpio: i2c3-gpio {
1567 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1568 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1573 i2c4_xfer: i2c4-xfer {
1574 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1575 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1577 i2c4_gpio: i2c4-gpio {
1578 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1579 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1584 i2c5_xfer: i2c5-xfer {
1585 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1586 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1588 i2c5_gpio: i2c5-gpio {
1589 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1590 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1595 uart0_xfer: uart0-xfer {
1596 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1597 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1600 uart0_cts: uart0-cts {
1601 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1604 uart0_rts: uart0-rts {
1605 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1608 uart0_rts_gpio: uart0-rts-gpio {
1609 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1614 uart1_xfer: uart1-xfer {
1615 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1616 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1619 uart1_cts: uart1-cts {
1620 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1623 uart1_rts: uart1-rts {
1624 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1629 uart2_xfer: uart2-xfer {
1630 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1631 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1636 uart3_xfer: uart3-xfer {
1637 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1638 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1641 uart3_cts: uart3-cts {
1642 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1645 uart3_rts: uart3-rts {
1646 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1651 uart4_xfer: uart4-xfer {
1652 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1653 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1656 uart4_cts: uart4-cts {
1657 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1660 uart4_rts: uart4-rts {
1661 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1666 spi0_clk: spi0-clk {
1667 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1669 spi0_cs0: spi0-cs0 {
1670 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1673 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1676 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1678 spi0_cs1: spi0-cs1 {
1679 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1684 spi1_clk: spi1-clk {
1685 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1687 spi1_cs0: spi1-cs0 {
1688 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1691 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1694 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1696 spi1_cs1: spi1-cs1 {
1697 rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
1702 spi2_clk: spi2-clk {
1703 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1705 spi2_cs0: spi2-cs0 {
1706 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1709 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1712 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1717 i2s_mclk: i2s-mclk {
1718 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1722 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1725 i2s_lrckrx:i2s-lrckrx {
1726 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1729 i2s_lrcktx:i2s-lrcktx {
1730 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1734 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1738 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1742 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1746 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1750 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1753 i2s_gpio: i2s-gpio {
1754 rockchip,pins = <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,
1755 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1756 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1757 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1758 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1759 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1760 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1761 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1762 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1767 spdif_tx: spdif-tx {
1768 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1773 sdmmc_clk: sdmmc-clk {
1774 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1777 sdmmc_cmd: sdmmc-cmd {
1778 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1781 sdmmc_dectn: sdmmc-dectn {
1782 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1785 sdmmc_bus1: sdmmc-bus1 {
1786 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1789 sdmmc_bus4: sdmmc-bus4 {
1790 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1791 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1792 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1793 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1796 sdmmc_gpio: sdmmc-gpio {
1797 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1798 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1799 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1800 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1801 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1802 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1803 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1808 sdio0_bus1: sdio0-bus1 {
1809 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1812 sdio0_bus4: sdio0-bus4 {
1813 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1814 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1815 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1816 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1819 sdio0_cmd: sdio0-cmd {
1820 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1823 sdio0_clk: sdio0-clk {
1824 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1827 sdio0_dectn: sdio0-dectn {
1828 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1831 sdio0_wrprt: sdio0-wrprt {
1832 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1835 sdio0_pwren: sdio0-pwren {
1836 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1839 sdio0_bkpwr: sdio0-bkpwr {
1840 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1843 sdio0_int: sdio0-int {
1844 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1847 sdio0_gpio: sdio0-gpio {
1848 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1849 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1850 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1851 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1852 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1853 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1854 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1855 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1856 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1857 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1858 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1863 emmc_clk: emmc-clk {
1864 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1867 emmc_cmd: emmc-cmd {
1868 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1871 emmc_pwren: emmc-pwren {
1872 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1875 emmc_rstnout: emmc_rstnout {
1876 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1879 emmc_bus1: emmc-bus1 {
1880 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1883 emmc_bus4: emmc-bus4 {
1884 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1885 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1886 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1887 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1892 pwm0_pin: pwm0-pin {
1893 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1896 vop_pwm_pin:vop-pwm {
1897 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1902 pwm1_pin: pwm1-pin {
1903 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1908 pwm3_pin: pwm3-pin {
1909 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1914 lcdc_lcdc: lcdc-lcdc {
1916 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1917 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1918 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1919 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1920 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1921 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1922 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1923 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1924 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1925 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1926 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1927 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1928 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1929 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1930 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1931 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1932 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1933 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1936 lcdc_gpio: lcdc-gpio {
1938 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1939 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1940 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1941 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1942 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1943 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1944 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1945 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1946 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1947 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1948 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1949 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1950 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1951 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1952 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1953 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1954 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1955 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1960 cif_clkout: cif-clkout {
1961 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1964 isp_dvp_d2d9: isp-dvp-d2d9 {
1965 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1966 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1967 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1968 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1969 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1970 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1971 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1972 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1973 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1974 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1975 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1976 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1979 isp_dvp_d0d1: isp-dvp-d0d1 {
1980 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1981 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1984 isp_dvp_d10d11:isp_d10d11 {
1985 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1986 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1989 isp_dvp_d0d7: isp-dvp-d0d7 {
1990 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1991 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1992 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1993 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1994 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1995 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1996 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1997 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2000 isp_shutter: isp-shutter {
2001 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2002 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2005 isp_flash_trigger: isp-flash-trigger {
2006 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2009 isp_prelight: isp-prelight {
2010 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2013 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2014 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2020 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
2024 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
2028 gps_rfclk: gps-rfclk {
2029 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
2034 rgmii_pins: rgmii-pins {
2035 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2036 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2037 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2038 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2039 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2040 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
2041 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
2042 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
2043 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2044 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2045 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2046 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
2047 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
2048 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
2049 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
2052 rmii_pins: rmii-pins {
2053 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2054 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2055 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2056 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2057 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2058 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2059 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2060 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2061 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
2062 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
2067 tsadc_int: tsadc-int {
2068 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
2070 tsadc_gpio: tsadc-gpio {
2071 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
2076 hdmi_cec: hdmi-cec {
2077 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2082 hdmii2c_xfer: hdmii2c-xfer {
2083 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2084 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2089 cpu_jtag: cpu-jtag {
2090 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2091 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2097 compatible = "rockchip,rk3368-reboot";
2098 rockchip,cru = <&cru>;
2099 rockchip,pmugrf = <&pmugrf>;