arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 idle-states {
  41                         entry-method = "arm,psci";
  42                         CPU_SLEEP_0: cpu-sleep-0 {
  43                                 compatible = "arm,idle-state";
  44                                 arm,psci-suspend-param = <0x1010000>;
  45                                 entry-latency-us = <0x3fffffff>;
  46                                 exit-latency-us = <0x40000000>;
  47                                 min-residency-us = <0xffffffff>;
  48                         };
  49                 };
  50
  51                 little0: cpu@100 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53", "arm,armv8";
  54                         reg = <0x0 0x100>;
  55                         enable-method = "psci";
  56                         cpu-idle-states = <&CPU_SLEEP_0>;
  57                 };
  58                 little1: cpu@101 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x101>;
  62                         enable-method = "psci";
  63                         cpu-idle-states = <&CPU_SLEEP_0>;
  64                 };
  65                 little2: cpu@102 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         reg = <0x0 0x102>;
  69                         enable-method = "psci";
  70                         cpu-idle-states = <&CPU_SLEEP_0>;
  71                 };
  72                 little3: cpu@103 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x103>;
  76                         enable-method = "psci";
  77                         cpu-idle-states = <&CPU_SLEEP_0>;
  78                 };
  79                 big0: cpu@0 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         reg = <0x0 0x0>;
  83                         enable-method = "psci";
  84                         cpu-idle-states = <&CPU_SLEEP_0>;
  85                 };
  86                 big1: cpu@1 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         reg = <0x0 0x1>;
  90                         enable-method = "psci";
  91                         cpu-idle-states = <&CPU_SLEEP_0>;
  92                 };
  93                 big2: cpu@2 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53", "arm,armv8";
  96                         reg = <0x0 0x2>;
  97                         enable-method = "psci";
  98                         cpu-idle-states = <&CPU_SLEEP_0>;
  99                 };
 100                 big3: cpu@3 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53", "arm,armv8";
 103                         reg = <0x0 0x3>;
 104                         enable-method = "psci";
 105                         cpu-idle-states = <&CPU_SLEEP_0>;
 106                 };
 107
 108                 cpu-map {
 109                         cluster0 {
 110                                 core0 {
 111                                         cpu = <&big0>;
 112                                 };
 113                                 core1 {
 114                                         cpu = <&big1>;
 115                                 };
 116                                 core2 {
 117                                         cpu = <&big2>;
 118                                 };
 119                                 core3 {
 120                                         cpu = <&big3>;
 121                                 };
 122                         };
 123                         cluster1 {
 124                                 core0 {
 125                                         cpu = <&little0>;
 126                                 };
 127                                 core1 {
 128                                         cpu = <&little1>;
 129                                 };
 130                                 core2 {
 131                                         cpu = <&little2>;
 132                                 };
 133                                 core3 {
 134                                         cpu = <&little3>;
 135                                 };
 136                         };
 137                 };
 138         };
 139
 140         psci {
 141                 compatible = "arm,psci-0.2";
 142                 method = "smc";
 143         };
 144
 145         gic: interrupt-controller@ffb70000 {
 146                 compatible = "arm,cortex-a15-gic";
 147                 #interrupt-cells = <3>;
 148                 #address-cells = <0>;
 149                 interrupt-controller;
 150                 reg = <0x0 0xffb71000 0 0x1000>,
 151                       <0x0 0xffb72000 0 0x1000>;
 152         };
 153
 154         pmu: syscon@ff730000 {
 155                 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
 156                 reg = <0x0 0xff730000 0x0 0x1000>;
 157         };
 158
 159         pmugrf: syscon@ff738000 {
 160                 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
 161                 reg = <0x0 0xff738000 0x0 0x1000>;
 162         };
 163
 164         sgrf: syscon@ff740000 {
 165                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 166                 reg = <0x0 0xff740000 0x0 0x1000>;
 167
 168         };
 169
 170         cru: syscon@ff760000 {
 171                 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
 172                 reg = <0x0 0xff760000 0x0 0x1000>;
 173         };
 174
 175         grf: syscon@ff770000 {
 176                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 177                 reg = <0x0 0xff770000 0x0 0x1000>;
 178         };
 179
 180         arm-pmu {
 181                 compatible = "arm,armv8-pmuv3";
 182                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 183                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 184                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 190         };
 191
 192         cpu_axi_bus: cpu_axi_bus {
 193                 compatible = "rockchip,cpu_axi_bus";
 194                 #address-cells = <2>;
 195                 #size-cells = <2>;
 196                 ranges;
 197
 198                 qos {
 199                         #address-cells = <2>;
 200                         #size-cells = <2>;
 201                         ranges;
 202
 203                         dmac {
 204                                 reg = <0x0 0xffa80000 0x0 0x20>;
 205                         };
 206                         crypto {
 207                                 reg = <0x0 0xffa80080 0x0 0x20>;
 208                         };
 209                         tsp {
 210                                 reg = <0x0 0xffa80280 0x0 0x20>;
 211                         };
 212                         bus_cpup {
 213                                 reg = <0x0 0xffa90000 0x0 0x20>;
 214                         };
 215                         cci_r {
 216                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 217                         };
 218                         cci_w {
 219                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 220                         };
 221                         peri {
 222                                 reg = <0x0 0xffab0000 0x0 0x20>;
 223                                 rockchip,priority = <2 2>;
 224                         };
 225                         iep {
 226                                 reg = <0x0 0xffad0000 0x0 0x20>;
 227                         };
 228                         isp_r0 {
 229                                 reg = <0x0 0xffad0080 0x0 0x20>;
 230                         };
 231                         isp_r1 {
 232                                 reg = <0x0 0xffad0100 0x0 0x20>;
 233                         };
 234                         isp_w0 {
 235                                 reg = <0x0 0xffad0180 0x0 0x20>;
 236                                 rockchip,priority = <2 2>;
 237                         };
 238                         isp_w1 {
 239                                 reg = <0x0 0xffad0200 0x0 0x20>;
 240                                 rockchip,priority = <2 2>;
 241                         };
 242                         vip {
 243                                 reg = <0x0 0xffad0280 0x0 0x20>;
 244                         };
 245                         vop {
 246                                 reg = <0x0 0xffad0300 0x0 0x20>;
 247                                 rockchip,priority = <2 2>;
 248                         };
 249                         rga_r {
 250                                 reg = <0x0 0xffad0380 0x0 0x20>;
 251                         };
 252                         rga_w {
 253                                 reg = <0x0 0xffad0400 0x0 0x20>;
 254                         };
 255                         hevc_r {
 256                                 reg = <0x0 0xffae0000 0x0 0x20>;
 257                         };
 258                         vpu_r {
 259                                 reg = <0x0 0xffae0100 0x0 0x20>;
 260                         };
 261                         vpu_w {
 262                                 reg = <0x0 0xffae0180 0x0 0x20>;
 263                         };
 264                         gpu {
 265                                 reg = <0x0 0xffaf0000 0x0 0x20>;
 266                         };
 267                 };
 268
 269                 msch {
 270                         #address-cells = <2>;
 271                         #size-cells = <2>;
 272                         ranges;
 273
 274                         msch {
 275                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 276                                 rockchip,read-latency = <0x34>;
 277                         };
 278                 };
 279         };
 280
 281         timer {
 282                 compatible = "arm,armv8-timer";
 283                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 284                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 285                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 286                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 287                 clock-frequency = <24000000>;
 288         };
 289
 290         timer@ff810000 {
 291                 compatible = "rockchip,timer";
 292                 reg = <0x0 0xff810000 0x0 0x20>;
 293                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 294                 rockchip,broadcast = <1>;
 295         };
 296
 297         sram: sram@ff8c0000 {
 298                 compatible = "mmio-sram";
 299                 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
 300                 map-exec;
 301         };
 302
 303         watchdog: wdt@ff800000 {
 304                 compatible = "rockchip,watch dog";
 305                 reg = <0x0 0xff800000 0x0 0x100>;
 306                 clocks = <&pclk_alive_pre>;
 307                 clock-names = "pclk_wdt";
 308                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 309                 rockchip,irq = <1>;
 310                 rockchip,timeout = <60>;
 311                 rockchip,atboot = <1>;
 312                 rockchip,debug = <0>;
 313                 status = "disabled";
 314         };
 315
 316         amba {
 317                 #address-cells = <2>;
 318                 #size-cells = <2>;
 319                 compatible = "arm,amba-bus";
 320                 interrupt-parent = <&gic>;
 321                 ranges;
 322
 323                 pdma0: pdma@ff600000 {
 324                         compatible = "arm,pl330", "arm,primecell";
 325                         reg = <0x0 0xff600000 0x0 0x4000>;
 326                         clocks = <&clk_gates12 11>;
 327                         clock-names = "apb_pclk";
 328                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 329                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 330                         #dma-cells = <1>;
 331
 332                 };
 333
 334                 pdma1: pdma@ff250000 {
 335                         compatible = "arm,pl330", "arm,primecell";
 336                         reg = <0x0 0xff250000 0x0 0x4000>;
 337                         clocks = <&clk_gates19 3>;
 338                         clock-names = "apb_pclk";
 339                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 340                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 341                         #dma-cells = <1>;
 342                 };
 343         };
 344
 345         reset: reset@ff760300{
 346                 compatible = "rockchip,reset";
 347                 reg = <0x0 0xff760300 0x0 0x38>;
 348                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 349                 #reset-cells = <1>;
 350         };
 351
 352         nandc0: nandc@ff400000 {
 353                 compatible = "rockchip,rk-nandc";
 354                 reg = <0x0 0xff400000 0x0 0x4000>;
 355                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 356                 nandc_id = <0>;
 357                 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
 358                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 359         };
 360
 361         nandc0reg: nandc0@ff400000 {
 362                 compatible = "rockchip,rk-nandc";
 363                 reg = <0x0 0xff400000 0x0 0x4000>;
 364         };
 365
 366         emmc: rksdmmc@ff0f0000 {
 367                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 368                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 369                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 370                 #address-cells = <1>;
 371                 #size-cells = <0>;
 372                 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
 373                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 374                 rockchip,grf = <&grf>;
 375                 num-slots = <1>;
 376                 fifo-depth = <0x100>;
 377                 bus-width = <8>;
 378         };
 379
 380         sdmmc: rksdmmc@ff0c0000 {
 381                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 382                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 383                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 pinctrl-names = "default", "idle", "udbg";
 387                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 388                 pinctrl-1 = <&sdmmc_gpio>;
 389                 pinctrl-2 = <&uart2_xfer &cpu_jtag &sdmmc_dectn>;
 390                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 391                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
 392                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 393                 rockchip,grf = <&grf>;
 394                 num-slots = <1>;
 395                 fifo-depth = <0x100>;
 396                 bus-width = <4>;
 397         };
 398
 399         sdio: rksdmmc@ff0d0000 {
 400                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 401                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 402                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 pinctrl-names = "default","idle";
 406                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 407                 pinctrl-1 = <&sdio0_gpio>;
 408                 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
 409                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 410                 rockchip,grf = <&grf>;
 411                 num-slots = <1>;
 412                 fifo-depth = <0x100>;
 413                 bus-width = <4>;
 414         };
 415
 416         spi0: spi@ff110000 {
 417                 compatible = "rockchip,rockchip-spi";
 418                 reg = <0x0 0xff110000 0x0 0x1000>;
 419                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422                 pinctrl-names = "default";
 423                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 424                 rockchip,spi-src-clk = <0>;
 425                 num-cs = <2>;
 426                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 427                 clock-names = "spi", "pclk_spi0";
 428                 //dmas = <&pdma1 11>, <&pdma1 12>;
 429                 //#dma-cells = <2>;
 430                 //dma-names = "tx", "rx";
 431                 status = "disabled";
 432         };
 433
 434         spi1: spi@ff120000 {
 435                 compatible = "rockchip,rockchip-spi";
 436                 reg = <0x0 0xff120000 0x0 0x1000>;
 437                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 pinctrl-names = "default";
 441                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
 442                 rockchip,spi-src-clk = <1>;
 443                 num-cs = <2>;
 444                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 445                 clock-names = "spi", "pclk_spi1";
 446                 //dmas = <&pdma1 13>, <&pdma1 14>;
 447                 //#dma-cells = <2>;
 448                 //dma-names = "tx", "rx";
 449                 status = "disabled";
 450         };
 451
 452         spi2: spi@ff130000 {
 453                 compatible = "rockchip,rockchip-spi";
 454                 reg = <0x0 0xff130000 0x0 0x1000>;
 455                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 456                 #address-cells = <1>;
 457                 #size-cells = <0>;
 458                 pinctrl-names = "default";
 459                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 460                 rockchip,spi-src-clk = <2>;
 461                 num-cs = <1>;
 462                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 463                 clock-names = "spi", "pclk_spi2";
 464                 //dmas = <&pdma1 15>, <&pdma1 16>;
 465                 //#dma-cells = <2>;
 466                 //dma-names = "tx", "rx";
 467                 status = "disabled";
 468         };
 469
 470         uart_bt: serial@ff180000 {
 471                 compatible = "rockchip,serial";
 472                 reg = <0x0 0xff180000 0x0 0x100>;
 473                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 474                 clock-frequency = <24000000>;
 475                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 476                 clock-names = "sclk_uart", "pclk_uart";
 477                 reg-shift = <2>;
 478                 reg-io-width = <4>;
 479                 //dmas = <&pdma1 1>, <&pdma1 2>;
 480                 //#dma-cells = <2>;
 481                 pinctrl-names = "default";
 482                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 483                 status = "disabled";
 484         };
 485
 486         uart_bb: serial@ff190000 {
 487                 compatible = "rockchip,serial";
 488                 reg = <0x0 0xff190000 0x0 0x100>;
 489                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 490                 clock-frequency = <24000000>;
 491                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 492                 clock-names = "sclk_uart", "pclk_uart";
 493                 reg-shift = <2>;
 494                 reg-io-width = <4>;
 495                 //dmas = <&pdma1 3>, <&pdma1 4>;
 496                 //#dma-cells = <2>;
 497                 pinctrl-names = "default";
 498                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 499                 status = "disabled";
 500         };
 501
 502         uart_dbg: serial@ff690000 {
 503                 compatible = "rockchip,serial";
 504                 reg = <0x0 0xff690000 0x0 0x100>;
 505                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 506                 clock-frequency = <24000000>;
 507                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 508                 clock-names = "sclk_uart", "pclk_uart";
 509                 reg-shift = <2>;
 510                 reg-io-width = <4>;
 511                 //dmas = <&pdma0 4>, <&pdma0 5>;
 512                 //#dma-cells = <2>;
 513                 //pinctrl-names = "default";
 514                 //pinctrl-0 = <&uart2_xfer>;
 515                 status = "disabled";
 516         };
 517
 518         uart_gps: serial@ff1b0000 {
 519                 compatible = "rockchip,serial";
 520                 reg = <0x0 0xff1b0000 0x0 0x100>;
 521                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 522                 clock-frequency = <24000000>;
 523                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 524                 clock-names = "sclk_uart", "pclk_uart";
 525                 current-speed = <115200>;
 526                 reg-shift = <2>;
 527                 reg-io-width = <4>;
 528                 //dmas = <&pdma1 7>, <&pdma1 8>;
 529                 //#dma-cells = <2>;
 530                 pinctrl-names = "default";
 531                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 532                 status = "disabled";
 533         };
 534
 535         uart_exp: serial@ff1c0000 {
 536                 compatible = "rockchip,serial";
 537                 reg = <0x0 0xff1c0000 0x0 0x100>;
 538                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 539                 clock-frequency = <24000000>;
 540                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 541                 clock-names = "sclk_uart", "pclk_uart";
 542                 reg-shift = <2>;
 543                 reg-io-width = <4>;
 544                 //dmas = <&pdma1 9>, <&pdma1 10>;
 545                 //#dma-cells = <2>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 548                 status = "disabled";
 549         };
 550
 551         rockchip_clocks_init: clocks-init{
 552                 compatible = "rockchip,clocks-init";
 553                 rockchip,clocks-init-parent =
 554                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 555                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 556                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 557                         <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
 558                 rockchip,clocks-init-rate =
 559                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 560                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 561                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 562                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 563                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 564                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 565                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 566                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 567                         <&aclk_cci 600000000>,          <&clk_mac 125000000>,
 568                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 569                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 570                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 571                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 572                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 573                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 574                         <&clk_hevc_cabac 300000000>;
 575 /*
 576                 rockchip,clocks-uboot-has-init =
 577                         <&aclk_vio0>;
 578 */
 579         };
 580
 581         rockchip_clocks_enable: clocks-enable {
 582                 compatible = "rockchip,clocks-enable";
 583                 clocks =
 584                 <&pd_vio>,
 585                <&pd_video>,
 586                <&pd_gpu_0>,
 587                <&pd_gpu_1>,
 588
 589                         /*PLL*/
 590                         <&clk_apllb>,
 591                         <&clk_aplll>,
 592                         <&clk_dpll>,
 593                         <&clk_gpll>,
 594                         <&clk_cpll>,
 595
 596                         /*PD_CORE*/
 597                         <&clk_cs>,
 598                         <&clkin_trace>,
 599                         <&aclk_cci>,
 600
 601                         /*PD_BUS*/
 602                         <&aclk_bus>,
 603                         <&hclk_bus>,
 604                         <&pclk_bus>,
 605                         <&clk_gates12 12>,/*aclk_strc_sys*/
 606                         <&clk_gates12 6>,/*aclk_intmem1*/
 607                         <&clk_gates12 5>,/*aclk_intmem0*/
 608                         <&clk_gates12 4>,/*aclk_intmem*/
 609                         <&clk_gates13 9>,/*aclk_gic400*/
 610                         <&clk_gates12 9>,/*hclk_rom*/
 611
 612                         /*PD_ALIVE*/
 613                         <&clk_gates22 13>,/*pclk_timer1*/
 614                         <&clk_gates22 12>,/*pclk_timer0*/
 615                         <&clk_gates22 9>,/*pclk_alive_niu*/
 616                         <&clk_gates22 8>,/*pclk_grf*/
 617
 618                         /*PD_PMU*/
 619                         <&clk_gates23 5>,/*pclk_pmugrf*/
 620                         <&clk_gates23 3>,/*pclk_sgrf*/
 621                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 622                         <&clk_gates23 1>,/*pclk_intmem1*/
 623                         <&clk_gates23 0>,/*pclk_pmu*/
 624
 625                         /*PD_PERI*/
 626                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 627                         <&clk_gates20 8>,/*aclk_peri_niu*/
 628                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 629                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 630                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 631                         <&clk_gates19 1>,/*pclk_peri_axi_matrix*/
 632
 633                         <&fclk_mcu>,
 634                         <&stclk_mcu>,
 635                         <&clk_gates7 0>;/*clk_jtag*/
 636         };
 637
 638         /* I2C_PMU */
 639         i2c0: i2c@ff650000 {
 640                 compatible = "rockchip,rk30-i2c";
 641                 reg = <0x0 0xff650000 0x0 0x1000>;
 642                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 643                 #address-cells = <1>;
 644                 #size-cells = <0>;
 645                 pinctrl-names = "default", "gpio";
 646                 pinctrl-0 = <&i2c0_xfer>;
 647                 pinctrl-1 = <&i2c0_gpio>;
 648                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 649                 clocks = <&clk_gates12 2>;
 650                 rockchip,check-idle = <1>;
 651                 status = "disabled";
 652         };
 653
 654         /* I2C_AUDIO */
 655         i2c1: i2c@ff660000 {
 656                 compatible = "rockchip,rk30-i2c";
 657                 reg = <0x0 0xff660000 0x0 0x1000>;
 658                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 659                 #address-cells = <1>;
 660                 #size-cells = <0>;
 661                 pinctrl-names = "default", "gpio";
 662                 pinctrl-0 = <&i2c1_xfer>;
 663                 pinctrl-1 = <&i2c1_gpio>;
 664                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 665                 clocks = <&clk_gates12 3>;
 666                 rockchip,check-idle = <1>;
 667                 status = "disabled";
 668         };
 669
 670         /* I2C_SENSOR */
 671         i2c2: i2c@ff140000 {
 672                 compatible = "rockchip,rk30-i2c";
 673                 reg = <0x0 0xff140000 0x0 0x1000>;
 674                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 675                 #address-cells = <1>;
 676                 #size-cells = <0>;
 677                 pinctrl-names = "default", "gpio";
 678                 pinctrl-0 = <&i2c2_xfer>;
 679                 pinctrl-1 = <&i2c2_gpio>;
 680                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 681                 clocks = <&clk_gates19 11>;
 682                 rockchip,check-idle = <1>;
 683                 status = "disabled";
 684         };
 685
 686         /* I2C_CAM */
 687         i2c3: i2c@ff150000 {
 688                 compatible = "rockchip,rk30-i2c";
 689                 reg = <0x0 0xff150000 0x0 0x1000>;
 690                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 691                 #address-cells = <1>;
 692                 #size-cells = <0>;
 693                 pinctrl-names = "default", "gpio";
 694                 pinctrl-0 = <&i2c3_xfer>;
 695                 pinctrl-1 = <&i2c3_gpio>;
 696                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 697                 clocks = <&clk_gates19 12>;
 698                 rockchip,check-idle = <1>;
 699                 status = "disabled";
 700         };
 701
 702         /* I2C_TP */
 703         i2c4: i2c@ff160000 {
 704                 compatible = "rockchip,rk30-i2c";
 705                 reg = <0x0 0xff160000 0x0 0x1000>;
 706                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 707                 #address-cells = <1>;
 708                 #size-cells = <0>;
 709                 pinctrl-names = "default", "gpio";
 710                 pinctrl-0 = <&i2c4_xfer>;
 711                 pinctrl-1 = <&i2c4_gpio>;
 712                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 713                 clocks = <&clk_gates19 13>;
 714                 rockchip,check-idle = <1>;
 715                 status = "disabled";
 716         };
 717
 718         /* I2C_HDMI */
 719         i2c5: i2c@ff170000 {
 720                 compatible = "rockchip,rk30-i2c";
 721                 reg = <0x0 0xff170000 0x0 0x1000>;
 722                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 723                 #address-cells = <1>;
 724                 #size-cells = <0>;
 725                 pinctrl-names = "default", "gpio";
 726                 pinctrl-0 = <&i2c5_xfer>;
 727                 pinctrl-1 = <&i2c5_gpio>;
 728                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 729                 clocks = <&clk_gates19 14>;
 730                 rockchip,check-idle = <1>;
 731                 status = "disabled";
 732         };
 733
 734         fb: fb {
 735                 compatible = "rockchip,rk-fb";
 736                 rockchip,disp-mode = <NO_DUAL>;
 737         };
 738
 739
 740         rk_screen: rk_screen {
 741                 compatible = "rockchip,screen";
 742         };
 743
 744         dsihost0: mipi@ff960000{
 745                 compatible = "rockchip,rk3368-dsi";
 746                 rockchip,prop = <0>;
 747                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 748                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 749                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 750                 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>;
 751                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 752                 status = "okay";
 753         };
 754
 755         lvds: lvds@ff968000 {
 756                 compatible = "rockchip,rk3368-lvds";
 757                 rockchip,grf = <&grf>;
 758                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 759                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 760                 clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
 761                 clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
 762                 status = "disabled";
 763         };
 764
 765         edp: edp@ff970000 {
 766                 compatible = "rockchip,rk32-edp";
 767                 reg = <0x0 0xff970000 0x0 0x4000>;
 768                 rockchip,grf = <&grf>;
 769                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 770                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 771                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 772                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 773                 reset-names = "edp_24m", "edp_apb";
 774         };
 775
 776         hdmi: hdmi@ff980000 {
 777                 compatible = "rockchip,rk3368-hdmi";
 778                 reg = <0x0 0xff980000 0x0 0x20000>;
 779                 rockchip,grf = <&grf>;
 780                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 781                 pinctrl-names = "default", "gpio";
 782                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 783                 pinctrl-1 = <&i2c5_gpio>;
 784                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 785                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 786                 status = "disabled";
 787         };
 788
 789         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 790                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 791                 reg = <0x0 0xff978000 0x0 0x2000>;
 792                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 793                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 794                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 795                 status = "disabled";
 796         };
 797
 798         lcdc: lcdc@ff930000 {
 799                  compatible = "rockchip,rk3368-lcdc";
 800                  rockchip,grf = <&grf>;
 801                  rockchip,pmugrf = <&pmugrf>;
 802                  rockchip,prop = <PRMRY>;
 803                  rockchip,pwr18 = <0>;
 804                  rockchip,iommu-enabled = <0>;
 805                  reg = <0x0 0xff930000 0x0 0x10000>;
 806                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 807                 /*pinctrl-names = "default", "gpio";
 808                  *pinctrl-0 = <&lcdc_lcdc>;
 809                  *pinctrl-1 = <&lcdc_gpio>;
 810                  */
 811                  status = "disabled";
 812                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
 813                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
 814         };
 815
 816         adc: adc@ff100000 {
 817                 compatible = "rockchip,saradc";
 818                 reg = <0x0 0xff100000 0x0 0x100>;
 819                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 820                 #io-channel-cells = <1>;
 821                 io-channel-ranges;
 822                 rockchip,adc-vref = <1800>;
 823                 clock-frequency = <1000000>;
 824                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 825                 clock-names = "saradc", "pclk_saradc";
 826                 status = "disabled";
 827         };
 828
 829         rga@ff920000 {
 830                 compatible = "rockchip,rk3368-rga2";
 831                 reg = <0x0 0xff920000 0x0 0x1000>;
 832                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 833                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 834                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 835         };
 836
 837         i2s0: i2s0@ff898000 {
 838                 compatible = "rockchip-i2s";
 839                 reg = <0x0 0xff898000 0x0 0x1000>;
 840                 i2s-id = <0>;
 841                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 842                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 843                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 844                 dmas = <&pdma0 0>, <&pdma0 1>;
 845                 #dma-cells = <2>;
 846                 dma-names = "tx", "rx";
 847                 pinctrl-names = "default", "sleep";
 848                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 849                 pinctrl-1 = <&i2s_gpio>;
 850         };
 851
 852         i2s1: i2s1@ff890000 {
 853                 compatible = "rockchip-i2s";
 854                 reg = <0x0 0xff890000 0x0 0x1000>;
 855                 i2s-id = <1>;
 856                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 857                 clock-names = "i2s_clk", "i2s_hclk";
 858                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 859                 dmas = <&pdma0 6>, <&pdma0 7>;
 860                 #dma-cells = <2>;
 861                 dma-names = "tx", "rx";
 862         };
 863
 864         spdif: spdif@ff880000 {
 865                 compatible = "rockchip-spdif";
 866                 reg = <0x0 0xff880000 0x0 0x1000>;
 867                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 868                 clock-names = "spdif_mclk", "spdif_hclk";
 869                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 870                 dmas = <&pdma0 3>;
 871                 #dma-cells = <1>;
 872                 dma-names = "tx";
 873                 pinctrl-names = "default";
 874                 pinctrl-0 = <&spdif_tx>;
 875         };
 876
 877         pwm0: pwm@ff680000 {
 878                 compatible = "rockchip,rk-pwm";
 879                 reg = <0x0 0xff680000 0x0 0x10>;
 880                 #pwm-cells = <2>;
 881                 pinctrl-names = "default";
 882                 pinctrl-0 = <&pwm0_pin>;
 883                 clocks = <&clk_gates13 6>;
 884                 clock-names = "pclk_pwm";
 885                 status = "disabled";
 886         };
 887
 888         pwm1: pwm@ff680010 {
 889                 compatible = "rockchip,rk-pwm";
 890                 reg = <0x0 0xff680010 0x0 0x10>;
 891                 #pwm-cells = <2>;
 892                 pinctrl-names = "default";
 893                 pinctrl-0 = <&pwm1_pin>;
 894                 clocks = <&clk_gates13 6>;
 895                 clock-names = "pclk_pwm";
 896                 status = "disabled";
 897         };
 898
 899         pwm2: pwm@ff680020 {
 900                 compatible = "rockchip,rk-pwm";
 901                 reg = <0x0 0xff680020 0x0 0x10>;
 902                 #pwm-cells = <2>;
 903                 //pinctrl-names = "default";
 904                 //pinctrl-0 = <&pwm1_pin>;
 905                 clocks = <&clk_gates13 6>;
 906                 clock-names = "pclk_pwm";
 907                 status = "disabled";
 908         };
 909
 910         pwm3: pwm@ff680030 {
 911                 compatible = "rockchip,rk-pwm";
 912                 reg = <0x0 0xff680030 0x0 0x10>;
 913                 #pwm-cells = <2>;
 914                 pinctrl-names = "default";
 915                 pinctrl-0 = <&pwm3_pin>;
 916                 clocks = <&clk_gates13 6>;
 917                 clock-names = "pclk_pwm";
 918                 status = "disabled";
 919         };
 920
 921         remotectl: pwm@ff680030 {
 922                 compatible = "rockchip,remotectl-pwm";
 923                 reg = <0x0 0xff680030 0x0 0x50>;
 924                 #pwm-cells = <2>;
 925                 pinctrl-names = "default";
 926                 pinctrl-0 = <&pwm3_pin>;
 927                 clocks = <&clk_gates13 6>;
 928                 clock-names = "pclk_pwm";
 929                 dmas = <&pdma0 2>;
 930                 #dma-cells = <2>;
 931                 dma-names = "rx";
 932                 remote_pwm_id = <3>;
 933                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 934                 status = "disabled";
 935         };
 936
 937         voppwm: pwm@ff9301a0 {
 938                 compatible = "rockchip,vop-pwm";
 939                 reg = <0x0 0xff9301a0 0x0 0x10>;
 940                 #pwm-cells = <2>;
 941                 pinctrl-names = "default";
 942                 pinctrl-0 = <&vop_pwm_pin>;
 943                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
 944                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 945                 status = "disabled";
 946         };
 947
 948         pvtm {
 949                 compatible = "rockchip,rk3368-pvtm";
 950                 rockchip,grf = <&grf>;
 951                 rockchip,pmugrf = <&pmugrf>;
 952                 rockchip,pvtm-clk-out = <1>;
 953         };
 954
 955         cpufreq {
 956                 compatible = "rockchip,rk3368-cpufreq";
 957                 rockchip,grf = <&grf>;
 958         };
 959
 960         dvfs {
 961
 962                 vd_arm: vd_arm {
 963                         regulator_name = "vdd_arm";
 964                         suspend_volt = <1000>; //mV
 965                         pd_core {
 966                                 clk_core_b_dvfs_table: clk_core_b {
 967                                         operating-points = <
 968                                                 /* KHz    uV */
 969                                                 312000 1200000
 970                                                 504000 1200000
 971                                                 816000 1200000
 972                                                 1008000 1200000
 973                                                 >;
 974                                         status = "okay";
 975                                         temp-limit-enable = <1>;
 976                                         target-temp = <80>;
 977                                         min_temp_limit = <216>;
 978                                         normal-temp-limit = <
 979                                         /*delta-temp    delta-freq*/
 980                                                 3       96000
 981                                                 6       144000
 982                                                 9       192000
 983                                                 15      384000
 984                                                 >;
 985                                         performance-temp-limit = <
 986                                                 /*temp    freq*/
 987                                                 100     816000
 988                                                 >;
 989                                 };
 990                                 clk_core_l_dvfs_table: clk_core_l {
 991                                         operating-points = <
 992                                                 /* KHz    uV */
 993                                                 312000 1200000
 994                                                 504000 1200000
 995                                                 816000 1200000
 996                                                 1008000 1200000
 997                                                 >;
 998                                         status = "okay";
 999                                         temp-limit-enable = <1>;
1000                                         target-temp = <80>;
1001                                         min_temp_limit = <216>;
1002                                         normal-temp-limit = <
1003                                         /*delta-temp    delta-freq*/
1004                                                 3       96000
1005                                                 6       144000
1006                                                 9       192000
1007                                                 15      384000
1008                                                 >;
1009                                         performance-temp-limit = <
1010                                                 /*temp    freq*/
1011                                                 100     816000
1012                                                 >;
1013                                 };
1014                         };
1015                 };
1016
1017                 vd_logic: vd_logic {
1018                         regulator_name = "vdd_logic";
1019                         suspend_volt = <1000>; //mV
1020                         pd_ddr {
1021                                 clk_ddr_dvfs_table: clk_ddr {
1022                                         operating-points = <
1023                                                 /* KHz    uV */
1024                                                 200000 1200000
1025                                                 300000 1200000
1026                                                 400000 1200000
1027                                                 >;
1028                                         channel = <2>;
1029                                         status = "disabled";
1030                                 };
1031                         };
1032
1033                         pd_gpu {
1034                                 clk_gpu_dvfs_table: clk_gpu {
1035                                         operating-points = <
1036                                                 /* KHz    uV */
1037                                                 200000 1200000
1038                                                 300000 1200000
1039                                                 400000 1200000
1040                                                 >;
1041                                         channel = <1>;
1042                                         status = "okay";
1043                                         regu-mode-table = <
1044                                                 /*freq     mode*/
1045                                                 200000     4
1046                                                 0          3
1047                                         >;
1048                                         regu-mode-en = <0>;
1049                                 };
1050                         };
1051                 };
1052         };
1053
1054         ion {
1055                 compatible = "rockchip,ion";
1056                 #address-cells = <1>;
1057                 #size-cells = <0>;
1058
1059                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1060                         compatible = "rockchip,ion-heap";
1061                         rockchip,ion_heap = <4>;
1062                         reg = <0x00000000 0x08000000>; /* 512MB */
1063                 };
1064                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1065                         compatible = "rockchip,ion-heap";
1066                         rockchip,ion_heap = <0>;
1067                 };
1068         };
1069
1070         vpu: vpu_service {
1071                 compatible = "rockchip,vpu_sub";
1072                 iommu_enabled = <0>;
1073                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1074                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1075                 interrupt-names = "irq_enc", "irq_dec";
1076                 dev_mode = <0>;
1077                 name = "vpu_service";
1078         };
1079
1080         hevc: hevc_service {
1081                 compatible = "rockchip,hevc_sub";
1082                 iommu_enabled = <0>;
1083                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1084                 interrupt-names = "irq_dec";
1085                 dev_mode = <1>;
1086                 name = "hevc_service";
1087         };
1088
1089         vpu_combo: vpu_combo@ff9a0000 {
1090                 compatible = "rockchip,vpu_combo";
1091                 reg = <0x0 0xff9a0000 0x0 0x800>;
1092                 rockchip,grf = <&grf>;
1093                 subcnt = <2>;
1094                 rockchip,sub = <&vpu>, <&hevc>;
1095                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1096                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1097                 mode_bit = <12>;
1098                 mode_ctrl = <0x418>;
1099                 name = "vpu_combo";
1100                 status = "okay";
1101         };
1102
1103         iep: iep@ff900000 {
1104                 compatible = "rockchip,iep";
1105                 iommu_enabled = <0>;
1106                 reg = <0x0 0xff900000 0x0 0x800>;
1107                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1108                 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1109                 clock-names = "aclk_iep", "hclk_iep";
1110                 status = "okay";
1111         };
1112
1113         gmac: eth@ff290000 {
1114                 compatible = "rockchip,rk3368-gmac";
1115                 reg = <0x0 0xff290000 0x0 0x10000>;
1116                 rockchip,grf = <&grf>;
1117                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1118                 interrupt-names = "macirq";
1119
1120                 clocks = <&clk_mac>, <&clk_gates7 4>,
1121                          <&clk_gates7 5>, <&clk_gates7 6>,
1122                          <&clk_gates7 7>, <&clk_gates20 13>,
1123                          <&clk_gates20 14>;
1124                 clock-names = "clk_mac", "mac_clk_rx",
1125                               "mac_clk_tx", "clk_mac_ref",
1126                               "clk_mac_refout", "aclk_mac",
1127                               "pclk_mac";
1128
1129                 phy-mode = "rgmii";
1130                 pinctrl-names = "default";
1131                 pinctrl-0 = <&rgmii_pins>;
1132                 status = "disabled";
1133         };
1134
1135         gpu {
1136                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1137                 reg = <0x0 0xffa30000 0x0 0x10000>;
1138                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1139                 interrupt-names = "GPU";
1140         };
1141
1142         iep_mmu {
1143                 dbgname = "iep";
1144                 compatible = "rockchip,iep_mmu";
1145                 reg = <0x0 0xff900800 0x0 0x100>;
1146                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1147                 interrupt-names = "iep_mmu";
1148         };
1149
1150         vip_mmu {
1151                 dbgname = "vip";
1152                 compatible = "rockchip,vip_mmu";
1153                 reg = <0x0 0xff950800 0x0 0x100>;
1154                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1155                 interrupt-names = "vip_mmu";
1156         };
1157
1158         vop_mmu {
1159                 dbgname = "vop";
1160                 compatible = "rockchip,vopb_mmu";
1161                 reg = <0x0 0xff930300 0x0 0x100>;
1162                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1163                 interrupt-names = "vop_mmu";
1164         };
1165
1166         isp_mmu {
1167                 dbgname = "isp_mmu";
1168                 compatible = "rockchip,isp_mmu";
1169                 reg = <0x0 0xff914000 0x0 0x100>,
1170                 <0x0 0xff915000 0x0 0x100>;
1171                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1172                 interrupt-names = "isp_mmu";
1173         };
1174
1175         hdcp_mmu {
1176                 dbgname = "hdcp_mmu";
1177                 compatible = "rockchip,hdcp_mmu";
1178                 reg = <0x0 0xff940000 0x0 0x100>;
1179                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1180                 interrupt-names = "hdcp_mmu";
1181         };
1182
1183         hevc_mmu {
1184                 dbgname = "hevc";
1185                 compatible = "rockchip,hevc_mmu";
1186                 reg = <0x0 0xff9c0440 0x0 0x40>,                      /*need to fix*/
1187                           <0x0 0xff9c0480 0x0 0x40>;
1188                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1189                 interrupt-names = "hevc_mmu";
1190         };
1191
1192         vpu_mmu {
1193                 dbgname = "vpu";
1194                 compatible = "rockchip,vpu_mmu";
1195                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1196                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;       /*need to fix*/
1197                 interrupt-names = "vpu_mmu";
1198         };
1199
1200         rockchip_suspend {
1201                 rockchip,ctrbits = <
1202                         (0
1203                          |RKPM_CTR_PWR_DMNS
1204                          |RKPM_CTR_GTCLKS
1205                          |RKPM_CTR_PLLS
1206                          |RKPM_CTR_GPIOS
1207                         /*
1208                          |RKPM_CTR_SYSCLK_DIV
1209                          |RKPM_CTR_IDLEAUTO_MD
1210                          |RKPM_CTR_ARMOFF_LPMD
1211                         */
1212                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1213                         )
1214                         >;
1215                 rockchip,pmic-suspend_gpios = <
1216                                  /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1217                         >;
1218                 rockchip,pmic-resume_gpios = <
1219                                 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1220                         >;
1221         };
1222
1223         isp: isp@ff910000{
1224                 compatible = "rockchip,isp";
1225                 reg = <0x0 0xff910000 0x0 0x10000>;
1226                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1227                 clocks = <&clk_gates16 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>, <&pd_isp>;
1228                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "pd_isp";
1229                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1230                 pinctrl-0 = <&cif_clkout>;
1231                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1232                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1233                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1234                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1235                 pinctrl-5 = <&cif_clkout>;
1236                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1237                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1238                 pinctrl-8 = <&isp_flash_trigger>;
1239                 rockchip,isp,mipiphy = <2>;
1240                 rockchip,isp,cifphy = <1>;
1241                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1242                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1243                 rockchip,grf = <&grf>;
1244                 rockchip,cru = <&cru>;
1245                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1246                 rockchip,isp,iommu_enable = <0>;
1247                 status = "okay";
1248         };
1249
1250         cif: cif@ff950000 {
1251                 compatible = "rockchip,cif";
1252                 reg = <0x0 0xff950000 0x0 0x10000>;
1253                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1254                 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1255                 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1256                 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1257                 pinctrl-names = "cif_pin_all";
1258                 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1259                 rockchip,grf = <&grf>;
1260                 rockchip,cru = <&cru>;
1261                 status = "okay";
1262         };
1263
1264 /*
1265         thermal-zones {
1266                 #include "rk3368-thermal.dtsi"
1267         };
1268 */
1269
1270         tsadc: tsadc@ff280000 {
1271                 compatible = "rockchip,rk3368-tsadc";
1272                 reg = <0x0 0xff280000 0x0 0x100>;
1273                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1274                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1275                 rockchip,grf = <&grf>;
1276                 rockchip,cru = <&cru>;
1277                 rockchip,pmu = <&pmu>;
1278                 clock-names = "tsadc", "apb_pclk";
1279                 clock-frequency = <32000>;
1280                 resets = <&reset RK3368_SRST_TSADC_P>;
1281                 reset-names = "tsadc-apb";
1282                 //pinctrl-names = "default";
1283                 //pinctrl-0 = <&tsadc_int>;
1284                 #thermal-sensor-cells = <1>;
1285                 hw-shut-temp = <120000>;
1286                 status = "disabled";
1287         };
1288
1289         tsp: tsp@FF8B0000 {
1290                 compatible = "rockchip,rk3368-tsp";
1291                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1292                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1293                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1294                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1295                 interrupt-names = "irq_tsp";
1296                 // pinctrl-names = "default";
1297                 // pinctrl-0 = <&isp_hsadc>;
1298                 status = "okay";
1299         };
1300
1301         crypto: crypto@FF8A0000{
1302                 compatible = "rockchip,rk3368-crypto";
1303                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1304                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1305                 interrupt-names = "irq_crypto";
1306                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1307                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1308                 status = "okay";
1309         };
1310
1311         dwc_control_usb: dwc-control-usb {
1312                 compatible = "rockchip,rk3368-dwc-control-usb";
1313                 rockchip,grf = <&grf>;
1314                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1315                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1316                 interrupt-names = "otg_id", "otg_bvalid",
1317                                   "otg_linestate", "host0_linestate";
1318                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1319                 clock-names = "hclk_usb_peri", "usbphy_480m";
1320                 //resets = <&reset RK3128_RST_USBPOR>;
1321                 //reset-names = "usbphy_por";
1322                 usb_bc{
1323                         compatible = "inno,phy";
1324                         regbase = &dwc_control_usb;
1325                         rk_usb,bvalid     = <0x4bc 23 1>;
1326                         rk_usb,iddig      = <0x4bc 26 1>;
1327                         rk_usb,vdmsrcen   = <0x718 12 1>;
1328                         rk_usb,vdpsrcen   = <0x718 11 1>;
1329                         rk_usb,rdmpden    = <0x718 10 1>;
1330                         rk_usb,idpsrcen   = <0x718  9 1>;
1331                         rk_usb,idmsinken  = <0x718  8 1>;
1332                         rk_usb,idpsinken  = <0x718  7 1>;
1333                         rk_usb,dpattach   = <0x4b8 31 1>;
1334                         rk_usb,cpdet      = <0x4b8 30 1>;
1335                         rk_usb,dcpattach  = <0x4b8 29 1>;
1336                 };
1337         };
1338
1339         usb0: usb@ff580000 {
1340                 compatible = "rockchip,rk3368_usb20_otg";
1341                 reg = <0x0 0xff580000 0x0 0x40000>;
1342                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1343                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1344                 clock-names = "clk_usbphy0", "hclk_otg";
1345                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1346                                 <&reset RK3368_SRST_USBOTGC0>;
1347                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1348                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1349                 rockchip,usb-mode = <0>;
1350         };
1351
1352         usb_ehci: usb@ff500000 {
1353                 compatible = "generic-ehci";
1354                 reg = <0x0 0xff500000 0x0 0x20000>;
1355                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1356                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1357                 clock-names = "clk_usbphy0", "hclk_ehci";
1358                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1359                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1360                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1361         };
1362
1363         usb_ohci: usb@ff520000 {
1364                 compatible = "generic-ohci";
1365                 reg = <0x0 0xff520000 0x0 0x20000>;
1366                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1367                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1368                 clock-names =  "clk_usbphy0", "hclk_ohci";
1369         };
1370
1371         usb_hsic: usb@ff5c0000 {
1372                 compatible = "rockchip,rk3288_rk_hsic_host";
1373                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1374                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1375 /*
1376                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1377                          <&hsicphy_12m>, <&usbphy_480m>,
1378                          <&otgphy1_480m>, <&otgphy2_480m>;
1379                 clock-names = "hsicphy_480m", "hclk_hsic",
1380                               "hsicphy_12m", "usbphy_480m",
1381                               "hsic_usbphy1", "hsic_usbphy2";
1382                 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1383                                 <&reset RK3288_SOFT_RST_HSICPHY>;
1384                 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1385 */
1386                 status = "disabled";
1387         };
1388
1389         pinctrl: pinctrl {
1390                 compatible = "rockchip,rk3368-pinctrl";
1391                 rockchip,grf = <&grf>;
1392                 rockchip,pmugrf = <&pmugrf>;
1393                 #address-cells = <2>;
1394                 #size-cells = <2>;
1395                 ranges;
1396
1397                 gpio0: gpio0@ff750000 {
1398                         compatible = "rockchip,gpio-bank";
1399                         reg =   <0x0 0xff750000 0x0 0x100>;
1400                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1401                         clocks = <&clk_gates23 4>;
1402
1403                         gpio-controller;
1404                         #gpio-cells = <2>;
1405
1406                         interrupt-controller;
1407                         #interrupt-cells = <2>;
1408                 };
1409
1410                 gpio1: gpio1@ff780000 {
1411                         compatible = "rockchip,gpio-bank";
1412                         reg = <0x0 0xff780000 0x0 0x100>;
1413                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1414                         clocks = <&clk_gates22 1>;
1415
1416                         gpio-controller;
1417                         #gpio-cells = <2>;
1418
1419                         interrupt-controller;
1420                         #interrupt-cells = <2>;
1421                 };
1422
1423                 gpio2: gpio2@ff790000 {
1424                         compatible = "rockchip,gpio-bank";
1425                         reg = <0x0 0xff790000 0x0 0x100>;
1426                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1427                         clocks = <&clk_gates22 2>;
1428
1429                         gpio-controller;
1430                         #gpio-cells = <2>;
1431
1432                         interrupt-controller;
1433                         #interrupt-cells = <2>;
1434                 };
1435
1436                 gpio3: gpio3@ff7a0000 {
1437                         compatible = "rockchip,gpio-bank";
1438                         reg = <0x0 0xff7a0000 0x0 0x100>;
1439                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1440                         clocks = <&clk_gates22 3>;
1441
1442                         gpio-controller;
1443                         #gpio-cells = <2>;
1444
1445                         interrupt-controller;
1446                         #interrupt-cells = <2>;
1447                 };
1448
1449                 pcfg_pull_up: pcfg-pull-up {
1450                         bias-pull-up;
1451                 };
1452
1453                 pcfg_pull_down: pcfg-pull-down {
1454                         bias-pull-down;
1455                 };
1456
1457                 pcfg_pull_none: pcfg-pull-none {
1458                         bias-disable;
1459                 };
1460
1461                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1462                         drive-strength = <8>;
1463                 };
1464
1465                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1466                         drive-strength = <12>;
1467                 };
1468
1469                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1470                         bias-pull-up;
1471                         drive-strength = <8>;
1472                 };
1473
1474                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1475                         drive-strength = <4>;
1476                 };
1477
1478                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1479                         bias-pull-up;
1480                         drive-strength = <4>;
1481                 };
1482
1483                 pcfg_output_high: pcfg-output-high {
1484                         output-high;
1485                 };
1486
1487                 pcfg_output_low: pcfg-output-low {
1488                         output-low;
1489                 };
1490
1491                 i2c0 {
1492                         i2c0_xfer: i2c0-xfer {
1493                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1494                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1495                         };
1496                         i2c0_gpio: i2c0-gpio {
1497                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1498                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1499                         };
1500                 };
1501
1502                 i2c1 {
1503                         i2c1_xfer: i2c1-xfer {
1504                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1505                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1506                         };
1507                         i2c1_gpio: i2c1-gpio {
1508                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1509                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1510                         };
1511                 };
1512
1513                 i2c2 {
1514                         i2c2_xfer: i2c2-xfer {
1515                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1516                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1517                         };
1518                         i2c2_gpio: i2c2-gpio {
1519                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1520                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1521             };
1522                 };
1523
1524                 i2c3 {
1525                         i2c3_xfer: i2c3-xfer {
1526                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1527                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1528                         };
1529                         i2c3_gpio: i2c3-gpio {
1530                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1531                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1532                         };
1533                 };
1534
1535                 i2c4 {
1536                         i2c4_xfer: i2c4-xfer {
1537                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1538                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1539                         };
1540                         i2c4_gpio: i2c4-gpio {
1541                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1542                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1543                         };
1544                 };
1545
1546                 i2c5 {
1547                         i2c5_xfer: i2c5-xfer {
1548                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1549                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1550                         };
1551                         i2c5_gpio: i2c5-gpio {
1552                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1553                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1554                         };
1555                 };
1556
1557                 uart0 {
1558                         uart0_xfer: uart0-xfer {
1559                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1560                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1561                         };
1562
1563                         uart0_cts: uart0-cts {
1564                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1565                         };
1566
1567                         uart0_rts: uart0-rts {
1568                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1569                         };
1570
1571                         uart0_rts_gpio: uart0-rts-gpio {
1572                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1573                         };
1574                 };
1575
1576                 uart1 {
1577                         uart1_xfer: uart1-xfer {
1578                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1579                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1580                         };
1581
1582                         uart1_cts: uart1-cts {
1583                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1584                         };
1585
1586                         uart1_rts: uart1-rts {
1587                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1588                         };
1589                 };
1590
1591                 uart2 {
1592                         uart2_xfer: uart2-xfer {
1593                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1594                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1595                         };
1596                 };
1597
1598                 uart3 {
1599                         uart3_xfer: uart3-xfer {
1600                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1601                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1602                         };
1603
1604                         uart3_cts: uart3-cts {
1605                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1606                         };
1607
1608                         uart3_rts: uart3-rts {
1609                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1610                         };
1611                 };
1612
1613                 uart4 {
1614                         uart4_xfer: uart4-xfer {
1615                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1616                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1617                         };
1618
1619                         uart4_cts: uart4-cts {
1620                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1621                         };
1622
1623                         uart4_rts: uart4-rts {
1624                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1625                         };
1626                 };
1627
1628                 spi0 {
1629                         spi0_clk: spi0-clk {
1630                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1631                         };
1632                         spi0_cs0: spi0-cs0 {
1633                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1634                         };
1635                         spi0_tx: spi0-tx {
1636                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1637                         };
1638                         spi0_rx: spi0-rx {
1639                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1640                         };
1641                         spi0_cs1: spi0-cs1 {
1642                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1643                         };
1644                 };
1645
1646                 spi1 {
1647                         spi1_clk: spi1-clk {
1648                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1649                         };
1650                         spi1_cs0: spi1-cs0 {
1651                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1652                         };
1653                         spi1_rx: spi1-rx {
1654                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1655                         };
1656                         spi1_tx: spi1-tx {
1657                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1658                         };
1659                         spi1_cs1: spi1-cs1 {
1660                                 rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
1661                         };
1662                 };
1663
1664                 spi2 {
1665                         spi2_clk: spi2-clk {
1666                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1667                         };
1668                         spi2_cs0: spi2-cs0 {
1669                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1670                         };
1671                         spi2_rx: spi2-rx {
1672                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1673                         };
1674                         spi2_tx: spi2-tx {
1675                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1676                         };
1677                 };
1678
1679                 i2s {
1680                         i2s_mclk: i2s-mclk {
1681                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1682                         };
1683
1684                         i2s_sclk:i2s-sclk {
1685                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1686                         };
1687
1688                         i2s_lrckrx:i2s-lrckrx {
1689                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1690                         };
1691
1692                         i2s_lrcktx:i2s-lrcktx {
1693                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1694                         };
1695
1696                         i2s_sdi:i2s-sdi {
1697                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1698                         };
1699
1700                         i2s_sdo0:i2s-sdo0 {
1701                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1702                         };
1703
1704                         i2s_sdo1:i2s-sdo1 {
1705                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1706                         };
1707
1708                         i2s_sdo2:i2s-sdo2 {
1709                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1710                         };
1711
1712                         i2s_sdo3:i2s-sdo3 {
1713                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1714                         };
1715
1716                         i2s_gpio: i2s-gpio {
1717                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1718                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1719                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1720                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1721                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1722                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1723                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1724                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1725                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1726                         };
1727                 };
1728
1729                 spdif {
1730                         spdif_tx: spdif-tx {
1731                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1732                         };
1733                 };
1734
1735                 sdmmc {
1736                         sdmmc_clk: sdmmc-clk {
1737                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1738                         };
1739
1740                         sdmmc_cmd: sdmmc-cmd {
1741                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1742                         };
1743
1744                         sdmmc_dectn: sdmmc-dectn {
1745                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1746                         };
1747
1748                         sdmmc_bus1: sdmmc-bus1 {
1749                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1750                         };
1751
1752                         sdmmc_bus4: sdmmc-bus4 {
1753                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1754                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1755                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1756                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1757                         };
1758
1759                         sdmmc_gpio: sdmmc-gpio {
1760                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1761                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1762                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1763                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1764                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1765                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1766                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1767                         };
1768                 };
1769
1770                 sdio0 {
1771                         sdio0_bus1: sdio0-bus1 {
1772                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1773                         };
1774
1775                         sdio0_bus4: sdio0-bus4 {
1776                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1777                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1778                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1779                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1780                         };
1781
1782                         sdio0_cmd: sdio0-cmd {
1783                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1784                         };
1785
1786                         sdio0_clk: sdio0-clk {
1787                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1788                         };
1789
1790                         sdio0_dectn: sdio0-dectn {
1791                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1792                         };
1793
1794                         sdio0_wrprt: sdio0-wrprt {
1795                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1796                         };
1797
1798                         sdio0_pwren: sdio0-pwren {
1799                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1800                         };
1801
1802                         sdio0_bkpwr: sdio0-bkpwr {
1803                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1804                         };
1805
1806                         sdio0_int: sdio0-int {
1807                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1808                         };
1809
1810                         sdio0_gpio: sdio0-gpio {
1811                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1812                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1813                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1814                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1815                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1816                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1817                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1818                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1819                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1820                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1821                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1822                         };
1823                 };
1824
1825                 emmc {
1826                         emmc_clk: emmc-clk {
1827                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1828                         };
1829
1830                         emmc_cmd: emmc-cmd {
1831                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1832                         };
1833
1834                         emmc_pwren: emmc-pwren {
1835                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1836                         };
1837
1838                         emmc_rstnout: emmc_rstnout {
1839                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1840                         };
1841
1842                         emmc_bus1: emmc-bus1 {
1843                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1844                         };
1845
1846                         emmc_bus4: emmc-bus4 {
1847                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1848                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1849                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1850                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1851                         };
1852                 };
1853
1854                 pwm0 {
1855                         pwm0_pin: pwm0-pin {
1856                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1857                         };
1858
1859                         vop_pwm_pin:vop-pwm {
1860                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1861                         };
1862                 };
1863
1864                 pwm1 {
1865                         pwm1_pin: pwm1-pin {
1866                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1867                         };
1868                 };
1869
1870                 pwm3 {
1871                         pwm3_pin: pwm3-pin {
1872                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1873                         };
1874                 };
1875
1876                 lcdc {
1877                         lcdc_lcdc: lcdc-lcdc {
1878                                 rockchip,pins =
1879                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1880                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1881                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1882                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1883                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1884                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1885                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1886                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1887                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1888                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1889                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1890                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1891                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1892                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1893                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1894                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1895                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1896                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1897                         };
1898
1899                         lcdc_gpio: lcdc-gpio {
1900                                 rockchip,pins =
1901                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1902                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1903                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1904                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1905                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1906                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1907                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1908                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1909                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1910                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1911                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1912                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1913                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1914                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1915                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1916                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1917                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1918                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1919                         };
1920                 };
1921
1922                 isp {
1923                         cif_clkout: cif-clkout {
1924                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1925                         };
1926
1927                         isp_dvp_d2d9: isp-dvp-d2d9 {
1928                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1929                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1930                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1931                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1932                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1933                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1934                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1935                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1936                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1937                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1938                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1939                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1940                         };
1941
1942                         isp_dvp_d0d1: isp-dvp-d0d1 {
1943                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1944                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1945                         };
1946
1947                         isp_dvp_d10d11:isp_d10d11       {
1948                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1949                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1950                         };
1951
1952                         isp_dvp_d0d7: isp-dvp-d0d7 {
1953                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1954                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1955                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1956                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1957                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1958                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1959                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1960                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1961                         };
1962
1963                         isp_shutter: isp-shutter {
1964                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1965                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1966                         };
1967
1968                         isp_flash_trigger: isp-flash-trigger {
1969                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1970                         };
1971
1972                         isp_prelight: isp-prelight {
1973                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1974                         };
1975
1976                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1977                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1978                         };
1979                 };
1980
1981                 gps {
1982                         gps_mag: gps-mag {
1983                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1984                         };
1985
1986                         gps_sig: gps-sig {
1987                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1988
1989                         };
1990
1991                         gps_rfclk: gps-rfclk {
1992                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1993                         };
1994                 };
1995
1996                 gmac {
1997                         rgmii_pins: rgmii-pins {
1998                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1999                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2000                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2001                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2002                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2003                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
2004                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
2005                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
2006                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2007                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2008                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2009                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
2010                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
2011                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
2012                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
2013                         };
2014
2015                         rmii_pins: rmii-pins {
2016                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2017                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2018                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2019                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2020                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2021                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2022                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2023                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2024                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
2025                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
2026                         };
2027                 };
2028
2029                 tsadc_pin {
2030                         tsadc_int: tsadc-int {
2031                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
2032                         };
2033                         tsadc_gpio: tsadc-gpio {
2034                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
2035                         };
2036                 };
2037
2038                 hdmi_pin {
2039                         hdmi_cec: hdmi-cec {
2040                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2041                         };
2042                 };
2043
2044                 hdmi_i2c {
2045                         hdmii2c_xfer: hdmii2c-xfer {
2046                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2047                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2048                         };
2049                 };
2050
2051                 cpu_jtag {
2052                         cpu_jtag: cpu-jtag {
2053                                 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2054                                                 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2055                         };
2056                 };
2057         };
2058
2059         reboot {
2060                 compatible = "rockchip,rk3368-reboot";
2061                 rockchip,cru = <&cru>;
2062                 rockchip,pmugrf = <&pmugrf>;
2063         };
2064 };