1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-pm.h>
3 #include <dt-bindings/pinctrl/rockchip.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/sensor-dev.h>
6 #include <dt-bindings/clock/rk_system_status.h>
8 #include "rk3368-clocks.dtsi"
11 compatible = "rockchip,rk3368";
13 rockchip,sram = <&sram>;
14 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a53","arm,armv8";
47 gic: interrupt-controller@ffb70000 {
48 compatible = "arm,cortex-a15-gic";
49 #interrupt-cells = <3>;
52 reg = <0x0 0xffb71000 0 0x1000>,
53 <0x0 0xffb72000 0 0x1000>;
56 pmu_grf: syscon@ff738000 {
57 compatible = "rockchip,rk3388-pmu-grf", "syscon";
58 reg = <0x0 0xff738000 0x0 0x100>;
61 sgrf: syscon@ff740000 {
62 compatible = "rockchip,rk3388-sgrf", "syscon";
63 reg = <0x0 0xff740000 0x0 0x1000>;
67 grf: syscon@ff770000 {
68 compatible = "rockchip,rk3388-grf", "syscon";
69 reg = <0x0 0xff770000 0x0 0x1000>;
73 compatible = "arm,armv8-pmuv3";
74 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
85 cpu_axi_bus: cpu_axi_bus {
86 compatible = "rockchip,cpu_axi_bus";
98 reg = <0x0 0xffa80000 0x0 0x20>;
102 reg = <0x0 0xffa90000 0x0 0x20>;
105 reg = <0x0 0xffa90080 0x0 0x20>;
108 reg = <0x0 0xffa90100 0x0 0x20>;
111 reg = <0x0 0xffa90280 0x0 0x20>;
115 reg = <0x0 0xffaa0000 0x0 0x20>;
118 reg = <0x0 0xffaa0080 0x0 0x20>;
122 reg = <0x0 0xffab0000 0x0 0x20>;
126 reg = <0x0 0xffad0000 0x0 0x20>;
129 reg = <0x0 0xffad0080 0x0 0x20>;
132 reg = <0x0 0xffad0100 0x0 0x20>;
135 reg = <0x0 0xffad0180 0x0 0x20>;
138 reg = <0x0 0xffad0200 0x0 0x20>;
141 reg = <0x0 0xffad0280 0x0 0x20>;
144 reg = <0x0 0xffad0300 0x0 0x20>;
147 reg = <0x0 0xffad0380 0x0 0x20>;
150 reg = <0x0 0xffad0400 0x0 0x20>;
154 reg = <0x0 0xffae0000 0x0 0x20>;
157 reg = <0x0 0xffae0000 0x0 0x20>;
158 rockchip,priority = <2 2>;
161 reg = <0x0 0xffae0080 0x0 0x20>;
162 rockchip,priority = <2 2>;
165 reg = <0x0 0xffae0100 0x0 0x20>;
168 reg = <0x0 0xffae0180 0x0 0x20>;
169 rockchip,priority = <2 2>;
174 #address-cells = <2>;
179 reg = <0x0 0xffac0000 0x0 0x3c>;
180 rockchip,read-latency = <0x34>;
187 compatible = "arm,armv8-timer";
188 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
189 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
190 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
191 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
192 clock-frequency = <24000000>;
196 compatible = "rockchip,timer";
197 reg = <0x0 0xff810000 0x0 0x20>;
198 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
199 rockchip,broadcast = <1>;
202 sram: sram@ff8c0000 {
203 compatible = "mmio-sram";
204 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
208 watchdog: wdt@ff800000 {
209 compatible = "rockchip,watch dog";
210 reg = <0x0 0xff800000 0x0 0x100>;
211 clocks = <&pclk_alive_pre>;
212 clock-names = "pclk_wdt";
213 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
215 rockchip,timeout = <60>;
216 rockchip,atboot = <1>;
217 rockchip,debug = <0>;
222 #address-cells = <2>;
224 compatible = "arm,amba-bus";
225 interrupt-parent = <&gic>;
228 pdma0: pdma@ffb20000 {
229 compatible = "arm,pl330", "arm,primecell";
230 reg = <0x0 0xffb20000 0x0 0x4000>;
231 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
236 pdma1: pdma@ff250000 {
237 compatible = "arm,pl330", "arm,primecell";
238 reg = <0x0 0xff250000 0x0 0x4000>;
239 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
245 reset: reset@ff760300{
246 compatible = "rockchip,reset";
247 reg = <0x0 0xff760300 0x0 0x38>;
248 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
252 nandc0: nandc@ff400000 {
253 compatible = "rockchip,rk-nandc";
254 reg = <0x0 0xff400000 0x0 0x4000>;
255 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
258 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
261 nandc0reg: nandc0@ff400000 {
262 compatible = "rockchip,rk-nandc";
263 reg = <0x0 0xff400000 0x0 0x4000>;
266 emmc: rksdmmc@ff0f0000 {
267 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
268 reg = <0x0 0xff0f0000 0x0 0x4000>;
269 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
270 #address-cells = <1>;
272 clocks = <&clk_emmc>, <&clk_gates21 2>;
273 clock-names = "clk_mmc", "hclk_mmc";
275 fifo-depth = <0x100>;
279 sdmmc: rksdmmc@ff0c0000 {
280 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
281 reg = <0x0 0xff0c0000 0x0 0x4000>;
282 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
283 #address-cells = <1>;
285 pinctrl-names = "default", "idle";
286 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
287 pinctrl-1 = <&sdmmc_gpio>;
288 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
289 clocks = <&clk_sdmmc0>, <&clk_gates21 0>;
290 clock-names = "clk_mmc", "hclk_mmc";
292 fifo-depth = <0x100>;
296 sdio: rksdmmc@ff0d0000 {
297 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
298 reg = <0x0 0xff0d0000 0x0 0x4000>;
299 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
300 #address-cells = <1>;
302 pinctrl-names = "default","idle";
303 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
304 pinctrl-1 = <&sdio0_gpio>;
305 clocks = <&clk_sdio0>, <&clk_gates21 1>;
306 clock-names = "clk_mmc", "hclk_mmc";
308 fifo-depth = <0x100>;
313 compatible = "rockchip,rockchip-spi";
314 reg = <0x0 0xff110000 0x0 0x1000>;
315 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
316 #address-cells = <1>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
320 rockchip,spi-src-clk = <0>;
322 clocks =<&clk_spi0>, <&clk_gates19 4>;
323 clock-names = "spi", "pclk_spi0";
324 //dmas = <&pdma1 11>, <&pdma1 12>;
326 //dma-names = "tx", "rx";
331 compatible = "rockchip,rockchip-spi";
332 reg = <0x0 0xff120000 0x0 0x1000>;
333 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
334 #address-cells = <1>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
338 rockchip,spi-src-clk = <1>;
340 clocks = <&clk_spi1>, <&clk_gates19 5>;
341 clock-names = "spi", "pclk_spi1";
342 //dmas = <&pdma1 13>, <&pdma1 14>;
344 //dma-names = "tx", "rx";
349 compatible = "rockchip,rockchip-spi";
350 reg = <0x0 0xff130000 0x0 0x1000>;
351 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
352 #address-cells = <1>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
356 rockchip,spi-src-clk = <2>;
358 clocks = <&clk_spi2>, <&clk_gates19 6>;
359 clock-names = "spi", "pclk_spi2";
360 //dmas = <&pdma1 15>, <&pdma1 16>;
362 //dma-names = "tx", "rx";
366 uart_bt: serial@ff180000 {
367 compatible = "rockchip,serial";
368 reg = <0x0 0xff180000 0x0 0x100>;
369 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
370 clock-frequency = <24000000>;
371 clocks = <&clk_uart0>, <&clk_gates19 7>;
372 clock-names = "sclk_uart", "pclk_uart";
375 //dmas = <&pdma1 1>, <&pdma1 2>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
382 uart_bb: serial@ff190000 {
383 compatible = "rockchip,serial";
384 reg = <0x0 0xff190000 0x0 0x100>;
385 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
386 clock-frequency = <24000000>;
387 clocks = <&clk_uart1>, <&clk_gates19 8>;
388 clock-names = "sclk_uart", "pclk_uart";
391 //dmas = <&pdma1 3>, <&pdma1 4>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
398 uart_dbg: serial@ff690000 {
399 compatible = "rockchip,serial";
400 reg = <0x0 0xff690000 0x0 0x100>;
401 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
402 clock-frequency = <24000000>;
403 clocks = <&clk_uart2>, <&clk_gates13 5>;
404 clock-names = "sclk_uart", "pclk_uart";
407 //dmas = <&pdma0 4>, <&pdma0 5>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&uart2_xfer>;
414 uart_gps: serial@ff1b0000 {
415 compatible = "rockchip,serial";
416 reg = <0x0 0xff1b0000 0x0 0x100>;
417 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
418 clock-frequency = <24000000>;
419 clocks = <&clk_uart3>, <&clk_gates19 9>;
420 clock-names = "sclk_uart", "pclk_uart";
421 current-speed = <115200>;
424 //dmas = <&pdma1 7>, <&pdma1 8>;
426 pinctrl-names = "default";
427 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
431 uart_exp: serial@ff1c0000 {
432 compatible = "rockchip,serial";
433 reg = <0x0 0xff1c0000 0x0 0x100>;
434 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
435 clock-frequency = <24000000>;
436 clocks = <&clk_uart4>, <&clk_gates19 10>;
437 clock-names = "sclk_uart", "pclk_uart";
440 //dmas = <&pdma1 9>, <&pdma1 10>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
447 rockchip_clocks_init: clocks-init{
448 compatible = "rockchip,clocks-init";
449 rockchip,clocks-init-parent =
450 <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
451 <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
452 <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
454 rockchip,clocks-init-rate =
455 <&clk_gpll 576000000>, <&clk_core_b 792000000>,
456 <&clk_core_l 600000000>, <&clk_cpll 400000000>,
457 /*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
458 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
459 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
460 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
461 <&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
462 <&clk_cs 300000000>, <&clkin_trace 300000000>,
463 <&aclk_cci 600000000>, <&clk_mac 50000000>,
464 <&aclk_vio0 400000000>, <&hclk_vio 100000000>,
465 <&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
466 <&clk_isp 400000000>, <&clk_edp 200000000>,
467 <&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
468 <&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
469 <&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
470 <&clk_hevc_cabac 300000000>;
472 rockchip,clocks-uboot-has-init =
477 rockchip_clocks_enable: clocks-enable {
478 compatible = "rockchip,clocks-enable";
495 <&clk_gates12 12>,/*aclk_strc_sys*/
496 <&clk_gates12 6>,/*aclk_intmem1*/
497 <&clk_gates12 5>,/*aclk_intmem0*/
498 <&clk_gates12 4>,/*aclk_intmem*/
499 <&clk_gates13 9>,/*aclk_gic400*/
502 <&clk_gates22 13>,/*pclk_timer1*/
503 <&clk_gates22 12>,/*pclk_timer0*/
504 <&clk_gates22 9>,/*pclk_alive_niu*/
505 <&clk_gates22 8>,/*pclk_grf*/
508 <&clk_gates23 5>,/*pclk_pmugrf*/
509 <&clk_gates23 3>,/*pclk_sgrf*/
510 <&clk_gates23 2>,/*pclk_pmu_noc*/
511 <&clk_gates23 1>,/*pclk_intmem1*/
512 <&clk_gates23 0>,/*pclk_pmu*/
515 <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
516 <&clk_gates20 8>,/*aclk_peri_niu*/
517 <&clk_gates21 4>,/*aclk_peri_mmu*/
518 <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
519 <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
520 <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
524 compatible = "rockchip,rk30-i2c";
525 reg = <0x0 0xff650000 0x0 0x1000>;
526 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
527 #address-cells = <1>;
529 pinctrl-names = "default", "gpio";
530 pinctrl-0 = <&i2c0_xfer>;
531 pinctrl-1 = <&i2c0_gpio>;
532 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
533 clocks = <&clk_gates12 2>;
534 rockchip,check-idle = <1>;
539 compatible = "rockchip,rk30-i2c";
540 reg = <0x0 0xff140000 0x0 0x1000>;
541 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
542 #address-cells = <1>;
544 pinctrl-names = "default", "gpio";
545 pinctrl-0 = <&i2c1_xfer>;
546 pinctrl-1 = <&i2c1_gpio>;
547 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
548 clocks = <&clk_gates19 11>;
549 rockchip,check-idle = <1>;
554 compatible = "rockchip,rk30-i2c";
555 reg = <0x0 0xff660000 0x0 0x1000>;
556 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
557 #address-cells = <1>;
559 pinctrl-names = "default", "gpio";
560 pinctrl-0 = <&i2c2_xfer>;
561 pinctrl-1 = <&i2c2_gpio>;
562 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
563 clocks = <&clk_gates12 3>;
564 rockchip,check-idle = <1>;
569 compatible = "rockchip,rk30-i2c";
570 reg = <0x0 0xff150000 0x0 0x1000>;
571 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
572 #address-cells = <1>;
574 pinctrl-names = "default", "gpio";
575 pinctrl-0 = <&i2c3_xfer>;
576 pinctrl-1 = <&i2c3_gpio>;
577 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
578 clocks = <&clk_gates19 12>;
579 rockchip,check-idle = <1>;
584 compatible = "rockchip,rk30-i2c";
585 reg = <0x0 0xff160000 0x0 0x1000>;
586 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
587 #address-cells = <1>;
589 pinctrl-names = "default", "gpio";
590 pinctrl-0 = <&i2c4_xfer>;
591 pinctrl-1 = <&i2c4_gpio>;
592 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
593 clocks = <&clk_gates19 13>;
594 rockchip,check-idle = <1>;
599 compatible = "rockchip,rk30-i2c";
600 reg = <0x0 0xff170000 0x0 0x1000>;
601 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
602 #address-cells = <1>;
604 pinctrl-names = "default", "gpio";
605 pinctrl-0 = <&i2c5_xfer>;
606 pinctrl-1 = <&i2c5_gpio>;
607 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
608 clocks = <&clk_gates19 14>;
609 rockchip,check-idle = <1>;
614 compatible = "rockchip,rk-fb";
615 rockchip,disp-mode = <NO_DUAL>;
619 rk_screen: rk_screen {
620 compatible = "rockchip,screen";
623 dsihost0: mipi@ff960000{
624 compatible = "rockchip,rk33x-dsi";
626 reg = <0xff960000 0x4000>, <0xff968000 0x4000>;
627 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
628 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&clk_gates4 14>, <&clk_gates17 3>, <&clk_gates22 10>;
630 clock-names = "clk_mipi_24m", "pclk_mipi_dsi_host", "pclk_mipi_dsi_phy";
634 lvds: lvds@ff968000 {
635 compatible = "rockchip,rk3368-lvds";
636 rockchip,grf = <&grf>;
637 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
638 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
639 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
640 clock-names = "pclk_lvds", "pclk_lvds_ctl";
645 compatible = "rockchip,rk32-edp";
646 reg = <0x0 0xff970000 0x0 0x4000>;
647 rockchip,grf = <&grf>;
648 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
650 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
653 hdmi: hdmi@ff980000 {
654 compatible = "rockchip,rk3368-hdmi";
655 reg = <0x0 0xff980000 0x0 0x20000>;
656 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
657 pinctrl-names = "default", "gpio";
658 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
659 pinctrl-1 = <&i2c5_gpio>;
660 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
661 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
665 hdmi_hdcp2: hdmi_hdcp2@ff978000 {
666 compatible = "rockchip,rk3368-hdmi-hdcp2";
667 reg = <0x0 0xff978000 0x0 0x2000>;
668 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
670 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
674 lcdc: lcdc@ff930000 {
675 compatible = "rockchip,rk3368-lcdc";
676 rockchip,prop = <PRMRY>;
677 rockchip,pwr18 = <0>;
678 rockchip,iommu-enabled = <0>;
679 reg = <0x0 0xff930000 0x0 0x10000>;
680 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
681 pinctrl-names = "default", "gpio";
682 pinctrl-0 = <&lcdc_lcdc>;
683 pinctrl-1 = <&lcdc_gpio>;
685 clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
686 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
690 compatible = "rockchip,saradc";
691 reg = <0x0 0xff100000 0x0 0x100>;
692 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
693 #io-channel-cells = <1>;
695 rockchip,adc-vref = <1800>;
696 clock-frequency = <1000000>;
697 clocks = <&clk_saradc>, <&clk_gates19 15>;
698 clock-names = "saradc", "pclk_saradc";
703 compatible = "rockchip,rk3368-rga2";
704 reg = <0x0 0xff920000 0x0 0x1000>;
705 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
707 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
710 i2s0: i2s0@ff898000 {
711 compatible = "rockchip-i2s";
712 reg = <0x0 0xff898000 0x0 0x1000>;
714 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
715 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
716 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
717 dmas = <&pdma0 0>, <&pdma0 1>;
719 dma-names = "tx", "rx";
720 pinctrl-names = "default", "sleep";
721 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
722 pinctrl-1 = <&i2s_gpio>;
725 i2s1: i2s1@ff890000 {
726 compatible = "rockchip-i2s";
727 reg = <0x0 0xff890000 0x0 0x1000>;
729 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
730 clock-names = "i2s_clk", "i2s_hclk";
731 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
732 dmas = <&pdma0 6>, <&pdma0 7>;
734 dma-names = "tx", "rx";
737 spdif: spdif@ff880000 {
738 compatible = "rockchip-spdif";
739 reg = <0x0 0xff880000 0x0 0x1000>;
740 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
741 clock-names = "spdif_mclk", "spdif_hclk";
742 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
746 pinctrl-names = "default";
747 pinctrl-0 = <&spdif_tx>;
751 compatible = "rockchip,rk-pwm";
752 reg = <0x0 0xff680000 0x0 0x10>;
754 pinctrl-names = "default";
755 pinctrl-0 = <&pwm0_pin>;
756 clocks = <&clk_gates13 6>;
757 clock-names = "pclk_pwm";
762 compatible = "rockchip,rk-pwm";
763 reg = <0x0 0xff680010 0x0 0x10>;
765 pinctrl-names = "default";
766 pinctrl-0 = <&pwm1_pin>;
767 clocks = <&clk_gates13 6>;
768 clock-names = "pclk_pwm";
773 compatible = "rockchip,rk-pwm";
774 reg = <0x0 0xff680020 0x0 0x10>;
776 //pinctrl-names = "default";
777 //pinctrl-0 = <&pwm1_pin>;
778 clocks = <&clk_gates13 6>;
779 clock-names = "pclk_pwm";
784 compatible = "rockchip,rk-pwm";
785 reg = <0x0 0xff680030 0x0 0x10>;
787 pinctrl-names = "default";
788 pinctrl-0 = <&pwm3_pin>;
789 clocks = <&clk_gates13 6>;
790 clock-names = "pclk_pwm";
797 regulator_name = "vdd_arm";
798 suspend_volt = <1000>; //mV
800 clk_core_dvfs_table: clk_core {
809 temp-limit-enable = <0>;
811 normal-temp-limit = <
812 /*delta-temp delta-freq*/
818 performance-temp-limit = <
834 regulator_name = "vdd_logic";
835 suspend_volt = <1000>; //mV
837 clk_ddr_dvfs_table: clk_ddr {
850 aclk_vio1_dvfs_table: aclk_vio1 {
862 regulator_name = "vdd_gpu";
863 suspend_volt = <1000>; //mV
865 clk_gpu_dvfs_table: clk_gpu {
886 compatible = "rockchip,ion";
887 #address-cells = <1>;
890 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
891 compatible = "rockchip,ion-heap";
892 rockchip,ion_heap = <1>;
893 reg = <0x0 0x00000000 0x0 0x08000000>; /* 512MB */
895 rockchip,ion-heap@3 { /* VMALLOC HEAP */
896 compatible = "rockchip,ion-heap";
897 rockchip,ion_heap = <3>;
901 vpu: vpu_service@ff9a0000 {
902 compatible = "vpu_service";
904 reg = <0x0 0xff9a0000 0x0 0x800>;
905 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
906 interrupt-names = "irq_enc", "irq_dec";
908 clocks = <&clk_vdpu>, <&hclk_vdpu>;
909 clock-names = "aclk_vcodec", "hclk_vcodec";
911 name = "vpu_service";
912 /* status = "disabled"; */
916 compatible = "rockchip,iep";
918 reg = <0x0 0xff900000 0x0 0x800>;
919 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
920 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
921 clock-names = "aclk_iep", "hclk_iep";
926 compatible = "rockchip,rk3368-gmac";
927 reg = <0x0 0xff290000 0x0 0x10000>;
928 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
929 interrupt-names = "macirq";
931 clocks = <&clk_mac>, <&clk_gates5 0>,
932 <&clk_gates5 1>, <&clk_gates5 2>,
933 <&clk_gates5 3>, <&clk_gates8 0>,
935 clock-names = "clk_mac", "mac_clk_rx",
936 "mac_clk_tx", "clk_mac_ref",
937 "clk_mac_refout", "aclk_mac",
941 pinctrl-names = "default";
942 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
946 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
947 reg = <0x0 0xffa30000 0x0 0x10000>;
948 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
949 interrupt-names = "GPU";
954 compatible = "rockchip,iep_mmu";
955 reg = <0x0 0xff900800 0x0 0x100>;
956 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
957 interrupt-names = "iep_mmu";
962 compatible = "rockchip,vip_mmu";
963 reg = <0x0 0xff950800 0x0 0x100>;
964 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-names = "vip_mmu";
970 compatible = "rockchip,vop_mmu";
971 reg = <0x0 0xff930300 0x0 0x100>;
972 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
973 interrupt-names = "vop_mmu";
978 compatible = "rockchip,isp_mmu";
979 reg = <0x0 0xff914000 0x0 0x100>,
980 <0x0 0xff915000 0x0 0x100>;
981 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
982 interrupt-names = "isp_mmu";
986 dbgname = "hdcp_mmu";
987 compatible = "rockchip,hdcp_mmu";
988 reg = <0x0 0xff940000 0x0 0x100>;
989 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
990 interrupt-names = "hdcp_mmu";
995 compatible = "rockchip,hevc_mmu";
996 reg = <0x0 0xff9c0440 0x0 0x40>, /*need to fix*/
997 <0x0 0xff9c0480 0x0 0x40>;
998 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
999 interrupt-names = "hevc_mmu";
1004 compatible = "rockchip,vpu_mmu";
1005 reg = <0x0 0xff9a0800 0x0 0x100>; /*need to fix*/
1006 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1007 interrupt-names = "vpu_mmu";
1011 rockchip,ctrbits = <
1018 |RKPM_CTR_SYSCLK_DIV
1019 |RKPM_CTR_IDLEAUTO_MD
1020 |RKPM_CTR_ARMOFF_LPMD
1022 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1025 rockchip,pmic-suspend_gpios = <
1026 /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1028 rockchip,pmic-resume_gpios = <
1029 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1034 compatible = "rockchip,isp";
1035 reg = <0x0 0xff910000 0x0 0x10000>;
1036 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1038 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1039 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1040 pinctrl-0 = <&cif_clkout>;
1041 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1042 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1043 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1044 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1045 pinctrl-5 = <&cif_clkout>;
1046 pinctrl-6 = <&cif_clkout &isp_prelight>;
1047 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1048 pinctrl-8 = <&isp_flash_trigger>;
1049 rockchip,isp,mipiphy = <2>;
1050 rockchip,isp,cifphy = <1>;
1051 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1052 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1053 rockchip,isp,iommu_enable = <1>;
1057 tsadc: tsadc@ff280000 {
1058 compatible = "rockchip,tsadc";
1059 reg = <0x0 0xff280000 0x0 0x100>;
1060 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1061 #io-channel-cells = <1>;
1063 clock-frequency = <10000>;
1064 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1065 clock-names = "tsadc", "pclk_tsadc";
1066 pinctrl-names = "default", "tsadc_int";
1067 pinctrl-0 = <&tsadc_gpio>;
1068 pinctrl-1 = <&tsadc_int>;
1069 tsadc-ht-temp = <120>;
1070 tsadc-ht-reset-cru = <1>;
1071 tsadc-ht-pull-gpio = <0>;
1072 status = "disabled";
1076 compatible = "rockchip,rk3368-tsp";
1077 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1078 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1079 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1080 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1081 interrupt-names = "irq_tsp";
1082 // pinctrl-names = "default";
1083 // pinctrl-0 = <&isp_hsadc>;
1087 crypto: crypto@FF8A0000{
1088 compatible = "rockchip,rk3368-crypto";
1089 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1090 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1091 interrupt-names = "irq_crypto";
1092 clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1093 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1098 compatible = "rockchip,rk3368-pinctrl";
1099 rockchip,grf = <&grf>;
1100 rockchip,pmu = <&pmu_grf>;
1101 #address-cells = <2>;
1105 gpio0: gpio0@ff750000 {
1106 compatible = "rockchip,gpio-bank";
1107 reg = <0x0 0xff750000 0x0 0x100>;
1108 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1109 clocks = <&clk_gates23 4>;
1114 interrupt-controller;
1115 #interrupt-cells = <2>;
1118 gpio1: gpio1@ff780000 {
1119 compatible = "rockchip,gpio-bank";
1120 reg = <0x0 0xff780000 0x0 0x100>;
1121 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1122 clocks = <&clk_gates22 1>;
1127 interrupt-controller;
1128 #interrupt-cells = <2>;
1131 gpio2: gpio2@ff790000 {
1132 compatible = "rockchip,gpio-bank";
1133 reg = <0x0 0xff790000 0x0 0x100>;
1134 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1135 clocks = <&clk_gates22 2>;
1140 interrupt-controller;
1141 #interrupt-cells = <2>;
1144 gpio3: gpio3@ff7a0000 {
1145 compatible = "rockchip,gpio-bank";
1146 reg = <0x0 0xff7a0000 0x0 0x100>;
1147 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1148 clocks = <&clk_gates22 3>;
1153 interrupt-controller;
1154 #interrupt-cells = <2>;
1157 pcfg_pull_up: pcfg-pull-up {
1161 pcfg_pull_down: pcfg-pull-down {
1165 pcfg_pull_none: pcfg-pull-none {
1169 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1170 drive-strength = <8>;
1173 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1175 drive-strength = <8>;
1178 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1179 drive-strength = <4>;
1182 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1184 drive-strength = <4>;
1187 pcfg_output_high: pcfg-output-high {
1191 pcfg_output_low: pcfg-output-low {
1196 i2c0_xfer: i2c0-xfer {
1197 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1198 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1200 i2c0_gpio: i2c0-gpio {
1201 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1202 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1207 i2c1_xfer: i2c1-xfer {
1208 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1209 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1211 i2c1_gpio: i2c1-gpio {
1212 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1213 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1218 i2c2_xfer: i2c2-xfer {
1219 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1220 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1222 i2c2_gpio: i2c2-gpio {
1223 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1224 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1229 i2c3_xfer: i2c3-xfer {
1230 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1231 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1233 i2c3_gpio: i2c3-gpio {
1234 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1235 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1240 i2c4_xfer: i2c4-xfer {
1241 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1242 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1244 i2c4_gpio: i2c4-gpio {
1245 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1246 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1251 i2c5_xfer: i2c5-xfer {
1252 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1253 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1255 i2c5_gpio: i2c5-gpio {
1256 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1257 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1262 uart0_xfer: uart0-xfer {
1263 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1264 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1267 uart0_cts: uart0-cts {
1268 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1271 uart0_rts: uart0-rts {
1272 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1275 uart0_rts_gpio: uart0-rts-gpio {
1276 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1281 uart1_xfer: uart1-xfer {
1282 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1283 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1286 uart1_cts: uart1-cts {
1287 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1290 uart1_rts: uart1-rts {
1291 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1296 uart2_xfer: uart2-xfer {
1297 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1298 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1303 uart3_xfer: uart3-xfer {
1304 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1305 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1308 uart3_cts: uart3-cts {
1309 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1312 uart3_rts: uart3-rts {
1313 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1318 uart4_xfer: uart4-xfer {
1319 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1320 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1323 uart4_cts: uart4-cts {
1324 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1327 uart4_rts: uart4-rts {
1328 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1333 spi0_clk: spi0-clk {
1334 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1336 spi0_cs0: spi0-cs0 {
1337 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1340 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1343 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1345 spi0_cs1: spi0-cs1 {
1346 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1351 spi1_clk: spi1-clk {
1352 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1354 spi1_cs0: spi1-cs0 {
1355 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1358 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1361 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1366 spi2_clk: spi2-clk {
1367 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1369 spi2_cs0: spi2-cs0 {
1370 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1373 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1376 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1381 i2s_mclk: i2s-mclk {
1382 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1386 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1389 i2s_lrckrx:i2s-lrckrx {
1390 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1393 i2s_lrcktx:i2s-lrcktx {
1394 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1398 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1402 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1406 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1410 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1414 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1417 i2s_gpio: i2s-gpio {
1418 rockchip,pins = <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,
1419 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1420 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1421 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1422 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1423 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1424 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1425 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1426 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1431 spdif_tx: spdif-tx {
1432 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1437 sdmmc_clk: sdmmc-clk {
1438 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1441 sdmmc_cmd: sdmmc-cmd {
1442 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1445 sdmmc_dectn: sdmmc-dectn {
1446 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1449 sdmmc_bus1: sdmmc-bus1 {
1450 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1453 sdmmc_bus4: sdmmc-bus4 {
1454 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1455 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1456 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1457 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1460 sdmmc_gpio: sdmmc-gpio {
1461 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1462 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1463 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1464 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1465 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1466 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1467 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1472 sdio0_bus1: sdio0-bus1 {
1473 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1476 sdio0_bus4: sdio0-bus4 {
1477 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1478 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1479 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1480 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1483 sdio0_cmd: sdio0-cmd {
1484 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1487 sdio0_clk: sdio0-clk {
1488 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1491 sdio0_dectn: sdio0-dectn {
1492 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1495 sdio0_wrprt: sdio0-wrprt {
1496 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1499 sdio0_pwren: sdio0-pwren {
1500 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1503 sdio0_bkpwr: sdio0-bkpwr {
1504 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1507 sdio0_int: sdio0-int {
1508 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1511 sdio0_gpio: sdio0-gpio {
1512 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1513 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1514 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1515 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1516 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1517 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1518 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1519 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1520 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1521 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1522 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1527 emmc_clk: emmc-clk {
1528 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1531 emmc_cmd: emmc-cmd {
1532 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1535 emmc_pwren: emmc-pwren {
1536 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1539 emmc_rstnout: emmc_rstnout {
1540 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1543 emmc_bus1: emmc-bus1 {
1544 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1547 emmc_bus4: emmc-bus4 {
1548 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1549 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1550 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1551 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1556 pwm0_pin: pwm0-pin {
1557 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1560 vop_pwm_pin:vop-pwm {
1561 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1566 pwm1_pin: pwm1-pin {
1567 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1572 pwm3_pin: pwm3-pin {
1573 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1578 lcdc_lcdc: lcdc-lcdc {
1579 rockchip,pins = <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1580 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1581 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1582 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1585 lcdc_gpio: lcdc-gpio {
1586 rockchip,pins = <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1587 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1588 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1589 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1594 cif_clkout: cif-clkout {
1595 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1598 isp_dvp_d2d9: isp-dvp-d2d9 {
1599 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1600 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1601 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1602 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1603 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1604 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1605 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1606 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1607 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1608 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1609 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1610 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1613 isp_dvp_d0d1: isp-dvp-d0d1 {
1614 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1615 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1618 isp_dvp_d10d11:isp_d10d11 {
1619 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1620 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1623 isp_dvp_d0d7: isp-dvp-d0d7 {
1624 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1625 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1626 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1627 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1628 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1629 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1630 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1631 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1634 isp_shutter: isp-shutter {
1635 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1636 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1639 isp_flash_trigger: isp-flash-trigger {
1640 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1643 isp_prelight: isp-prelight {
1644 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1647 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1648 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1654 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1658 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1662 gps_rfclk: gps-rfclk {
1663 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1669 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1672 mac_txpins: mac-txpins {
1673 rockchip,pins = <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//TXD0
1674 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//TXD1
1675 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//TXD2
1676 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//TXD3
1677 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//TXEN
1678 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;//TXCLK
1681 mac_rxpins: mac-rxpins {
1682 rockchip,pins = <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1683 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1684 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1685 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1686 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1687 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//RXER
1688 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1689 <3 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;//COL
1693 rockchip,pins = <3 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>; //CRS
1696 mac_mdpins: mac-mdpins {
1697 rockchip,pins = <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1698 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;//MDC
1703 tsadc_int: tsadc-int {
1704 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1706 tsadc_gpio: tsadc-gpio {
1707 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1712 hdmi_cec: hdmi-cec {
1713 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1718 hdmii2c_xfer: hdmii2c-xfer {
1719 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
1720 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;