1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-pm.h>
3 #include <dt-bindings/pinctrl/rockchip.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/sensor-dev.h>
6 #include <dt-bindings/clock/rk_system_status.h>
8 #include "rk3368-clocks.dtsi"
11 compatible = "rockchip,rk3368";
13 rockchip,sram = <&sram>;
14 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a53", "arm,armv8";
44 enable-method = "psci";
48 compatible = "arm,cortex-a53", "arm,armv8";
50 enable-method = "psci";
54 compatible = "arm,cortex-a53", "arm,armv8";
56 enable-method = "psci";
60 compatible = "arm,cortex-a53", "arm,armv8";
62 enable-method = "psci";
66 compatible = "arm,cortex-a53", "arm,armv8";
68 enable-method = "psci";
72 compatible = "arm,cortex-a53", "arm,armv8";
74 enable-method = "psci";
78 compatible = "arm,cortex-a53", "arm,armv8";
80 enable-method = "psci";
84 compatible = "arm,cortex-a53", "arm,armv8";
86 enable-method = "psci";
122 compatible = "arm,psci";
124 cpu_on = <0xC4000003>;
127 gic: interrupt-controller@ffb70000 {
128 compatible = "arm,cortex-a15-gic";
129 #interrupt-cells = <3>;
130 #address-cells = <0>;
131 interrupt-controller;
132 reg = <0x0 0xffb71000 0 0x1000>,
133 <0x0 0xffb72000 0 0x1000>;
136 pmu: syscon@ff730000 {
137 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
138 reg = <0x0 0xff730000 0x0 0x1000>;
141 pmugrf: syscon@ff738000 {
142 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
143 reg = <0x0 0xff738000 0x0 0x1000>;
146 sgrf: syscon@ff740000 {
147 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
148 reg = <0x0 0xff740000 0x0 0x1000>;
152 cru: syscon@ff760000 {
153 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
154 reg = <0x0 0xff760000 0x0 0x1000>;
157 grf: syscon@ff770000 {
158 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
159 reg = <0x0 0xff770000 0x0 0x1000>;
163 compatible = "arm,armv8-pmuv3";
164 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
174 cpu_axi_bus: cpu_axi_bus {
175 compatible = "rockchip,cpu_axi_bus";
176 #address-cells = <2>;
181 #address-cells = <2>;
186 reg = <0x0 0xffa80000 0x0 0x20>;
189 reg = <0x0 0xffa80080 0x0 0x20>;
192 reg = <0x0 0xffa90000 0x0 0x20>;
195 reg = <0x0 0xffaa0000 0x0 0x20>;
198 reg = <0x0 0xffaa0080 0x0 0x20>;
201 reg = <0x0 0xffab0000 0x0 0x20>;
204 reg = <0x0 0xffad0000 0x0 0x20>;
207 reg = <0x0 0xffad0080 0x0 0x20>;
210 reg = <0x0 0xffad0100 0x0 0x20>;
213 reg = <0x0 0xffad0180 0x0 0x20>;
214 rockchip,priority = <2 2>;
217 reg = <0x0 0xffad0200 0x0 0x20>;
218 rockchip,priority = <2 2>;
221 reg = <0x0 0xffad0280 0x0 0x20>;
224 reg = <0x0 0xffad0300 0x0 0x20>;
225 rockchip,priority = <2 2>;
228 reg = <0x0 0xffad0380 0x0 0x20>;
231 reg = <0x0 0xffad0400 0x0 0x20>;
234 reg = <0x0 0xffae0000 0x0 0x20>;
237 reg = <0x0 0xffae0080 0x0 0x20>;
240 reg = <0x0 0xffae0100 0x0 0x20>;
245 #address-cells = <2>;
250 reg = <0x0 0xffac0000 0x0 0x3c>;
251 rockchip,read-latency = <0x34>;
257 compatible = "arm,armv8-timer";
258 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
259 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
260 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
261 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
262 clock-frequency = <24000000>;
266 compatible = "rockchip,timer";
267 reg = <0x0 0xff810000 0x0 0x20>;
268 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
269 rockchip,broadcast = <1>;
272 sram: sram@ff8c0000 {
273 compatible = "mmio-sram";
274 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
278 watchdog: wdt@ff800000 {
279 compatible = "rockchip,watch dog";
280 reg = <0x0 0xff800000 0x0 0x100>;
281 clocks = <&pclk_alive_pre>;
282 clock-names = "pclk_wdt";
283 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
285 rockchip,timeout = <60>;
286 rockchip,atboot = <1>;
287 rockchip,debug = <0>;
292 #address-cells = <2>;
294 compatible = "arm,amba-bus";
295 interrupt-parent = <&gic>;
298 pdma0: pdma@ff600000 {
299 compatible = "arm,pl330", "arm,primecell";
300 reg = <0x0 0xff600000 0x0 0x4000>;
301 clocks = <&clk_gates12 11>;
302 clock-names = "apb_pclk";
303 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
309 pdma1: pdma@ff250000 {
310 compatible = "arm,pl330", "arm,primecell";
311 reg = <0x0 0xff250000 0x0 0x4000>;
312 clocks = <&clk_gates19 3>;
313 clock-names = "apb_pclk";
314 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
320 reset: reset@ff760300{
321 compatible = "rockchip,reset";
322 reg = <0x0 0xff760300 0x0 0x38>;
323 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
327 nandc0: nandc@ff400000 {
328 compatible = "rockchip,rk-nandc";
329 reg = <0x0 0xff400000 0x0 0x4000>;
330 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
333 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
336 nandc0reg: nandc0@ff400000 {
337 compatible = "rockchip,rk-nandc";
338 reg = <0x0 0xff400000 0x0 0x4000>;
341 emmc: rksdmmc@ff0f0000 {
342 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
343 reg = <0x0 0xff0f0000 0x0 0x4000>;
344 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
345 #address-cells = <1>;
347 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
348 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
349 rockchip,grf = <&grf>;
351 fifo-depth = <0x100>;
355 sdmmc: rksdmmc@ff0c0000 {
356 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
357 reg = <0x0 0xff0c0000 0x0 0x4000>;
358 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
361 pinctrl-names = "default", "idle", "udbg";
362 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
363 pinctrl-1 = <&sdmmc_gpio>;
364 pinctrl-2 = <&uart2_xfer &cpu_jtag &sdmmc_dectn>;
365 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
366 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
367 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
368 rockchip,grf = <&grf>;
370 fifo-depth = <0x100>;
374 sdio: rksdmmc@ff0d0000 {
375 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
376 reg = <0x0 0xff0d0000 0x0 0x4000>;
377 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
380 pinctrl-names = "default","idle";
381 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
382 pinctrl-1 = <&sdio0_gpio>;
383 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
384 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
385 rockchip,grf = <&grf>;
387 fifo-depth = <0x100>;
392 compatible = "rockchip,rockchip-spi";
393 reg = <0x0 0xff110000 0x0 0x1000>;
394 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
395 #address-cells = <1>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
399 rockchip,spi-src-clk = <0>;
401 clocks =<&clk_spi0>, <&clk_gates19 4>;
402 clock-names = "spi", "pclk_spi0";
403 //dmas = <&pdma1 11>, <&pdma1 12>;
405 //dma-names = "tx", "rx";
410 compatible = "rockchip,rockchip-spi";
411 reg = <0x0 0xff120000 0x0 0x1000>;
412 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
413 #address-cells = <1>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
417 rockchip,spi-src-clk = <1>;
419 clocks = <&clk_spi1>, <&clk_gates19 5>;
420 clock-names = "spi", "pclk_spi1";
421 //dmas = <&pdma1 13>, <&pdma1 14>;
423 //dma-names = "tx", "rx";
428 compatible = "rockchip,rockchip-spi";
429 reg = <0x0 0xff130000 0x0 0x1000>;
430 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
435 rockchip,spi-src-clk = <2>;
437 clocks = <&clk_spi2>, <&clk_gates19 6>;
438 clock-names = "spi", "pclk_spi2";
439 //dmas = <&pdma1 15>, <&pdma1 16>;
441 //dma-names = "tx", "rx";
445 uart_bt: serial@ff180000 {
446 compatible = "rockchip,serial";
447 reg = <0x0 0xff180000 0x0 0x100>;
448 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
449 clock-frequency = <24000000>;
450 clocks = <&clk_uart0>, <&clk_gates19 7>;
451 clock-names = "sclk_uart", "pclk_uart";
454 //dmas = <&pdma1 1>, <&pdma1 2>;
456 pinctrl-names = "default";
457 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
461 uart_bb: serial@ff190000 {
462 compatible = "rockchip,serial";
463 reg = <0x0 0xff190000 0x0 0x100>;
464 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
465 clock-frequency = <24000000>;
466 clocks = <&clk_uart1>, <&clk_gates19 8>;
467 clock-names = "sclk_uart", "pclk_uart";
470 //dmas = <&pdma1 3>, <&pdma1 4>;
472 pinctrl-names = "default";
473 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
477 uart_dbg: serial@ff690000 {
478 compatible = "rockchip,serial";
479 reg = <0x0 0xff690000 0x0 0x100>;
480 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
481 clock-frequency = <24000000>;
482 clocks = <&clk_uart2>, <&clk_gates13 5>;
483 clock-names = "sclk_uart", "pclk_uart";
486 //dmas = <&pdma0 4>, <&pdma0 5>;
488 //pinctrl-names = "default";
489 //pinctrl-0 = <&uart2_xfer>;
493 uart_gps: serial@ff1b0000 {
494 compatible = "rockchip,serial";
495 reg = <0x0 0xff1b0000 0x0 0x100>;
496 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
497 clock-frequency = <24000000>;
498 clocks = <&clk_uart3>, <&clk_gates19 9>;
499 clock-names = "sclk_uart", "pclk_uart";
500 current-speed = <115200>;
503 //dmas = <&pdma1 7>, <&pdma1 8>;
505 pinctrl-names = "default";
506 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
510 uart_exp: serial@ff1c0000 {
511 compatible = "rockchip,serial";
512 reg = <0x0 0xff1c0000 0x0 0x100>;
513 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
514 clock-frequency = <24000000>;
515 clocks = <&clk_uart4>, <&clk_gates19 10>;
516 clock-names = "sclk_uart", "pclk_uart";
519 //dmas = <&pdma1 9>, <&pdma1 10>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
526 rockchip_clocks_init: clocks-init{
527 compatible = "rockchip,clocks-init";
528 rockchip,clocks-init-parent =
529 <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
530 <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
531 <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
532 <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
533 rockchip,clocks-init-rate =
534 <&clk_gpll 576000000>, <&clk_core_b 792000000>,
535 <&clk_core_l 600000000>, <&clk_cpll 400000000>,
536 /*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
537 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
538 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
539 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
540 <&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
541 <&clk_cs 300000000>, <&clkin_trace 300000000>,
542 <&aclk_cci 600000000>, <&clk_mac 125000000>,
543 <&aclk_vio0 400000000>, <&hclk_vio 100000000>,
544 <&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
545 <&clk_isp 400000000>, <&clk_edp 200000000>,
546 <&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
547 <&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
548 <&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
549 <&clk_hevc_cabac 300000000>;
551 rockchip,clocks-uboot-has-init =
556 rockchip_clocks_enable: clocks-enable {
557 compatible = "rockchip,clocks-enable";
580 <&clk_gates12 12>,/*aclk_strc_sys*/
581 <&clk_gates12 6>,/*aclk_intmem1*/
582 <&clk_gates12 5>,/*aclk_intmem0*/
583 <&clk_gates12 4>,/*aclk_intmem*/
584 <&clk_gates13 9>,/*aclk_gic400*/
587 <&clk_gates22 13>,/*pclk_timer1*/
588 <&clk_gates22 12>,/*pclk_timer0*/
589 <&clk_gates22 9>,/*pclk_alive_niu*/
590 <&clk_gates22 8>,/*pclk_grf*/
593 <&clk_gates23 5>,/*pclk_pmugrf*/
594 <&clk_gates23 3>,/*pclk_sgrf*/
595 <&clk_gates23 2>,/*pclk_pmu_noc*/
596 <&clk_gates23 1>,/*pclk_intmem1*/
597 <&clk_gates23 0>,/*pclk_pmu*/
600 <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
601 <&clk_gates20 8>,/*aclk_peri_niu*/
602 <&clk_gates21 4>,/*aclk_peri_mmu*/
603 <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
604 <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
605 <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
610 compatible = "rockchip,rk30-i2c";
611 reg = <0x0 0xff650000 0x0 0x1000>;
612 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
613 #address-cells = <1>;
615 pinctrl-names = "default", "gpio";
616 pinctrl-0 = <&i2c0_xfer>;
617 pinctrl-1 = <&i2c0_gpio>;
618 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
619 clocks = <&clk_gates12 2>;
620 rockchip,check-idle = <1>;
626 compatible = "rockchip,rk30-i2c";
627 reg = <0x0 0xff660000 0x0 0x1000>;
628 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
629 #address-cells = <1>;
631 pinctrl-names = "default", "gpio";
632 pinctrl-0 = <&i2c1_xfer>;
633 pinctrl-1 = <&i2c1_gpio>;
634 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
635 clocks = <&clk_gates12 3>;
636 rockchip,check-idle = <1>;
642 compatible = "rockchip,rk30-i2c";
643 reg = <0x0 0xff140000 0x0 0x1000>;
644 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
645 #address-cells = <1>;
647 pinctrl-names = "default", "gpio";
648 pinctrl-0 = <&i2c2_xfer>;
649 pinctrl-1 = <&i2c2_gpio>;
650 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
651 clocks = <&clk_gates19 11>;
652 rockchip,check-idle = <1>;
658 compatible = "rockchip,rk30-i2c";
659 reg = <0x0 0xff150000 0x0 0x1000>;
660 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
661 #address-cells = <1>;
663 pinctrl-names = "default", "gpio";
664 pinctrl-0 = <&i2c3_xfer>;
665 pinctrl-1 = <&i2c3_gpio>;
666 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
667 clocks = <&clk_gates19 12>;
668 rockchip,check-idle = <1>;
674 compatible = "rockchip,rk30-i2c";
675 reg = <0x0 0xff160000 0x0 0x1000>;
676 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
677 #address-cells = <1>;
679 pinctrl-names = "default", "gpio";
680 pinctrl-0 = <&i2c4_xfer>;
681 pinctrl-1 = <&i2c4_gpio>;
682 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
683 clocks = <&clk_gates19 13>;
684 rockchip,check-idle = <1>;
690 compatible = "rockchip,rk30-i2c";
691 reg = <0x0 0xff170000 0x0 0x1000>;
692 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
693 #address-cells = <1>;
695 pinctrl-names = "default", "gpio";
696 pinctrl-0 = <&i2c5_xfer>;
697 pinctrl-1 = <&i2c5_gpio>;
698 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
699 clocks = <&clk_gates19 14>;
700 rockchip,check-idle = <1>;
705 compatible = "rockchip,rk-fb";
706 rockchip,disp-mode = <NO_DUAL>;
710 rk_screen: rk_screen {
711 compatible = "rockchip,screen";
714 dsihost0: mipi@ff960000{
715 compatible = "rockchip,rk3368-dsi";
717 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
718 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
719 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>;
721 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
725 lvds: lvds@ff968000 {
726 compatible = "rockchip,rk3368-lvds";
727 rockchip,grf = <&grf>;
728 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
729 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
730 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
731 clock-names = "pclk_lvds", "pclk_lvds_ctl";
736 compatible = "rockchip,rk32-edp";
737 reg = <0x0 0xff970000 0x0 0x4000>;
738 rockchip,grf = <&grf>;
739 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
741 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
742 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
743 reset-names = "edp_24m", "edp_apb";
746 hdmi: hdmi@ff980000 {
747 compatible = "rockchip,rk3368-hdmi";
748 reg = <0x0 0xff980000 0x0 0x20000>;
749 rockchip,grf = <&grf>;
750 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
751 pinctrl-names = "default", "gpio";
752 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
753 pinctrl-1 = <&i2c5_gpio>;
754 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
755 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
759 hdmi_hdcp2: hdmi_hdcp2@ff978000 {
760 compatible = "rockchip,rk3368-hdmi-hdcp2";
761 reg = <0x0 0xff978000 0x0 0x2000>;
762 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
764 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
768 lcdc: lcdc@ff930000 {
769 compatible = "rockchip,rk3368-lcdc";
770 rockchip,grf = <&grf>;
771 rockchip,pmugrf = <&pmugrf>;
772 rockchip,prop = <PRMRY>;
773 rockchip,pwr18 = <0>;
774 rockchip,iommu-enabled = <0>;
775 reg = <0x0 0xff930000 0x0 0x10000>;
776 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
777 /*pinctrl-names = "default", "gpio";
778 *pinctrl-0 = <&lcdc_lcdc>;
779 *pinctrl-1 = <&lcdc_gpio>;
782 clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
783 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
787 compatible = "rockchip,saradc";
788 reg = <0x0 0xff100000 0x0 0x100>;
789 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
790 #io-channel-cells = <1>;
792 rockchip,adc-vref = <1800>;
793 clock-frequency = <1000000>;
794 clocks = <&clk_saradc>, <&clk_gates19 15>;
795 clock-names = "saradc", "pclk_saradc";
800 compatible = "rockchip,rk3368-rga2";
801 reg = <0x0 0xff920000 0x0 0x1000>;
802 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
804 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
807 i2s0: i2s0@ff898000 {
808 compatible = "rockchip-i2s";
809 reg = <0x0 0xff898000 0x0 0x1000>;
811 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
812 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
813 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
814 dmas = <&pdma0 0>, <&pdma0 1>;
816 dma-names = "tx", "rx";
817 pinctrl-names = "default", "sleep";
818 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
819 pinctrl-1 = <&i2s_gpio>;
822 i2s1: i2s1@ff890000 {
823 compatible = "rockchip-i2s";
824 reg = <0x0 0xff890000 0x0 0x1000>;
826 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
827 clock-names = "i2s_clk", "i2s_hclk";
828 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
829 dmas = <&pdma0 6>, <&pdma0 7>;
831 dma-names = "tx", "rx";
834 spdif: spdif@ff880000 {
835 compatible = "rockchip-spdif";
836 reg = <0x0 0xff880000 0x0 0x1000>;
837 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
838 clock-names = "spdif_mclk", "spdif_hclk";
839 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
843 pinctrl-names = "default";
844 pinctrl-0 = <&spdif_tx>;
848 compatible = "rockchip,rk-pwm";
849 reg = <0x0 0xff680000 0x0 0x10>;
851 pinctrl-names = "default";
852 pinctrl-0 = <&pwm0_pin>;
853 clocks = <&clk_gates13 6>;
854 clock-names = "pclk_pwm";
859 compatible = "rockchip,rk-pwm";
860 reg = <0x0 0xff680010 0x0 0x10>;
862 pinctrl-names = "default";
863 pinctrl-0 = <&pwm1_pin>;
864 clocks = <&clk_gates13 6>;
865 clock-names = "pclk_pwm";
870 compatible = "rockchip,rk-pwm";
871 reg = <0x0 0xff680020 0x0 0x10>;
873 //pinctrl-names = "default";
874 //pinctrl-0 = <&pwm1_pin>;
875 clocks = <&clk_gates13 6>;
876 clock-names = "pclk_pwm";
881 compatible = "rockchip,rk-pwm";
882 reg = <0x0 0xff680030 0x0 0x10>;
884 pinctrl-names = "default";
885 pinctrl-0 = <&pwm3_pin>;
886 clocks = <&clk_gates13 6>;
887 clock-names = "pclk_pwm";
891 remotectl: pwm@ff680030 {
892 compatible = "rockchip,remotectl-pwm";
893 reg = <0x0 0xff680030 0x0 0x50>;
895 pinctrl-names = "default";
896 pinctrl-0 = <&pwm3_pin>;
897 clocks = <&clk_gates13 6>;
898 clock-names = "pclk_pwm";
903 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
907 voppwm: pwm@ff9301a0 {
908 compatible = "rockchip,vop-pwm";
909 reg = <0x0 0xff9301a0 0x0 0x10>;
911 pinctrl-names = "default";
912 pinctrl-0 = <&vop_pwm_pin>;
913 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
914 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
919 compatible = "rockchip,rk3368-pvtm";
920 rockchip,grf = <&grf>;
921 rockchip,pmugrf = <&pmugrf>;
922 rockchip,pvtm-clk-out = <1>;
926 compatible = "rockchip,rk3368-cpufreq";
927 rockchip,grf = <&grf>;
933 regulator_name = "vdd_arm";
934 suspend_volt = <1000>; //mV
936 clk_core_b_dvfs_table: clk_core_b {
946 clk_core_l_dvfs_table: clk_core_l {
960 regulator_name = "vdd_logic";
961 suspend_volt = <1000>; //mV
963 clk_ddr_dvfs_table: clk_ddr {
976 clk_gpu_dvfs_table: clk_gpu {
997 compatible = "rockchip,ion";
998 #address-cells = <1>;
1001 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1002 compatible = "rockchip,ion-heap";
1003 rockchip,ion_heap = <4>;
1004 reg = <0x00000000 0x08000000>; /* 512MB */
1006 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1007 compatible = "rockchip,ion-heap";
1008 rockchip,ion_heap = <0>;
1013 compatible = "rockchip,vpu_sub";
1014 iommu_enabled = <0>;
1015 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1017 interrupt-names = "irq_enc", "irq_dec";
1019 name = "vpu_service";
1022 hevc: hevc_service {
1023 compatible = "rockchip,hevc_sub";
1024 iommu_enabled = <0>;
1025 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1026 interrupt-names = "irq_dec";
1028 name = "hevc_service";
1031 vpu_combo: vpu_combo@ff9a0000 {
1032 compatible = "rockchip,vpu_combo";
1033 reg = <0x0 0xff9a0000 0x0 0x800>;
1034 rockchip,grf = <&grf>;
1036 rockchip,sub = <&vpu>, <&hevc>;
1037 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1038 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1040 mode_ctrl = <0x418>;
1046 compatible = "rockchip,iep";
1047 iommu_enabled = <0>;
1048 reg = <0x0 0xff900000 0x0 0x800>;
1049 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1050 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1051 clock-names = "aclk_iep", "hclk_iep";
1055 gmac: eth@ff290000 {
1056 compatible = "rockchip,rk3368-gmac";
1057 reg = <0x0 0xff290000 0x0 0x10000>;
1058 rockchip,grf = <&grf>;
1059 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1060 interrupt-names = "macirq";
1062 clocks = <&clk_mac>, <&clk_gates7 4>,
1063 <&clk_gates7 5>, <&clk_gates7 6>,
1064 <&clk_gates7 7>, <&clk_gates20 13>,
1066 clock-names = "clk_mac", "mac_clk_rx",
1067 "mac_clk_tx", "clk_mac_ref",
1068 "clk_mac_refout", "aclk_mac",
1072 pinctrl-names = "default";
1073 pinctrl-0 = <&rgmii_pins>;
1077 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1078 reg = <0x0 0xffa30000 0x0 0x10000>;
1079 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1080 interrupt-names = "GPU";
1085 compatible = "rockchip,iep_mmu";
1086 reg = <0x0 0xff900800 0x0 0x100>;
1087 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1088 interrupt-names = "iep_mmu";
1093 compatible = "rockchip,vip_mmu";
1094 reg = <0x0 0xff950800 0x0 0x100>;
1095 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1096 interrupt-names = "vip_mmu";
1101 compatible = "rockchip,vopb_mmu";
1102 reg = <0x0 0xff930300 0x0 0x100>;
1103 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1104 interrupt-names = "vop_mmu";
1108 dbgname = "isp_mmu";
1109 compatible = "rockchip,isp_mmu";
1110 reg = <0x0 0xff914000 0x0 0x100>,
1111 <0x0 0xff915000 0x0 0x100>;
1112 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1113 interrupt-names = "isp_mmu";
1117 dbgname = "hdcp_mmu";
1118 compatible = "rockchip,hdcp_mmu";
1119 reg = <0x0 0xff940000 0x0 0x100>;
1120 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1121 interrupt-names = "hdcp_mmu";
1126 compatible = "rockchip,hevc_mmu";
1127 reg = <0x0 0xff9c0440 0x0 0x40>, /*need to fix*/
1128 <0x0 0xff9c0480 0x0 0x40>;
1129 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1130 interrupt-names = "hevc_mmu";
1135 compatible = "rockchip,vpu_mmu";
1136 reg = <0x0 0xff9a0800 0x0 0x100>; /*need to fix*/
1137 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1138 interrupt-names = "vpu_mmu";
1142 rockchip,ctrbits = <
1149 |RKPM_CTR_SYSCLK_DIV
1150 |RKPM_CTR_IDLEAUTO_MD
1151 |RKPM_CTR_ARMOFF_LPMD
1153 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1156 rockchip,pmic-suspend_gpios = <
1157 /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1159 rockchip,pmic-resume_gpios = <
1160 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1165 compatible = "rockchip,isp";
1166 reg = <0x0 0xff910000 0x0 0x10000>;
1167 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1168 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1169 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1170 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1171 pinctrl-0 = <&cif_clkout>;
1172 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1173 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1174 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1175 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1176 pinctrl-5 = <&cif_clkout>;
1177 pinctrl-6 = <&cif_clkout &isp_prelight>;
1178 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1179 pinctrl-8 = <&isp_flash_trigger>;
1180 rockchip,isp,mipiphy = <2>;
1181 rockchip,isp,cifphy = <1>;
1182 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1183 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1184 rockchip,grf = <&grf>;
1185 rockchip,cru = <&cru>;
1186 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1187 rockchip,isp,iommu_enable = <0>;
1192 compatible = "rockchip,cif";
1193 reg = <0x0 0xff950000 0x0 0x10000>;
1194 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1195 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1196 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1197 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1198 pinctrl-names = "cif_pin_all";
1199 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1200 rockchip,grf = <&grf>;
1201 rockchip,cru = <&cru>;
1207 #include "rk3368-thermal.dtsi"
1211 tsadc: tsadc@ff280000 {
1212 compatible = "rockchip,rk3368-tsadc";
1213 reg = <0x0 0xff280000 0x0 0x100>;
1214 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1216 rockchip,grf = <&grf>;
1217 rockchip,cru = <&cru>;
1218 rockchip,pmu = <&pmu>;
1219 clock-names = "tsadc", "apb_pclk";
1220 clock-frequency = <32000>;
1221 resets = <&reset RK3368_SRST_TSADC_P>;
1222 reset-names = "tsadc-apb";
1223 //pinctrl-names = "default";
1224 //pinctrl-0 = <&tsadc_int>;
1225 #thermal-sensor-cells = <1>;
1226 hw-shut-temp = <120000>;
1227 status = "disabled";
1231 compatible = "rockchip,rk3368-tsp";
1232 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1233 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1234 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1235 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1236 interrupt-names = "irq_tsp";
1237 // pinctrl-names = "default";
1238 // pinctrl-0 = <&isp_hsadc>;
1242 crypto: crypto@FF8A0000{
1243 compatible = "rockchip,rk3368-crypto";
1244 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1245 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1246 interrupt-names = "irq_crypto";
1247 clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1248 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1252 dwc_control_usb: dwc-control-usb {
1253 compatible = "rockchip,rk3368-dwc-control-usb";
1254 rockchip,grf = <&grf>;
1255 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1256 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1257 interrupt-names = "otg_id", "otg_bvalid",
1258 "otg_linestate", "host0_linestate";
1259 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1260 clock-names = "hclk_usb_peri", "usbphy_480m";
1261 //resets = <&reset RK3128_RST_USBPOR>;
1262 //reset-names = "usbphy_por";
1264 compatible = "inno,phy";
1265 regbase = &dwc_control_usb;
1266 rk_usb,bvalid = <0x4bc 23 1>;
1267 rk_usb,iddig = <0x4bc 26 1>;
1268 rk_usb,vdmsrcen = <0x718 12 1>;
1269 rk_usb,vdpsrcen = <0x718 11 1>;
1270 rk_usb,rdmpden = <0x718 10 1>;
1271 rk_usb,idpsrcen = <0x718 9 1>;
1272 rk_usb,idmsinken = <0x718 8 1>;
1273 rk_usb,idpsinken = <0x718 7 1>;
1274 rk_usb,dpattach = <0x4b8 31 1>;
1275 rk_usb,cpdet = <0x4b8 30 1>;
1276 rk_usb,dcpattach = <0x4b8 29 1>;
1280 usb0: usb@ff580000 {
1281 compatible = "rockchip,rk3368_usb20_otg";
1282 reg = <0x0 0xff580000 0x0 0x40000>;
1283 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1284 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1285 clock-names = "clk_usbphy0", "hclk_otg";
1286 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1287 <&reset RK3368_SRST_USBOTGC0>;
1288 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1289 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1290 rockchip,usb-mode = <0>;
1293 usb_ehci: usb@ff500000 {
1294 compatible = "generic-ehci";
1295 reg = <0x0 0xff500000 0x0 0x20000>;
1296 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1297 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1298 clock-names = "clk_usbphy0", "hclk_ehci";
1299 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1300 // <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1301 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1304 usb_ohci: usb@ff520000 {
1305 compatible = "generic-ohci";
1306 reg = <0x0 0xff520000 0x0 0x20000>;
1307 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1308 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1309 clock-names = "clk_usbphy0", "hclk_ohci";
1312 usb_hsic: usb@ff5c0000 {
1313 compatible = "rockchip,rk3288_rk_hsic_host";
1314 reg = <0x0 0xff5c0000 0x0 0x40000>;
1315 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1317 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1318 <&hsicphy_12m>, <&usbphy_480m>,
1319 <&otgphy1_480m>, <&otgphy2_480m>;
1320 clock-names = "hsicphy_480m", "hclk_hsic",
1321 "hsicphy_12m", "usbphy_480m",
1322 "hsic_usbphy1", "hsic_usbphy2";
1323 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1324 <&reset RK3288_SOFT_RST_HSICPHY>;
1325 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1327 status = "disabled";
1331 compatible = "rockchip,rk3368-pinctrl";
1332 rockchip,grf = <&grf>;
1333 rockchip,pmugrf = <&pmugrf>;
1334 #address-cells = <2>;
1338 gpio0: gpio0@ff750000 {
1339 compatible = "rockchip,gpio-bank";
1340 reg = <0x0 0xff750000 0x0 0x100>;
1341 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1342 clocks = <&clk_gates23 4>;
1347 interrupt-controller;
1348 #interrupt-cells = <2>;
1351 gpio1: gpio1@ff780000 {
1352 compatible = "rockchip,gpio-bank";
1353 reg = <0x0 0xff780000 0x0 0x100>;
1354 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1355 clocks = <&clk_gates22 1>;
1360 interrupt-controller;
1361 #interrupt-cells = <2>;
1364 gpio2: gpio2@ff790000 {
1365 compatible = "rockchip,gpio-bank";
1366 reg = <0x0 0xff790000 0x0 0x100>;
1367 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1368 clocks = <&clk_gates22 2>;
1373 interrupt-controller;
1374 #interrupt-cells = <2>;
1377 gpio3: gpio3@ff7a0000 {
1378 compatible = "rockchip,gpio-bank";
1379 reg = <0x0 0xff7a0000 0x0 0x100>;
1380 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1381 clocks = <&clk_gates22 3>;
1386 interrupt-controller;
1387 #interrupt-cells = <2>;
1390 pcfg_pull_up: pcfg-pull-up {
1394 pcfg_pull_down: pcfg-pull-down {
1398 pcfg_pull_none: pcfg-pull-none {
1402 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1403 drive-strength = <8>;
1406 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1407 drive-strength = <12>;
1410 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1412 drive-strength = <8>;
1415 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1416 drive-strength = <4>;
1419 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1421 drive-strength = <4>;
1424 pcfg_output_high: pcfg-output-high {
1428 pcfg_output_low: pcfg-output-low {
1433 i2c0_xfer: i2c0-xfer {
1434 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1435 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1437 i2c0_gpio: i2c0-gpio {
1438 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1439 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1444 i2c1_xfer: i2c1-xfer {
1445 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1446 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1448 i2c1_gpio: i2c1-gpio {
1449 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1450 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1455 i2c2_xfer: i2c2-xfer {
1456 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1457 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1459 i2c2_gpio: i2c2-gpio {
1460 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1461 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1466 i2c3_xfer: i2c3-xfer {
1467 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1468 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1470 i2c3_gpio: i2c3-gpio {
1471 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1472 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1477 i2c4_xfer: i2c4-xfer {
1478 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1479 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1481 i2c4_gpio: i2c4-gpio {
1482 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1483 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1488 i2c5_xfer: i2c5-xfer {
1489 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1490 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1492 i2c5_gpio: i2c5-gpio {
1493 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1494 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1499 uart0_xfer: uart0-xfer {
1500 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1501 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1504 uart0_cts: uart0-cts {
1505 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1508 uart0_rts: uart0-rts {
1509 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1512 uart0_rts_gpio: uart0-rts-gpio {
1513 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1518 uart1_xfer: uart1-xfer {
1519 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1520 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1523 uart1_cts: uart1-cts {
1524 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1527 uart1_rts: uart1-rts {
1528 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1533 uart2_xfer: uart2-xfer {
1534 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1535 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1540 uart3_xfer: uart3-xfer {
1541 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1542 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1545 uart3_cts: uart3-cts {
1546 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1549 uart3_rts: uart3-rts {
1550 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1555 uart4_xfer: uart4-xfer {
1556 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1557 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1560 uart4_cts: uart4-cts {
1561 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1564 uart4_rts: uart4-rts {
1565 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1570 spi0_clk: spi0-clk {
1571 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1573 spi0_cs0: spi0-cs0 {
1574 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1577 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1580 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1582 spi0_cs1: spi0-cs1 {
1583 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1588 spi1_clk: spi1-clk {
1589 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1591 spi1_cs0: spi1-cs0 {
1592 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1595 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1598 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1603 spi2_clk: spi2-clk {
1604 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1606 spi2_cs0: spi2-cs0 {
1607 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1610 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1613 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1618 i2s_mclk: i2s-mclk {
1619 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1623 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1626 i2s_lrckrx:i2s-lrckrx {
1627 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1630 i2s_lrcktx:i2s-lrcktx {
1631 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1635 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1639 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1643 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1647 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1651 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1654 i2s_gpio: i2s-gpio {
1655 rockchip,pins = <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,
1656 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1657 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1658 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1659 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1660 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1661 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1662 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1663 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1668 spdif_tx: spdif-tx {
1669 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1674 sdmmc_clk: sdmmc-clk {
1675 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1678 sdmmc_cmd: sdmmc-cmd {
1679 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1682 sdmmc_dectn: sdmmc-dectn {
1683 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1686 sdmmc_bus1: sdmmc-bus1 {
1687 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1690 sdmmc_bus4: sdmmc-bus4 {
1691 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1692 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1693 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1694 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1697 sdmmc_gpio: sdmmc-gpio {
1698 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1699 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1700 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1701 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1702 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1703 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1704 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1709 sdio0_bus1: sdio0-bus1 {
1710 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1713 sdio0_bus4: sdio0-bus4 {
1714 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1715 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1716 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1717 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1720 sdio0_cmd: sdio0-cmd {
1721 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1724 sdio0_clk: sdio0-clk {
1725 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1728 sdio0_dectn: sdio0-dectn {
1729 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1732 sdio0_wrprt: sdio0-wrprt {
1733 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1736 sdio0_pwren: sdio0-pwren {
1737 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1740 sdio0_bkpwr: sdio0-bkpwr {
1741 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1744 sdio0_int: sdio0-int {
1745 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1748 sdio0_gpio: sdio0-gpio {
1749 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1750 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1751 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1752 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1753 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1754 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1755 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1756 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1757 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1758 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1759 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1764 emmc_clk: emmc-clk {
1765 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1768 emmc_cmd: emmc-cmd {
1769 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1772 emmc_pwren: emmc-pwren {
1773 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1776 emmc_rstnout: emmc_rstnout {
1777 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1780 emmc_bus1: emmc-bus1 {
1781 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1784 emmc_bus4: emmc-bus4 {
1785 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1786 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1787 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1788 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1793 pwm0_pin: pwm0-pin {
1794 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1797 vop_pwm_pin:vop-pwm {
1798 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1803 pwm1_pin: pwm1-pin {
1804 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1809 pwm3_pin: pwm3-pin {
1810 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1815 lcdc_lcdc: lcdc-lcdc {
1817 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1818 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1819 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1820 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1821 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1822 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1823 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1824 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1825 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1826 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1827 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1828 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1829 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1830 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1831 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1832 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1833 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1834 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1837 lcdc_gpio: lcdc-gpio {
1839 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1840 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1841 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1842 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1843 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1844 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1845 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1846 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1847 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1848 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1849 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1850 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1851 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1852 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1853 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1854 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1855 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1856 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1861 cif_clkout: cif-clkout {
1862 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1865 isp_dvp_d2d9: isp-dvp-d2d9 {
1866 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1867 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1868 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1869 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1870 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1871 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1872 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1873 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1874 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1875 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1876 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1877 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1880 isp_dvp_d0d1: isp-dvp-d0d1 {
1881 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1882 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1885 isp_dvp_d10d11:isp_d10d11 {
1886 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1887 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1890 isp_dvp_d0d7: isp-dvp-d0d7 {
1891 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1892 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1893 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1894 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1895 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1896 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1897 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1898 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1901 isp_shutter: isp-shutter {
1902 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1903 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1906 isp_flash_trigger: isp-flash-trigger {
1907 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1910 isp_prelight: isp-prelight {
1911 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1914 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1915 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1921 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1925 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1929 gps_rfclk: gps-rfclk {
1930 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1935 rgmii_pins: rgmii-pins {
1936 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1937 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1938 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1939 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1940 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1941 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
1942 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
1943 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
1944 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1945 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1946 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1947 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1948 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1949 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1950 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
1953 rmii_pins: rmii-pins {
1954 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1955 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1956 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1957 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1958 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1959 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1960 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1961 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1962 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1963 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
1968 tsadc_int: tsadc-int {
1969 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1971 tsadc_gpio: tsadc-gpio {
1972 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1977 hdmi_cec: hdmi-cec {
1978 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1983 hdmii2c_xfer: hdmii2c-xfer {
1984 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
1985 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1990 cpu_jtag: cpu-jtag {
1991 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
1992 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
1998 compatible = "rockchip,rk3368-reboot";
1999 rockchip,cru = <&cru>;
2000 rockchip,pmugrf = <&pmugrf>;