arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 big0: cpu@100 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53", "arm,armv8";
  43                         reg = <0x0 0x100>;
  44                         enable-method = "psci";
  45                 };
  46                 big1: cpu@101 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53", "arm,armv8";
  49                         reg = <0x0 0x101>;
  50                         enable-method = "psci";
  51                 };
  52                 big2: cpu@102 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a53", "arm,armv8";
  55                         reg = <0x0 0x102>;
  56                         enable-method = "psci";
  57                 };
  58                 big3: cpu@103 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x103>;
  62                         enable-method = "psci";
  63                 };
  64                 little0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53", "arm,armv8";
  67                         reg = <0x0 0x0>;
  68                         enable-method = "psci";
  69                 };
  70                 little1: cpu@1 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a53", "arm,armv8";
  73                         reg = <0x0 0x1>;
  74                         enable-method = "psci";
  75                 };
  76                 little2: cpu@2 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53", "arm,armv8";
  79                         reg = <0x0 0x2>;
  80                         enable-method = "psci";
  81                 };
  82                 little3: cpu@3 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53", "arm,armv8";
  85                         reg = <0x0 0x3>;
  86                         enable-method = "psci";
  87                 };
  88
  89                 cpu-map {
  90                         cluster0 {
  91                                 core0 {
  92                                         cpu = <&big0>;
  93                                 };
  94                                 core1 {
  95                                         cpu = <&big1>;
  96                                 };
  97                                 core2 {
  98                                         cpu = <&big2>;
  99                                 };
 100                                 core3 {
 101                                         cpu = <&big3>;
 102                                 };
 103                         };
 104                         cluster1 {
 105                                 core0 {
 106                                         cpu = <&little0>;
 107                                 };
 108                                 core1 {
 109                                         cpu = <&little1>;
 110                                 };
 111                                 core2 {
 112                                         cpu = <&little2>;
 113                                 };
 114                                 core3 {
 115                                         cpu = <&little3>;
 116                                 };
 117                         };
 118                 };
 119         };
 120
 121         psci {
 122                 compatible = "arm,psci";
 123                 method = "smc";
 124                 cpu_on = <0xC4000003>;
 125         };
 126
 127         gic: interrupt-controller@ffb70000 {
 128                 compatible = "arm,cortex-a15-gic";
 129                 #interrupt-cells = <3>;
 130                 #address-cells = <0>;
 131                 interrupt-controller;
 132                 reg = <0x0 0xffb71000 0 0x1000>,
 133                       <0x0 0xffb72000 0 0x1000>;
 134         };
 135
 136         pmu: syscon@ff730000 {
 137                 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
 138                 reg = <0x0 0xff730000 0x0 0x1000>;
 139         };
 140
 141         pmugrf: syscon@ff738000 {
 142                 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
 143                 reg = <0x0 0xff738000 0x0 0x1000>;
 144         };
 145
 146         sgrf: syscon@ff740000 {
 147                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 148                 reg = <0x0 0xff740000 0x0 0x1000>;
 149
 150         };
 151
 152         cru: syscon@ff760000 {
 153                 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
 154                 reg = <0x0 0xff760000 0x0 0x1000>;
 155         };
 156
 157         grf: syscon@ff770000 {
 158                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 159                 reg = <0x0 0xff770000 0x0 0x1000>;
 160         };
 161
 162         arm-pmu {
 163                 compatible = "arm,armv8-pmuv3";
 164                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 172         };
 173
 174         cpu_axi_bus: cpu_axi_bus {
 175                 compatible = "rockchip,cpu_axi_bus";
 176                 #address-cells = <2>;
 177                 #size-cells = <2>;
 178                 ranges;
 179
 180                 qos {
 181                         #address-cells = <2>;
 182                         #size-cells = <2>;
 183                         ranges;
 184
 185                         dmac {
 186                                 reg = <0x0 0xffa80000 0x0 0x20>;
 187                         };
 188                         crypto {
 189                                 reg = <0x0 0xffa80080 0x0 0x20>;
 190                         };
 191                         bus_cpup {
 192                                 reg = <0x0 0xffa90000 0x0 0x20>;
 193                         };
 194                         cci_r {
 195                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 196                         };
 197                         cci_w {
 198                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 199                         };
 200                         peri {
 201                                 reg = <0x0 0xffab0000 0x0 0x20>;
 202                         };
 203                         iep {
 204                                 reg = <0x0 0xffad0000 0x0 0x20>;
 205                         };
 206                         isp_r0 {
 207                                 reg = <0x0 0xffad0080 0x0 0x20>;
 208                         };
 209                         isp_r1 {
 210                                 reg = <0x0 0xffad0100 0x0 0x20>;
 211                         };
 212                         isp_w0 {
 213                                 reg = <0x0 0xffad0180 0x0 0x20>;
 214                                 rockchip,priority = <2 2>;
 215                         };
 216                         isp_w1 {
 217                                 reg = <0x0 0xffad0200 0x0 0x20>;
 218                                 rockchip,priority = <2 2>;
 219                         };
 220                         vip {
 221                                 reg = <0x0 0xffad0280 0x0 0x20>;
 222                         };
 223                         vop {
 224                                 reg = <0x0 0xffad0300 0x0 0x20>;
 225                                 rockchip,priority = <2 2>;
 226                         };
 227                         rga_r {
 228                                 reg = <0x0 0xffad0380 0x0 0x20>;
 229                         };
 230                         rga_w {
 231                                 reg = <0x0 0xffad0400 0x0 0x20>;
 232                         };
 233                         hevc_r {
 234                                 reg = <0x0 0xffae0000 0x0 0x20>;
 235                         };
 236                         vpu_r {
 237                                 reg = <0x0 0xffae0080 0x0 0x20>;
 238                         };
 239                         vpu_w {
 240                                 reg = <0x0 0xffae0100 0x0 0x20>;
 241                         };
 242                 };
 243
 244                 msch {
 245                         #address-cells = <2>;
 246                         #size-cells = <2>;
 247                         ranges;
 248
 249                         msch {
 250                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 251                                 rockchip,read-latency = <0x34>;
 252                         };
 253                 };
 254         };
 255
 256         timer {
 257                 compatible = "arm,armv8-timer";
 258                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 259                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 260                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 261                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 262                 clock-frequency = <24000000>;
 263         };
 264
 265         timer@ff810000 {
 266                 compatible = "rockchip,timer";
 267                 reg = <0x0 0xff810000 0x0 0x20>;
 268                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 269                 rockchip,broadcast = <1>;
 270         };
 271
 272         sram: sram@ff8c0000 {
 273                 compatible = "mmio-sram";
 274                 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
 275                 map-exec;
 276         };
 277
 278         watchdog: wdt@ff800000 {
 279                 compatible = "rockchip,watch dog";
 280                 reg = <0x0 0xff800000 0x0 0x100>;
 281                 clocks = <&pclk_alive_pre>;
 282                 clock-names = "pclk_wdt";
 283                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 284                 rockchip,irq = <1>;
 285                 rockchip,timeout = <60>;
 286                 rockchip,atboot = <1>;
 287                 rockchip,debug = <0>;
 288                 status = "disabled";
 289         };
 290
 291         amba {
 292                 #address-cells = <2>;
 293                 #size-cells = <2>;
 294                 compatible = "arm,amba-bus";
 295                 interrupt-parent = <&gic>;
 296                 ranges;
 297
 298                 pdma0: pdma@ff600000 {
 299                         compatible = "arm,pl330", "arm,primecell";
 300                         reg = <0x0 0xff600000 0x0 0x4000>;
 301                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 302                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 303                         #dma-cells = <1>;
 304                 };
 305
 306                 pdma1: pdma@ff250000 {
 307                         compatible = "arm,pl330", "arm,primecell";
 308                         reg = <0x0 0xff250000 0x0 0x4000>;
 309                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 310                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 311                         #dma-cells = <1>;
 312                 };
 313         };
 314
 315         reset: reset@ff760300{
 316                 compatible = "rockchip,reset";
 317                 reg = <0x0 0xff760300 0x0 0x38>;
 318                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 319                 #reset-cells = <1>;
 320         };
 321
 322         nandc0: nandc@ff400000 {
 323                 compatible = "rockchip,rk-nandc";
 324                 reg = <0x0 0xff400000 0x0 0x4000>;
 325                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 326                 nandc_id = <0>;
 327                 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
 328                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 329         };
 330
 331         nandc0reg: nandc0@ff400000 {
 332                 compatible = "rockchip,rk-nandc";
 333                 reg = <0x0 0xff400000 0x0 0x4000>;
 334         };
 335
 336         emmc: rksdmmc@ff0f0000 {
 337                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 338                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 339                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
 343                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 344                 rockchip,grf = <&grf>;
 345                 num-slots = <1>;
 346                 fifo-depth = <0x100>;
 347                 bus-width = <8>;
 348         };
 349
 350         sdmmc: rksdmmc@ff0c0000 {
 351                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 352                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 353                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 354                 #address-cells = <1>;
 355                 #size-cells = <0>;
 356                 pinctrl-names = "default", "idle";
 357                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 358                 pinctrl-1 = <&sdmmc_gpio>;
 359                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 360                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
 361                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 362                 rockchip,grf = <&grf>;
 363                 num-slots = <1>;
 364                 fifo-depth = <0x100>;
 365                 bus-width = <4>;
 366         };
 367
 368         sdio: rksdmmc@ff0d0000 {
 369                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 370                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 371                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 pinctrl-names = "default","idle";
 375                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 376                 pinctrl-1 = <&sdio0_gpio>;
 377                 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
 378                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 379                 rockchip,grf = <&grf>;
 380                 num-slots = <1>;
 381                 fifo-depth = <0x100>;
 382                 bus-width = <4>;
 383         };
 384
 385         spi0: spi@ff110000 {
 386                 compatible = "rockchip,rockchip-spi";
 387                 reg = <0x0 0xff110000 0x0 0x1000>;
 388                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 389                 #address-cells = <1>;
 390                 #size-cells = <0>;
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 393                 rockchip,spi-src-clk = <0>;
 394                 num-cs = <2>;
 395                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 396                 clock-names = "spi", "pclk_spi0";
 397                 //dmas = <&pdma1 11>, <&pdma1 12>;
 398                 //#dma-cells = <2>;
 399                 //dma-names = "tx", "rx";
 400                 status = "disabled";
 401         };
 402
 403         spi1: spi@ff120000 {
 404                 compatible = "rockchip,rockchip-spi";
 405                 reg = <0x0 0xff120000 0x0 0x1000>;
 406                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 411                 rockchip,spi-src-clk = <1>;
 412                 num-cs = <1>;
 413                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 414                 clock-names = "spi", "pclk_spi1";
 415                 //dmas = <&pdma1 13>, <&pdma1 14>;
 416                 //#dma-cells = <2>;
 417                 //dma-names = "tx", "rx";
 418                 status = "disabled";
 419         };
 420
 421         spi2: spi@ff130000 {
 422                 compatible = "rockchip,rockchip-spi";
 423                 reg = <0x0 0xff130000 0x0 0x1000>;
 424                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 425                 #address-cells = <1>;
 426                 #size-cells = <0>;
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 429                 rockchip,spi-src-clk = <2>;
 430                 num-cs = <1>;
 431                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 432                 clock-names = "spi", "pclk_spi2";
 433                 //dmas = <&pdma1 15>, <&pdma1 16>;
 434                 //#dma-cells = <2>;
 435                 //dma-names = "tx", "rx";
 436                 status = "disabled";
 437         };
 438
 439         uart_bt: serial@ff180000 {
 440                 compatible = "rockchip,serial";
 441                 reg = <0x0 0xff180000 0x0 0x100>;
 442                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 443                 clock-frequency = <24000000>;
 444                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 445                 clock-names = "sclk_uart", "pclk_uart";
 446                 reg-shift = <2>;
 447                 reg-io-width = <4>;
 448                 //dmas = <&pdma1 1>, <&pdma1 2>;
 449                 //#dma-cells = <2>;
 450                 pinctrl-names = "default";
 451                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 452                 status = "disabled";
 453         };
 454
 455         uart_bb: serial@ff190000 {
 456                 compatible = "rockchip,serial";
 457                 reg = <0x0 0xff190000 0x0 0x100>;
 458                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 459                 clock-frequency = <24000000>;
 460                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 461                 clock-names = "sclk_uart", "pclk_uart";
 462                 reg-shift = <2>;
 463                 reg-io-width = <4>;
 464                 //dmas = <&pdma1 3>, <&pdma1 4>;
 465                 //#dma-cells = <2>;
 466                 pinctrl-names = "default";
 467                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 468                 status = "disabled";
 469         };
 470
 471         uart_dbg: serial@ff690000 {
 472                 compatible = "rockchip,serial";
 473                 reg = <0x0 0xff690000 0x0 0x100>;
 474                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 475                 clock-frequency = <24000000>;
 476                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 477                 clock-names = "sclk_uart", "pclk_uart";
 478                 reg-shift = <2>;
 479                 reg-io-width = <4>;
 480                 //dmas = <&pdma0 4>, <&pdma0 5>;
 481                 //#dma-cells = <2>;
 482                 //pinctrl-names = "default";
 483                 //pinctrl-0 = <&uart2_xfer>;
 484                 status = "disabled";
 485         };
 486
 487         uart_gps: serial@ff1b0000 {
 488                 compatible = "rockchip,serial";
 489                 reg = <0x0 0xff1b0000 0x0 0x100>;
 490                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 491                 clock-frequency = <24000000>;
 492                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 493                 clock-names = "sclk_uart", "pclk_uart";
 494                 current-speed = <115200>;
 495                 reg-shift = <2>;
 496                 reg-io-width = <4>;
 497                 //dmas = <&pdma1 7>, <&pdma1 8>;
 498                 //#dma-cells = <2>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 501                 status = "disabled";
 502         };
 503
 504         uart_exp: serial@ff1c0000 {
 505                 compatible = "rockchip,serial";
 506                 reg = <0x0 0xff1c0000 0x0 0x100>;
 507                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 508                 clock-frequency = <24000000>;
 509                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 510                 clock-names = "sclk_uart", "pclk_uart";
 511                 reg-shift = <2>;
 512                 reg-io-width = <4>;
 513                 //dmas = <&pdma1 9>, <&pdma1 10>;
 514                 //#dma-cells = <2>;
 515                 pinctrl-names = "default";
 516                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 517                 status = "disabled";
 518         };
 519
 520         rockchip_clocks_init: clocks-init{
 521                 compatible = "rockchip,clocks-init";
 522                 rockchip,clocks-init-parent =
 523                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 524                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 525                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 526                         <&clk_cs &clk_gpll>;
 527                 rockchip,clocks-init-rate =
 528                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 529                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 530                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 531                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 532                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 533                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 534                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 535                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 536                         <&aclk_cci 600000000>,          <&clk_mac 125000000>,
 537                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 538                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 539                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 540                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 541                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 542                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 543                         <&clk_hevc_cabac 300000000>;
 544 /*
 545                 rockchip,clocks-uboot-has-init =
 546                         <&aclk_vio0>;
 547 */
 548         };
 549
 550         rockchip_clocks_enable: clocks-enable {
 551                 compatible = "rockchip,clocks-enable";
 552                 clocks =
 553                         /*PLL*/
 554                         <&clk_apllb>,
 555                         <&clk_aplll>,
 556                         <&clk_dpll>,
 557                         <&clk_gpll>,
 558                         <&clk_cpll>,
 559
 560                         /*PD_CORE*/
 561                         <&clk_cs>,
 562                         <&clkin_trace>,
 563
 564                         /*PD_BUS*/
 565                         <&aclk_bus>,
 566                         <&hclk_bus>,
 567                         <&pclk_bus>,
 568                         <&clk_gates12 12>,/*aclk_strc_sys*/
 569                         <&clk_gates12 6>,/*aclk_intmem1*/
 570                         <&clk_gates12 5>,/*aclk_intmem0*/
 571                         <&clk_gates12 4>,/*aclk_intmem*/
 572                         <&clk_gates13 9>,/*aclk_gic400*/
 573
 574                         /*PD_ALIVE*/
 575                         <&clk_gates22 13>,/*pclk_timer1*/
 576                         <&clk_gates22 12>,/*pclk_timer0*/
 577                         <&clk_gates22 9>,/*pclk_alive_niu*/
 578                         <&clk_gates22 8>,/*pclk_grf*/
 579
 580                         /*PD_PMU*/
 581                         <&clk_gates23 5>,/*pclk_pmugrf*/
 582                         <&clk_gates23 3>,/*pclk_sgrf*/
 583                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 584                         <&clk_gates23 1>,/*pclk_intmem1*/
 585                         <&clk_gates23 0>,/*pclk_pmu*/
 586
 587                         /*PD_PERI*/
 588                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 589                         <&clk_gates20 8>,/*aclk_peri_niu*/
 590                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 591                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 592                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 593                         <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
 594         };
 595
 596         /* I2C_PMU */
 597         i2c0: i2c@ff650000 {
 598                 compatible = "rockchip,rk30-i2c";
 599                 reg = <0x0 0xff650000 0x0 0x1000>;
 600                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 601                 #address-cells = <1>;
 602                 #size-cells = <0>;
 603                 pinctrl-names = "default", "gpio";
 604                 pinctrl-0 = <&i2c0_xfer>;
 605                 pinctrl-1 = <&i2c0_gpio>;
 606                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 607                 clocks = <&clk_gates12 2>;
 608                 rockchip,check-idle = <1>;
 609                 status = "disabled";
 610         };
 611
 612         /* I2C_AUDIO */
 613         i2c1: i2c@ff660000 {
 614                 compatible = "rockchip,rk30-i2c";
 615                 reg = <0x0 0xff660000 0x0 0x1000>;
 616                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 617                 #address-cells = <1>;
 618                 #size-cells = <0>;
 619                 pinctrl-names = "default", "gpio";
 620                 pinctrl-0 = <&i2c1_xfer>;
 621                 pinctrl-1 = <&i2c1_gpio>;
 622                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 623                 clocks = <&clk_gates12 3>;
 624                 rockchip,check-idle = <1>;
 625                 status = "disabled";
 626         };
 627
 628         /* I2C_SENSOR */
 629         i2c2: i2c@ff140000 {
 630                 compatible = "rockchip,rk30-i2c";
 631                 reg = <0x0 0xff140000 0x0 0x1000>;
 632                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 633                 #address-cells = <1>;
 634                 #size-cells = <0>;
 635                 pinctrl-names = "default", "gpio";
 636                 pinctrl-0 = <&i2c2_xfer>;
 637                 pinctrl-1 = <&i2c2_gpio>;
 638                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 639                 clocks = <&clk_gates19 11>;
 640                 rockchip,check-idle = <1>;
 641                 status = "disabled";
 642         };
 643
 644         /* I2C_CAM */
 645         i2c3: i2c@ff150000 {
 646                 compatible = "rockchip,rk30-i2c";
 647                 reg = <0x0 0xff150000 0x0 0x1000>;
 648                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 649                 #address-cells = <1>;
 650                 #size-cells = <0>;
 651                 pinctrl-names = "default", "gpio";
 652                 pinctrl-0 = <&i2c3_xfer>;
 653                 pinctrl-1 = <&i2c3_gpio>;
 654                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 655                 clocks = <&clk_gates19 12>;
 656                 rockchip,check-idle = <1>;
 657                 status = "disabled";
 658         };
 659
 660         /* I2C_TP */
 661         i2c4: i2c@ff160000 {
 662                 compatible = "rockchip,rk30-i2c";
 663                 reg = <0x0 0xff160000 0x0 0x1000>;
 664                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 665                 #address-cells = <1>;
 666                 #size-cells = <0>;
 667                 pinctrl-names = "default", "gpio";
 668                 pinctrl-0 = <&i2c4_xfer>;
 669                 pinctrl-1 = <&i2c4_gpio>;
 670                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 671                 clocks = <&clk_gates19 13>;
 672                 rockchip,check-idle = <1>;
 673                 status = "disabled";
 674         };
 675
 676         /* I2C_HDMI */
 677         i2c5: i2c@ff170000 {
 678                 compatible = "rockchip,rk30-i2c";
 679                 reg = <0x0 0xff170000 0x0 0x1000>;
 680                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 681                 #address-cells = <1>;
 682                 #size-cells = <0>;
 683                 pinctrl-names = "default", "gpio";
 684                 pinctrl-0 = <&i2c5_xfer>;
 685                 pinctrl-1 = <&i2c5_gpio>;
 686                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 687                 clocks = <&clk_gates19 14>;
 688                 rockchip,check-idle = <1>;
 689                 status = "disabled";
 690         };
 691
 692         fb: fb {
 693                 compatible = "rockchip,rk-fb";
 694                 rockchip,disp-mode = <NO_DUAL>;
 695         };
 696
 697
 698         rk_screen: rk_screen {
 699                 compatible = "rockchip,screen";
 700         };
 701
 702         dsihost0: mipi@ff960000{
 703                 compatible = "rockchip,rk3368-dsi";
 704                 rockchip,prop = <0>;
 705                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 706                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 707                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 708                 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>;
 709                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 710                 status = "okay";
 711         };
 712
 713         lvds: lvds@ff968000 {
 714                 compatible = "rockchip,rk3368-lvds";
 715                 rockchip,grf = <&grf>;
 716                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 717                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 718                 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
 719                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 720                 status = "disabled";
 721         };
 722
 723         edp: edp@ff970000 {
 724                 compatible = "rockchip,rk32-edp";
 725                 reg = <0x0 0xff970000 0x0 0x4000>;
 726                 rockchip,grf = <&grf>;
 727                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 728                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 729                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 730                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 731                 reset-names = "edp_24m", "edp_apb";
 732         };
 733
 734         hdmi: hdmi@ff980000 {
 735                 compatible = "rockchip,rk3368-hdmi";
 736                 reg = <0x0 0xff980000 0x0 0x20000>;
 737                 rockchip,grf = <&grf>;
 738                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 739                 pinctrl-names = "default", "gpio";
 740                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 741                 pinctrl-1 = <&i2c5_gpio>;
 742                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 743                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 744                 status = "disabled";
 745         };
 746
 747         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 748                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 749                 reg = <0x0 0xff978000 0x0 0x2000>;
 750                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 751                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 752                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 753                 status = "disabled";
 754         };
 755
 756         lcdc: lcdc@ff930000 {
 757                  compatible = "rockchip,rk3368-lcdc";
 758                  rockchip,grf = <&grf>;
 759                  rockchip,pmugrf = <&pmugrf>;
 760                  rockchip,prop = <PRMRY>;
 761                  rockchip,pwr18 = <0>;
 762                  rockchip,iommu-enabled = <0>;
 763                  reg = <0x0 0xff930000 0x0 0x10000>;
 764                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 765                 /*pinctrl-names = "default", "gpio";
 766                  *pinctrl-0 = <&lcdc_lcdc>;
 767                  *pinctrl-1 = <&lcdc_gpio>;
 768                  */
 769                  status = "disabled";
 770                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
 771                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
 772         };
 773
 774         adc: adc@ff100000 {
 775                 compatible = "rockchip,saradc";
 776                 reg = <0x0 0xff100000 0x0 0x100>;
 777                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 778                 #io-channel-cells = <1>;
 779                 io-channel-ranges;
 780                 rockchip,adc-vref = <1800>;
 781                 clock-frequency = <1000000>;
 782                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 783                 clock-names = "saradc", "pclk_saradc";
 784                 status = "disabled";
 785         };
 786
 787         rga@ff920000 {
 788                 compatible = "rockchip,rk3368-rga2";
 789                 reg = <0x0 0xff920000 0x0 0x1000>;
 790                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 791                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 792                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 793         };
 794
 795         i2s0: i2s0@ff898000 {
 796                 compatible = "rockchip-i2s";
 797                 reg = <0x0 0xff898000 0x0 0x1000>;
 798                 i2s-id = <0>;
 799                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 800                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 801                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 802                 dmas = <&pdma0 0>, <&pdma0 1>;
 803                 #dma-cells = <2>;
 804                 dma-names = "tx", "rx";
 805                 pinctrl-names = "default", "sleep";
 806                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 807                 pinctrl-1 = <&i2s_gpio>;
 808         };
 809
 810         i2s1: i2s1@ff890000 {
 811                 compatible = "rockchip-i2s";
 812                 reg = <0x0 0xff890000 0x0 0x1000>;
 813                 i2s-id = <1>;
 814                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 815                 clock-names = "i2s_clk", "i2s_hclk";
 816                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 817                 dmas = <&pdma0 6>, <&pdma0 7>;
 818                 #dma-cells = <2>;
 819                 dma-names = "tx", "rx";
 820         };
 821
 822         spdif: spdif@ff880000 {
 823                 compatible = "rockchip-spdif";
 824                 reg = <0x0 0xff880000 0x0 0x1000>;
 825                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 826                 clock-names = "spdif_mclk", "spdif_hclk";
 827                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 828                 dmas = <&pdma0 3>;
 829                 #dma-cells = <1>;
 830                 dma-names = "tx";
 831                 pinctrl-names = "default";
 832                 pinctrl-0 = <&spdif_tx>;
 833         };
 834
 835         pwm0: pwm@ff680000 {
 836                 compatible = "rockchip,rk-pwm";
 837                 reg = <0x0 0xff680000 0x0 0x10>;
 838                 #pwm-cells = <2>;
 839                 pinctrl-names = "default";
 840                 pinctrl-0 = <&pwm0_pin>;
 841                 clocks = <&clk_gates13 6>;
 842                 clock-names = "pclk_pwm";
 843                 status = "disabled";
 844         };
 845
 846         pwm1: pwm@ff680010 {
 847                 compatible = "rockchip,rk-pwm";
 848                 reg = <0x0 0xff680010 0x0 0x10>;
 849                 #pwm-cells = <2>;
 850                 pinctrl-names = "default";
 851                 pinctrl-0 = <&pwm1_pin>;
 852                 clocks = <&clk_gates13 6>;
 853                 clock-names = "pclk_pwm";
 854                 status = "disabled";
 855         };
 856
 857         pwm2: pwm@ff680020 {
 858                 compatible = "rockchip,rk-pwm";
 859                 reg = <0x0 0xff680020 0x0 0x10>;
 860                 #pwm-cells = <2>;
 861                 //pinctrl-names = "default";
 862                 //pinctrl-0 = <&pwm1_pin>;
 863                 clocks = <&clk_gates13 6>;
 864                 clock-names = "pclk_pwm";
 865                 status = "disabled";
 866         };
 867
 868         pwm3: pwm@ff680030 {
 869                 compatible = "rockchip,rk-pwm";
 870                 reg = <0x0 0xff680030 0x0 0x10>;
 871                 #pwm-cells = <2>;
 872                 pinctrl-names = "default";
 873                 pinctrl-0 = <&pwm3_pin>;
 874                 clocks = <&clk_gates13 6>;
 875                 clock-names = "pclk_pwm";
 876                 status = "disabled";
 877         };
 878
 879         remotectl: pwm@ff680030 {
 880                 compatible = "rockchip,remotectl-pwm";
 881                 reg = <0x0 0xff680030 0x0 0x50>;
 882                 #pwm-cells = <2>;
 883                 pinctrl-names = "default";
 884                 pinctrl-0 = <&pwm3_pin>;
 885                 clocks = <&clk_gates13 6>;
 886                 clock-names = "pclk_pwm";
 887                 dmas = <&pdma0 2>;
 888                 #dma-cells = <2>;
 889                 dma-names = "rx";
 890                 remote_pwm_id = <3>;
 891                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 892                 status = "disabled";
 893         };
 894
 895         voppwm: pwm@ff9301a0 {
 896                 compatible = "rockchip,vop-pwm";
 897                 reg = <0x0 0xff9301a0 0x0 0x10>;
 898                 #pwm-cells = <2>;
 899                 pinctrl-names = "default";
 900                 pinctrl-0 = <&vop_pwm_pin>;
 901                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
 902                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 903                 status = "disabled";
 904         };
 905
 906         pvtm {
 907                 compatible = "rockchip,rk3368-pvtm";
 908                 rockchip,grf = <&grf>;
 909         };
 910
 911         cpufreq {
 912                 compatible = "rockchip,rk3368-cpufreq";
 913                 rockchip,grf = <&grf>;
 914         };
 915
 916         dvfs {
 917
 918                 vd_arm: vd_arm {
 919                         regulator_name = "vdd_arm";
 920                         suspend_volt = <1000>; //mV
 921                         pd_core {
 922                                 clk_core_b_dvfs_table: clk_core_b {
 923                                         operating-points = <
 924                                                 /* KHz    uV */
 925                                                 312000 1200000
 926                                                 504000 1200000
 927                                                 816000 1200000
 928                                                 1008000 1200000
 929                                                 >;
 930                                         status = "okay";
 931                                 };
 932                                 clk_core_l_dvfs_table: clk_core_l {
 933                                         operating-points = <
 934                                                 /* KHz    uV */
 935                                                 312000 1200000
 936                                                 504000 1200000
 937                                                 816000 1200000
 938                                                 1008000 1200000
 939                                                 >;
 940                                         status = "okay";
 941                                 };
 942                         };
 943                 };
 944
 945                 vd_logic: vd_logic {
 946                         regulator_name = "vdd_logic";
 947                         suspend_volt = <1000>; //mV
 948                         pd_ddr {
 949                                 clk_ddr_dvfs_table: clk_ddr {
 950                                         operating-points = <
 951                                                 /* KHz    uV */
 952                                                 200000 1200000
 953                                                 300000 1200000
 954                                                 400000 1200000
 955                                                 >;
 956                                         channel = <2>;
 957                                         status = "disabled";
 958                                 };
 959                         };
 960
 961                         pd_gpu {
 962                                 clk_gpu_dvfs_table: clk_gpu {
 963                                         operating-points = <
 964                                                 /* KHz    uV */
 965                                                 200000 1200000
 966                                                 300000 1200000
 967                                                 400000 1200000
 968                                                 >;
 969                                         channel = <1>;
 970                                         status = "okay";
 971                                         regu-mode-table = <
 972                                                 /*freq     mode*/
 973                                                 200000     4
 974                                                 0          3
 975                                         >;
 976                                         regu-mode-en = <0>;
 977                                 };
 978                         };
 979                 };
 980         };
 981
 982         ion {
 983                 compatible = "rockchip,ion";
 984                 #address-cells = <1>;
 985                 #size-cells = <0>;
 986
 987                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
 988                         compatible = "rockchip,ion-heap";
 989                         rockchip,ion_heap = <4>;
 990                         reg = <0x00000000 0x08000000>; /* 512MB */
 991                 };
 992                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
 993                         compatible = "rockchip,ion-heap";
 994                         rockchip,ion_heap = <0>;
 995                 };
 996         };
 997
 998         vpu: vpu_service {
 999                 compatible = "rockchip,vpu_sub";
1000                 iommu_enabled = <0>;
1001                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1002                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1003                 interrupt-names = "irq_enc", "irq_dec";
1004                 dev_mode = <0>;
1005                 name = "vpu_service";
1006         };
1007
1008         hevc: hevc_service {
1009                 compatible = "rockchip,hevc_sub";
1010                 iommu_enabled = <0>;
1011                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1012                 interrupt-names = "irq_dec";
1013                 dev_mode = <1>;
1014                 name = "hevc_service";
1015         };
1016
1017         vpu_combo: vpu_combo@ff9a0000 {
1018                 compatible = "rockchip,vpu_combo";
1019                 reg = <0x0 0xff9a0000 0x0 0x800>;
1020                 rockchip,grf = <&grf>;
1021                 subcnt = <2>;
1022                 rockchip,sub = <&vpu>, <&hevc>;
1023                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1024                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1025                 mode_bit = <12>;
1026                 mode_ctrl = <0x418>;
1027                 name = "vpu_combo";
1028                 status = "okay";
1029         };
1030
1031         iep: iep@ff900000 {
1032                 compatible = "rockchip,iep";
1033                 iommu_enabled = <0>;
1034                 reg = <0x0 0xff900000 0x0 0x800>;
1035                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1036                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1037                 clock-names = "aclk_iep", "hclk_iep";
1038                 status = "okay";
1039         };
1040
1041         gmac: eth@ff290000 {
1042                 compatible = "rockchip,rk3368-gmac";
1043                 reg = <0x0 0xff290000 0x0 0x10000>;
1044                 rockchip,grf = <&grf>;
1045                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1046                 interrupt-names = "macirq";
1047
1048                 clocks = <&clk_mac>, <&clk_gates7 4>,
1049                          <&clk_gates7 5>, <&clk_gates7 6>,
1050                          <&clk_gates7 7>, <&clk_gates20 13>,
1051                          <&clk_gates20 14>;
1052                 clock-names = "clk_mac", "mac_clk_rx",
1053                               "mac_clk_tx", "clk_mac_ref",
1054                               "clk_mac_refout", "aclk_mac",
1055                               "pclk_mac";
1056
1057                 phy-mode = "rgmii";
1058                 pinctrl-names = "default";
1059                 pinctrl-0 = <&rgmii_pins>;
1060         };
1061
1062         gpu {
1063                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1064                 reg = <0x0 0xffa30000 0x0 0x10000>;
1065                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1066                 interrupt-names = "GPU";
1067         };
1068
1069         iep_mmu {
1070                 dbgname = "iep";
1071                 compatible = "rockchip,iep_mmu";
1072                 reg = <0x0 0xff900800 0x0 0x100>;
1073                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1074                 interrupt-names = "iep_mmu";
1075         };
1076
1077         vip_mmu {
1078                 dbgname = "vip";
1079                 compatible = "rockchip,vip_mmu";
1080                 reg = <0x0 0xff950800 0x0 0x100>;
1081                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1082                 interrupt-names = "vip_mmu";
1083         };
1084
1085         vop_mmu {
1086                 dbgname = "vop";
1087                 compatible = "rockchip,vop_mmu";
1088                 reg = <0x0 0xff930300 0x0 0x100>;
1089                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1090                 interrupt-names = "vop_mmu";
1091         };
1092
1093         isp_mmu {
1094                 dbgname = "isp_mmu";
1095                 compatible = "rockchip,isp_mmu";
1096                 reg = <0x0 0xff914000 0x0 0x100>,
1097                 <0x0 0xff915000 0x0 0x100>;
1098                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1099                 interrupt-names = "isp_mmu";
1100         };
1101
1102         hdcp_mmu {
1103                 dbgname = "hdcp_mmu";
1104                 compatible = "rockchip,hdcp_mmu";
1105                 reg = <0x0 0xff940000 0x0 0x100>;
1106                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1107                 interrupt-names = "hdcp_mmu";
1108         };
1109
1110         hevc_mmu {
1111                 dbgname = "hevc";
1112                 compatible = "rockchip,hevc_mmu";
1113                 reg = <0x0 0xff9c0440 0x0 0x40>,                      /*need to fix*/
1114                           <0x0 0xff9c0480 0x0 0x40>;
1115                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1116                 interrupt-names = "hevc_mmu";
1117         };
1118
1119         vpu_mmu {
1120                 dbgname = "vpu";
1121                 compatible = "rockchip,vpu_mmu";
1122                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1123                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;       /*need to fix*/
1124                 interrupt-names = "vpu_mmu";
1125         };
1126
1127         rockchip_suspend {
1128                 rockchip,ctrbits = <
1129                         (0
1130                          |RKPM_CTR_PWR_DMNS
1131                          |RKPM_CTR_GTCLKS
1132                          |RKPM_CTR_PLLS
1133                          |RKPM_CTR_GPIOS
1134                         /*
1135                          |RKPM_CTR_SYSCLK_DIV
1136                          |RKPM_CTR_IDLEAUTO_MD
1137                          |RKPM_CTR_ARMOFF_LPMD
1138                         */
1139                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1140                         )
1141                         >;
1142                 rockchip,pmic-suspend_gpios = <
1143                                  /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1144                         >;
1145                 rockchip,pmic-resume_gpios = <
1146                                 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1147                         >;
1148         };
1149
1150         isp: isp@ff910000{
1151                 compatible = "rockchip,isp";
1152                 reg = <0x0 0xff910000 0x0 0x10000>;
1153                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1154                 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1155                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1156                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1157                 pinctrl-0 = <&cif_clkout>;
1158                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1159                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1160                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1161                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1162                 pinctrl-5 = <&cif_clkout>;
1163                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1164                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1165                 pinctrl-8 = <&isp_flash_trigger>;
1166                 rockchip,isp,mipiphy = <2>;
1167                 rockchip,isp,cifphy = <1>;
1168                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1169                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1170                 rockchip,grf = <&grf>;
1171                 rockchip,cru = <&cru>;
1172                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1173                 rockchip,isp,iommu_enable = <0>;
1174                 status = "okay";
1175         };
1176
1177         cif: cif@ff950000 {
1178                 compatible = "rockchip,cif";
1179                 reg = <0x0 0xff950000 0x0 0x10000>;
1180                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1181                 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1182                 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1183                 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1184                 pinctrl-names = "cif_pin_all";
1185                 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1186                 rockchip,grf = <&grf>;
1187                 rockchip,cru = <&cru>;
1188                 status = "okay";
1189         };
1190
1191         thermal-zones {
1192                 #include "rk3368-thermal.dtsi"
1193         };
1194
1195         tsadc: tsadc@ff280000 {
1196                 compatible = "rockchip,rk3368-tsadc";
1197                 reg = <0x0 0xff280000 0x0 0x100>;
1198                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1199                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1200                 clock-names = "tsadc", "apb_pclk";
1201                 resets = <&reset RK3368_SRST_TSADC_P>;
1202                 reset-names = "tsadc-apb";
1203                 pinctrl-names = "default";
1204                 pinctrl-0 = <&tsadc_int>;
1205                 #thermal-sensor-cells = <1>;
1206                 hw-shut-temp = <120000>;
1207                 status = "disabled";
1208         };
1209
1210         tsp: tsp@FF8B0000 {
1211                 compatible = "rockchip,rk3368-tsp";
1212                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1213                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1214                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1215                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1216                 interrupt-names = "irq_tsp";
1217                 // pinctrl-names = "default";
1218                 // pinctrl-0 = <&isp_hsadc>;
1219                 status = "okay";
1220         };
1221
1222         crypto: crypto@FF8A0000{
1223                 compatible = "rockchip,rk3368-crypto";
1224                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1225                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1226                 interrupt-names = "irq_crypto";
1227                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1228                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1229                 status = "okay";
1230         };
1231
1232         dwc_control_usb: dwc-control-usb {
1233                 compatible = "rockchip,rk3368-dwc-control-usb";
1234                 rockchip,grf = <&grf>;
1235                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1236                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1237                 interrupt-names = "otg_id", "otg_bvalid",
1238                                   "otg_linestate", "host0_linestate";
1239                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1240                 clock-names = "hclk_usb_peri", "usbphy_480m";
1241                 //resets = <&reset RK3128_RST_USBPOR>;
1242                 //reset-names = "usbphy_por";
1243                 usb_bc{
1244                         compatible = "inno,phy";
1245                         regbase = &dwc_control_usb;
1246                         rk_usb,bvalid     = <0x4bc 23 1>;
1247                         rk_usb,iddig      = <0x4bc 26 1>;
1248                         rk_usb,vdmsrcen   = <0x718 12 1>;
1249                         rk_usb,vdpsrcen   = <0x718 11 1>;
1250                         rk_usb,rdmpden    = <0x718 10 1>;
1251                         rk_usb,idpsrcen   = <0x718  9 1>;
1252                         rk_usb,idmsinken  = <0x718  8 1>;
1253                         rk_usb,idpsinken  = <0x718  7 1>;
1254                         rk_usb,dpattach   = <0x4b8 31 1>;
1255                         rk_usb,cpdet      = <0x4b8 30 1>;
1256                         rk_usb,dcpattach  = <0x4b8 29 1>;
1257                 };
1258         };
1259
1260         usb0: usb@ff580000 {
1261                 compatible = "rockchip,rk3368_usb20_otg";
1262                 reg = <0x0 0xff580000 0x0 0x40000>;
1263                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1264                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1265                 clock-names = "clk_usbphy0", "hclk_otg";
1266                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1267                                 <&reset RK3368_SRST_USBOTGC0>;
1268                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1269                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1270                 rockchip,usb-mode = <0>;
1271         };
1272
1273         usb_ehci: usb@ff500000 {
1274                 compatible = "generic-ehci";
1275                 reg = <0x0 0xff500000 0x0 0x20000>;
1276                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1277                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1278                 clock-names = "clk_usbphy0", "hclk_ehci";
1279                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1280                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1281                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1282         };
1283
1284         usb_ohci: usb@ff520000 {
1285                 compatible = "generic-ohci";
1286                 reg = <0x0 0xff520000 0x0 0x20000>;
1287                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1288                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1289                 clock-names =  "clk_usbphy0", "hclk_ohci";
1290         };
1291
1292         usb_hsic: usb@ff5c0000 {
1293                 compatible = "rockchip,rk3288_rk_hsic_host";
1294                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1295                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1296 /*
1297                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1298                          <&hsicphy_12m>, <&usbphy_480m>,
1299                          <&otgphy1_480m>, <&otgphy2_480m>;
1300                 clock-names = "hsicphy_480m", "hclk_hsic",
1301                               "hsicphy_12m", "usbphy_480m",
1302                               "hsic_usbphy1", "hsic_usbphy2";
1303                 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1304                                 <&reset RK3288_SOFT_RST_HSICPHY>;
1305                 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1306 */
1307                 status = "disabled";
1308         };
1309
1310         pinctrl: pinctrl {
1311                 compatible = "rockchip,rk3368-pinctrl";
1312                 rockchip,grf = <&grf>;
1313                 rockchip,pmugrf = <&pmugrf>;
1314                 #address-cells = <2>;
1315                 #size-cells = <2>;
1316                 ranges;
1317
1318                 gpio0: gpio0@ff750000 {
1319                         compatible = "rockchip,gpio-bank";
1320                         reg =   <0x0 0xff750000 0x0 0x100>;
1321                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1322                         clocks = <&clk_gates23 4>;
1323
1324                         gpio-controller;
1325                         #gpio-cells = <2>;
1326
1327                         interrupt-controller;
1328                         #interrupt-cells = <2>;
1329                 };
1330
1331                 gpio1: gpio1@ff780000 {
1332                         compatible = "rockchip,gpio-bank";
1333                         reg = <0x0 0xff780000 0x0 0x100>;
1334                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1335                         clocks = <&clk_gates22 1>;
1336
1337                         gpio-controller;
1338                         #gpio-cells = <2>;
1339
1340                         interrupt-controller;
1341                         #interrupt-cells = <2>;
1342                 };
1343
1344                 gpio2: gpio2@ff790000 {
1345                         compatible = "rockchip,gpio-bank";
1346                         reg = <0x0 0xff790000 0x0 0x100>;
1347                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1348                         clocks = <&clk_gates22 2>;
1349
1350                         gpio-controller;
1351                         #gpio-cells = <2>;
1352
1353                         interrupt-controller;
1354                         #interrupt-cells = <2>;
1355                 };
1356
1357                 gpio3: gpio3@ff7a0000 {
1358                         compatible = "rockchip,gpio-bank";
1359                         reg = <0x0 0xff7a0000 0x0 0x100>;
1360                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1361                         clocks = <&clk_gates22 3>;
1362
1363                         gpio-controller;
1364                         #gpio-cells = <2>;
1365
1366                         interrupt-controller;
1367                         #interrupt-cells = <2>;
1368                 };
1369
1370                 pcfg_pull_up: pcfg-pull-up {
1371                         bias-pull-up;
1372                 };
1373
1374                 pcfg_pull_down: pcfg-pull-down {
1375                         bias-pull-down;
1376                 };
1377
1378                 pcfg_pull_none: pcfg-pull-none {
1379                         bias-disable;
1380                 };
1381
1382                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1383                         drive-strength = <8>;
1384                 };
1385
1386                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1387                         drive-strength = <12>;
1388                 };
1389
1390                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1391                         bias-pull-up;
1392                         drive-strength = <8>;
1393                 };
1394
1395                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1396                         drive-strength = <4>;
1397                 };
1398
1399                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1400                         bias-pull-up;
1401                         drive-strength = <4>;
1402                 };
1403
1404                 pcfg_output_high: pcfg-output-high {
1405                         output-high;
1406                 };
1407
1408                 pcfg_output_low: pcfg-output-low {
1409                         output-low;
1410                 };
1411
1412                 i2c0 {
1413                         i2c0_xfer: i2c0-xfer {
1414                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1415                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1416                         };
1417                         i2c0_gpio: i2c0-gpio {
1418                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1419                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1420                         };
1421                 };
1422
1423                 i2c1 {
1424                         i2c1_xfer: i2c1-xfer {
1425                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1426                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1427                         };
1428                         i2c1_gpio: i2c1-gpio {
1429                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1430                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1431                         };
1432                 };
1433
1434                 i2c2 {
1435                         i2c2_xfer: i2c2-xfer {
1436                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1437                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1438                         };
1439                         i2c2_gpio: i2c2-gpio {
1440                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1441                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1442             };
1443                 };
1444
1445                 i2c3 {
1446                         i2c3_xfer: i2c3-xfer {
1447                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1448                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1449                         };
1450                         i2c3_gpio: i2c3-gpio {
1451                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1452                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1453                         };
1454                 };
1455
1456                 i2c4 {
1457                         i2c4_xfer: i2c4-xfer {
1458                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1459                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1460                         };
1461                         i2c4_gpio: i2c4-gpio {
1462                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1463                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1464                         };
1465                 };
1466
1467                 i2c5 {
1468                         i2c5_xfer: i2c5-xfer {
1469                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1470                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1471                         };
1472                         i2c5_gpio: i2c5-gpio {
1473                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1474                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1475                         };
1476                 };
1477
1478                 uart0 {
1479                         uart0_xfer: uart0-xfer {
1480                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1481                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1482                         };
1483
1484                         uart0_cts: uart0-cts {
1485                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1486                         };
1487
1488                         uart0_rts: uart0-rts {
1489                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1490                         };
1491
1492                         uart0_rts_gpio: uart0-rts-gpio {
1493                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1494                         };
1495                 };
1496
1497                 uart1 {
1498                         uart1_xfer: uart1-xfer {
1499                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1500                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1501                         };
1502
1503                         uart1_cts: uart1-cts {
1504                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1505                         };
1506
1507                         uart1_rts: uart1-rts {
1508                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1509                         };
1510                 };
1511
1512                 uart2 {
1513                         uart2_xfer: uart2-xfer {
1514                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1515                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1516                         };
1517                 };
1518
1519                 uart3 {
1520                         uart3_xfer: uart3-xfer {
1521                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1522                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1523                         };
1524
1525                         uart3_cts: uart3-cts {
1526                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1527                         };
1528
1529                         uart3_rts: uart3-rts {
1530                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1531                         };
1532                 };
1533
1534                 uart4 {
1535                         uart4_xfer: uart4-xfer {
1536                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1537                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1538                         };
1539
1540                         uart4_cts: uart4-cts {
1541                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1542                         };
1543
1544                         uart4_rts: uart4-rts {
1545                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1546                         };
1547                 };
1548
1549                 spi0 {
1550                         spi0_clk: spi0-clk {
1551                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1552                         };
1553                         spi0_cs0: spi0-cs0 {
1554                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1555                         };
1556                         spi0_tx: spi0-tx {
1557                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1558                         };
1559                         spi0_rx: spi0-rx {
1560                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1561                         };
1562                         spi0_cs1: spi0-cs1 {
1563                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1564                         };
1565                 };
1566
1567                 spi1 {
1568                         spi1_clk: spi1-clk {
1569                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1570                         };
1571                         spi1_cs0: spi1-cs0 {
1572                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1573                         };
1574                         spi1_rx: spi1-rx {
1575                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1576                         };
1577                         spi1_tx: spi1-tx {
1578                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1579                         };
1580                 };
1581
1582                 spi2 {
1583                         spi2_clk: spi2-clk {
1584                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1585                         };
1586                         spi2_cs0: spi2-cs0 {
1587                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1588                         };
1589                         spi2_rx: spi2-rx {
1590                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1591                         };
1592                         spi2_tx: spi2-tx {
1593                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1594                         };
1595                 };
1596
1597                 i2s {
1598                         i2s_mclk: i2s-mclk {
1599                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1600                         };
1601
1602                         i2s_sclk:i2s-sclk {
1603                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1604                         };
1605
1606                         i2s_lrckrx:i2s-lrckrx {
1607                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1608                         };
1609
1610                         i2s_lrcktx:i2s-lrcktx {
1611                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1612                         };
1613
1614                         i2s_sdi:i2s-sdi {
1615                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1616                         };
1617
1618                         i2s_sdo0:i2s-sdo0 {
1619                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1620                         };
1621
1622                         i2s_sdo1:i2s-sdo1 {
1623                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1624                         };
1625
1626                         i2s_sdo2:i2s-sdo2 {
1627                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1628                         };
1629
1630                         i2s_sdo3:i2s-sdo3 {
1631                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1632                         };
1633
1634                         i2s_gpio: i2s-gpio {
1635                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1636                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1637                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1638                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1639                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1640                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1641                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1642                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1643                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1644                         };
1645                 };
1646
1647                 spdif {
1648                         spdif_tx: spdif-tx {
1649                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1650                         };
1651                 };
1652
1653                 sdmmc {
1654                         sdmmc_clk: sdmmc-clk {
1655                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1656                         };
1657
1658                         sdmmc_cmd: sdmmc-cmd {
1659                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1660                         };
1661
1662                         sdmmc_dectn: sdmmc-dectn {
1663                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1664                         };
1665
1666                         sdmmc_bus1: sdmmc-bus1 {
1667                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1668                         };
1669
1670                         sdmmc_bus4: sdmmc-bus4 {
1671                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1672                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1673                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1674                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1675                         };
1676
1677                         sdmmc_gpio: sdmmc-gpio {
1678                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1679                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1680                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1681                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1682                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1683                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1684                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1685                         };
1686                 };
1687
1688                 sdio0 {
1689                         sdio0_bus1: sdio0-bus1 {
1690                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1691                         };
1692
1693                         sdio0_bus4: sdio0-bus4 {
1694                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1695                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1696                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1697                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1698                         };
1699
1700                         sdio0_cmd: sdio0-cmd {
1701                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1702                         };
1703
1704                         sdio0_clk: sdio0-clk {
1705                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1706                         };
1707
1708                         sdio0_dectn: sdio0-dectn {
1709                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1710                         };
1711
1712                         sdio0_wrprt: sdio0-wrprt {
1713                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1714                         };
1715
1716                         sdio0_pwren: sdio0-pwren {
1717                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1718                         };
1719
1720                         sdio0_bkpwr: sdio0-bkpwr {
1721                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1722                         };
1723
1724                         sdio0_int: sdio0-int {
1725                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1726                         };
1727
1728                         sdio0_gpio: sdio0-gpio {
1729                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1730                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1731                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1732                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1733                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1734                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1735                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1736                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1737                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1738                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1739                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1740                         };
1741                 };
1742
1743                 emmc {
1744                         emmc_clk: emmc-clk {
1745                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1746                         };
1747
1748                         emmc_cmd: emmc-cmd {
1749                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1750                         };
1751
1752                         emmc_pwren: emmc-pwren {
1753                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1754                         };
1755
1756                         emmc_rstnout: emmc_rstnout {
1757                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1758                         };
1759
1760                         emmc_bus1: emmc-bus1 {
1761                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1762                         };
1763
1764                         emmc_bus4: emmc-bus4 {
1765                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1766                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1767                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1768                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1769                         };
1770                 };
1771
1772                 pwm0 {
1773                         pwm0_pin: pwm0-pin {
1774                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1775                         };
1776
1777                         vop_pwm_pin:vop-pwm {
1778                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1779                         };
1780                 };
1781
1782                 pwm1 {
1783                         pwm1_pin: pwm1-pin {
1784                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1785                         };
1786                 };
1787
1788                 pwm3 {
1789                         pwm3_pin: pwm3-pin {
1790                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1791                         };
1792                 };
1793
1794                 lcdc {
1795                         lcdc_lcdc: lcdc-lcdc {
1796                                 rockchip,pins =
1797                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1798                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1799                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1800                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1801                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1802                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1803                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1804                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1805                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1806                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1807                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1808                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1809                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1810                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1811                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1812                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1813                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1814                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1815                         };
1816
1817                         lcdc_gpio: lcdc-gpio {
1818                                 rockchip,pins =
1819                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1820                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1821                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1822                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1823                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1824                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1825                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1826                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1827                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1828                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1829                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1830                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1831                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1832                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1833                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1834                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1835                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1836                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1837                         };
1838                 };
1839
1840                 isp {
1841                         cif_clkout: cif-clkout {
1842                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1843                         };
1844
1845                         isp_dvp_d2d9: isp-dvp-d2d9 {
1846                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1847                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1848                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1849                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1850                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1851                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1852                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1853                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1854                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1855                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1856                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1857                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1858                         };
1859
1860                         isp_dvp_d0d1: isp-dvp-d0d1 {
1861                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1862                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1863                         };
1864
1865                         isp_dvp_d10d11:isp_d10d11       {
1866                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1867                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1868                         };
1869
1870                         isp_dvp_d0d7: isp-dvp-d0d7 {
1871                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1872                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1873                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1874                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1875                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1876                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1877                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1878                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1879                         };
1880
1881                         isp_shutter: isp-shutter {
1882                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1883                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1884                         };
1885
1886                         isp_flash_trigger: isp-flash-trigger {
1887                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1888                         };
1889
1890                         isp_prelight: isp-prelight {
1891                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1892                         };
1893
1894                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1895                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1896                         };
1897                 };
1898
1899                 gps {
1900                         gps_mag: gps-mag {
1901                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1902                         };
1903
1904                         gps_sig: gps-sig {
1905                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1906
1907                         };
1908
1909                         gps_rfclk: gps-rfclk {
1910                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1911                         };
1912                 };
1913
1914                 gmac {
1915                         rgmii_pins: rgmii-pins {
1916                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1917                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1918                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1919                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1920                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1921                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
1922                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
1923                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
1924                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1925                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1926                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1927                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1928                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1929                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1930                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
1931                         };
1932
1933                         rmii_pins: rmii-pins {
1934                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1935                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1936                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1937                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1938                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1939                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1940                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1941                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1942                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1943                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
1944                         };
1945                 };
1946
1947                 tsadc_pin {
1948                         tsadc_int: tsadc-int {
1949                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1950                         };
1951                         tsadc_gpio: tsadc-gpio {
1952                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1953                         };
1954                 };
1955
1956                 hdmi_pin {
1957                         hdmi_cec: hdmi-cec {
1958                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1959                         };
1960                 };
1961
1962                 hdmi_i2c {
1963                         hdmii2c_xfer: hdmii2c-xfer {
1964                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
1965                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1966                         };
1967                 };
1968         };
1969
1970         reboot {
1971                 compatible = "rockchip,rk3368-reboot";
1972                 rockchip,cru = <&cru>;
1973                 rockchip,pmugrf = <&pmugrf>;
1974         };
1975 };