arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 idle-states {
  41                         entry-method = "arm,psci";
  42                         CPU_SLEEP_0: cpu-sleep-0 {
  43                                 compatible = "arm,idle-state";
  44                                 arm,psci-suspend-param = <0x0000000>;
  45                                 entry-latency-us = <10000000>;
  46                                 exit-latency-us = <10000000>;
  47                                 min-residency-us = <25000>;
  48                         };
  49                 };
  50
  51                 little0: cpu@100 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53", "arm,armv8";
  54                         reg = <0x0 0x100>;
  55                         enable-method = "psci";
  56                         cpu-idle-states = <&CPU_SLEEP_0>;
  57                 };
  58                 little1: cpu@101 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x101>;
  62                         enable-method = "psci";
  63                         cpu-idle-states = <&CPU_SLEEP_0>;
  64                 };
  65                 little2: cpu@102 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         reg = <0x0 0x102>;
  69                         enable-method = "psci";
  70                         cpu-idle-states = <&CPU_SLEEP_0>;
  71                 };
  72                 little3: cpu@103 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x103>;
  76                         enable-method = "psci";
  77                         cpu-idle-states = <&CPU_SLEEP_0>;
  78                 };
  79                 big0: cpu@0 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         reg = <0x0 0x0>;
  83                         enable-method = "psci";
  84                         cpu-idle-states = <&CPU_SLEEP_0>;
  85                 };
  86                 big1: cpu@1 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         reg = <0x0 0x1>;
  90                         enable-method = "psci";
  91                         cpu-idle-states = <&CPU_SLEEP_0>;
  92                 };
  93                 big2: cpu@2 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53", "arm,armv8";
  96                         reg = <0x0 0x2>;
  97                         enable-method = "psci";
  98                         cpu-idle-states = <&CPU_SLEEP_0>;
  99                 };
 100                 big3: cpu@3 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53", "arm,armv8";
 103                         reg = <0x0 0x3>;
 104                         enable-method = "psci";
 105                         cpu-idle-states = <&CPU_SLEEP_0>;
 106                 };
 107
 108                 cpu-map {
 109                         cluster0 {
 110                                 core0 {
 111                                         cpu = <&big0>;
 112                                 };
 113                                 core1 {
 114                                         cpu = <&big1>;
 115                                 };
 116                                 core2 {
 117                                         cpu = <&big2>;
 118                                 };
 119                                 core3 {
 120                                         cpu = <&big3>;
 121                                 };
 122                         };
 123                         cluster1 {
 124                                 core0 {
 125                                         cpu = <&little0>;
 126                                 };
 127                                 core1 {
 128                                         cpu = <&little1>;
 129                                 };
 130                                 core2 {
 131                                         cpu = <&little2>;
 132                                 };
 133                                 core3 {
 134                                         cpu = <&little3>;
 135                                 };
 136                         };
 137                 };
 138         };
 139
 140         psci {
 141                 compatible = "arm,psci";
 142                 method = "smc";
 143                 cpu_on = <0xC4000003>;
 144                 cpu_suspend = <0x84000001>;
 145                 cpu_off = <0x84000002>;
 146         };
 147
 148         gic: interrupt-controller@ffb70000 {
 149                 compatible = "arm,cortex-a15-gic";
 150                 #interrupt-cells = <3>;
 151                 #address-cells = <0>;
 152                 interrupt-controller;
 153                 reg = <0x0 0xffb71000 0 0x1000>,
 154                       <0x0 0xffb72000 0 0x1000>;
 155         };
 156
 157         pmu: syscon@ff730000 {
 158                 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
 159                 reg = <0x0 0xff730000 0x0 0x1000>;
 160         };
 161
 162         pmugrf: syscon@ff738000 {
 163                 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
 164                 reg = <0x0 0xff738000 0x0 0x1000>;
 165         };
 166
 167         sgrf: syscon@ff740000 {
 168                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 169                 reg = <0x0 0xff740000 0x0 0x1000>;
 170
 171         };
 172
 173         cru: syscon@ff760000 {
 174                 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
 175                 reg = <0x0 0xff760000 0x0 0x1000>;
 176         };
 177
 178         grf: syscon@ff770000 {
 179                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 180                 reg = <0x0 0xff770000 0x0 0x1000>;
 181         };
 182
 183         arm-pmu {
 184                 compatible = "arm,armv8-pmuv3";
 185                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 193         };
 194
 195         cpu_axi_bus: cpu_axi_bus {
 196                 compatible = "rockchip,cpu_axi_bus";
 197                 #address-cells = <2>;
 198                 #size-cells = <2>;
 199                 ranges;
 200
 201                 qos {
 202                         #address-cells = <2>;
 203                         #size-cells = <2>;
 204                         ranges;
 205
 206                         dmac {
 207                                 reg = <0x0 0xffa80000 0x0 0x20>;
 208                         };
 209                         crypto {
 210                                 reg = <0x0 0xffa80080 0x0 0x20>;
 211                         };
 212                         tsp {
 213                                 reg = <0x0 0xffa80280 0x0 0x20>;
 214                         };
 215                         bus_cpup {
 216                                 reg = <0x0 0xffa90000 0x0 0x20>;
 217                         };
 218                         cci_r {
 219                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 220                         };
 221                         cci_w {
 222                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 223                         };
 224                         peri {
 225                                 reg = <0x0 0xffab0000 0x0 0x20>;
 226                                 rockchip,priority = <2 2>;
 227                         };
 228                         iep {
 229                                 reg = <0x0 0xffad0000 0x0 0x20>;
 230                         };
 231                         isp_r0 {
 232                                 reg = <0x0 0xffad0080 0x0 0x20>;
 233                         };
 234                         isp_r1 {
 235                                 reg = <0x0 0xffad0100 0x0 0x20>;
 236                         };
 237                         isp_w0 {
 238                                 reg = <0x0 0xffad0180 0x0 0x20>;
 239                                 rockchip,priority = <2 2>;
 240                         };
 241                         isp_w1 {
 242                                 reg = <0x0 0xffad0200 0x0 0x20>;
 243                                 rockchip,priority = <2 2>;
 244                         };
 245                         vip {
 246                                 reg = <0x0 0xffad0280 0x0 0x20>;
 247                         };
 248                         vop {
 249                                 reg = <0x0 0xffad0300 0x0 0x20>;
 250                                 rockchip,priority = <2 2>;
 251                         };
 252                         rga_r {
 253                                 reg = <0x0 0xffad0380 0x0 0x20>;
 254                         };
 255                         rga_w {
 256                                 reg = <0x0 0xffad0400 0x0 0x20>;
 257                         };
 258                         hevc_r {
 259                                 reg = <0x0 0xffae0000 0x0 0x20>;
 260                         };
 261                         vpu_r {
 262                                 reg = <0x0 0xffae0100 0x0 0x20>;
 263                         };
 264                         vpu_w {
 265                                 reg = <0x0 0xffae0180 0x0 0x20>;
 266                         };
 267                         gpu {
 268                                 reg = <0x0 0xffaf0000 0x0 0x20>;
 269                         };
 270                 };
 271
 272                 msch {
 273                         #address-cells = <2>;
 274                         #size-cells = <2>;
 275                         ranges;
 276
 277                         msch {
 278                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 279                                 rockchip,read-latency = <0x34>;
 280                         };
 281                 };
 282         };
 283
 284         timer {
 285                 compatible = "arm,armv8-timer";
 286                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 287                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 288                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 289                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 290                 clock-frequency = <24000000>;
 291         };
 292
 293         timer@ff810000 {
 294                 compatible = "rockchip,timer";
 295                 reg = <0x0 0xff810000 0x0 0x20>;
 296                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 297                 rockchip,broadcast = <1>;
 298         };
 299
 300         sram: sram@ff8c0000 {
 301                 compatible = "mmio-sram";
 302                 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
 303                 map-exec;
 304         };
 305
 306         watchdog: wdt@ff800000 {
 307                 compatible = "rockchip,watch dog";
 308                 reg = <0x0 0xff800000 0x0 0x100>;
 309                 clocks = <&pclk_alive_pre>;
 310                 clock-names = "pclk_wdt";
 311                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 312                 rockchip,irq = <1>;
 313                 rockchip,timeout = <60>;
 314                 rockchip,atboot = <1>;
 315                 rockchip,debug = <0>;
 316                 status = "disabled";
 317         };
 318
 319         amba {
 320                 #address-cells = <2>;
 321                 #size-cells = <2>;
 322                 compatible = "arm,amba-bus";
 323                 interrupt-parent = <&gic>;
 324                 ranges;
 325
 326                 pdma0: pdma@ff600000 {
 327                         compatible = "arm,pl330", "arm,primecell";
 328                         reg = <0x0 0xff600000 0x0 0x4000>;
 329                         clocks = <&clk_gates12 11>;
 330                         clock-names = "apb_pclk";
 331                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 332                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 333                         #dma-cells = <1>;
 334
 335                 };
 336
 337                 pdma1: pdma@ff250000 {
 338                         compatible = "arm,pl330", "arm,primecell";
 339                         reg = <0x0 0xff250000 0x0 0x4000>;
 340                         clocks = <&clk_gates19 3>;
 341                         clock-names = "apb_pclk";
 342                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 343                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 344                         #dma-cells = <1>;
 345                 };
 346         };
 347
 348         reset: reset@ff760300{
 349                 compatible = "rockchip,reset";
 350                 reg = <0x0 0xff760300 0x0 0x38>;
 351                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 352                 #reset-cells = <1>;
 353         };
 354
 355         nandc0: nandc@ff400000 {
 356                 compatible = "rockchip,rk-nandc";
 357                 reg = <0x0 0xff400000 0x0 0x4000>;
 358                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 359                 nandc_id = <0>;
 360                 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
 361                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 362         };
 363
 364         nandc0reg: nandc0@ff400000 {
 365                 compatible = "rockchip,rk-nandc";
 366                 reg = <0x0 0xff400000 0x0 0x4000>;
 367         };
 368
 369         emmc: rksdmmc@ff0f0000 {
 370                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 371                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 372                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
 376                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 377                 rockchip,grf = <&grf>;
 378                 num-slots = <1>;
 379                 fifo-depth = <0x100>;
 380                 bus-width = <8>;
 381         };
 382
 383         sdmmc: rksdmmc@ff0c0000 {
 384                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 385                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 386                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 387                 #address-cells = <1>;
 388                 #size-cells = <0>;
 389                 pinctrl-names = "default", "idle", "udbg";
 390                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 391                 pinctrl-1 = <&sdmmc_gpio>;
 392                 pinctrl-2 = <&uart2_xfer &cpu_jtag &sdmmc_dectn>;
 393                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 394                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
 395                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 396                 rockchip,grf = <&grf>;
 397                 num-slots = <1>;
 398                 fifo-depth = <0x100>;
 399                 bus-width = <4>;
 400         };
 401
 402         sdio: rksdmmc@ff0d0000 {
 403                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 404                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 405                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 pinctrl-names = "default","idle";
 409                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 410                 pinctrl-1 = <&sdio0_gpio>;
 411                 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
 412                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 413                 rockchip,grf = <&grf>;
 414                 num-slots = <1>;
 415                 fifo-depth = <0x100>;
 416                 bus-width = <4>;
 417         };
 418
 419         spi0: spi@ff110000 {
 420                 compatible = "rockchip,rockchip-spi";
 421                 reg = <0x0 0xff110000 0x0 0x1000>;
 422                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 423                 #address-cells = <1>;
 424                 #size-cells = <0>;
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 427                 rockchip,spi-src-clk = <0>;
 428                 num-cs = <2>;
 429                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 430                 clock-names = "spi", "pclk_spi0";
 431                 //dmas = <&pdma1 11>, <&pdma1 12>;
 432                 //#dma-cells = <2>;
 433                 //dma-names = "tx", "rx";
 434                 status = "disabled";
 435         };
 436
 437         spi1: spi@ff120000 {
 438                 compatible = "rockchip,rockchip-spi";
 439                 reg = <0x0 0xff120000 0x0 0x1000>;
 440                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 441                 #address-cells = <1>;
 442                 #size-cells = <0>;
 443                 pinctrl-names = "default";
 444                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 445                 rockchip,spi-src-clk = <1>;
 446                 num-cs = <1>;
 447                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 448                 clock-names = "spi", "pclk_spi1";
 449                 //dmas = <&pdma1 13>, <&pdma1 14>;
 450                 //#dma-cells = <2>;
 451                 //dma-names = "tx", "rx";
 452                 status = "disabled";
 453         };
 454
 455         spi2: spi@ff130000 {
 456                 compatible = "rockchip,rockchip-spi";
 457                 reg = <0x0 0xff130000 0x0 0x1000>;
 458                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 pinctrl-names = "default";
 462                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 463                 rockchip,spi-src-clk = <2>;
 464                 num-cs = <1>;
 465                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 466                 clock-names = "spi", "pclk_spi2";
 467                 //dmas = <&pdma1 15>, <&pdma1 16>;
 468                 //#dma-cells = <2>;
 469                 //dma-names = "tx", "rx";
 470                 status = "disabled";
 471         };
 472
 473         uart_bt: serial@ff180000 {
 474                 compatible = "rockchip,serial";
 475                 reg = <0x0 0xff180000 0x0 0x100>;
 476                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 477                 clock-frequency = <24000000>;
 478                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 479                 clock-names = "sclk_uart", "pclk_uart";
 480                 reg-shift = <2>;
 481                 reg-io-width = <4>;
 482                 //dmas = <&pdma1 1>, <&pdma1 2>;
 483                 //#dma-cells = <2>;
 484                 pinctrl-names = "default";
 485                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 486                 status = "disabled";
 487         };
 488
 489         uart_bb: serial@ff190000 {
 490                 compatible = "rockchip,serial";
 491                 reg = <0x0 0xff190000 0x0 0x100>;
 492                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 493                 clock-frequency = <24000000>;
 494                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 495                 clock-names = "sclk_uart", "pclk_uart";
 496                 reg-shift = <2>;
 497                 reg-io-width = <4>;
 498                 //dmas = <&pdma1 3>, <&pdma1 4>;
 499                 //#dma-cells = <2>;
 500                 pinctrl-names = "default";
 501                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 502                 status = "disabled";
 503         };
 504
 505         uart_dbg: serial@ff690000 {
 506                 compatible = "rockchip,serial";
 507                 reg = <0x0 0xff690000 0x0 0x100>;
 508                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 509                 clock-frequency = <24000000>;
 510                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 511                 clock-names = "sclk_uart", "pclk_uart";
 512                 reg-shift = <2>;
 513                 reg-io-width = <4>;
 514                 //dmas = <&pdma0 4>, <&pdma0 5>;
 515                 //#dma-cells = <2>;
 516                 //pinctrl-names = "default";
 517                 //pinctrl-0 = <&uart2_xfer>;
 518                 status = "disabled";
 519         };
 520
 521         uart_gps: serial@ff1b0000 {
 522                 compatible = "rockchip,serial";
 523                 reg = <0x0 0xff1b0000 0x0 0x100>;
 524                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 525                 clock-frequency = <24000000>;
 526                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 527                 clock-names = "sclk_uart", "pclk_uart";
 528                 current-speed = <115200>;
 529                 reg-shift = <2>;
 530                 reg-io-width = <4>;
 531                 //dmas = <&pdma1 7>, <&pdma1 8>;
 532                 //#dma-cells = <2>;
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 535                 status = "disabled";
 536         };
 537
 538         uart_exp: serial@ff1c0000 {
 539                 compatible = "rockchip,serial";
 540                 reg = <0x0 0xff1c0000 0x0 0x100>;
 541                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 542                 clock-frequency = <24000000>;
 543                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 544                 clock-names = "sclk_uart", "pclk_uart";
 545                 reg-shift = <2>;
 546                 reg-io-width = <4>;
 547                 //dmas = <&pdma1 9>, <&pdma1 10>;
 548                 //#dma-cells = <2>;
 549                 pinctrl-names = "default";
 550                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 551                 status = "disabled";
 552         };
 553
 554         rockchip_clocks_init: clocks-init{
 555                 compatible = "rockchip,clocks-init";
 556                 rockchip,clocks-init-parent =
 557                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 558                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 559                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 560                         <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
 561                 rockchip,clocks-init-rate =
 562                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 563                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 564                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 565                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 566                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 567                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 568                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 569                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 570                         <&aclk_cci 600000000>,          <&clk_mac 125000000>,
 571                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 572                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 573                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 574                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 575                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 576                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 577                         <&clk_hevc_cabac 300000000>;
 578 /*
 579                 rockchip,clocks-uboot-has-init =
 580                         <&aclk_vio0>;
 581 */
 582         };
 583
 584         rockchip_clocks_enable: clocks-enable {
 585                 compatible = "rockchip,clocks-enable";
 586                 clocks =
 587                 <&pd_vio>,
 588                <&pd_video>,
 589                <&pd_gpu_0>,
 590                <&pd_gpu_1>,
 591
 592                         /*PLL*/
 593                         <&clk_apllb>,
 594                         <&clk_aplll>,
 595                         <&clk_dpll>,
 596                         <&clk_gpll>,
 597                         <&clk_cpll>,
 598
 599                         /*PD_CORE*/
 600                         <&clk_cs>,
 601                         <&clkin_trace>,
 602                         <&aclk_cci>,
 603
 604                         /*PD_BUS*/
 605                         <&aclk_bus>,
 606                         <&hclk_bus>,
 607                         <&pclk_bus>,
 608                         <&clk_gates12 12>,/*aclk_strc_sys*/
 609                         <&clk_gates12 6>,/*aclk_intmem1*/
 610                         <&clk_gates12 5>,/*aclk_intmem0*/
 611                         <&clk_gates12 4>,/*aclk_intmem*/
 612                         <&clk_gates13 9>,/*aclk_gic400*/
 613                         <&clk_gates12 9>,/*hclk_rom*/
 614
 615                         /*PD_ALIVE*/
 616                         <&clk_gates22 13>,/*pclk_timer1*/
 617                         <&clk_gates22 12>,/*pclk_timer0*/
 618                         <&clk_gates22 9>,/*pclk_alive_niu*/
 619                         <&clk_gates22 8>,/*pclk_grf*/
 620
 621                         /*PD_PMU*/
 622                         <&clk_gates23 5>,/*pclk_pmugrf*/
 623                         <&clk_gates23 3>,/*pclk_sgrf*/
 624                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 625                         <&clk_gates23 1>,/*pclk_intmem1*/
 626                         <&clk_gates23 0>,/*pclk_pmu*/
 627
 628                         /*PD_PERI*/
 629                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 630                         <&clk_gates20 8>,/*aclk_peri_niu*/
 631                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 632                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 633                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 634                         <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
 635         };
 636
 637         /* I2C_PMU */
 638         i2c0: i2c@ff650000 {
 639                 compatible = "rockchip,rk30-i2c";
 640                 reg = <0x0 0xff650000 0x0 0x1000>;
 641                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 642                 #address-cells = <1>;
 643                 #size-cells = <0>;
 644                 pinctrl-names = "default", "gpio";
 645                 pinctrl-0 = <&i2c0_xfer>;
 646                 pinctrl-1 = <&i2c0_gpio>;
 647                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 648                 clocks = <&clk_gates12 2>;
 649                 rockchip,check-idle = <1>;
 650                 status = "disabled";
 651         };
 652
 653         /* I2C_AUDIO */
 654         i2c1: i2c@ff660000 {
 655                 compatible = "rockchip,rk30-i2c";
 656                 reg = <0x0 0xff660000 0x0 0x1000>;
 657                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 658                 #address-cells = <1>;
 659                 #size-cells = <0>;
 660                 pinctrl-names = "default", "gpio";
 661                 pinctrl-0 = <&i2c1_xfer>;
 662                 pinctrl-1 = <&i2c1_gpio>;
 663                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 664                 clocks = <&clk_gates12 3>;
 665                 rockchip,check-idle = <1>;
 666                 status = "disabled";
 667         };
 668
 669         /* I2C_SENSOR */
 670         i2c2: i2c@ff140000 {
 671                 compatible = "rockchip,rk30-i2c";
 672                 reg = <0x0 0xff140000 0x0 0x1000>;
 673                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 674                 #address-cells = <1>;
 675                 #size-cells = <0>;
 676                 pinctrl-names = "default", "gpio";
 677                 pinctrl-0 = <&i2c2_xfer>;
 678                 pinctrl-1 = <&i2c2_gpio>;
 679                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 680                 clocks = <&clk_gates19 11>;
 681                 rockchip,check-idle = <1>;
 682                 status = "disabled";
 683         };
 684
 685         /* I2C_CAM */
 686         i2c3: i2c@ff150000 {
 687                 compatible = "rockchip,rk30-i2c";
 688                 reg = <0x0 0xff150000 0x0 0x1000>;
 689                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 690                 #address-cells = <1>;
 691                 #size-cells = <0>;
 692                 pinctrl-names = "default", "gpio";
 693                 pinctrl-0 = <&i2c3_xfer>;
 694                 pinctrl-1 = <&i2c3_gpio>;
 695                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 696                 clocks = <&clk_gates19 12>;
 697                 rockchip,check-idle = <1>;
 698                 status = "disabled";
 699         };
 700
 701         /* I2C_TP */
 702         i2c4: i2c@ff160000 {
 703                 compatible = "rockchip,rk30-i2c";
 704                 reg = <0x0 0xff160000 0x0 0x1000>;
 705                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 706                 #address-cells = <1>;
 707                 #size-cells = <0>;
 708                 pinctrl-names = "default", "gpio";
 709                 pinctrl-0 = <&i2c4_xfer>;
 710                 pinctrl-1 = <&i2c4_gpio>;
 711                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 712                 clocks = <&clk_gates19 13>;
 713                 rockchip,check-idle = <1>;
 714                 status = "disabled";
 715         };
 716
 717         /* I2C_HDMI */
 718         i2c5: i2c@ff170000 {
 719                 compatible = "rockchip,rk30-i2c";
 720                 reg = <0x0 0xff170000 0x0 0x1000>;
 721                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 722                 #address-cells = <1>;
 723                 #size-cells = <0>;
 724                 pinctrl-names = "default", "gpio";
 725                 pinctrl-0 = <&i2c5_xfer>;
 726                 pinctrl-1 = <&i2c5_gpio>;
 727                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 728                 clocks = <&clk_gates19 14>;
 729                 rockchip,check-idle = <1>;
 730                 status = "disabled";
 731         };
 732
 733         fb: fb {
 734                 compatible = "rockchip,rk-fb";
 735                 rockchip,disp-mode = <NO_DUAL>;
 736         };
 737
 738
 739         rk_screen: rk_screen {
 740                 compatible = "rockchip,screen";
 741         };
 742
 743         dsihost0: mipi@ff960000{
 744                 compatible = "rockchip,rk3368-dsi";
 745                 rockchip,prop = <0>;
 746                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 747                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 748                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 749                 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>;
 750                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 751                 status = "okay";
 752         };
 753
 754         lvds: lvds@ff968000 {
 755                 compatible = "rockchip,rk3368-lvds";
 756                 rockchip,grf = <&grf>;
 757                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 758                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 759                 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
 760                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 761                 status = "disabled";
 762         };
 763
 764         edp: edp@ff970000 {
 765                 compatible = "rockchip,rk32-edp";
 766                 reg = <0x0 0xff970000 0x0 0x4000>;
 767                 rockchip,grf = <&grf>;
 768                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 769                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 770                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 771                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 772                 reset-names = "edp_24m", "edp_apb";
 773         };
 774
 775         hdmi: hdmi@ff980000 {
 776                 compatible = "rockchip,rk3368-hdmi";
 777                 reg = <0x0 0xff980000 0x0 0x20000>;
 778                 rockchip,grf = <&grf>;
 779                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 780                 pinctrl-names = "default", "gpio";
 781                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 782                 pinctrl-1 = <&i2c5_gpio>;
 783                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 784                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 785                 status = "disabled";
 786         };
 787
 788         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 789                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 790                 reg = <0x0 0xff978000 0x0 0x2000>;
 791                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 792                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 793                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 794                 status = "disabled";
 795         };
 796
 797         lcdc: lcdc@ff930000 {
 798                  compatible = "rockchip,rk3368-lcdc";
 799                  rockchip,grf = <&grf>;
 800                  rockchip,pmugrf = <&pmugrf>;
 801                  rockchip,prop = <PRMRY>;
 802                  rockchip,pwr18 = <0>;
 803                  rockchip,iommu-enabled = <0>;
 804                  reg = <0x0 0xff930000 0x0 0x10000>;
 805                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 806                 /*pinctrl-names = "default", "gpio";
 807                  *pinctrl-0 = <&lcdc_lcdc>;
 808                  *pinctrl-1 = <&lcdc_gpio>;
 809                  */
 810                  status = "disabled";
 811                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
 812                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
 813         };
 814
 815         adc: adc@ff100000 {
 816                 compatible = "rockchip,saradc";
 817                 reg = <0x0 0xff100000 0x0 0x100>;
 818                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 819                 #io-channel-cells = <1>;
 820                 io-channel-ranges;
 821                 rockchip,adc-vref = <1800>;
 822                 clock-frequency = <1000000>;
 823                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 824                 clock-names = "saradc", "pclk_saradc";
 825                 status = "disabled";
 826         };
 827
 828         rga@ff920000 {
 829                 compatible = "rockchip,rk3368-rga2";
 830                 reg = <0x0 0xff920000 0x0 0x1000>;
 831                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 832                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 833                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 834         };
 835
 836         i2s0: i2s0@ff898000 {
 837                 compatible = "rockchip-i2s";
 838                 reg = <0x0 0xff898000 0x0 0x1000>;
 839                 i2s-id = <0>;
 840                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 841                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 842                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 843                 dmas = <&pdma0 0>, <&pdma0 1>;
 844                 #dma-cells = <2>;
 845                 dma-names = "tx", "rx";
 846                 pinctrl-names = "default", "sleep";
 847                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 848                 pinctrl-1 = <&i2s_gpio>;
 849         };
 850
 851         i2s1: i2s1@ff890000 {
 852                 compatible = "rockchip-i2s";
 853                 reg = <0x0 0xff890000 0x0 0x1000>;
 854                 i2s-id = <1>;
 855                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 856                 clock-names = "i2s_clk", "i2s_hclk";
 857                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 858                 dmas = <&pdma0 6>, <&pdma0 7>;
 859                 #dma-cells = <2>;
 860                 dma-names = "tx", "rx";
 861         };
 862
 863         spdif: spdif@ff880000 {
 864                 compatible = "rockchip-spdif";
 865                 reg = <0x0 0xff880000 0x0 0x1000>;
 866                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 867                 clock-names = "spdif_mclk", "spdif_hclk";
 868                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 869                 dmas = <&pdma0 3>;
 870                 #dma-cells = <1>;
 871                 dma-names = "tx";
 872                 pinctrl-names = "default";
 873                 pinctrl-0 = <&spdif_tx>;
 874         };
 875
 876         pwm0: pwm@ff680000 {
 877                 compatible = "rockchip,rk-pwm";
 878                 reg = <0x0 0xff680000 0x0 0x10>;
 879                 #pwm-cells = <2>;
 880                 pinctrl-names = "default";
 881                 pinctrl-0 = <&pwm0_pin>;
 882                 clocks = <&clk_gates13 6>;
 883                 clock-names = "pclk_pwm";
 884                 status = "disabled";
 885         };
 886
 887         pwm1: pwm@ff680010 {
 888                 compatible = "rockchip,rk-pwm";
 889                 reg = <0x0 0xff680010 0x0 0x10>;
 890                 #pwm-cells = <2>;
 891                 pinctrl-names = "default";
 892                 pinctrl-0 = <&pwm1_pin>;
 893                 clocks = <&clk_gates13 6>;
 894                 clock-names = "pclk_pwm";
 895                 status = "disabled";
 896         };
 897
 898         pwm2: pwm@ff680020 {
 899                 compatible = "rockchip,rk-pwm";
 900                 reg = <0x0 0xff680020 0x0 0x10>;
 901                 #pwm-cells = <2>;
 902                 //pinctrl-names = "default";
 903                 //pinctrl-0 = <&pwm1_pin>;
 904                 clocks = <&clk_gates13 6>;
 905                 clock-names = "pclk_pwm";
 906                 status = "disabled";
 907         };
 908
 909         pwm3: pwm@ff680030 {
 910                 compatible = "rockchip,rk-pwm";
 911                 reg = <0x0 0xff680030 0x0 0x10>;
 912                 #pwm-cells = <2>;
 913                 pinctrl-names = "default";
 914                 pinctrl-0 = <&pwm3_pin>;
 915                 clocks = <&clk_gates13 6>;
 916                 clock-names = "pclk_pwm";
 917                 status = "disabled";
 918         };
 919
 920         remotectl: pwm@ff680030 {
 921                 compatible = "rockchip,remotectl-pwm";
 922                 reg = <0x0 0xff680030 0x0 0x50>;
 923                 #pwm-cells = <2>;
 924                 pinctrl-names = "default";
 925                 pinctrl-0 = <&pwm3_pin>;
 926                 clocks = <&clk_gates13 6>;
 927                 clock-names = "pclk_pwm";
 928                 dmas = <&pdma0 2>;
 929                 #dma-cells = <2>;
 930                 dma-names = "rx";
 931                 remote_pwm_id = <3>;
 932                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 933                 status = "disabled";
 934         };
 935
 936         voppwm: pwm@ff9301a0 {
 937                 compatible = "rockchip,vop-pwm";
 938                 reg = <0x0 0xff9301a0 0x0 0x10>;
 939                 #pwm-cells = <2>;
 940                 pinctrl-names = "default";
 941                 pinctrl-0 = <&vop_pwm_pin>;
 942                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
 943                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 944                 status = "disabled";
 945         };
 946
 947         pvtm {
 948                 compatible = "rockchip,rk3368-pvtm";
 949                 rockchip,grf = <&grf>;
 950                 rockchip,pmugrf = <&pmugrf>;
 951                 rockchip,pvtm-clk-out = <1>;
 952         };
 953
 954         cpufreq {
 955                 compatible = "rockchip,rk3368-cpufreq";
 956                 rockchip,grf = <&grf>;
 957         };
 958
 959         dvfs {
 960
 961                 vd_arm: vd_arm {
 962                         regulator_name = "vdd_arm";
 963                         suspend_volt = <1000>; //mV
 964                         pd_core {
 965                                 clk_core_b_dvfs_table: clk_core_b {
 966                                         operating-points = <
 967                                                 /* KHz    uV */
 968                                                 312000 1200000
 969                                                 504000 1200000
 970                                                 816000 1200000
 971                                                 1008000 1200000
 972                                                 >;
 973                                         status = "okay";
 974                                 };
 975                                 clk_core_l_dvfs_table: clk_core_l {
 976                                         operating-points = <
 977                                                 /* KHz    uV */
 978                                                 312000 1200000
 979                                                 504000 1200000
 980                                                 816000 1200000
 981                                                 1008000 1200000
 982                                                 >;
 983                                         status = "okay";
 984                                 };
 985                         };
 986                 };
 987
 988                 vd_logic: vd_logic {
 989                         regulator_name = "vdd_logic";
 990                         suspend_volt = <1000>; //mV
 991                         pd_ddr {
 992                                 clk_ddr_dvfs_table: clk_ddr {
 993                                         operating-points = <
 994                                                 /* KHz    uV */
 995                                                 200000 1200000
 996                                                 300000 1200000
 997                                                 400000 1200000
 998                                                 >;
 999                                         channel = <2>;
1000                                         status = "disabled";
1001                                 };
1002                         };
1003
1004                         pd_gpu {
1005                                 clk_gpu_dvfs_table: clk_gpu {
1006                                         operating-points = <
1007                                                 /* KHz    uV */
1008                                                 200000 1200000
1009                                                 300000 1200000
1010                                                 400000 1200000
1011                                                 >;
1012                                         channel = <1>;
1013                                         status = "okay";
1014                                         regu-mode-table = <
1015                                                 /*freq     mode*/
1016                                                 200000     4
1017                                                 0          3
1018                                         >;
1019                                         regu-mode-en = <0>;
1020                                 };
1021                         };
1022                 };
1023         };
1024
1025         ion {
1026                 compatible = "rockchip,ion";
1027                 #address-cells = <1>;
1028                 #size-cells = <0>;
1029
1030                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1031                         compatible = "rockchip,ion-heap";
1032                         rockchip,ion_heap = <4>;
1033                         reg = <0x00000000 0x08000000>; /* 512MB */
1034                 };
1035                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1036                         compatible = "rockchip,ion-heap";
1037                         rockchip,ion_heap = <0>;
1038                 };
1039         };
1040
1041         vpu: vpu_service {
1042                 compatible = "rockchip,vpu_sub";
1043                 iommu_enabled = <0>;
1044                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1045                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1046                 interrupt-names = "irq_enc", "irq_dec";
1047                 dev_mode = <0>;
1048                 name = "vpu_service";
1049         };
1050
1051         hevc: hevc_service {
1052                 compatible = "rockchip,hevc_sub";
1053                 iommu_enabled = <0>;
1054                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1055                 interrupt-names = "irq_dec";
1056                 dev_mode = <1>;
1057                 name = "hevc_service";
1058         };
1059
1060         vpu_combo: vpu_combo@ff9a0000 {
1061                 compatible = "rockchip,vpu_combo";
1062                 reg = <0x0 0xff9a0000 0x0 0x800>;
1063                 rockchip,grf = <&grf>;
1064                 subcnt = <2>;
1065                 rockchip,sub = <&vpu>, <&hevc>;
1066                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1067                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1068                 mode_bit = <12>;
1069                 mode_ctrl = <0x418>;
1070                 name = "vpu_combo";
1071                 status = "okay";
1072         };
1073
1074         iep: iep@ff900000 {
1075                 compatible = "rockchip,iep";
1076                 iommu_enabled = <0>;
1077                 reg = <0x0 0xff900000 0x0 0x800>;
1078                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1079                 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1080                 clock-names = "aclk_iep", "hclk_iep";
1081                 status = "okay";
1082         };
1083
1084         gmac: eth@ff290000 {
1085                 compatible = "rockchip,rk3368-gmac";
1086                 reg = <0x0 0xff290000 0x0 0x10000>;
1087                 rockchip,grf = <&grf>;
1088                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1089                 interrupt-names = "macirq";
1090
1091                 clocks = <&clk_mac>, <&clk_gates7 4>,
1092                          <&clk_gates7 5>, <&clk_gates7 6>,
1093                          <&clk_gates7 7>, <&clk_gates20 13>,
1094                          <&clk_gates20 14>;
1095                 clock-names = "clk_mac", "mac_clk_rx",
1096                               "mac_clk_tx", "clk_mac_ref",
1097                               "clk_mac_refout", "aclk_mac",
1098                               "pclk_mac";
1099
1100                 phy-mode = "rgmii";
1101                 pinctrl-names = "default";
1102                 pinctrl-0 = <&rgmii_pins>;
1103         };
1104
1105         gpu {
1106                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1107                 reg = <0x0 0xffa30000 0x0 0x10000>;
1108                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1109                 interrupt-names = "GPU";
1110         };
1111
1112         iep_mmu {
1113                 dbgname = "iep";
1114                 compatible = "rockchip,iep_mmu";
1115                 reg = <0x0 0xff900800 0x0 0x100>;
1116                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1117                 interrupt-names = "iep_mmu";
1118         };
1119
1120         vip_mmu {
1121                 dbgname = "vip";
1122                 compatible = "rockchip,vip_mmu";
1123                 reg = <0x0 0xff950800 0x0 0x100>;
1124                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1125                 interrupt-names = "vip_mmu";
1126         };
1127
1128         vop_mmu {
1129                 dbgname = "vop";
1130                 compatible = "rockchip,vopb_mmu";
1131                 reg = <0x0 0xff930300 0x0 0x100>;
1132                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1133                 interrupt-names = "vop_mmu";
1134         };
1135
1136         isp_mmu {
1137                 dbgname = "isp_mmu";
1138                 compatible = "rockchip,isp_mmu";
1139                 reg = <0x0 0xff914000 0x0 0x100>,
1140                 <0x0 0xff915000 0x0 0x100>;
1141                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1142                 interrupt-names = "isp_mmu";
1143         };
1144
1145         hdcp_mmu {
1146                 dbgname = "hdcp_mmu";
1147                 compatible = "rockchip,hdcp_mmu";
1148                 reg = <0x0 0xff940000 0x0 0x100>;
1149                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1150                 interrupt-names = "hdcp_mmu";
1151         };
1152
1153         hevc_mmu {
1154                 dbgname = "hevc";
1155                 compatible = "rockchip,hevc_mmu";
1156                 reg = <0x0 0xff9c0440 0x0 0x40>,                      /*need to fix*/
1157                           <0x0 0xff9c0480 0x0 0x40>;
1158                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1159                 interrupt-names = "hevc_mmu";
1160         };
1161
1162         vpu_mmu {
1163                 dbgname = "vpu";
1164                 compatible = "rockchip,vpu_mmu";
1165                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1166                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;       /*need to fix*/
1167                 interrupt-names = "vpu_mmu";
1168         };
1169
1170         rockchip_suspend {
1171                 rockchip,ctrbits = <
1172                         (0
1173                          |RKPM_CTR_PWR_DMNS
1174                          |RKPM_CTR_GTCLKS
1175                          |RKPM_CTR_PLLS
1176                          |RKPM_CTR_GPIOS
1177                         /*
1178                          |RKPM_CTR_SYSCLK_DIV
1179                          |RKPM_CTR_IDLEAUTO_MD
1180                          |RKPM_CTR_ARMOFF_LPMD
1181                         */
1182                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1183                         )
1184                         >;
1185                 rockchip,pmic-suspend_gpios = <
1186                                  /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1187                         >;
1188                 rockchip,pmic-resume_gpios = <
1189                                 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1190                         >;
1191         };
1192
1193         isp: isp@ff910000{
1194                 compatible = "rockchip,isp";
1195                 reg = <0x0 0xff910000 0x0 0x10000>;
1196                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1197                 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1198                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1199                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1200                 pinctrl-0 = <&cif_clkout>;
1201                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1202                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1203                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1204                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1205                 pinctrl-5 = <&cif_clkout>;
1206                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1207                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1208                 pinctrl-8 = <&isp_flash_trigger>;
1209                 rockchip,isp,mipiphy = <2>;
1210                 rockchip,isp,cifphy = <1>;
1211                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1212                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1213                 rockchip,grf = <&grf>;
1214                 rockchip,cru = <&cru>;
1215                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1216                 rockchip,isp,iommu_enable = <0>;
1217                 status = "okay";
1218         };
1219
1220         cif: cif@ff950000 {
1221                 compatible = "rockchip,cif";
1222                 reg = <0x0 0xff950000 0x0 0x10000>;
1223                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1224                 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1225                 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1226                 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1227                 pinctrl-names = "cif_pin_all";
1228                 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1229                 rockchip,grf = <&grf>;
1230                 rockchip,cru = <&cru>;
1231                 status = "okay";
1232         };
1233
1234 /*
1235         thermal-zones {
1236                 #include "rk3368-thermal.dtsi"
1237         };
1238 */
1239
1240         tsadc: tsadc@ff280000 {
1241                 compatible = "rockchip,rk3368-tsadc";
1242                 reg = <0x0 0xff280000 0x0 0x100>;
1243                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1244                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1245                 rockchip,grf = <&grf>;
1246                 rockchip,cru = <&cru>;
1247                 rockchip,pmu = <&pmu>;
1248                 clock-names = "tsadc", "apb_pclk";
1249                 clock-frequency = <32000>;
1250                 resets = <&reset RK3368_SRST_TSADC_P>;
1251                 reset-names = "tsadc-apb";
1252                 //pinctrl-names = "default";
1253                 //pinctrl-0 = <&tsadc_int>;
1254                 #thermal-sensor-cells = <1>;
1255                 hw-shut-temp = <120000>;
1256                 status = "disabled";
1257         };
1258
1259         tsp: tsp@FF8B0000 {
1260                 compatible = "rockchip,rk3368-tsp";
1261                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1262                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1263                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1264                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1265                 interrupt-names = "irq_tsp";
1266                 // pinctrl-names = "default";
1267                 // pinctrl-0 = <&isp_hsadc>;
1268                 status = "okay";
1269         };
1270
1271         crypto: crypto@FF8A0000{
1272                 compatible = "rockchip,rk3368-crypto";
1273                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1274                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1275                 interrupt-names = "irq_crypto";
1276                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1277                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1278                 status = "okay";
1279         };
1280
1281         dwc_control_usb: dwc-control-usb {
1282                 compatible = "rockchip,rk3368-dwc-control-usb";
1283                 rockchip,grf = <&grf>;
1284                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1285                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1286                 interrupt-names = "otg_id", "otg_bvalid",
1287                                   "otg_linestate", "host0_linestate";
1288                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1289                 clock-names = "hclk_usb_peri", "usbphy_480m";
1290                 //resets = <&reset RK3128_RST_USBPOR>;
1291                 //reset-names = "usbphy_por";
1292                 usb_bc{
1293                         compatible = "inno,phy";
1294                         regbase = &dwc_control_usb;
1295                         rk_usb,bvalid     = <0x4bc 23 1>;
1296                         rk_usb,iddig      = <0x4bc 26 1>;
1297                         rk_usb,vdmsrcen   = <0x718 12 1>;
1298                         rk_usb,vdpsrcen   = <0x718 11 1>;
1299                         rk_usb,rdmpden    = <0x718 10 1>;
1300                         rk_usb,idpsrcen   = <0x718  9 1>;
1301                         rk_usb,idmsinken  = <0x718  8 1>;
1302                         rk_usb,idpsinken  = <0x718  7 1>;
1303                         rk_usb,dpattach   = <0x4b8 31 1>;
1304                         rk_usb,cpdet      = <0x4b8 30 1>;
1305                         rk_usb,dcpattach  = <0x4b8 29 1>;
1306                 };
1307         };
1308
1309         usb0: usb@ff580000 {
1310                 compatible = "rockchip,rk3368_usb20_otg";
1311                 reg = <0x0 0xff580000 0x0 0x40000>;
1312                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1313                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1314                 clock-names = "clk_usbphy0", "hclk_otg";
1315                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1316                                 <&reset RK3368_SRST_USBOTGC0>;
1317                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1318                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1319                 rockchip,usb-mode = <0>;
1320         };
1321
1322         usb_ehci: usb@ff500000 {
1323                 compatible = "generic-ehci";
1324                 reg = <0x0 0xff500000 0x0 0x20000>;
1325                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1326                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1327                 clock-names = "clk_usbphy0", "hclk_ehci";
1328                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1329                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1330                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1331         };
1332
1333         usb_ohci: usb@ff520000 {
1334                 compatible = "generic-ohci";
1335                 reg = <0x0 0xff520000 0x0 0x20000>;
1336                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1337                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1338                 clock-names =  "clk_usbphy0", "hclk_ohci";
1339         };
1340
1341         usb_hsic: usb@ff5c0000 {
1342                 compatible = "rockchip,rk3288_rk_hsic_host";
1343                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1344                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1345 /*
1346                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1347                          <&hsicphy_12m>, <&usbphy_480m>,
1348                          <&otgphy1_480m>, <&otgphy2_480m>;
1349                 clock-names = "hsicphy_480m", "hclk_hsic",
1350                               "hsicphy_12m", "usbphy_480m",
1351                               "hsic_usbphy1", "hsic_usbphy2";
1352                 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1353                                 <&reset RK3288_SOFT_RST_HSICPHY>;
1354                 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1355 */
1356                 status = "disabled";
1357         };
1358
1359         pinctrl: pinctrl {
1360                 compatible = "rockchip,rk3368-pinctrl";
1361                 rockchip,grf = <&grf>;
1362                 rockchip,pmugrf = <&pmugrf>;
1363                 #address-cells = <2>;
1364                 #size-cells = <2>;
1365                 ranges;
1366
1367                 gpio0: gpio0@ff750000 {
1368                         compatible = "rockchip,gpio-bank";
1369                         reg =   <0x0 0xff750000 0x0 0x100>;
1370                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1371                         clocks = <&clk_gates23 4>;
1372
1373                         gpio-controller;
1374                         #gpio-cells = <2>;
1375
1376                         interrupt-controller;
1377                         #interrupt-cells = <2>;
1378                 };
1379
1380                 gpio1: gpio1@ff780000 {
1381                         compatible = "rockchip,gpio-bank";
1382                         reg = <0x0 0xff780000 0x0 0x100>;
1383                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1384                         clocks = <&clk_gates22 1>;
1385
1386                         gpio-controller;
1387                         #gpio-cells = <2>;
1388
1389                         interrupt-controller;
1390                         #interrupt-cells = <2>;
1391                 };
1392
1393                 gpio2: gpio2@ff790000 {
1394                         compatible = "rockchip,gpio-bank";
1395                         reg = <0x0 0xff790000 0x0 0x100>;
1396                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1397                         clocks = <&clk_gates22 2>;
1398
1399                         gpio-controller;
1400                         #gpio-cells = <2>;
1401
1402                         interrupt-controller;
1403                         #interrupt-cells = <2>;
1404                 };
1405
1406                 gpio3: gpio3@ff7a0000 {
1407                         compatible = "rockchip,gpio-bank";
1408                         reg = <0x0 0xff7a0000 0x0 0x100>;
1409                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1410                         clocks = <&clk_gates22 3>;
1411
1412                         gpio-controller;
1413                         #gpio-cells = <2>;
1414
1415                         interrupt-controller;
1416                         #interrupt-cells = <2>;
1417                 };
1418
1419                 pcfg_pull_up: pcfg-pull-up {
1420                         bias-pull-up;
1421                 };
1422
1423                 pcfg_pull_down: pcfg-pull-down {
1424                         bias-pull-down;
1425                 };
1426
1427                 pcfg_pull_none: pcfg-pull-none {
1428                         bias-disable;
1429                 };
1430
1431                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1432                         drive-strength = <8>;
1433                 };
1434
1435                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1436                         drive-strength = <12>;
1437                 };
1438
1439                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1440                         bias-pull-up;
1441                         drive-strength = <8>;
1442                 };
1443
1444                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1445                         drive-strength = <4>;
1446                 };
1447
1448                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1449                         bias-pull-up;
1450                         drive-strength = <4>;
1451                 };
1452
1453                 pcfg_output_high: pcfg-output-high {
1454                         output-high;
1455                 };
1456
1457                 pcfg_output_low: pcfg-output-low {
1458                         output-low;
1459                 };
1460
1461                 i2c0 {
1462                         i2c0_xfer: i2c0-xfer {
1463                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1464                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1465                         };
1466                         i2c0_gpio: i2c0-gpio {
1467                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1468                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1469                         };
1470                 };
1471
1472                 i2c1 {
1473                         i2c1_xfer: i2c1-xfer {
1474                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1475                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1476                         };
1477                         i2c1_gpio: i2c1-gpio {
1478                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1479                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1480                         };
1481                 };
1482
1483                 i2c2 {
1484                         i2c2_xfer: i2c2-xfer {
1485                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1486                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1487                         };
1488                         i2c2_gpio: i2c2-gpio {
1489                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1490                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1491             };
1492                 };
1493
1494                 i2c3 {
1495                         i2c3_xfer: i2c3-xfer {
1496                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1497                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1498                         };
1499                         i2c3_gpio: i2c3-gpio {
1500                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1501                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1502                         };
1503                 };
1504
1505                 i2c4 {
1506                         i2c4_xfer: i2c4-xfer {
1507                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1508                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1509                         };
1510                         i2c4_gpio: i2c4-gpio {
1511                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1512                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1513                         };
1514                 };
1515
1516                 i2c5 {
1517                         i2c5_xfer: i2c5-xfer {
1518                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1519                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1520                         };
1521                         i2c5_gpio: i2c5-gpio {
1522                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1523                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1524                         };
1525                 };
1526
1527                 uart0 {
1528                         uart0_xfer: uart0-xfer {
1529                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1530                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1531                         };
1532
1533                         uart0_cts: uart0-cts {
1534                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1535                         };
1536
1537                         uart0_rts: uart0-rts {
1538                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1539                         };
1540
1541                         uart0_rts_gpio: uart0-rts-gpio {
1542                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1543                         };
1544                 };
1545
1546                 uart1 {
1547                         uart1_xfer: uart1-xfer {
1548                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1549                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1550                         };
1551
1552                         uart1_cts: uart1-cts {
1553                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1554                         };
1555
1556                         uart1_rts: uart1-rts {
1557                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1558                         };
1559                 };
1560
1561                 uart2 {
1562                         uart2_xfer: uart2-xfer {
1563                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1564                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1565                         };
1566                 };
1567
1568                 uart3 {
1569                         uart3_xfer: uart3-xfer {
1570                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1571                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1572                         };
1573
1574                         uart3_cts: uart3-cts {
1575                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1576                         };
1577
1578                         uart3_rts: uart3-rts {
1579                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1580                         };
1581                 };
1582
1583                 uart4 {
1584                         uart4_xfer: uart4-xfer {
1585                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1586                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1587                         };
1588
1589                         uart4_cts: uart4-cts {
1590                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1591                         };
1592
1593                         uart4_rts: uart4-rts {
1594                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1595                         };
1596                 };
1597
1598                 spi0 {
1599                         spi0_clk: spi0-clk {
1600                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1601                         };
1602                         spi0_cs0: spi0-cs0 {
1603                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1604                         };
1605                         spi0_tx: spi0-tx {
1606                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1607                         };
1608                         spi0_rx: spi0-rx {
1609                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1610                         };
1611                         spi0_cs1: spi0-cs1 {
1612                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1613                         };
1614                 };
1615
1616                 spi1 {
1617                         spi1_clk: spi1-clk {
1618                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1619                         };
1620                         spi1_cs0: spi1-cs0 {
1621                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1622                         };
1623                         spi1_rx: spi1-rx {
1624                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1625                         };
1626                         spi1_tx: spi1-tx {
1627                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1628                         };
1629                 };
1630
1631                 spi2 {
1632                         spi2_clk: spi2-clk {
1633                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1634                         };
1635                         spi2_cs0: spi2-cs0 {
1636                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1637                         };
1638                         spi2_rx: spi2-rx {
1639                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1640                         };
1641                         spi2_tx: spi2-tx {
1642                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1643                         };
1644                 };
1645
1646                 i2s {
1647                         i2s_mclk: i2s-mclk {
1648                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1649                         };
1650
1651                         i2s_sclk:i2s-sclk {
1652                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1653                         };
1654
1655                         i2s_lrckrx:i2s-lrckrx {
1656                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1657                         };
1658
1659                         i2s_lrcktx:i2s-lrcktx {
1660                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1661                         };
1662
1663                         i2s_sdi:i2s-sdi {
1664                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1665                         };
1666
1667                         i2s_sdo0:i2s-sdo0 {
1668                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1669                         };
1670
1671                         i2s_sdo1:i2s-sdo1 {
1672                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1673                         };
1674
1675                         i2s_sdo2:i2s-sdo2 {
1676                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1677                         };
1678
1679                         i2s_sdo3:i2s-sdo3 {
1680                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1681                         };
1682
1683                         i2s_gpio: i2s-gpio {
1684                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1685                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1686                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1687                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1688                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1689                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1690                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1691                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1692                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1693                         };
1694                 };
1695
1696                 spdif {
1697                         spdif_tx: spdif-tx {
1698                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1699                         };
1700                 };
1701
1702                 sdmmc {
1703                         sdmmc_clk: sdmmc-clk {
1704                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1705                         };
1706
1707                         sdmmc_cmd: sdmmc-cmd {
1708                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1709                         };
1710
1711                         sdmmc_dectn: sdmmc-dectn {
1712                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1713                         };
1714
1715                         sdmmc_bus1: sdmmc-bus1 {
1716                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1717                         };
1718
1719                         sdmmc_bus4: sdmmc-bus4 {
1720                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1721                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1722                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1723                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1724                         };
1725
1726                         sdmmc_gpio: sdmmc-gpio {
1727                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1728                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1729                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1730                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1731                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1732                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1733                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1734                         };
1735                 };
1736
1737                 sdio0 {
1738                         sdio0_bus1: sdio0-bus1 {
1739                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1740                         };
1741
1742                         sdio0_bus4: sdio0-bus4 {
1743                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1744                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1745                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1746                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1747                         };
1748
1749                         sdio0_cmd: sdio0-cmd {
1750                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1751                         };
1752
1753                         sdio0_clk: sdio0-clk {
1754                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1755                         };
1756
1757                         sdio0_dectn: sdio0-dectn {
1758                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1759                         };
1760
1761                         sdio0_wrprt: sdio0-wrprt {
1762                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1763                         };
1764
1765                         sdio0_pwren: sdio0-pwren {
1766                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1767                         };
1768
1769                         sdio0_bkpwr: sdio0-bkpwr {
1770                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1771                         };
1772
1773                         sdio0_int: sdio0-int {
1774                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1775                         };
1776
1777                         sdio0_gpio: sdio0-gpio {
1778                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1779                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1780                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1781                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1782                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1783                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1784                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1785                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1786                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1787                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1788                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1789                         };
1790                 };
1791
1792                 emmc {
1793                         emmc_clk: emmc-clk {
1794                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1795                         };
1796
1797                         emmc_cmd: emmc-cmd {
1798                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1799                         };
1800
1801                         emmc_pwren: emmc-pwren {
1802                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1803                         };
1804
1805                         emmc_rstnout: emmc_rstnout {
1806                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1807                         };
1808
1809                         emmc_bus1: emmc-bus1 {
1810                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1811                         };
1812
1813                         emmc_bus4: emmc-bus4 {
1814                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1815                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1816                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1817                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1818                         };
1819                 };
1820
1821                 pwm0 {
1822                         pwm0_pin: pwm0-pin {
1823                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1824                         };
1825
1826                         vop_pwm_pin:vop-pwm {
1827                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1828                         };
1829                 };
1830
1831                 pwm1 {
1832                         pwm1_pin: pwm1-pin {
1833                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1834                         };
1835                 };
1836
1837                 pwm3 {
1838                         pwm3_pin: pwm3-pin {
1839                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1840                         };
1841                 };
1842
1843                 lcdc {
1844                         lcdc_lcdc: lcdc-lcdc {
1845                                 rockchip,pins =
1846                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1847                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1848                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1849                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1850                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1851                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1852                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1853                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1854                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1855                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1856                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1857                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1858                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1859                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1860                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1861                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1862                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1863                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1864                         };
1865
1866                         lcdc_gpio: lcdc-gpio {
1867                                 rockchip,pins =
1868                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1869                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1870                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1871                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1872                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1873                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1874                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1875                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1876                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1877                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1878                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1879                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1880                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1881                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1882                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1883                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1884                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1885                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1886                         };
1887                 };
1888
1889                 isp {
1890                         cif_clkout: cif-clkout {
1891                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1892                         };
1893
1894                         isp_dvp_d2d9: isp-dvp-d2d9 {
1895                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1896                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1897                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1898                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1899                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1900                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1901                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1902                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1903                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1904                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1905                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1906                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1907                         };
1908
1909                         isp_dvp_d0d1: isp-dvp-d0d1 {
1910                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1911                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1912                         };
1913
1914                         isp_dvp_d10d11:isp_d10d11       {
1915                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1916                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1917                         };
1918
1919                         isp_dvp_d0d7: isp-dvp-d0d7 {
1920                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1921                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1922                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1923                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1924                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1925                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1926                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1927                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1928                         };
1929
1930                         isp_shutter: isp-shutter {
1931                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1932                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1933                         };
1934
1935                         isp_flash_trigger: isp-flash-trigger {
1936                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1937                         };
1938
1939                         isp_prelight: isp-prelight {
1940                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1941                         };
1942
1943                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1944                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1945                         };
1946                 };
1947
1948                 gps {
1949                         gps_mag: gps-mag {
1950                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1951                         };
1952
1953                         gps_sig: gps-sig {
1954                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1955
1956                         };
1957
1958                         gps_rfclk: gps-rfclk {
1959                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1960                         };
1961                 };
1962
1963                 gmac {
1964                         rgmii_pins: rgmii-pins {
1965                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1966                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1967                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1968                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1969                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1970                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
1971                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
1972                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
1973                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1974                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1975                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1976                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1977                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1978                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1979                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
1980                         };
1981
1982                         rmii_pins: rmii-pins {
1983                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1984                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1985                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1986                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1987                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1988                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1989                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1990                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1991                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1992                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
1993                         };
1994                 };
1995
1996                 tsadc_pin {
1997                         tsadc_int: tsadc-int {
1998                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1999                         };
2000                         tsadc_gpio: tsadc-gpio {
2001                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
2002                         };
2003                 };
2004
2005                 hdmi_pin {
2006                         hdmi_cec: hdmi-cec {
2007                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2008                         };
2009                 };
2010
2011                 hdmi_i2c {
2012                         hdmii2c_xfer: hdmii2c-xfer {
2013                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2014                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2015                         };
2016                 };
2017
2018                 cpu_jtag {
2019                         cpu_jtag: cpu-jtag {
2020                                 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2021                                                 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2022                         };
2023                 };
2024         };
2025
2026         reboot {
2027                 compatible = "rockchip,rk3368-reboot";
2028                 rockchip,cru = <&cru>;
2029                 rockchip,pmugrf = <&pmugrf>;
2030         };
2031 };