arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 big0: cpu@100 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53", "arm,armv8";
  43                         reg = <0x0 0x100>;
  44                         enable-method = "psci";
  45                 };
  46                 big1: cpu@101 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53", "arm,armv8";
  49                         reg = <0x0 0x101>;
  50                         enable-method = "psci";
  51                 };
  52                 big2: cpu@102 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a53", "arm,armv8";
  55                         reg = <0x0 0x102>;
  56                         enable-method = "psci";
  57                 };
  58                 big3: cpu@103 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x103>;
  62                         enable-method = "psci";
  63                 };
  64                 little0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53", "arm,armv8";
  67                         reg = <0x0 0x0>;
  68                         enable-method = "psci";
  69                 };
  70                 little1: cpu@1 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a53", "arm,armv8";
  73                         reg = <0x0 0x1>;
  74                         enable-method = "psci";
  75                 };
  76                 little2: cpu@2 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53", "arm,armv8";
  79                         reg = <0x0 0x2>;
  80                         enable-method = "psci";
  81                 };
  82                 little3: cpu@3 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53", "arm,armv8";
  85                         reg = <0x0 0x3>;
  86                         enable-method = "psci";
  87                 };
  88
  89                 cpu-map {
  90                         cluster0 {
  91                                 core0 {
  92                                         cpu = <&big0>;
  93                                 };
  94                                 core1 {
  95                                         cpu = <&big1>;
  96                                 };
  97                                 core2 {
  98                                         cpu = <&big2>;
  99                                 };
 100                                 core3 {
 101                                         cpu = <&big3>;
 102                                 };
 103                         };
 104                         cluster1 {
 105                                 core0 {
 106                                         cpu = <&little0>;
 107                                 };
 108                                 core1 {
 109                                         cpu = <&little1>;
 110                                 };
 111                                 core2 {
 112                                         cpu = <&little2>;
 113                                 };
 114                                 core3 {
 115                                         cpu = <&little3>;
 116                                 };
 117                         };
 118                 };
 119         };
 120
 121         psci {
 122                 compatible = "arm,psci";
 123                 method = "smc";
 124                 cpu_on = <0xC4000003>;
 125         };
 126
 127         gic: interrupt-controller@ffb70000 {
 128                 compatible = "arm,cortex-a15-gic";
 129                 #interrupt-cells = <3>;
 130                 #address-cells = <0>;
 131                 interrupt-controller;
 132                 reg = <0x0 0xffb71000 0 0x1000>,
 133                       <0x0 0xffb72000 0 0x1000>;
 134         };
 135
 136         pmu: syscon@ff730000 {
 137                 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
 138                 reg = <0x0 0xff730000 0x0 0x1000>;
 139         };
 140
 141         pmugrf: syscon@ff738000 {
 142                 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
 143                 reg = <0x0 0xff738000 0x0 0x1000>;
 144         };
 145
 146         sgrf: syscon@ff740000 {
 147                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 148                 reg = <0x0 0xff740000 0x0 0x1000>;
 149
 150         };
 151
 152         cru: syscon@ff760000 {
 153                 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
 154                 reg = <0x0 0xff760000 0x0 0x1000>;
 155         };
 156
 157         grf: syscon@ff770000 {
 158                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 159                 reg = <0x0 0xff770000 0x0 0x1000>;
 160         };
 161
 162         arm-pmu {
 163                 compatible = "arm,armv8-pmuv3";
 164                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 172         };
 173
 174         cpu_axi_bus: cpu_axi_bus {
 175                 compatible = "rockchip,cpu_axi_bus";
 176                 #address-cells = <2>;
 177                 #size-cells = <2>;
 178                 ranges;
 179
 180                 qos {
 181                         #address-cells = <2>;
 182                         #size-cells = <2>;
 183                         ranges;
 184
 185                         dmac {
 186                                 reg = <0x0 0xffa80000 0x0 0x20>;
 187                         };
 188                         crypto {
 189                                 reg = <0x0 0xffa80080 0x0 0x20>;
 190                         };
 191                         bus_cpup {
 192                                 reg = <0x0 0xffa90000 0x0 0x20>;
 193                         };
 194                         cci_r {
 195                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 196                         };
 197                         cci_w {
 198                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 199                         };
 200                         peri {
 201                                 reg = <0x0 0xffab0000 0x0 0x20>;
 202                         };
 203                         iep {
 204                                 reg = <0x0 0xffad0000 0x0 0x20>;
 205                         };
 206                         isp_r0 {
 207                                 reg = <0x0 0xffad0080 0x0 0x20>;
 208                         };
 209                         isp_r1 {
 210                                 reg = <0x0 0xffad0100 0x0 0x20>;
 211                         };
 212                         isp_w0 {
 213                                 reg = <0x0 0xffad0180 0x0 0x20>;
 214                                 rockchip,priority = <2 2>;
 215                         };
 216                         isp_w1 {
 217                                 reg = <0x0 0xffad0200 0x0 0x20>;
 218                                 rockchip,priority = <2 2>;
 219                         };
 220                         vip {
 221                                 reg = <0x0 0xffad0280 0x0 0x20>;
 222                         };
 223                         vop {
 224                                 reg = <0x0 0xffad0300 0x0 0x20>;
 225                                 rockchip,priority = <2 2>;
 226                         };
 227                         rga_r {
 228                                 reg = <0x0 0xffad0380 0x0 0x20>;
 229                         };
 230                         rga_w {
 231                                 reg = <0x0 0xffad0400 0x0 0x20>;
 232                         };
 233                         hevc_r {
 234                                 reg = <0x0 0xffae0000 0x0 0x20>;
 235                         };
 236                         vpu_r {
 237                                 reg = <0x0 0xffae0080 0x0 0x20>;
 238                         };
 239                         vpu_w {
 240                                 reg = <0x0 0xffae0100 0x0 0x20>;
 241                         };
 242                 };
 243
 244                 msch {
 245                         #address-cells = <2>;
 246                         #size-cells = <2>;
 247                         ranges;
 248
 249                         msch {
 250                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 251                                 rockchip,read-latency = <0x34>;
 252                         };
 253                 };
 254         };
 255
 256         timer {
 257                 compatible = "arm,armv8-timer";
 258                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 259                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 260                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 261                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 262                 clock-frequency = <24000000>;
 263         };
 264
 265         timer@ff810000 {
 266                 compatible = "rockchip,timer";
 267                 reg = <0x0 0xff810000 0x0 0x20>;
 268                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 269                 rockchip,broadcast = <1>;
 270         };
 271
 272         sram: sram@ff8c0000 {
 273                 compatible = "mmio-sram";
 274                 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
 275                 map-exec;
 276         };
 277
 278         watchdog: wdt@ff800000 {
 279                 compatible = "rockchip,watch dog";
 280                 reg = <0x0 0xff800000 0x0 0x100>;
 281                 clocks = <&pclk_alive_pre>;
 282                 clock-names = "pclk_wdt";
 283                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 284                 rockchip,irq = <1>;
 285                 rockchip,timeout = <60>;
 286                 rockchip,atboot = <1>;
 287                 rockchip,debug = <0>;
 288                 status = "disabled";
 289         };
 290
 291         amba {
 292                 #address-cells = <2>;
 293                 #size-cells = <2>;
 294                 compatible = "arm,amba-bus";
 295                 interrupt-parent = <&gic>;
 296                 ranges;
 297
 298                 pdma0: pdma@ff600000 {
 299                         compatible = "arm,pl330", "arm,primecell";
 300                         reg = <0x0 0xff600000 0x0 0x4000>;
 301                         clocks = <&clk_gates12 11>;
 302                         clock-names = "apb_pclk";
 303                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 305                         #dma-cells = <1>;
 306
 307                 };
 308
 309                 pdma1: pdma@ff250000 {
 310                         compatible = "arm,pl330", "arm,primecell";
 311                         reg = <0x0 0xff250000 0x0 0x4000>;
 312                         clocks = <&clk_gates19 3>;
 313                         clock-names = "apb_pclk";
 314                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 315                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 316                         #dma-cells = <1>;
 317                 };
 318         };
 319
 320         reset: reset@ff760300{
 321                 compatible = "rockchip,reset";
 322                 reg = <0x0 0xff760300 0x0 0x38>;
 323                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 324                 #reset-cells = <1>;
 325         };
 326
 327         nandc0: nandc@ff400000 {
 328                 compatible = "rockchip,rk-nandc";
 329                 reg = <0x0 0xff400000 0x0 0x4000>;
 330                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 331                 nandc_id = <0>;
 332                 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
 333                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 334         };
 335
 336         nandc0reg: nandc0@ff400000 {
 337                 compatible = "rockchip,rk-nandc";
 338                 reg = <0x0 0xff400000 0x0 0x4000>;
 339         };
 340
 341         emmc: rksdmmc@ff0f0000 {
 342                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 343                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 344                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 345                 #address-cells = <1>;
 346                 #size-cells = <0>;
 347                 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
 348                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 349                 rockchip,grf = <&grf>;
 350                 num-slots = <1>;
 351                 fifo-depth = <0x100>;
 352                 bus-width = <8>;
 353         };
 354
 355         sdmmc: rksdmmc@ff0c0000 {
 356                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 357                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 358                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 pinctrl-names = "default", "idle";
 362                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 363                 pinctrl-1 = <&sdmmc_gpio>;
 364                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 365                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
 366                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 367                 rockchip,grf = <&grf>;
 368                 num-slots = <1>;
 369                 fifo-depth = <0x100>;
 370                 bus-width = <4>;
 371         };
 372
 373         sdio: rksdmmc@ff0d0000 {
 374                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 375                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 376                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 377                 #address-cells = <1>;
 378                 #size-cells = <0>;
 379                 pinctrl-names = "default","idle";
 380                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 381                 pinctrl-1 = <&sdio0_gpio>;
 382                 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
 383                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 384                 rockchip,grf = <&grf>;
 385                 num-slots = <1>;
 386                 fifo-depth = <0x100>;
 387                 bus-width = <4>;
 388         };
 389
 390         spi0: spi@ff110000 {
 391                 compatible = "rockchip,rockchip-spi";
 392                 reg = <0x0 0xff110000 0x0 0x1000>;
 393                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 398                 rockchip,spi-src-clk = <0>;
 399                 num-cs = <2>;
 400                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 401                 clock-names = "spi", "pclk_spi0";
 402                 //dmas = <&pdma1 11>, <&pdma1 12>;
 403                 //#dma-cells = <2>;
 404                 //dma-names = "tx", "rx";
 405                 status = "disabled";
 406         };
 407
 408         spi1: spi@ff120000 {
 409                 compatible = "rockchip,rockchip-spi";
 410                 reg = <0x0 0xff120000 0x0 0x1000>;
 411                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 412                 #address-cells = <1>;
 413                 #size-cells = <0>;
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 416                 rockchip,spi-src-clk = <1>;
 417                 num-cs = <1>;
 418                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 419                 clock-names = "spi", "pclk_spi1";
 420                 //dmas = <&pdma1 13>, <&pdma1 14>;
 421                 //#dma-cells = <2>;
 422                 //dma-names = "tx", "rx";
 423                 status = "disabled";
 424         };
 425
 426         spi2: spi@ff130000 {
 427                 compatible = "rockchip,rockchip-spi";
 428                 reg = <0x0 0xff130000 0x0 0x1000>;
 429                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 434                 rockchip,spi-src-clk = <2>;
 435                 num-cs = <1>;
 436                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 437                 clock-names = "spi", "pclk_spi2";
 438                 //dmas = <&pdma1 15>, <&pdma1 16>;
 439                 //#dma-cells = <2>;
 440                 //dma-names = "tx", "rx";
 441                 status = "disabled";
 442         };
 443
 444         uart_bt: serial@ff180000 {
 445                 compatible = "rockchip,serial";
 446                 reg = <0x0 0xff180000 0x0 0x100>;
 447                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 448                 clock-frequency = <24000000>;
 449                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 450                 clock-names = "sclk_uart", "pclk_uart";
 451                 reg-shift = <2>;
 452                 reg-io-width = <4>;
 453                 //dmas = <&pdma1 1>, <&pdma1 2>;
 454                 //#dma-cells = <2>;
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 457                 status = "disabled";
 458         };
 459
 460         uart_bb: serial@ff190000 {
 461                 compatible = "rockchip,serial";
 462                 reg = <0x0 0xff190000 0x0 0x100>;
 463                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 464                 clock-frequency = <24000000>;
 465                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 466                 clock-names = "sclk_uart", "pclk_uart";
 467                 reg-shift = <2>;
 468                 reg-io-width = <4>;
 469                 //dmas = <&pdma1 3>, <&pdma1 4>;
 470                 //#dma-cells = <2>;
 471                 pinctrl-names = "default";
 472                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 473                 status = "disabled";
 474         };
 475
 476         uart_dbg: serial@ff690000 {
 477                 compatible = "rockchip,serial";
 478                 reg = <0x0 0xff690000 0x0 0x100>;
 479                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 480                 clock-frequency = <24000000>;
 481                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 482                 clock-names = "sclk_uart", "pclk_uart";
 483                 reg-shift = <2>;
 484                 reg-io-width = <4>;
 485                 //dmas = <&pdma0 4>, <&pdma0 5>;
 486                 //#dma-cells = <2>;
 487                 //pinctrl-names = "default";
 488                 //pinctrl-0 = <&uart2_xfer>;
 489                 status = "disabled";
 490         };
 491
 492         uart_gps: serial@ff1b0000 {
 493                 compatible = "rockchip,serial";
 494                 reg = <0x0 0xff1b0000 0x0 0x100>;
 495                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 496                 clock-frequency = <24000000>;
 497                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 498                 clock-names = "sclk_uart", "pclk_uart";
 499                 current-speed = <115200>;
 500                 reg-shift = <2>;
 501                 reg-io-width = <4>;
 502                 //dmas = <&pdma1 7>, <&pdma1 8>;
 503                 //#dma-cells = <2>;
 504                 pinctrl-names = "default";
 505                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 506                 status = "disabled";
 507         };
 508
 509         uart_exp: serial@ff1c0000 {
 510                 compatible = "rockchip,serial";
 511                 reg = <0x0 0xff1c0000 0x0 0x100>;
 512                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 513                 clock-frequency = <24000000>;
 514                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 515                 clock-names = "sclk_uart", "pclk_uart";
 516                 reg-shift = <2>;
 517                 reg-io-width = <4>;
 518                 //dmas = <&pdma1 9>, <&pdma1 10>;
 519                 //#dma-cells = <2>;
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 522                 status = "disabled";
 523         };
 524
 525         rockchip_clocks_init: clocks-init{
 526                 compatible = "rockchip,clocks-init";
 527                 rockchip,clocks-init-parent =
 528                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 529                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 530                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 531                         <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
 532                 rockchip,clocks-init-rate =
 533                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 534                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 535                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 536                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 537                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 538                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 539                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 540                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 541                         <&aclk_cci 600000000>,          <&clk_mac 125000000>,
 542                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 543                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 544                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 545                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 546                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 547                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 548                         <&clk_hevc_cabac 300000000>;
 549 /*
 550                 rockchip,clocks-uboot-has-init =
 551                         <&aclk_vio0>;
 552 */
 553         };
 554
 555         rockchip_clocks_enable: clocks-enable {
 556                 compatible = "rockchip,clocks-enable";
 557                 clocks =
 558                         /*PLL*/
 559                         <&clk_apllb>,
 560                         <&clk_aplll>,
 561                         <&clk_dpll>,
 562                         <&clk_gpll>,
 563                         <&clk_cpll>,
 564
 565                         /*PD_CORE*/
 566                         <&clk_cs>,
 567                         <&clkin_trace>,
 568
 569                         /*PD_BUS*/
 570                         <&aclk_bus>,
 571                         <&hclk_bus>,
 572                         <&pclk_bus>,
 573                         <&clk_gates12 12>,/*aclk_strc_sys*/
 574                         <&clk_gates12 6>,/*aclk_intmem1*/
 575                         <&clk_gates12 5>,/*aclk_intmem0*/
 576                         <&clk_gates12 4>,/*aclk_intmem*/
 577                         <&clk_gates13 9>,/*aclk_gic400*/
 578
 579                         /*PD_ALIVE*/
 580                         <&clk_gates22 13>,/*pclk_timer1*/
 581                         <&clk_gates22 12>,/*pclk_timer0*/
 582                         <&clk_gates22 9>,/*pclk_alive_niu*/
 583                         <&clk_gates22 8>,/*pclk_grf*/
 584
 585                         /*PD_PMU*/
 586                         <&clk_gates23 5>,/*pclk_pmugrf*/
 587                         <&clk_gates23 3>,/*pclk_sgrf*/
 588                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 589                         <&clk_gates23 1>,/*pclk_intmem1*/
 590                         <&clk_gates23 0>,/*pclk_pmu*/
 591
 592                         /*PD_PERI*/
 593                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 594                         <&clk_gates20 8>,/*aclk_peri_niu*/
 595                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 596                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 597                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 598                         <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
 599         };
 600
 601         /* I2C_PMU */
 602         i2c0: i2c@ff650000 {
 603                 compatible = "rockchip,rk30-i2c";
 604                 reg = <0x0 0xff650000 0x0 0x1000>;
 605                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 606                 #address-cells = <1>;
 607                 #size-cells = <0>;
 608                 pinctrl-names = "default", "gpio";
 609                 pinctrl-0 = <&i2c0_xfer>;
 610                 pinctrl-1 = <&i2c0_gpio>;
 611                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 612                 clocks = <&clk_gates12 2>;
 613                 rockchip,check-idle = <1>;
 614                 status = "disabled";
 615         };
 616
 617         /* I2C_AUDIO */
 618         i2c1: i2c@ff660000 {
 619                 compatible = "rockchip,rk30-i2c";
 620                 reg = <0x0 0xff660000 0x0 0x1000>;
 621                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 622                 #address-cells = <1>;
 623                 #size-cells = <0>;
 624                 pinctrl-names = "default", "gpio";
 625                 pinctrl-0 = <&i2c1_xfer>;
 626                 pinctrl-1 = <&i2c1_gpio>;
 627                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 628                 clocks = <&clk_gates12 3>;
 629                 rockchip,check-idle = <1>;
 630                 status = "disabled";
 631         };
 632
 633         /* I2C_SENSOR */
 634         i2c2: i2c@ff140000 {
 635                 compatible = "rockchip,rk30-i2c";
 636                 reg = <0x0 0xff140000 0x0 0x1000>;
 637                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 638                 #address-cells = <1>;
 639                 #size-cells = <0>;
 640                 pinctrl-names = "default", "gpio";
 641                 pinctrl-0 = <&i2c2_xfer>;
 642                 pinctrl-1 = <&i2c2_gpio>;
 643                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 644                 clocks = <&clk_gates19 11>;
 645                 rockchip,check-idle = <1>;
 646                 status = "disabled";
 647         };
 648
 649         /* I2C_CAM */
 650         i2c3: i2c@ff150000 {
 651                 compatible = "rockchip,rk30-i2c";
 652                 reg = <0x0 0xff150000 0x0 0x1000>;
 653                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 654                 #address-cells = <1>;
 655                 #size-cells = <0>;
 656                 pinctrl-names = "default", "gpio";
 657                 pinctrl-0 = <&i2c3_xfer>;
 658                 pinctrl-1 = <&i2c3_gpio>;
 659                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 660                 clocks = <&clk_gates19 12>;
 661                 rockchip,check-idle = <1>;
 662                 status = "disabled";
 663         };
 664
 665         /* I2C_TP */
 666         i2c4: i2c@ff160000 {
 667                 compatible = "rockchip,rk30-i2c";
 668                 reg = <0x0 0xff160000 0x0 0x1000>;
 669                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 670                 #address-cells = <1>;
 671                 #size-cells = <0>;
 672                 pinctrl-names = "default", "gpio";
 673                 pinctrl-0 = <&i2c4_xfer>;
 674                 pinctrl-1 = <&i2c4_gpio>;
 675                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 676                 clocks = <&clk_gates19 13>;
 677                 rockchip,check-idle = <1>;
 678                 status = "disabled";
 679         };
 680
 681         /* I2C_HDMI */
 682         i2c5: i2c@ff170000 {
 683                 compatible = "rockchip,rk30-i2c";
 684                 reg = <0x0 0xff170000 0x0 0x1000>;
 685                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 686                 #address-cells = <1>;
 687                 #size-cells = <0>;
 688                 pinctrl-names = "default", "gpio";
 689                 pinctrl-0 = <&i2c5_xfer>;
 690                 pinctrl-1 = <&i2c5_gpio>;
 691                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 692                 clocks = <&clk_gates19 14>;
 693                 rockchip,check-idle = <1>;
 694                 status = "disabled";
 695         };
 696
 697         fb: fb {
 698                 compatible = "rockchip,rk-fb";
 699                 rockchip,disp-mode = <NO_DUAL>;
 700         };
 701
 702
 703         rk_screen: rk_screen {
 704                 compatible = "rockchip,screen";
 705         };
 706
 707         dsihost0: mipi@ff960000{
 708                 compatible = "rockchip,rk3368-dsi";
 709                 rockchip,prop = <0>;
 710                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 711                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 712                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 713                 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>;
 714                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 715                 status = "okay";
 716         };
 717
 718         lvds: lvds@ff968000 {
 719                 compatible = "rockchip,rk3368-lvds";
 720                 rockchip,grf = <&grf>;
 721                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 722                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 723                 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
 724                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 725                 status = "disabled";
 726         };
 727
 728         edp: edp@ff970000 {
 729                 compatible = "rockchip,rk32-edp";
 730                 reg = <0x0 0xff970000 0x0 0x4000>;
 731                 rockchip,grf = <&grf>;
 732                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 733                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 734                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 735                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 736                 reset-names = "edp_24m", "edp_apb";
 737         };
 738
 739         hdmi: hdmi@ff980000 {
 740                 compatible = "rockchip,rk3368-hdmi";
 741                 reg = <0x0 0xff980000 0x0 0x20000>;
 742                 rockchip,grf = <&grf>;
 743                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 744                 pinctrl-names = "default", "gpio";
 745                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 746                 pinctrl-1 = <&i2c5_gpio>;
 747                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 748                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 749                 status = "disabled";
 750         };
 751
 752         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 753                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 754                 reg = <0x0 0xff978000 0x0 0x2000>;
 755                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 756                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 757                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 758                 status = "disabled";
 759         };
 760
 761         lcdc: lcdc@ff930000 {
 762                  compatible = "rockchip,rk3368-lcdc";
 763                  rockchip,grf = <&grf>;
 764                  rockchip,pmugrf = <&pmugrf>;
 765                  rockchip,prop = <PRMRY>;
 766                  rockchip,pwr18 = <0>;
 767                  rockchip,iommu-enabled = <0>;
 768                  reg = <0x0 0xff930000 0x0 0x10000>;
 769                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 770                 /*pinctrl-names = "default", "gpio";
 771                  *pinctrl-0 = <&lcdc_lcdc>;
 772                  *pinctrl-1 = <&lcdc_gpio>;
 773                  */
 774                  status = "disabled";
 775                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
 776                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
 777         };
 778
 779         adc: adc@ff100000 {
 780                 compatible = "rockchip,saradc";
 781                 reg = <0x0 0xff100000 0x0 0x100>;
 782                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 783                 #io-channel-cells = <1>;
 784                 io-channel-ranges;
 785                 rockchip,adc-vref = <1800>;
 786                 clock-frequency = <1000000>;
 787                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 788                 clock-names = "saradc", "pclk_saradc";
 789                 status = "disabled";
 790         };
 791
 792         rga@ff920000 {
 793                 compatible = "rockchip,rk3368-rga2";
 794                 reg = <0x0 0xff920000 0x0 0x1000>;
 795                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 796                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 797                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 798         };
 799
 800         i2s0: i2s0@ff898000 {
 801                 compatible = "rockchip-i2s";
 802                 reg = <0x0 0xff898000 0x0 0x1000>;
 803                 i2s-id = <0>;
 804                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 805                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 806                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 807                 dmas = <&pdma0 0>, <&pdma0 1>;
 808                 #dma-cells = <2>;
 809                 dma-names = "tx", "rx";
 810                 pinctrl-names = "default", "sleep";
 811                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 812                 pinctrl-1 = <&i2s_gpio>;
 813         };
 814
 815         i2s1: i2s1@ff890000 {
 816                 compatible = "rockchip-i2s";
 817                 reg = <0x0 0xff890000 0x0 0x1000>;
 818                 i2s-id = <1>;
 819                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 820                 clock-names = "i2s_clk", "i2s_hclk";
 821                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 822                 dmas = <&pdma0 6>, <&pdma0 7>;
 823                 #dma-cells = <2>;
 824                 dma-names = "tx", "rx";
 825         };
 826
 827         spdif: spdif@ff880000 {
 828                 compatible = "rockchip-spdif";
 829                 reg = <0x0 0xff880000 0x0 0x1000>;
 830                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 831                 clock-names = "spdif_mclk", "spdif_hclk";
 832                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 833                 dmas = <&pdma0 3>;
 834                 #dma-cells = <1>;
 835                 dma-names = "tx";
 836                 pinctrl-names = "default";
 837                 pinctrl-0 = <&spdif_tx>;
 838         };
 839
 840         pwm0: pwm@ff680000 {
 841                 compatible = "rockchip,rk-pwm";
 842                 reg = <0x0 0xff680000 0x0 0x10>;
 843                 #pwm-cells = <2>;
 844                 pinctrl-names = "default";
 845                 pinctrl-0 = <&pwm0_pin>;
 846                 clocks = <&clk_gates13 6>;
 847                 clock-names = "pclk_pwm";
 848                 status = "disabled";
 849         };
 850
 851         pwm1: pwm@ff680010 {
 852                 compatible = "rockchip,rk-pwm";
 853                 reg = <0x0 0xff680010 0x0 0x10>;
 854                 #pwm-cells = <2>;
 855                 pinctrl-names = "default";
 856                 pinctrl-0 = <&pwm1_pin>;
 857                 clocks = <&clk_gates13 6>;
 858                 clock-names = "pclk_pwm";
 859                 status = "disabled";
 860         };
 861
 862         pwm2: pwm@ff680020 {
 863                 compatible = "rockchip,rk-pwm";
 864                 reg = <0x0 0xff680020 0x0 0x10>;
 865                 #pwm-cells = <2>;
 866                 //pinctrl-names = "default";
 867                 //pinctrl-0 = <&pwm1_pin>;
 868                 clocks = <&clk_gates13 6>;
 869                 clock-names = "pclk_pwm";
 870                 status = "disabled";
 871         };
 872
 873         pwm3: pwm@ff680030 {
 874                 compatible = "rockchip,rk-pwm";
 875                 reg = <0x0 0xff680030 0x0 0x10>;
 876                 #pwm-cells = <2>;
 877                 pinctrl-names = "default";
 878                 pinctrl-0 = <&pwm3_pin>;
 879                 clocks = <&clk_gates13 6>;
 880                 clock-names = "pclk_pwm";
 881                 status = "disabled";
 882         };
 883
 884         remotectl: pwm@ff680030 {
 885                 compatible = "rockchip,remotectl-pwm";
 886                 reg = <0x0 0xff680030 0x0 0x50>;
 887                 #pwm-cells = <2>;
 888                 pinctrl-names = "default";
 889                 pinctrl-0 = <&pwm3_pin>;
 890                 clocks = <&clk_gates13 6>;
 891                 clock-names = "pclk_pwm";
 892                 dmas = <&pdma0 2>;
 893                 #dma-cells = <2>;
 894                 dma-names = "rx";
 895                 remote_pwm_id = <3>;
 896                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 897                 status = "disabled";
 898         };
 899
 900         voppwm: pwm@ff9301a0 {
 901                 compatible = "rockchip,vop-pwm";
 902                 reg = <0x0 0xff9301a0 0x0 0x10>;
 903                 #pwm-cells = <2>;
 904                 pinctrl-names = "default";
 905                 pinctrl-0 = <&vop_pwm_pin>;
 906                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
 907                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 908                 status = "disabled";
 909         };
 910
 911         pvtm {
 912                 compatible = "rockchip,rk3368-pvtm";
 913                 rockchip,grf = <&grf>;
 914                 rockchip,pmugrf = <&pmugrf>;
 915                 rockchip,pvtm-clk-out = <1>;
 916         };
 917
 918         cpufreq {
 919                 compatible = "rockchip,rk3368-cpufreq";
 920                 rockchip,grf = <&grf>;
 921         };
 922
 923         dvfs {
 924
 925                 vd_arm: vd_arm {
 926                         regulator_name = "vdd_arm";
 927                         suspend_volt = <1000>; //mV
 928                         pd_core {
 929                                 clk_core_b_dvfs_table: clk_core_b {
 930                                         operating-points = <
 931                                                 /* KHz    uV */
 932                                                 312000 1200000
 933                                                 504000 1200000
 934                                                 816000 1200000
 935                                                 1008000 1200000
 936                                                 >;
 937                                         status = "okay";
 938                                 };
 939                                 clk_core_l_dvfs_table: clk_core_l {
 940                                         operating-points = <
 941                                                 /* KHz    uV */
 942                                                 312000 1200000
 943                                                 504000 1200000
 944                                                 816000 1200000
 945                                                 1008000 1200000
 946                                                 >;
 947                                         status = "okay";
 948                                 };
 949                         };
 950                 };
 951
 952                 vd_logic: vd_logic {
 953                         regulator_name = "vdd_logic";
 954                         suspend_volt = <1000>; //mV
 955                         pd_ddr {
 956                                 clk_ddr_dvfs_table: clk_ddr {
 957                                         operating-points = <
 958                                                 /* KHz    uV */
 959                                                 200000 1200000
 960                                                 300000 1200000
 961                                                 400000 1200000
 962                                                 >;
 963                                         channel = <2>;
 964                                         status = "disabled";
 965                                 };
 966                         };
 967
 968                         pd_gpu {
 969                                 clk_gpu_dvfs_table: clk_gpu {
 970                                         operating-points = <
 971                                                 /* KHz    uV */
 972                                                 200000 1200000
 973                                                 300000 1200000
 974                                                 400000 1200000
 975                                                 >;
 976                                         channel = <1>;
 977                                         status = "okay";
 978                                         regu-mode-table = <
 979                                                 /*freq     mode*/
 980                                                 200000     4
 981                                                 0          3
 982                                         >;
 983                                         regu-mode-en = <0>;
 984                                 };
 985                         };
 986                 };
 987         };
 988
 989         ion {
 990                 compatible = "rockchip,ion";
 991                 #address-cells = <1>;
 992                 #size-cells = <0>;
 993
 994                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
 995                         compatible = "rockchip,ion-heap";
 996                         rockchip,ion_heap = <4>;
 997                         reg = <0x00000000 0x08000000>; /* 512MB */
 998                 };
 999                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1000                         compatible = "rockchip,ion-heap";
1001                         rockchip,ion_heap = <0>;
1002                 };
1003         };
1004
1005         vpu: vpu_service {
1006                 compatible = "rockchip,vpu_sub";
1007                 iommu_enabled = <0>;
1008                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1009                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1010                 interrupt-names = "irq_enc", "irq_dec";
1011                 dev_mode = <0>;
1012                 name = "vpu_service";
1013         };
1014
1015         hevc: hevc_service {
1016                 compatible = "rockchip,hevc_sub";
1017                 iommu_enabled = <0>;
1018                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1019                 interrupt-names = "irq_dec";
1020                 dev_mode = <1>;
1021                 name = "hevc_service";
1022         };
1023
1024         vpu_combo: vpu_combo@ff9a0000 {
1025                 compatible = "rockchip,vpu_combo";
1026                 reg = <0x0 0xff9a0000 0x0 0x800>;
1027                 rockchip,grf = <&grf>;
1028                 subcnt = <2>;
1029                 rockchip,sub = <&vpu>, <&hevc>;
1030                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1031                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1032                 mode_bit = <12>;
1033                 mode_ctrl = <0x418>;
1034                 name = "vpu_combo";
1035                 status = "okay";
1036         };
1037
1038         iep: iep@ff900000 {
1039                 compatible = "rockchip,iep";
1040                 iommu_enabled = <0>;
1041                 reg = <0x0 0xff900000 0x0 0x800>;
1042                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1043                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1044                 clock-names = "aclk_iep", "hclk_iep";
1045                 status = "okay";
1046         };
1047
1048         gmac: eth@ff290000 {
1049                 compatible = "rockchip,rk3368-gmac";
1050                 reg = <0x0 0xff290000 0x0 0x10000>;
1051                 rockchip,grf = <&grf>;
1052                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1053                 interrupt-names = "macirq";
1054
1055                 clocks = <&clk_mac>, <&clk_gates7 4>,
1056                          <&clk_gates7 5>, <&clk_gates7 6>,
1057                          <&clk_gates7 7>, <&clk_gates20 13>,
1058                          <&clk_gates20 14>;
1059                 clock-names = "clk_mac", "mac_clk_rx",
1060                               "mac_clk_tx", "clk_mac_ref",
1061                               "clk_mac_refout", "aclk_mac",
1062                               "pclk_mac";
1063
1064                 phy-mode = "rgmii";
1065                 pinctrl-names = "default";
1066                 pinctrl-0 = <&rgmii_pins>;
1067         };
1068
1069         gpu {
1070                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1071                 reg = <0x0 0xffa30000 0x0 0x10000>;
1072                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1073                 interrupt-names = "GPU";
1074         };
1075
1076         iep_mmu {
1077                 dbgname = "iep";
1078                 compatible = "rockchip,iep_mmu";
1079                 reg = <0x0 0xff900800 0x0 0x100>;
1080                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1081                 interrupt-names = "iep_mmu";
1082         };
1083
1084         vip_mmu {
1085                 dbgname = "vip";
1086                 compatible = "rockchip,vip_mmu";
1087                 reg = <0x0 0xff950800 0x0 0x100>;
1088                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1089                 interrupt-names = "vip_mmu";
1090         };
1091
1092         vop_mmu {
1093                 dbgname = "vop";
1094                 compatible = "rockchip,vopb_mmu";
1095                 reg = <0x0 0xff930300 0x0 0x100>;
1096                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1097                 interrupt-names = "vop_mmu";
1098         };
1099
1100         isp_mmu {
1101                 dbgname = "isp_mmu";
1102                 compatible = "rockchip,isp_mmu";
1103                 reg = <0x0 0xff914000 0x0 0x100>,
1104                 <0x0 0xff915000 0x0 0x100>;
1105                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1106                 interrupt-names = "isp_mmu";
1107         };
1108
1109         hdcp_mmu {
1110                 dbgname = "hdcp_mmu";
1111                 compatible = "rockchip,hdcp_mmu";
1112                 reg = <0x0 0xff940000 0x0 0x100>;
1113                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1114                 interrupt-names = "hdcp_mmu";
1115         };
1116
1117         hevc_mmu {
1118                 dbgname = "hevc";
1119                 compatible = "rockchip,hevc_mmu";
1120                 reg = <0x0 0xff9c0440 0x0 0x40>,                      /*need to fix*/
1121                           <0x0 0xff9c0480 0x0 0x40>;
1122                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1123                 interrupt-names = "hevc_mmu";
1124         };
1125
1126         vpu_mmu {
1127                 dbgname = "vpu";
1128                 compatible = "rockchip,vpu_mmu";
1129                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1130                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;       /*need to fix*/
1131                 interrupt-names = "vpu_mmu";
1132         };
1133
1134         rockchip_suspend {
1135                 rockchip,ctrbits = <
1136                         (0
1137                          |RKPM_CTR_PWR_DMNS
1138                          |RKPM_CTR_GTCLKS
1139                          |RKPM_CTR_PLLS
1140                          |RKPM_CTR_GPIOS
1141                         /*
1142                          |RKPM_CTR_SYSCLK_DIV
1143                          |RKPM_CTR_IDLEAUTO_MD
1144                          |RKPM_CTR_ARMOFF_LPMD
1145                         */
1146                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1147                         )
1148                         >;
1149                 rockchip,pmic-suspend_gpios = <
1150                                  /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1151                         >;
1152                 rockchip,pmic-resume_gpios = <
1153                                 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1154                         >;
1155         };
1156
1157         isp: isp@ff910000{
1158                 compatible = "rockchip,isp";
1159                 reg = <0x0 0xff910000 0x0 0x10000>;
1160                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1161                 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1162                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1163                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1164                 pinctrl-0 = <&cif_clkout>;
1165                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1166                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1167                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1168                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1169                 pinctrl-5 = <&cif_clkout>;
1170                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1171                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1172                 pinctrl-8 = <&isp_flash_trigger>;
1173                 rockchip,isp,mipiphy = <2>;
1174                 rockchip,isp,cifphy = <1>;
1175                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1176                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1177                 rockchip,grf = <&grf>;
1178                 rockchip,cru = <&cru>;
1179                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1180                 rockchip,isp,iommu_enable = <0>;
1181                 status = "okay";
1182         };
1183
1184         cif: cif@ff950000 {
1185                 compatible = "rockchip,cif";
1186                 reg = <0x0 0xff950000 0x0 0x10000>;
1187                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1188                 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1189                 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1190                 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1191                 pinctrl-names = "cif_pin_all";
1192                 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1193                 rockchip,grf = <&grf>;
1194                 rockchip,cru = <&cru>;
1195                 status = "okay";
1196         };
1197
1198 /*
1199         thermal-zones {
1200                 #include "rk3368-thermal.dtsi"
1201         };
1202 */
1203
1204         tsadc: tsadc@ff280000 {
1205                 compatible = "rockchip,rk3368-tsadc";
1206                 reg = <0x0 0xff280000 0x0 0x100>;
1207                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1208                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1209                 rockchip,grf = <&grf>;
1210                 rockchip,cru = <&cru>;
1211                 rockchip,pmu = <&pmu>;
1212                 clock-names = "tsadc", "apb_pclk";
1213                 clock-frequency = <32000>;
1214                 resets = <&reset RK3368_SRST_TSADC_P>;
1215                 reset-names = "tsadc-apb";
1216                 //pinctrl-names = "default";
1217                 //pinctrl-0 = <&tsadc_int>;
1218                 #thermal-sensor-cells = <1>;
1219                 hw-shut-temp = <120000>;
1220                 status = "disabled";
1221         };
1222
1223         tsp: tsp@FF8B0000 {
1224                 compatible = "rockchip,rk3368-tsp";
1225                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1226                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1227                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1228                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1229                 interrupt-names = "irq_tsp";
1230                 // pinctrl-names = "default";
1231                 // pinctrl-0 = <&isp_hsadc>;
1232                 status = "okay";
1233         };
1234
1235         crypto: crypto@FF8A0000{
1236                 compatible = "rockchip,rk3368-crypto";
1237                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1238                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1239                 interrupt-names = "irq_crypto";
1240                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1241                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1242                 status = "okay";
1243         };
1244
1245         dwc_control_usb: dwc-control-usb {
1246                 compatible = "rockchip,rk3368-dwc-control-usb";
1247                 rockchip,grf = <&grf>;
1248                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1249                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1250                 interrupt-names = "otg_id", "otg_bvalid",
1251                                   "otg_linestate", "host0_linestate";
1252                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1253                 clock-names = "hclk_usb_peri", "usbphy_480m";
1254                 //resets = <&reset RK3128_RST_USBPOR>;
1255                 //reset-names = "usbphy_por";
1256                 usb_bc{
1257                         compatible = "inno,phy";
1258                         regbase = &dwc_control_usb;
1259                         rk_usb,bvalid     = <0x4bc 23 1>;
1260                         rk_usb,iddig      = <0x4bc 26 1>;
1261                         rk_usb,vdmsrcen   = <0x718 12 1>;
1262                         rk_usb,vdpsrcen   = <0x718 11 1>;
1263                         rk_usb,rdmpden    = <0x718 10 1>;
1264                         rk_usb,idpsrcen   = <0x718  9 1>;
1265                         rk_usb,idmsinken  = <0x718  8 1>;
1266                         rk_usb,idpsinken  = <0x718  7 1>;
1267                         rk_usb,dpattach   = <0x4b8 31 1>;
1268                         rk_usb,cpdet      = <0x4b8 30 1>;
1269                         rk_usb,dcpattach  = <0x4b8 29 1>;
1270                 };
1271         };
1272
1273         usb0: usb@ff580000 {
1274                 compatible = "rockchip,rk3368_usb20_otg";
1275                 reg = <0x0 0xff580000 0x0 0x40000>;
1276                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1277                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1278                 clock-names = "clk_usbphy0", "hclk_otg";
1279                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1280                                 <&reset RK3368_SRST_USBOTGC0>;
1281                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1282                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1283                 rockchip,usb-mode = <0>;
1284         };
1285
1286         usb_ehci: usb@ff500000 {
1287                 compatible = "generic-ehci";
1288                 reg = <0x0 0xff500000 0x0 0x20000>;
1289                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1290                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1291                 clock-names = "clk_usbphy0", "hclk_ehci";
1292                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1293                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1294                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1295         };
1296
1297         usb_ohci: usb@ff520000 {
1298                 compatible = "generic-ohci";
1299                 reg = <0x0 0xff520000 0x0 0x20000>;
1300                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1301                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1302                 clock-names =  "clk_usbphy0", "hclk_ohci";
1303         };
1304
1305         usb_hsic: usb@ff5c0000 {
1306                 compatible = "rockchip,rk3288_rk_hsic_host";
1307                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1308                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1309 /*
1310                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1311                          <&hsicphy_12m>, <&usbphy_480m>,
1312                          <&otgphy1_480m>, <&otgphy2_480m>;
1313                 clock-names = "hsicphy_480m", "hclk_hsic",
1314                               "hsicphy_12m", "usbphy_480m",
1315                               "hsic_usbphy1", "hsic_usbphy2";
1316                 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1317                                 <&reset RK3288_SOFT_RST_HSICPHY>;
1318                 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1319 */
1320                 status = "disabled";
1321         };
1322
1323         pinctrl: pinctrl {
1324                 compatible = "rockchip,rk3368-pinctrl";
1325                 rockchip,grf = <&grf>;
1326                 rockchip,pmugrf = <&pmugrf>;
1327                 #address-cells = <2>;
1328                 #size-cells = <2>;
1329                 ranges;
1330
1331                 gpio0: gpio0@ff750000 {
1332                         compatible = "rockchip,gpio-bank";
1333                         reg =   <0x0 0xff750000 0x0 0x100>;
1334                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1335                         clocks = <&clk_gates23 4>;
1336
1337                         gpio-controller;
1338                         #gpio-cells = <2>;
1339
1340                         interrupt-controller;
1341                         #interrupt-cells = <2>;
1342                 };
1343
1344                 gpio1: gpio1@ff780000 {
1345                         compatible = "rockchip,gpio-bank";
1346                         reg = <0x0 0xff780000 0x0 0x100>;
1347                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1348                         clocks = <&clk_gates22 1>;
1349
1350                         gpio-controller;
1351                         #gpio-cells = <2>;
1352
1353                         interrupt-controller;
1354                         #interrupt-cells = <2>;
1355                 };
1356
1357                 gpio2: gpio2@ff790000 {
1358                         compatible = "rockchip,gpio-bank";
1359                         reg = <0x0 0xff790000 0x0 0x100>;
1360                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1361                         clocks = <&clk_gates22 2>;
1362
1363                         gpio-controller;
1364                         #gpio-cells = <2>;
1365
1366                         interrupt-controller;
1367                         #interrupt-cells = <2>;
1368                 };
1369
1370                 gpio3: gpio3@ff7a0000 {
1371                         compatible = "rockchip,gpio-bank";
1372                         reg = <0x0 0xff7a0000 0x0 0x100>;
1373                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1374                         clocks = <&clk_gates22 3>;
1375
1376                         gpio-controller;
1377                         #gpio-cells = <2>;
1378
1379                         interrupt-controller;
1380                         #interrupt-cells = <2>;
1381                 };
1382
1383                 pcfg_pull_up: pcfg-pull-up {
1384                         bias-pull-up;
1385                 };
1386
1387                 pcfg_pull_down: pcfg-pull-down {
1388                         bias-pull-down;
1389                 };
1390
1391                 pcfg_pull_none: pcfg-pull-none {
1392                         bias-disable;
1393                 };
1394
1395                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1396                         drive-strength = <8>;
1397                 };
1398
1399                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1400                         drive-strength = <12>;
1401                 };
1402
1403                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1404                         bias-pull-up;
1405                         drive-strength = <8>;
1406                 };
1407
1408                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1409                         drive-strength = <4>;
1410                 };
1411
1412                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1413                         bias-pull-up;
1414                         drive-strength = <4>;
1415                 };
1416
1417                 pcfg_output_high: pcfg-output-high {
1418                         output-high;
1419                 };
1420
1421                 pcfg_output_low: pcfg-output-low {
1422                         output-low;
1423                 };
1424
1425                 i2c0 {
1426                         i2c0_xfer: i2c0-xfer {
1427                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1428                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1429                         };
1430                         i2c0_gpio: i2c0-gpio {
1431                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1432                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1433                         };
1434                 };
1435
1436                 i2c1 {
1437                         i2c1_xfer: i2c1-xfer {
1438                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1439                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1440                         };
1441                         i2c1_gpio: i2c1-gpio {
1442                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1443                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1444                         };
1445                 };
1446
1447                 i2c2 {
1448                         i2c2_xfer: i2c2-xfer {
1449                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1450                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1451                         };
1452                         i2c2_gpio: i2c2-gpio {
1453                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1454                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1455             };
1456                 };
1457
1458                 i2c3 {
1459                         i2c3_xfer: i2c3-xfer {
1460                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1461                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1462                         };
1463                         i2c3_gpio: i2c3-gpio {
1464                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1465                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1466                         };
1467                 };
1468
1469                 i2c4 {
1470                         i2c4_xfer: i2c4-xfer {
1471                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1472                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1473                         };
1474                         i2c4_gpio: i2c4-gpio {
1475                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1476                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1477                         };
1478                 };
1479
1480                 i2c5 {
1481                         i2c5_xfer: i2c5-xfer {
1482                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1483                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1484                         };
1485                         i2c5_gpio: i2c5-gpio {
1486                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1487                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1488                         };
1489                 };
1490
1491                 uart0 {
1492                         uart0_xfer: uart0-xfer {
1493                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1494                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1495                         };
1496
1497                         uart0_cts: uart0-cts {
1498                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1499                         };
1500
1501                         uart0_rts: uart0-rts {
1502                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1503                         };
1504
1505                         uart0_rts_gpio: uart0-rts-gpio {
1506                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1507                         };
1508                 };
1509
1510                 uart1 {
1511                         uart1_xfer: uart1-xfer {
1512                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1513                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1514                         };
1515
1516                         uart1_cts: uart1-cts {
1517                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1518                         };
1519
1520                         uart1_rts: uart1-rts {
1521                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1522                         };
1523                 };
1524
1525                 uart2 {
1526                         uart2_xfer: uart2-xfer {
1527                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1528                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1529                         };
1530                 };
1531
1532                 uart3 {
1533                         uart3_xfer: uart3-xfer {
1534                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1535                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1536                         };
1537
1538                         uart3_cts: uart3-cts {
1539                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1540                         };
1541
1542                         uart3_rts: uart3-rts {
1543                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1544                         };
1545                 };
1546
1547                 uart4 {
1548                         uart4_xfer: uart4-xfer {
1549                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1550                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1551                         };
1552
1553                         uart4_cts: uart4-cts {
1554                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1555                         };
1556
1557                         uart4_rts: uart4-rts {
1558                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1559                         };
1560                 };
1561
1562                 spi0 {
1563                         spi0_clk: spi0-clk {
1564                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1565                         };
1566                         spi0_cs0: spi0-cs0 {
1567                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1568                         };
1569                         spi0_tx: spi0-tx {
1570                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1571                         };
1572                         spi0_rx: spi0-rx {
1573                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1574                         };
1575                         spi0_cs1: spi0-cs1 {
1576                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1577                         };
1578                 };
1579
1580                 spi1 {
1581                         spi1_clk: spi1-clk {
1582                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1583                         };
1584                         spi1_cs0: spi1-cs0 {
1585                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1586                         };
1587                         spi1_rx: spi1-rx {
1588                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1589                         };
1590                         spi1_tx: spi1-tx {
1591                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1592                         };
1593                 };
1594
1595                 spi2 {
1596                         spi2_clk: spi2-clk {
1597                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1598                         };
1599                         spi2_cs0: spi2-cs0 {
1600                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1601                         };
1602                         spi2_rx: spi2-rx {
1603                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1604                         };
1605                         spi2_tx: spi2-tx {
1606                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1607                         };
1608                 };
1609
1610                 i2s {
1611                         i2s_mclk: i2s-mclk {
1612                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1613                         };
1614
1615                         i2s_sclk:i2s-sclk {
1616                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1617                         };
1618
1619                         i2s_lrckrx:i2s-lrckrx {
1620                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1621                         };
1622
1623                         i2s_lrcktx:i2s-lrcktx {
1624                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1625                         };
1626
1627                         i2s_sdi:i2s-sdi {
1628                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1629                         };
1630
1631                         i2s_sdo0:i2s-sdo0 {
1632                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1633                         };
1634
1635                         i2s_sdo1:i2s-sdo1 {
1636                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1637                         };
1638
1639                         i2s_sdo2:i2s-sdo2 {
1640                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1641                         };
1642
1643                         i2s_sdo3:i2s-sdo3 {
1644                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1645                         };
1646
1647                         i2s_gpio: i2s-gpio {
1648                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1649                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1650                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1651                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1652                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1653                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1654                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1655                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1656                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1657                         };
1658                 };
1659
1660                 spdif {
1661                         spdif_tx: spdif-tx {
1662                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1663                         };
1664                 };
1665
1666                 sdmmc {
1667                         sdmmc_clk: sdmmc-clk {
1668                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1669                         };
1670
1671                         sdmmc_cmd: sdmmc-cmd {
1672                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1673                         };
1674
1675                         sdmmc_dectn: sdmmc-dectn {
1676                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1677                         };
1678
1679                         sdmmc_bus1: sdmmc-bus1 {
1680                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1681                         };
1682
1683                         sdmmc_bus4: sdmmc-bus4 {
1684                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1685                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1686                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1687                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1688                         };
1689
1690                         sdmmc_gpio: sdmmc-gpio {
1691                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1692                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1693                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1694                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1695                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1696                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1697                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1698                         };
1699                 };
1700
1701                 sdio0 {
1702                         sdio0_bus1: sdio0-bus1 {
1703                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1704                         };
1705
1706                         sdio0_bus4: sdio0-bus4 {
1707                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1708                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1709                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1710                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1711                         };
1712
1713                         sdio0_cmd: sdio0-cmd {
1714                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1715                         };
1716
1717                         sdio0_clk: sdio0-clk {
1718                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1719                         };
1720
1721                         sdio0_dectn: sdio0-dectn {
1722                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1723                         };
1724
1725                         sdio0_wrprt: sdio0-wrprt {
1726                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1727                         };
1728
1729                         sdio0_pwren: sdio0-pwren {
1730                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1731                         };
1732
1733                         sdio0_bkpwr: sdio0-bkpwr {
1734                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1735                         };
1736
1737                         sdio0_int: sdio0-int {
1738                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1739                         };
1740
1741                         sdio0_gpio: sdio0-gpio {
1742                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1743                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1744                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1745                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1746                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1747                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1748                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1749                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1750                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1751                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1752                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1753                         };
1754                 };
1755
1756                 emmc {
1757                         emmc_clk: emmc-clk {
1758                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1759                         };
1760
1761                         emmc_cmd: emmc-cmd {
1762                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1763                         };
1764
1765                         emmc_pwren: emmc-pwren {
1766                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1767                         };
1768
1769                         emmc_rstnout: emmc_rstnout {
1770                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1771                         };
1772
1773                         emmc_bus1: emmc-bus1 {
1774                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1775                         };
1776
1777                         emmc_bus4: emmc-bus4 {
1778                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1779                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1780                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1781                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1782                         };
1783                 };
1784
1785                 pwm0 {
1786                         pwm0_pin: pwm0-pin {
1787                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1788                         };
1789
1790                         vop_pwm_pin:vop-pwm {
1791                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1792                         };
1793                 };
1794
1795                 pwm1 {
1796                         pwm1_pin: pwm1-pin {
1797                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1798                         };
1799                 };
1800
1801                 pwm3 {
1802                         pwm3_pin: pwm3-pin {
1803                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1804                         };
1805                 };
1806
1807                 lcdc {
1808                         lcdc_lcdc: lcdc-lcdc {
1809                                 rockchip,pins =
1810                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1811                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1812                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1813                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1814                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1815                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1816                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1817                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1818                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1819                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1820                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1821                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1822                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1823                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1824                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1825                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1826                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1827                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1828                         };
1829
1830                         lcdc_gpio: lcdc-gpio {
1831                                 rockchip,pins =
1832                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1833                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1834                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1835                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1836                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1837                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1838                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1839                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1840                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1841                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1842                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1843                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1844                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1845                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1846                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1847                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1848                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1849                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1850                         };
1851                 };
1852
1853                 isp {
1854                         cif_clkout: cif-clkout {
1855                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1856                         };
1857
1858                         isp_dvp_d2d9: isp-dvp-d2d9 {
1859                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1860                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1861                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1862                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1863                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1864                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1865                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1866                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1867                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1868                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1869                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1870                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1871                         };
1872
1873                         isp_dvp_d0d1: isp-dvp-d0d1 {
1874                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1875                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1876                         };
1877
1878                         isp_dvp_d10d11:isp_d10d11       {
1879                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1880                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1881                         };
1882
1883                         isp_dvp_d0d7: isp-dvp-d0d7 {
1884                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1885                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1886                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1887                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1888                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1889                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1890                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1891                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1892                         };
1893
1894                         isp_shutter: isp-shutter {
1895                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1896                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1897                         };
1898
1899                         isp_flash_trigger: isp-flash-trigger {
1900                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1901                         };
1902
1903                         isp_prelight: isp-prelight {
1904                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1905                         };
1906
1907                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1908                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1909                         };
1910                 };
1911
1912                 gps {
1913                         gps_mag: gps-mag {
1914                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1915                         };
1916
1917                         gps_sig: gps-sig {
1918                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1919
1920                         };
1921
1922                         gps_rfclk: gps-rfclk {
1923                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1924                         };
1925                 };
1926
1927                 gmac {
1928                         rgmii_pins: rgmii-pins {
1929                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1930                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1931                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1932                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1933                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1934                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
1935                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
1936                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
1937                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1938                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1939                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1940                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1941                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1942                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1943                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
1944                         };
1945
1946                         rmii_pins: rmii-pins {
1947                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1948                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1949                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1950                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1951                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1952                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1953                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1954                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1955                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1956                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
1957                         };
1958                 };
1959
1960                 tsadc_pin {
1961                         tsadc_int: tsadc-int {
1962                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1963                         };
1964                         tsadc_gpio: tsadc-gpio {
1965                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1966                         };
1967                 };
1968
1969                 hdmi_pin {
1970                         hdmi_cec: hdmi-cec {
1971                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1972                         };
1973                 };
1974
1975                 hdmi_i2c {
1976                         hdmii2c_xfer: hdmii2c-xfer {
1977                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
1978                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1979                         };
1980                 };
1981         };
1982
1983         reboot {
1984                 compatible = "rockchip,rk3368-reboot";
1985                 rockchip,cru = <&cru>;
1986                 rockchip,pmugrf = <&pmugrf>;
1987         };
1988 };