1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-pm.h>
3 #include <dt-bindings/pinctrl/rockchip.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/sensor-dev.h>
6 #include <dt-bindings/clock/rk_system_status.h>
8 #include "rk3368-clocks.dtsi"
11 compatible = "rockchip,rk3368";
13 rockchip,sram = <&sram>;
14 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a53","arm,armv8";
47 gic: interrupt-controller@ffb70000 {
48 compatible = "arm,cortex-a15-gic";
49 #interrupt-cells = <3>;
52 reg = <0x0 0xffb71000 0 0x1000>,
53 <0x0 0xffb72000 0 0x1000>;
56 pmu_grf: syscon@ff738000 {
57 compatible = "rockchip,rk3388-pmu-grf", "syscon";
58 reg = <0x0 0xff738000 0x0 0x100>;
61 sgrf: syscon@ff740000 {
62 compatible = "rockchip,rk3388-sgrf", "syscon";
63 reg = <0x0 0xff740000 0x0 0x1000>;
67 grf: syscon@ff770000 {
68 compatible = "rockchip,rk3388-grf", "syscon";
69 reg = <0x0 0xff770000 0x0 0x1000>;
73 compatible = "arm,armv8-pmuv3";
74 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
84 cpu_axi_bus: cpu_axi_bus {
85 compatible = "rockchip,cpu_axi_bus";
97 reg = <0x0 0xffa80000 0x0 0x20>;
101 reg = <0x0 0xffa90000 0x0 0x20>;
104 reg = <0x0 0xffa90080 0x0 0x20>;
107 reg = <0x0 0xffa90100 0x0 0x20>;
110 reg = <0x0 0xffa90280 0x0 0x20>;
114 reg = <0x0 0xffaa0000 0x0 0x20>;
117 reg = <0x0 0xffaa0080 0x0 0x20>;
121 reg = <0x0 0xffab0000 0x0 0x20>;
125 reg = <0x0 0xffad0000 0x0 0x20>;
128 reg = <0x0 0xffad0080 0x0 0x20>;
131 reg = <0x0 0xffad0100 0x0 0x20>;
134 reg = <0x0 0xffad0180 0x0 0x20>;
137 reg = <0x0 0xffad0200 0x0 0x20>;
140 reg = <0x0 0xffad0280 0x0 0x20>;
143 reg = <0x0 0xffad0300 0x0 0x20>;
146 reg = <0x0 0xffad0380 0x0 0x20>;
149 reg = <0x0 0xffad0400 0x0 0x20>;
153 reg = <0x0 0xffae0000 0x0 0x20>;
156 reg = <0x0 0xffae0000 0x0 0x20>;
157 rockchip,priority = <2 2>;
160 reg = <0x0 0xffae0080 0x0 0x20>;
161 rockchip,priority = <2 2>;
164 reg = <0x0 0xffae0100 0x0 0x20>;
167 reg = <0x0 0xffae0180 0x0 0x20>;
168 rockchip,priority = <2 2>;
173 #address-cells = <2>;
178 reg = <0x0 0xffac0000 0x0 0x3c>;
179 rockchip,read-latency = <0x34>;
185 compatible = "arm,armv8-timer";
186 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
187 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
188 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
189 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
190 clock-frequency = <24000000>;
194 compatible = "rockchip,timer";
195 reg = <0x0 0xff810000 0x0 0x20>;
196 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
197 rockchip,broadcast = <1>;
200 sram: sram@ff8c0000 {
201 compatible = "mmio-sram";
202 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
206 watchdog: wdt@ff800000 {
207 compatible = "rockchip,watch dog";
208 reg = <0x0 0xff800000 0x0 0x100>;
209 clocks = <&pclk_alive_pre>;
210 clock-names = "pclk_wdt";
211 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
213 rockchip,timeout = <60>;
214 rockchip,atboot = <1>;
215 rockchip,debug = <0>;
220 #address-cells = <2>;
222 compatible = "arm,amba-bus";
223 interrupt-parent = <&gic>;
226 pdma0: pdma@ffb20000 {
227 compatible = "arm,pl330", "arm,primecell";
228 reg = <0x0 0xffb20000 0x0 0x4000>;
229 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
234 pdma1: pdma@ff250000 {
235 compatible = "arm,pl330", "arm,primecell";
236 reg = <0x0 0xff250000 0x0 0x4000>;
237 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
243 reset: reset@ff760300{
244 compatible = "rockchip,reset";
245 reg = <0x0 0xff760300 0x0 0x38>;
246 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
250 nandc0: nandc@ff400000 {
251 compatible = "rockchip,rk-nandc";
252 reg = <0x0 0xff400000 0x0 0x4000>;
253 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
256 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
259 nandc0reg: nandc0@ff400000 {
260 compatible = "rockchip,rk-nandc";
261 reg = <0x0 0xff400000 0x0 0x4000>;
264 emmc: rksdmmc@ff0f0000 {
265 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
266 reg = <0x0 0xff0f0000 0x0 0x4000>;
267 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
268 #address-cells = <1>;
270 clocks = <&clk_emmc>, <&clk_gates21 2>;
271 clock-names = "clk_mmc", "hclk_mmc";
273 fifo-depth = <0x100>;
277 sdmmc: rksdmmc@ff0c0000 {
278 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
279 reg = <0x0 0xff0c0000 0x0 0x4000>;
280 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
281 #address-cells = <1>;
283 pinctrl-names = "default", "idle";
284 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
285 pinctrl-1 = <&sdmmc_gpio>;
286 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
287 clocks = <&clk_sdmmc0>, <&clk_gates21 0>;
288 clock-names = "clk_mmc", "hclk_mmc";
290 fifo-depth = <0x100>;
294 sdio: rksdmmc@ff0d0000 {
295 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
296 reg = <0x0 0xff0d0000 0x0 0x4000>;
297 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
298 #address-cells = <1>;
300 pinctrl-names = "default","idle";
301 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
302 pinctrl-1 = <&sdio0_gpio>;
303 clocks = <&clk_sdio0>, <&clk_gates21 1>;
304 clock-names = "clk_mmc", "hclk_mmc";
306 fifo-depth = <0x100>;
311 compatible = "rockchip,rockchip-spi";
312 reg = <0x0 0xff110000 0x0 0x1000>;
313 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
318 rockchip,spi-src-clk = <0>;
320 clocks =<&clk_spi0>, <&clk_gates19 4>;
321 clock-names = "spi", "pclk_spi0";
322 //dmas = <&pdma1 11>, <&pdma1 12>;
324 //dma-names = "tx", "rx";
329 compatible = "rockchip,rockchip-spi";
330 reg = <0x0 0xff120000 0x0 0x1000>;
331 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
332 #address-cells = <1>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
336 rockchip,spi-src-clk = <1>;
338 clocks = <&clk_spi1>, <&clk_gates19 5>;
339 clock-names = "spi", "pclk_spi1";
340 //dmas = <&pdma1 13>, <&pdma1 14>;
342 //dma-names = "tx", "rx";
347 compatible = "rockchip,rockchip-spi";
348 reg = <0x0 0xff130000 0x0 0x1000>;
349 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
350 #address-cells = <1>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
354 rockchip,spi-src-clk = <2>;
356 clocks = <&clk_spi2>, <&clk_gates19 6>;
357 clock-names = "spi", "pclk_spi2";
358 //dmas = <&pdma1 15>, <&pdma1 16>;
360 //dma-names = "tx", "rx";
364 uart_bt: serial@ff180000 {
365 compatible = "rockchip,serial";
366 reg = <0x0 0xff180000 0x0 0x100>;
367 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
368 clock-frequency = <24000000>;
369 clocks = <&clk_uart0>, <&clk_gates19 7>;
370 clock-names = "sclk_uart", "pclk_uart";
373 //dmas = <&pdma1 1>, <&pdma1 2>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
380 uart_bb: serial@ff190000 {
381 compatible = "rockchip,serial";
382 reg = <0x0 0xff190000 0x0 0x100>;
383 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
384 clock-frequency = <24000000>;
385 clocks = <&clk_uart1>, <&clk_gates19 8>;
386 clock-names = "sclk_uart", "pclk_uart";
389 //dmas = <&pdma1 3>, <&pdma1 4>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
396 uart_dbg: serial@ff690000 {
397 compatible = "rockchip,serial";
398 reg = <0x0 0xff690000 0x0 0x100>;
399 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
400 clock-frequency = <24000000>;
401 clocks = <&clk_uart2>, <&clk_gates13 5>;
402 clock-names = "sclk_uart", "pclk_uart";
405 //dmas = <&pdma0 4>, <&pdma0 5>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&uart2_xfer>;
412 uart_gps: serial@ff1b0000 {
413 compatible = "rockchip,serial";
414 reg = <0x0 0xff1b0000 0x0 0x100>;
415 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
416 clock-frequency = <24000000>;
417 clocks = <&clk_uart3>, <&clk_gates19 9>;
418 clock-names = "sclk_uart", "pclk_uart";
419 current-speed = <115200>;
422 //dmas = <&pdma1 7>, <&pdma1 8>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
429 uart_exp: serial@ff1c0000 {
430 compatible = "rockchip,serial";
431 reg = <0x0 0xff1c0000 0x0 0x100>;
432 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
433 clock-frequency = <24000000>;
434 clocks = <&clk_uart4>, <&clk_gates19 10>;
435 clock-names = "sclk_uart", "pclk_uart";
438 //dmas = <&pdma1 9>, <&pdma1 10>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
445 rockchip_clocks_init: clocks-init{
446 compatible = "rockchip,clocks-init";
447 rockchip,clocks-init-parent =
448 <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
449 <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
450 <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
452 rockchip,clocks-init-rate =
453 <&clk_gpll 576000000>, <&clk_core_b 792000000>,
454 <&clk_core_l 600000000>, <&clk_cpll 400000000>,
455 /*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
456 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
457 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
458 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
459 <&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
460 <&clk_cs 300000000>, <&clkin_trace 300000000>,
461 <&aclk_cci 600000000>, <&clk_mac 50000000>,
462 <&aclk_vio0 400000000>, <&hclk_vio 100000000>,
463 <&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
464 <&clk_isp 400000000>, <&clk_edp 200000000>,
465 <&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
466 <&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
467 <&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
468 <&clk_hevc_cabac 300000000>;
470 rockchip,clocks-uboot-has-init =
475 rockchip_clocks_enable: clocks-enable {
476 compatible = "rockchip,clocks-enable";
493 <&clk_gates12 12>,/*aclk_strc_sys*/
494 <&clk_gates12 6>,/*aclk_intmem1*/
495 <&clk_gates12 5>,/*aclk_intmem0*/
496 <&clk_gates12 4>,/*aclk_intmem*/
497 <&clk_gates13 9>,/*aclk_gic400*/
500 <&clk_gates22 13>,/*pclk_timer1*/
501 <&clk_gates22 12>,/*pclk_timer0*/
502 <&clk_gates22 9>,/*pclk_alive_niu*/
503 <&clk_gates22 8>,/*pclk_grf*/
506 <&clk_gates23 5>,/*pclk_pmugrf*/
507 <&clk_gates23 3>,/*pclk_sgrf*/
508 <&clk_gates23 2>,/*pclk_pmu_noc*/
509 <&clk_gates23 1>,/*pclk_intmem1*/
510 <&clk_gates23 0>,/*pclk_pmu*/
513 <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
514 <&clk_gates20 8>,/*aclk_peri_niu*/
515 <&clk_gates21 4>,/*aclk_peri_mmu*/
516 <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
517 <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
518 <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
522 compatible = "rockchip,rk30-i2c";
523 reg = <0x0 0xff650000 0x0 0x1000>;
524 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
525 #address-cells = <1>;
527 pinctrl-names = "default", "gpio";
528 pinctrl-0 = <&i2c0_xfer>;
529 pinctrl-1 = <&i2c0_gpio>;
530 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
531 clocks = <&clk_gates12 2>;
532 rockchip,check-idle = <1>;
537 compatible = "rockchip,rk30-i2c";
538 reg = <0x0 0xff140000 0x0 0x1000>;
539 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
540 #address-cells = <1>;
542 pinctrl-names = "default", "gpio";
543 pinctrl-0 = <&i2c1_xfer>;
544 pinctrl-1 = <&i2c1_gpio>;
545 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
546 clocks = <&clk_gates19 11>;
547 rockchip,check-idle = <1>;
552 compatible = "rockchip,rk30-i2c";
553 reg = <0x0 0xff660000 0x0 0x1000>;
554 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
555 #address-cells = <1>;
557 pinctrl-names = "default", "gpio";
558 pinctrl-0 = <&i2c2_xfer>;
559 pinctrl-1 = <&i2c2_gpio>;
560 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
561 clocks = <&clk_gates12 3>;
562 rockchip,check-idle = <1>;
567 compatible = "rockchip,rk30-i2c";
568 reg = <0x0 0xff150000 0x0 0x1000>;
569 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
570 #address-cells = <1>;
572 pinctrl-names = "default", "gpio";
573 pinctrl-0 = <&i2c3_xfer>;
574 pinctrl-1 = <&i2c3_gpio>;
575 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
576 clocks = <&clk_gates19 12>;
577 rockchip,check-idle = <1>;
582 compatible = "rockchip,rk30-i2c";
583 reg = <0x0 0xff160000 0x0 0x1000>;
584 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
585 #address-cells = <1>;
587 pinctrl-names = "default", "gpio";
588 pinctrl-0 = <&i2c4_xfer>;
589 pinctrl-1 = <&i2c4_gpio>;
590 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
591 clocks = <&clk_gates19 13>;
592 rockchip,check-idle = <1>;
597 compatible = "rockchip,rk30-i2c";
598 reg = <0x0 0xff170000 0x0 0x1000>;
599 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
600 #address-cells = <1>;
602 pinctrl-names = "default", "gpio";
603 pinctrl-0 = <&i2c5_xfer>;
604 pinctrl-1 = <&i2c5_gpio>;
605 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
606 clocks = <&clk_gates19 14>;
607 rockchip,check-idle = <1>;
612 compatible = "rockchip,rk-fb";
613 rockchip,disp-mode = <NO_DUAL>;
617 rk_screen: rk_screen {
618 compatible = "rockchip,screen";
621 dsihost0: mipi@ff960000{
622 compatible = "rockchip,rk33x-dsi";
624 reg = <0xff960000 0x4000>, <0xff968000 0x4000>;
625 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
626 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&clk_gates4 14>, <&clk_gates17 3>, <&clk_gates22 10>;
628 clock-names = "clk_mipi_24m", "pclk_mipi_dsi_host", "pclk_mipi_dsi_phy";
632 lvds: lvds@ff968000 {
633 compatible = "rockchip,rk3368-lvds";
634 rockchip,grf = <&grf>;
635 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
636 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
637 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
638 clock-names = "pclk_lvds", "pclk_lvds_ctl";
643 compatible = "rockchip,rk32-edp";
644 reg = <0x0 0xff970000 0x0 0x4000>;
645 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
647 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
650 hdmi: hdmi@ff980000 {
651 compatible = "rockchip,rk3368-hdmi";
652 reg = <0x0 0xff980000 0x0 0x20000>;
653 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
654 pinctrl-names = "default", "gpio";
655 pinctrl-0 = <&i2c5_xfer &hdmi_cec>;
656 pinctrl-1 = <&i2c5_gpio>;
657 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
658 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
662 hdmi_hdcp2: hdmi_hdcp2@ff978000 {
663 compatible = "rockchip,rk3368-hdmi-hdcp2";
664 reg = <0x0 0xff978000 0x0 0x2000>;
665 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
667 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
671 lcdc: lcdc@ff930000 {
672 compatible = "rockchip,rk3368-lcdc";
673 rockchip,prop = <PRMRY>;
674 rockchip,pwr18 = <0>;
675 rockchip,iommu-enabled = <0>;
676 reg = <0x0 0xff930000 0x0 0x10000>;
677 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
678 pinctrl-names = "default", "gpio";
679 pinctrl-0 = <&lcdc_lcdc>;
680 pinctrl-1 = <&lcdc_gpio>;
682 clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
683 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
687 compatible = "rockchip,saradc";
688 reg = <0x0 0xff100000 0x0 0x100>;
689 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
690 #io-channel-cells = <1>;
692 rockchip,adc-vref = <1800>;
693 clock-frequency = <1000000>;
694 clocks = <&clk_saradc>, <&clk_gates19 15>;
695 clock-names = "saradc", "pclk_saradc";
700 compatible = "rockchip,rk3368-rga2";
701 reg = <0x0 0xff920000 0x0 0x1000>;
702 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
704 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
707 i2s0: i2s0@ff898000 {
708 compatible = "rockchip-i2s";
709 reg = <0x0 0xff898000 0x0 0x1000>;
711 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
712 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
713 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
714 dmas = <&pdma0 0>, <&pdma0 1>;
716 dma-names = "tx", "rx";
717 pinctrl-names = "default", "sleep";
718 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
719 pinctrl-1 = <&i2s_gpio>;
722 i2s1: i2s1@ff890000 {
723 compatible = "rockchip-i2s";
724 reg = <0x0 0xff890000 0x0 0x1000>;
726 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
727 clock-names = "i2s_clk", "i2s_hclk";
728 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
729 dmas = <&pdma0 6>, <&pdma0 7>;
731 dma-names = "tx", "rx";
734 spdif: spdif@ff880000 {
735 compatible = "rockchip-spdif";
736 reg = <0x0 0xff880000 0x0 0x1000>;
737 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
738 clock-names = "spdif_mclk", "spdif_hclk";
739 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
743 pinctrl-names = "default";
744 pinctrl-0 = <&spdif_tx>;
748 compatible = "rockchip,rk-pwm";
749 reg = <0x0 0xff680000 0x0 0x10>;
751 pinctrl-names = "default";
752 pinctrl-0 = <&pwm0_pin>;
753 clocks = <&clk_gates13 6>;
754 clock-names = "pclk_pwm";
759 compatible = "rockchip,rk-pwm";
760 reg = <0x0 0xff680010 0x0 0x10>;
762 pinctrl-names = "default";
763 pinctrl-0 = <&pwm1_pin>;
764 clocks = <&clk_gates13 6>;
765 clock-names = "pclk_pwm";
770 compatible = "rockchip,rk-pwm";
771 reg = <0x0 0xff680020 0x0 0x10>;
773 //pinctrl-names = "default";
774 //pinctrl-0 = <&pwm1_pin>;
775 clocks = <&clk_gates13 6>;
776 clock-names = "pclk_pwm";
781 compatible = "rockchip,rk-pwm";
782 reg = <0x0 0xff680030 0x0 0x10>;
784 pinctrl-names = "default";
785 pinctrl-0 = <&pwm3_pin>;
786 clocks = <&clk_gates13 6>;
787 clock-names = "pclk_pwm";
794 regulator_name = "vdd_arm";
795 suspend_volt = <1000>; //mV
797 clk_core_dvfs_table: clk_core {
806 temp-limit-enable = <0>;
808 normal-temp-limit = <
809 /*delta-temp delta-freq*/
815 performance-temp-limit = <
831 regulator_name = "vdd_logic";
832 suspend_volt = <1000>; //mV
834 clk_ddr_dvfs_table: clk_ddr {
847 aclk_vio1_dvfs_table: aclk_vio1 {
859 regulator_name = "vdd_gpu";
860 suspend_volt = <1000>; //mV
862 clk_gpu_dvfs_table: clk_gpu {
883 compatible = "rockchip,ion";
884 #address-cells = <1>;
887 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
888 compatible = "rockchip,ion-heap";
889 rockchip,ion_heap = <1>;
890 reg = <0x0 0x00000000 0x0 0x08000000>; /* 512MB */
892 rockchip,ion-heap@3 { /* VMALLOC HEAP */
893 compatible = "rockchip,ion-heap";
894 rockchip,ion_heap = <3>;
898 vpu: vpu_service@ff9a0000 {
899 compatible = "vpu_service";
901 reg = <0x0 0xff9a0000 0x0 0x800>;
902 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
903 interrupt-names = "irq_enc", "irq_dec";
905 clocks = <&clk_vdpu>, <&hclk_vdpu>;
906 clock-names = "aclk_vcodec", "hclk_vcodec";
908 name = "vpu_service";
909 /* status = "disabled"; */
913 compatible = "rockchip,iep";
915 reg = <0x0 0xff900000 0x0 0x800>;
916 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
918 clock-names = "aclk_iep", "hclk_iep";
923 compatible = "rockchip,rk3368-gmac";
924 reg = <0x0 0xff290000 0x0 0x10000>;
925 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
926 interrupt-names = "macirq";
928 clocks = <&clk_mac>, <&clk_gates5 0>,
929 <&clk_gates5 1>, <&clk_gates5 2>,
930 <&clk_gates5 3>, <&clk_gates8 0>,
932 clock-names = "clk_mac", "mac_clk_rx",
933 "mac_clk_tx", "clk_mac_ref",
934 "clk_mac_refout", "aclk_mac",
938 pinctrl-names = "default";
939 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
943 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
944 reg = <0x0 0xffa30000 0x0 0x10000>;
945 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
946 interrupt-names = "GPU";
951 compatible = "rockchip,iep_mmu";
952 reg = <0x0 0xff900800 0x0 0x100>;
953 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
954 interrupt-names = "iep_mmu";
959 compatible = "rockchip,vip_mmu";
960 reg = <0x0 0xff950800 0x0 0x100>;
961 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
962 interrupt-names = "vip_mmu";
967 compatible = "rockchip,vop_mmu";
968 reg = <0x0 0xff930300 0x0 0x100>;
969 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
970 interrupt-names = "vop_mmu";
975 compatible = "rockchip,isp_mmu";
976 reg = <0x0 0xff914000 0x0 0x100>,
977 <0x0 0xff915000 0x0 0x100>;
978 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
979 interrupt-names = "isp_mmu";
983 dbgname = "hdcp_mmu";
984 compatible = "rockchip,hdcp_mmu";
985 reg = <0x0 0xff940000 0x0 0x100>;
986 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
987 interrupt-names = "hdcp_mmu";
992 compatible = "rockchip,hevc_mmu";
993 reg = <0x0 0xff9c0440 0x0 0x40>, /*need to fix*/
994 <0x0 0xff9c0480 0x0 0x40>;
995 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
996 interrupt-names = "hevc_mmu";
1001 compatible = "rockchip,vpu_mmu";
1002 reg = <0x0 0xff9a0800 0x0 0x100>; /*need to fix*/
1003 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1004 interrupt-names = "vpu_mmu";
1008 rockchip,ctrbits = <
1015 |RKPM_CTR_SYSCLK_DIV
1016 |RKPM_CTR_IDLEAUTO_MD
1017 |RKPM_CTR_ARMOFF_LPMD
1019 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1022 rockchip,pmic-suspend_gpios = <
1023 /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1025 rockchip,pmic-resume_gpios = <
1026 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1031 compatible = "rockchip,isp";
1032 reg = <0x0 0xff910000 0x0 0x10000>;
1033 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1034 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1035 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1036 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1037 pinctrl-0 = <&cif_clkout>;
1038 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1039 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1040 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1041 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1042 pinctrl-5 = <&cif_clkout>;
1043 pinctrl-6 = <&cif_clkout &isp_prelight>;
1044 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1045 pinctrl-8 = <&isp_flash_trigger>;
1046 rockchip,isp,mipiphy = <2>;
1047 rockchip,isp,cifphy = <1>;
1048 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1049 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1050 rockchip,isp,iommu_enable = <1>;
1054 tsadc: tsadc@ff280000 {
1055 compatible = "rockchip,tsadc";
1056 reg = <0x0 0xff280000 0x0 0x100>;
1057 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1058 #io-channel-cells = <1>;
1060 clock-frequency = <10000>;
1061 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1062 clock-names = "tsadc", "pclk_tsadc";
1063 pinctrl-names = "default", "tsadc_int";
1064 pinctrl-0 = <&tsadc_gpio>;
1065 pinctrl-1 = <&tsadc_int>;
1066 tsadc-ht-temp = <120>;
1067 tsadc-ht-reset-cru = <1>;
1068 tsadc-ht-pull-gpio = <0>;
1069 status = "disabled";
1073 compatible = "rockchip,rk3368-tsp";
1074 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1075 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1076 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1077 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1078 interrupt-names = "irq_tsp";
1079 // pinctrl-names = "default";
1080 // pinctrl-0 = <&isp_hsadc>;
1084 crypto: crypto@FF8A0000{
1085 compatible = "rockchip,rk3368-crypto";
1086 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1087 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1088 interrupt-names = "irq_crypto";
1089 clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1090 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1095 compatible = "rockchip,rk3368-pinctrl";
1096 rockchip,grf = <&grf>;
1097 rockchip,pmu = <&pmu_grf>;
1098 #address-cells = <2>;
1102 gpio0: gpio0@ff750000 {
1103 compatible = "rockchip,gpio-bank";
1104 reg = <0x0 0xff750000 0x0 0x100>;
1105 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&clk_gates23 4>;
1111 interrupt-controller;
1112 #interrupt-cells = <2>;
1115 gpio1: gpio1@ff780000 {
1116 compatible = "rockchip,gpio-bank";
1117 reg = <0x0 0xff780000 0x0 0x100>;
1118 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1119 clocks = <&clk_gates22 1>;
1124 interrupt-controller;
1125 #interrupt-cells = <2>;
1128 gpio2: gpio2@ff790000 {
1129 compatible = "rockchip,gpio-bank";
1130 reg = <0x0 0xff790000 0x0 0x100>;
1131 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1132 clocks = <&clk_gates22 2>;
1137 interrupt-controller;
1138 #interrupt-cells = <2>;
1141 gpio3: gpio3@ff7a0000 {
1142 compatible = "rockchip,gpio-bank";
1143 reg = <0x0 0xff7a0000 0x0 0x100>;
1144 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&clk_gates22 3>;
1150 interrupt-controller;
1151 #interrupt-cells = <2>;
1154 pcfg_pull_up: pcfg-pull-up {
1158 pcfg_pull_down: pcfg-pull-down {
1162 pcfg_pull_none: pcfg-pull-none {
1166 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1167 drive-strength = <8>;
1170 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1172 drive-strength = <8>;
1175 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1176 drive-strength = <4>;
1179 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1181 drive-strength = <4>;
1184 pcfg_output_high: pcfg-output-high {
1188 pcfg_output_low: pcfg-output-low {
1193 i2c0_xfer: i2c0-xfer {
1194 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1195 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1197 i2c0_gpio: i2c0-gpio {
1198 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1199 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1204 i2c1_xfer: i2c1-xfer {
1205 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1206 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1208 i2c1_gpio: i2c1-gpio {
1209 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1210 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1215 i2c2_xfer: i2c2-xfer {
1216 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1217 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1219 i2c2_gpio: i2c2-gpio {
1220 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1221 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1226 i2c3_xfer: i2c3-xfer {
1227 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1228 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1230 i2c3_gpio: i2c3-gpio {
1231 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1232 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1237 i2c4_xfer: i2c4-xfer {
1238 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1239 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1241 i2c4_gpio: i2c4-gpio {
1242 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1243 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1248 i2c5_xfer: i2c5-xfer {
1249 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1250 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1252 i2c5_gpio: i2c5-gpio {
1253 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1254 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1259 uart0_xfer: uart0-xfer {
1260 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1261 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1264 uart0_cts: uart0-cts {
1265 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1268 uart0_rts: uart0-rts {
1269 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1272 uart0_rts_gpio: uart0-rts-gpio {
1273 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1278 uart1_xfer: uart1-xfer {
1279 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1280 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1283 uart1_cts: uart1-cts {
1284 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1287 uart1_rts: uart1-rts {
1288 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1293 uart2_xfer: uart2-xfer {
1294 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1295 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1300 uart3_xfer: uart3-xfer {
1301 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1302 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1305 uart3_cts: uart3-cts {
1306 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1309 uart3_rts: uart3-rts {
1310 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1315 uart4_xfer: uart4-xfer {
1316 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1317 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1320 uart4_cts: uart4-cts {
1321 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1324 uart4_rts: uart4-rts {
1325 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1330 spi0_clk: spi0-clk {
1331 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1333 spi0_cs0: spi0-cs0 {
1334 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1337 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1340 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1342 spi0_cs1: spi0-cs1 {
1343 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1348 spi1_clk: spi1-clk {
1349 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1351 spi1_cs0: spi1-cs0 {
1352 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1355 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1358 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1363 spi2_clk: spi2-clk {
1364 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1366 spi2_cs0: spi2-cs0 {
1367 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1370 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1373 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1378 i2s_mclk: i2s-mclk {
1379 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1383 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1386 i2s_lrckrx:i2s-lrckrx {
1387 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1390 i2s_lrcktx:i2s-lrcktx {
1391 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1395 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1399 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1403 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1407 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1411 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1414 i2s_gpio: i2s-gpio {
1415 rockchip,pins = <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,
1416 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1417 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1418 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1419 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1420 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1421 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1422 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1423 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1428 spdif_tx: spdif-tx {
1429 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1434 sdmmc_clk: sdmmc-clk {
1435 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1438 sdmmc_cmd: sdmmc-cmd {
1439 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1442 sdmmc_dectn: sdmmc-dectn {
1443 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1446 sdmmc_bus1: sdmmc-bus1 {
1447 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1450 sdmmc_bus4: sdmmc-bus4 {
1451 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1452 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1453 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1454 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1457 sdmmc_gpio: sdmmc-gpio {
1458 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1459 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1460 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1461 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1462 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1463 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1464 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1469 sdio0_bus1: sdio0-bus1 {
1470 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1473 sdio0_bus4: sdio0-bus4 {
1474 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1475 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1476 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1477 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1480 sdio0_cmd: sdio0-cmd {
1481 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1484 sdio0_clk: sdio0-clk {
1485 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1488 sdio0_dectn: sdio0-dectn {
1489 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1492 sdio0_wrprt: sdio0-wrprt {
1493 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1496 sdio0_pwren: sdio0-pwren {
1497 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1500 sdio0_bkpwr: sdio0-bkpwr {
1501 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1504 sdio0_int: sdio0-int {
1505 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1508 sdio0_gpio: sdio0-gpio {
1509 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1510 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1511 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1512 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1513 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1514 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1515 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1516 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1517 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1518 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1519 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1524 emmc_clk: emmc-clk {
1525 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1528 emmc_cmd: emmc-cmd {
1529 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1532 emmc_pwren: emmc-pwren {
1533 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1536 emmc_rstnout: emmc_rstnout {
1537 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1540 emmc_bus1: emmc-bus1 {
1541 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1544 emmc_bus4: emmc-bus4 {
1545 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1546 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1547 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1548 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1553 pwm0_pin: pwm0-pin {
1554 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1557 vop_pwm_pin:vop-pwm {
1558 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1563 pwm1_pin: pwm1-pin {
1564 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1569 pwm3_pin: pwm3-pin {
1570 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1575 lcdc_lcdc: lcdc-lcdc {
1576 rockchip,pins = <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1577 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1578 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1579 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1582 lcdc_gpio: lcdc-gpio {
1583 rockchip,pins = <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1584 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1585 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1586 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1591 cif_clkout: cif-clkout {
1592 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1595 isp_dvp_d2d9: isp-dvp-d2d9 {
1596 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1597 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1598 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1599 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1600 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1601 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1602 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1603 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1604 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1605 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1606 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1607 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1610 isp_dvp_d0d1: isp-dvp-d0d1 {
1611 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1612 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1615 isp_dvp_d10d11:isp_d10d11 {
1616 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1617 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1620 isp_dvp_d0d7: isp-dvp-d0d7 {
1621 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1622 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1623 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1624 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1625 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1626 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1627 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1628 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1631 isp_shutter: isp-shutter {
1632 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1633 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1636 isp_flash_trigger: isp-flash-trigger {
1637 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1640 isp_prelight: isp-prelight {
1641 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1644 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1645 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1651 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1655 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1659 gps_rfclk: gps-rfclk {
1660 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1666 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1669 mac_txpins: mac-txpins {
1670 rockchip,pins = <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//TXD0
1671 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//TXD1
1672 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//TXD2
1673 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//TXD3
1674 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//TXEN
1675 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;//TXCLK
1678 mac_rxpins: mac-rxpins {
1679 rockchip,pins = <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1680 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1681 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1682 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1683 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1684 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//RXER
1685 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1686 <3 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;//COL
1690 rockchip,pins = <3 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>; //CRS
1693 mac_mdpins: mac-mdpins {
1694 rockchip,pins = <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1695 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;//MDC
1700 tsadc_int: tsadc-int {
1701 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1703 tsadc_gpio: tsadc-gpio {
1704 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1709 hdmi_cec: hdmi-cec {
1710 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;