arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53","arm,armv8";
  43                         reg = <0x0 0x0>;
  44                 };
  45         };
  46
  47         gic: interrupt-controller@ffb70000 {
  48                 compatible = "arm,cortex-a15-gic";
  49                 #interrupt-cells = <3>;
  50                 #address-cells = <0>;
  51                 interrupt-controller;
  52                 reg = <0x0 0xffb71000 0 0x1000>,
  53                       <0x0 0xffb72000 0 0x1000>;
  54         };
  55
  56         pmu_grf: syscon@ff738000 {
  57                 compatible = "rockchip,rk3388-pmu-grf", "syscon";
  58                 reg = <0x0 0xff738000 0x0 0x100>;
  59         };
  60
  61         sgrf: syscon@ff740000 {
  62                 compatible = "rockchip,rk3388-sgrf", "syscon";
  63                 reg = <0x0 0xff740000 0x0 0x1000>;
  64
  65         };
  66
  67         grf: syscon@ff770000 {
  68                 compatible = "rockchip,rk3388-grf", "syscon";
  69                 reg = <0x0 0xff770000 0x0 0x1000>;
  70         };
  71
  72         arm-pmu {
  73                 compatible = "arm,armv8-pmuv3";
  74                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
  77                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
  78                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  79                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
  82         };
  83
  84 #if 0
  85         cpu_axi_bus: cpu_axi_bus {
  86                 compatible = "rockchip,cpu_axi_bus";
  87                 #address-cells = <2>;
  88                 #size-cells = <2>;
  89                 ranges;
  90
  91                 qos {
  92                         #address-cells = <2>;
  93                         #size-cells = <2>;
  94                         ranges;
  95
  96                         /* service cpup */
  97                         bus_cpup {
  98                                 reg = <0x0 0xffa80000 0x0 0x20>;
  99                         };
 100                         /* service dmac */
 101                         bus_dmac {
 102                                 reg = <0x0 0xffa90000 0x0 0x20>;
 103                         };
 104                         crypto {
 105                                 reg = <0x0 0xffa90080 0x0 0x20>;
 106                         };
 107                         mcu {
 108                                 reg = <0x0 0xffa90100 0x0 0x20>;
 109                         };
 110                         tsp {
 111                                 reg = <0x0 0xffa90280 0x0 0x20>;
 112                         };
 113                         /* service cci */
 114                         cci_r {
 115                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 116                         };
 117                         cci_w {
 118                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 119                         };
 120                         /* service peri */
 121                         peri {
 122                                 reg = <0x0 0xffab0000 0x0 0x20>;
 123                         };
 124                         /* service vio */
 125                         vio0_iep {
 126                                 reg = <0x0 0xffad0000 0x0 0x20>;
 127                         };
 128                         vio0_isp_r0 {
 129                                 reg = <0x0 0xffad0080 0x0 0x20>;
 130                         };
 131                         vio0_isp_r1 {
 132                                 reg = <0x0 0xffad0100 0x0 0x20>;
 133                         };
 134                         vio0_isp_w0 {
 135                                 reg = <0x0 0xffad0180 0x0 0x20>;
 136                         };
 137                         vio0_isp_w1 {
 138                                 reg = <0x0 0xffad0200 0x0 0x20>;
 139                         };
 140                         vio_vip {
 141                                 reg = <0x0 0xffad0280 0x0 0x20>;
 142                         };
 143                         vio1_vop {
 144                                 reg = <0x0 0xffad0300 0x0 0x20>;
 145                         };
 146                         vio1_rga_r {
 147                                 reg = <0x0 0xffad0380 0x0 0x20>;
 148                         };
 149                         vio1_rga_w {
 150                                 reg = <0x0 0xffad0400 0x0 0x20>;
 151                         };
 152                         /* service video */
 153                         video {
 154                                 reg = <0x0 0xffae0000 0x0 0x20>;
 155                         };
 156                         hevc_r {
 157                                 reg = <0x0 0xffae0000 0x0 0x20>;
 158                                 rockchip,priority = <2 2>;
 159                         };
 160                         hevc_w {
 161                                 reg = <0x0 0xffae0080 0x0 0x20>;
 162                                 rockchip,priority = <2 2>;
 163                         };
 164                         vpu_r {
 165                                 reg = <0x0 0xffae0100 0x0 0x20>;
 166                         };
 167                         vpu_w {
 168                                 reg = <0x0 0xffae0180 0x0 0x20>;
 169                                 rockchip,priority = <2 2>;
 170                         };
 171                 };
 172
 173                 msch {
 174                         #address-cells = <2>;
 175                         #size-cells = <2>;
 176                         ranges;
 177
 178                         msch {
 179                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 180                                 rockchip,read-latency = <0x34>;
 181                         };
 182                 };
 183         };
 184 #endif
 185
 186         timer {
 187                 compatible = "arm,armv8-timer";
 188                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 189                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 190                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 191                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 192                 clock-frequency = <24000000>;
 193         };
 194
 195         timer@ff810000 {
 196                 compatible = "rockchip,timer";
 197                 reg = <0x0 0xff810000 0x0 0x20>;
 198                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 199                 rockchip,broadcast = <1>;
 200         };
 201
 202         sram: sram@ff8c0000 {
 203                 compatible = "mmio-sram";
 204                 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
 205                 map-exec;
 206         };
 207
 208         watchdog: wdt@ff800000 {
 209                 compatible = "rockchip,watch dog";
 210                 reg = <0x0 0xff800000 0x0 0x100>;
 211                 clocks = <&pclk_alive_pre>;
 212                 clock-names = "pclk_wdt";
 213                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 214                 rockchip,irq = <1>;
 215                 rockchip,timeout = <60>;
 216                 rockchip,atboot = <1>;
 217                 rockchip,debug = <0>;
 218                 status = "disabled";
 219         };
 220
 221         amba {
 222                 #address-cells = <2>;
 223                 #size-cells = <2>;
 224                 compatible = "arm,amba-bus";
 225                 interrupt-parent = <&gic>;
 226                 ranges;
 227
 228                 pdma0: pdma@ffb20000 {
 229                         compatible = "arm,pl330", "arm,primecell";
 230                         reg = <0x0 0xffb20000 0x0 0x4000>;
 231                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 232                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 233                         #dma-cells = <1>;
 234                 };
 235
 236                 pdma1: pdma@ff250000 {
 237                         compatible = "arm,pl330", "arm,primecell";
 238                         reg = <0x0 0xff250000 0x0 0x4000>;
 239                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 240                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 241                         #dma-cells = <1>;
 242                 };
 243         };
 244
 245         reset: reset@ff760300{
 246                 compatible = "rockchip,reset";
 247                 reg = <0x0 0xff760300 0x0 0x38>;
 248                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 249                 #reset-cells = <1>;
 250         };
 251
 252         nandc0: nandc@ff400000 {
 253                 compatible = "rockchip,rk-nandc";
 254                 reg = <0x0 0xff400000 0x0 0x4000>;
 255                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 256                 nandc_id = <0>;
 257                 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
 258                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 259         };
 260
 261         nandc0reg: nandc0@ff400000 {
 262                 compatible = "rockchip,rk-nandc";
 263                 reg = <0x0 0xff400000 0x0 0x4000>;
 264         };
 265
 266         emmc: rksdmmc@ff0f0000 {
 267                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 268                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 269                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 270                 #address-cells = <1>;
 271                 #size-cells = <0>;
 272                 clocks = <&clk_emmc>, <&clk_gates21 2>;
 273                 clock-names = "clk_mmc", "hclk_mmc";
 274                 num-slots = <1>;
 275                 fifo-depth = <0x100>;
 276                 bus-width = <8>;
 277         };
 278
 279         sdmmc: rksdmmc@ff0c0000 {
 280                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 281                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 282                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 283                 #address-cells = <1>;
 284                 #size-cells = <0>;
 285                 pinctrl-names = "default", "idle";
 286                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 287                 pinctrl-1 = <&sdmmc_gpio>;
 288                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 289                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>;
 290                 clock-names = "clk_mmc", "hclk_mmc";
 291                 num-slots = <1>;
 292                 fifo-depth = <0x100>;
 293                 bus-width = <4>;
 294         };
 295
 296         sdio: rksdmmc@ff0d0000 {
 297                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 298                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 299                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 300                 #address-cells = <1>;
 301                 #size-cells = <0>;
 302                 pinctrl-names = "default","idle";
 303                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 304                 pinctrl-1 = <&sdio0_gpio>;
 305                 clocks = <&clk_sdio0>, <&clk_gates21 1>;
 306                 clock-names = "clk_mmc", "hclk_mmc";
 307                 num-slots = <1>;
 308                 fifo-depth = <0x100>;
 309                 bus-width = <4>;
 310         };
 311
 312         spi0: spi@ff110000 {
 313                 compatible = "rockchip,rockchip-spi";
 314                 reg = <0x0 0xff110000 0x0 0x1000>;
 315                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 320                 rockchip,spi-src-clk = <0>;
 321                 num-cs = <2>;
 322                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 323                 clock-names = "spi", "pclk_spi0";
 324                 //dmas = <&pdma1 11>, <&pdma1 12>;
 325                 //#dma-cells = <2>;
 326                 //dma-names = "tx", "rx";
 327                 status = "disabled";
 328         };
 329
 330         spi1: spi@ff120000 {
 331                 compatible = "rockchip,rockchip-spi";
 332                 reg = <0x0 0xff120000 0x0 0x1000>;
 333                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 pinctrl-names = "default";
 337                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 338                 rockchip,spi-src-clk = <1>;
 339                 num-cs = <1>;
 340                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 341                 clock-names = "spi", "pclk_spi1";
 342                 //dmas = <&pdma1 13>, <&pdma1 14>;
 343                 //#dma-cells = <2>;
 344                 //dma-names = "tx", "rx";
 345                 status = "disabled";
 346         };
 347
 348         spi2: spi@ff130000 {
 349                 compatible = "rockchip,rockchip-spi";
 350                 reg = <0x0 0xff130000 0x0 0x1000>;
 351                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 356                 rockchip,spi-src-clk = <2>;
 357                 num-cs = <1>;
 358                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 359                 clock-names = "spi", "pclk_spi2";
 360                 //dmas = <&pdma1 15>, <&pdma1 16>;
 361                 //#dma-cells = <2>;
 362                 //dma-names = "tx", "rx";
 363                 status = "disabled";
 364         };
 365
 366         uart_bt: serial@ff180000 {
 367                 compatible = "rockchip,serial";
 368                 reg = <0x0 0xff180000 0x0 0x100>;
 369                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 370                 clock-frequency = <24000000>;
 371                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 372                 clock-names = "sclk_uart", "pclk_uart";
 373                 reg-shift = <2>;
 374                 reg-io-width = <4>;
 375                 //dmas = <&pdma1 1>, <&pdma1 2>;
 376                 //#dma-cells = <2>;
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 379                 status = "disabled";
 380         };
 381
 382         uart_bb: serial@ff190000 {
 383                 compatible = "rockchip,serial";
 384                 reg = <0x0 0xff190000 0x0 0x100>;
 385                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 386                 clock-frequency = <24000000>;
 387                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 388                 clock-names = "sclk_uart", "pclk_uart";
 389                 reg-shift = <2>;
 390                 reg-io-width = <4>;
 391                 //dmas = <&pdma1 3>, <&pdma1 4>;
 392                 //#dma-cells = <2>;
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 395                 status = "disabled";
 396         };
 397
 398         uart_dbg: serial@ff690000 {
 399                 compatible = "rockchip,serial";
 400                 reg = <0x0 0xff690000 0x0 0x100>;
 401                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 402                 clock-frequency = <24000000>;
 403                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 404                 clock-names = "sclk_uart", "pclk_uart";
 405                 reg-shift = <2>;
 406                 reg-io-width = <4>;
 407                 //dmas = <&pdma0 4>, <&pdma0 5>;
 408                 //#dma-cells = <2>;
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&uart2_xfer>;
 411                 status = "disabled";
 412         };
 413
 414         uart_gps: serial@ff1b0000 {
 415                 compatible = "rockchip,serial";
 416                 reg = <0x0 0xff1b0000 0x0 0x100>;
 417                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 418                 clock-frequency = <24000000>;
 419                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 420                 clock-names = "sclk_uart", "pclk_uart";
 421                 current-speed = <115200>;
 422                 reg-shift = <2>;
 423                 reg-io-width = <4>;
 424                 //dmas = <&pdma1 7>, <&pdma1 8>;
 425                 //#dma-cells = <2>;
 426                 pinctrl-names = "default";
 427                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 428                 status = "disabled";
 429         };
 430
 431         uart_exp: serial@ff1c0000 {
 432                 compatible = "rockchip,serial";
 433                 reg = <0x0 0xff1c0000 0x0 0x100>;
 434                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 435                 clock-frequency = <24000000>;
 436                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 437                 clock-names = "sclk_uart", "pclk_uart";
 438                 reg-shift = <2>;
 439                 reg-io-width = <4>;
 440                 //dmas = <&pdma1 9>, <&pdma1 10>;
 441                 //#dma-cells = <2>;
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 444                 status = "disabled";
 445         };
 446
 447         rockchip_clocks_init: clocks-init{
 448                 compatible = "rockchip,clocks-init";
 449                 rockchip,clocks-init-parent =
 450                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 451                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 452                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 453                         <&clk_cs &clk_gpll>;
 454                 rockchip,clocks-init-rate =
 455                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 456                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 457                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 458                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 459                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 460                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 461                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 462                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 463                         <&aclk_cci 600000000>,          <&clk_mac 50000000>,
 464                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 465                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 466                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 467                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 468                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 469                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 470                         <&clk_hevc_cabac 300000000>;
 471 /*
 472                 rockchip,clocks-uboot-has-init =
 473                         <&aclk_vio0>;
 474 */
 475         };
 476
 477         rockchip_clocks_enable: clocks-enable {
 478                 compatible = "rockchip,clocks-enable";
 479                 clocks =
 480                         /*PLL*/
 481                         <&clk_apllb>,
 482                         <&clk_aplll>,
 483                         <&clk_dpll>,
 484                         <&clk_gpll>,
 485                         <&clk_cpll>,
 486
 487                         /*PD_CORE*/
 488                         <&clk_cs>,
 489                         <&clkin_trace>,
 490
 491                         /*PD_BUS*/
 492                         <&aclk_bus>,
 493                         <&hclk_bus>,
 494                         <&pclk_bus>,
 495                         <&clk_gates12 12>,/*aclk_strc_sys*/
 496                         <&clk_gates12 6>,/*aclk_intmem1*/
 497                         <&clk_gates12 5>,/*aclk_intmem0*/
 498                         <&clk_gates12 4>,/*aclk_intmem*/
 499                         <&clk_gates13 9>,/*aclk_gic400*/
 500
 501                         /*PD_ALIVE*/
 502                         <&clk_gates22 13>,/*pclk_timer1*/
 503                         <&clk_gates22 12>,/*pclk_timer0*/
 504                         <&clk_gates22 9>,/*pclk_alive_niu*/
 505                         <&clk_gates22 8>,/*pclk_grf*/
 506
 507                         /*PD_PMU*/
 508                         <&clk_gates23 5>,/*pclk_pmugrf*/
 509                         <&clk_gates23 3>,/*pclk_sgrf*/
 510                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 511                         <&clk_gates23 1>,/*pclk_intmem1*/
 512                         <&clk_gates23 0>,/*pclk_pmu*/
 513
 514                         /*PD_PERI*/
 515                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 516                         <&clk_gates20 8>,/*aclk_peri_niu*/
 517                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 518                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 519                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 520                         <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
 521         };
 522
 523         i2c0: i2c@ff650000 {
 524                 compatible = "rockchip,rk30-i2c";
 525                 reg = <0x0 0xff650000 0x0 0x1000>;
 526                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 527                 #address-cells = <1>;
 528                 #size-cells = <0>;
 529                 pinctrl-names = "default", "gpio";
 530                 pinctrl-0 = <&i2c0_xfer>;
 531                 pinctrl-1 = <&i2c0_gpio>;
 532                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 533                 clocks = <&clk_gates12 2>;
 534                 rockchip,check-idle = <1>;
 535                 status = "disabled";
 536         };
 537
 538         i2c1: i2c@ff140000 {
 539                 compatible = "rockchip,rk30-i2c";
 540                 reg = <0x0 0xff140000 0x0 0x1000>;
 541                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 pinctrl-names = "default", "gpio";
 545                 pinctrl-0 = <&i2c1_xfer>;
 546                 pinctrl-1 = <&i2c1_gpio>;
 547                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 548                 clocks = <&clk_gates19 11>;
 549                 rockchip,check-idle = <1>;
 550                 status = "disabled";
 551         };
 552
 553         i2c2: i2c@ff660000 {
 554                 compatible = "rockchip,rk30-i2c";
 555                 reg = <0x0 0xff660000 0x0 0x1000>;
 556                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 557                 #address-cells = <1>;
 558                 #size-cells = <0>;
 559                 pinctrl-names = "default", "gpio";
 560                 pinctrl-0 = <&i2c2_xfer>;
 561                 pinctrl-1 = <&i2c2_gpio>;
 562                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 563                 clocks = <&clk_gates12 3>;
 564                 rockchip,check-idle = <1>;
 565                 status = "disabled";
 566         };
 567
 568         i2c3: i2c@ff150000 {
 569                 compatible = "rockchip,rk30-i2c";
 570                 reg = <0x0 0xff150000 0x0 0x1000>;
 571                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 pinctrl-names = "default", "gpio";
 575                 pinctrl-0 = <&i2c3_xfer>;
 576                 pinctrl-1 = <&i2c3_gpio>;
 577                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 578                 clocks = <&clk_gates19 12>;
 579                 rockchip,check-idle = <1>;
 580                 status = "disabled";
 581         };
 582
 583         i2c4: i2c@ff160000 {
 584                 compatible = "rockchip,rk30-i2c";
 585                 reg = <0x0 0xff160000 0x0 0x1000>;
 586                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 pinctrl-names = "default", "gpio";
 590                 pinctrl-0 = <&i2c4_xfer>;
 591                 pinctrl-1 = <&i2c4_gpio>;
 592                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 593                 clocks = <&clk_gates19 13>;
 594                 rockchip,check-idle = <1>;
 595                 status = "disabled";
 596         };
 597
 598         i2c5: i2c@ff170000 {
 599                 compatible = "rockchip,rk30-i2c";
 600                 reg = <0x0 0xff170000 0x0 0x1000>;
 601                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 602                 #address-cells = <1>;
 603                 #size-cells = <0>;
 604                 pinctrl-names = "default", "gpio";
 605                 pinctrl-0 = <&i2c5_xfer>;
 606                 pinctrl-1 = <&i2c5_gpio>;
 607                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 608                 clocks = <&clk_gates19 14>;
 609                 rockchip,check-idle = <1>;
 610                 status = "disabled";
 611         };
 612
 613         fb: fb {
 614                 compatible = "rockchip,rk-fb";
 615                 rockchip,disp-mode = <NO_DUAL>;
 616         };
 617
 618
 619         rk_screen: rk_screen {
 620                 compatible = "rockchip,screen";
 621         };
 622
 623         dsihost0: mipi@ff960000{
 624                 compatible = "rockchip,rk33x-dsi";
 625                 rockchip,prop = <0>;
 626                 reg = <0xff960000 0x4000>, <0xff968000 0x4000>;
 627                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 628                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 629                 clocks = <&clk_gates4 14>, <&clk_gates17 3>, <&clk_gates22 10>;
 630                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi_host", "pclk_mipi_dsi_phy";
 631                 status = "okay";
 632         };
 633
 634         lvds: lvds@ff968000 {
 635                 compatible = "rockchip,rk3368-lvds";
 636                 rockchip,grf = <&grf>;
 637                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
 638                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 639                 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
 640                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 641                 status = "disabled";
 642         };
 643
 644         edp: edp@ff970000 {
 645                 compatible = "rockchip,rk32-edp";
 646                 reg = <0x0 0xff970000 0x0 0x4000>;
 647                 rockchip,grf = <&grf>;
 648                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 649                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 650                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 651                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 652                 reset-names = "edp_24m", "edp_apb";
 653         };
 654
 655         hdmi: hdmi@ff980000 {
 656                 compatible = "rockchip,rk3368-hdmi";
 657                 reg = <0x0 0xff980000 0x0 0x20000>;
 658                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 659                 pinctrl-names = "default", "gpio";
 660                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 661                 pinctrl-1 = <&i2c5_gpio>;
 662                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 663                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 664                 status = "disabled";
 665         };
 666
 667         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 668                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 669                 reg = <0x0 0xff978000 0x0 0x2000>;
 670                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 671                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 672                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 673                 status = "disabled";
 674         };
 675
 676         lcdc: lcdc@ff930000 {
 677                  compatible = "rockchip,rk3368-lcdc";
 678                  rockchip,grf = <&grf>;
 679                  rockchip,pmu = <&pmu_grf>;
 680                  rockchip,prop = <PRMRY>;
 681                  rockchip,pwr18 = <0>;
 682                  rockchip,iommu-enabled = <0>;
 683                  reg = <0x0 0xff930000 0x0 0x10000>;
 684                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 685                 /*pinctrl-names = "default", "gpio";
 686                  *pinctrl-0 = <&lcdc_lcdc>;
 687                  *pinctrl-1 = <&lcdc_gpio>;
 688                  */
 689                  status = "disabled";
 690                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
 691                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
 692         };
 693
 694         adc: adc@ff100000 {
 695                 compatible = "rockchip,saradc";
 696                 reg = <0x0 0xff100000 0x0 0x100>;
 697                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 698                 #io-channel-cells = <1>;
 699                 io-channel-ranges;
 700                 rockchip,adc-vref = <1800>;
 701                 clock-frequency = <1000000>;
 702                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 703                 clock-names = "saradc", "pclk_saradc";
 704                 status = "disabled";
 705         };
 706
 707         rga@ff920000 {
 708                 compatible = "rockchip,rk3368-rga2";
 709                 reg = <0x0 0xff920000 0x0 0x1000>;
 710                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 711                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 712                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 713         };
 714
 715         i2s0: i2s0@ff898000 {
 716                 compatible = "rockchip-i2s";
 717                 reg = <0x0 0xff898000 0x0 0x1000>;
 718                 i2s-id = <0>;
 719                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 720                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 721                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 722                 dmas = <&pdma0 0>, <&pdma0 1>;
 723                 #dma-cells = <2>;
 724                 dma-names = "tx", "rx";
 725                 pinctrl-names = "default", "sleep";
 726                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 727                 pinctrl-1 = <&i2s_gpio>;
 728         };
 729
 730         i2s1: i2s1@ff890000 {
 731                 compatible = "rockchip-i2s";
 732                 reg = <0x0 0xff890000 0x0 0x1000>;
 733                 i2s-id = <1>;
 734                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 735                 clock-names = "i2s_clk", "i2s_hclk";
 736                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 737                 dmas = <&pdma0 6>, <&pdma0 7>;
 738                 #dma-cells = <2>;
 739                 dma-names = "tx", "rx";
 740         };
 741
 742         spdif: spdif@ff880000 {
 743                 compatible = "rockchip-spdif";
 744                 reg = <0x0 0xff880000 0x0 0x1000>;
 745                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 746                 clock-names = "spdif_mclk", "spdif_hclk";
 747                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 748                 dmas = <&pdma0 3>;
 749                 #dma-cells = <1>;
 750                 dma-names = "tx";
 751                 pinctrl-names = "default";
 752                 pinctrl-0 = <&spdif_tx>;
 753         };
 754
 755         pwm0: pwm@ff680000 {
 756                 compatible = "rockchip,rk-pwm";
 757                 reg = <0x0 0xff680000 0x0 0x10>;
 758                 #pwm-cells = <2>;
 759                 pinctrl-names = "default";
 760                 pinctrl-0 = <&pwm0_pin>;
 761                 clocks = <&clk_gates13 6>;
 762                 clock-names = "pclk_pwm";
 763                 status = "disabled";
 764         };
 765
 766         pwm1: pwm@ff680010 {
 767                 compatible = "rockchip,rk-pwm";
 768                 reg = <0x0 0xff680010 0x0 0x10>;
 769                 #pwm-cells = <2>;
 770                 pinctrl-names = "default";
 771                 pinctrl-0 = <&pwm1_pin>;
 772                 clocks = <&clk_gates13 6>;
 773                 clock-names = "pclk_pwm";
 774                 status = "disabled";
 775         };
 776
 777         pwm2: pwm@ff680020 {
 778                 compatible = "rockchip,rk-pwm";
 779                 reg = <0x0 0xff680020 0x0 0x10>;
 780                 #pwm-cells = <2>;
 781                 //pinctrl-names = "default";
 782                 //pinctrl-0 = <&pwm1_pin>;
 783                 clocks = <&clk_gates13 6>;
 784                 clock-names = "pclk_pwm";
 785                 status = "disabled";
 786         };
 787
 788         pwm3: pwm@ff680030 {
 789                 compatible = "rockchip,rk-pwm";
 790                 reg = <0x0 0xff680030 0x0 0x10>;
 791                 #pwm-cells = <2>;
 792                 pinctrl-names = "default";
 793                 pinctrl-0 = <&pwm3_pin>;
 794                 clocks = <&clk_gates13 6>;
 795                 clock-names = "pclk_pwm";
 796                 status = "disabled";
 797         };
 798
 799         voppwm: pwm@ff9301a0 {
 800                 compatible = "rockchip,vop-pwm";
 801                 reg = <0x0 0xff9301a0 0x0 0x10>;
 802                 #pwm-cells = <2>;
 803                 pinctrl-names = "default";
 804                 pinctrl-0 = <&vop_pwm_pin>;
 805                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
 806                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 807                 status = "disabled";
 808         };
 809
 810         dvfs {
 811
 812                 vd_arm: vd_arm {
 813                         regulator_name = "vdd_arm";
 814                         suspend_volt = <1000>; //mV
 815                         pd_core {
 816                                 clk_core_dvfs_table: clk_core {
 817                                         operating-points = <
 818                                                 /* KHz    uV */
 819                                                 312000 1100000
 820                                                 504000 1100000
 821                                                 816000 1100000
 822                                                 1008000 1100000
 823                                                 >;
 824                                         channel = <0>;
 825                                         temp-limit-enable = <0>;
 826                                         target-temp = <80>;
 827                                         normal-temp-limit = <
 828                                         /*delta-temp    delta-freq*/
 829                                                 3       96000
 830                                                 6       144000
 831                                                 9       192000
 832                                                 15      384000
 833                                                 >;
 834                                         performance-temp-limit = <
 835                                                 /*temp    freq*/
 836                                                 100     816000
 837                                                 >;
 838                                         status = "okay";
 839                                         regu-mode-table = <
 840                                                 /*freq     mode*/
 841                                                 1008000    4
 842                                                 0          3
 843                                         >;
 844                                         regu-mode-en = <0>;
 845                                 };
 846                         };
 847                 };
 848
 849                 vd_logic: vd_logic {
 850                         regulator_name = "vdd_logic";
 851                         suspend_volt = <1000>; //mV
 852                         pd_ddr {
 853                                 clk_ddr_dvfs_table: clk_ddr {
 854                                         operating-points = <
 855                                                 /* KHz    uV */
 856                                                 200000 1200000
 857                                                 300000 1200000
 858                                                 400000 1200000
 859                                                 >;
 860                                         channel = <2>;
 861                                         status = "disabled";
 862                                 };
 863                         };
 864
 865                         pd_vio {
 866                                 aclk_vio1_dvfs_table: aclk_vio1 {
 867                                         operating-points = <
 868                                                 /* KHz    uV */
 869                                                 100000 1100000
 870                                                 500000 1100000
 871                                                 >;
 872                                         status = "okay";
 873                                 };
 874                         };
 875                 };
 876
 877                 vd_gpu: vd_gpu {
 878                         regulator_name = "vdd_gpu";
 879                         suspend_volt = <1000>; //mV
 880                         pd_gpu {
 881                                 clk_gpu_dvfs_table: clk_gpu {
 882                                         operating-points = <
 883                                                 /* KHz    uV */
 884                                                 200000 1200000
 885                                                 300000 1200000
 886                                                 400000 1200000
 887                                                 >;
 888                                         channel = <1>;
 889                                         status = "okay";
 890                                         regu-mode-table = <
 891                                                 /*freq     mode*/
 892                                                 200000     4
 893                                                 0          3
 894                                         >;
 895                                         regu-mode-en = <0>;
 896                                 };
 897                         };
 898                 };
 899         };
 900
 901         ion {
 902                 compatible = "rockchip,ion";
 903                 #address-cells = <1>;
 904                 #size-cells = <0>;
 905
 906                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
 907                         compatible = "rockchip,ion-heap";
 908                         rockchip,ion_heap = <1>;
 909                         reg = <0x0 0x00000000 0x0 0x08000000>; /* 512MB */
 910                 };
 911                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
 912                         compatible = "rockchip,ion-heap";
 913                         rockchip,ion_heap = <3>;
 914                 };
 915         };
 916
 917         vpu: vpu_service@ff9a0000 {
 918                 compatible = "vpu_service";
 919                 iommu_enabled = <0>;
 920                 reg = <0x0 0xff9a0000 0x0 0x800>;
 921                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 922                 interrupt-names = "irq_enc", "irq_dec";
 923                 /*
 924                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 925                 clock-names = "aclk_vcodec", "hclk_vcodec";
 926                 */
 927                 name = "vpu_service";
 928                 /* status = "disabled"; */
 929         };
 930
 931         iep: iep@ff900000 {
 932                 compatible = "rockchip,iep";
 933                 iommu_enabled = <0>;
 934                 reg = <0x0 0xff900000 0x0 0x800>;
 935                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 936                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
 937                 clock-names = "aclk_iep", "hclk_iep";
 938                 status = "okay";
 939         };
 940
 941         gmac: eth@ff290000 {
 942                 compatible = "rockchip,rk3368-gmac";
 943                 reg = <0x0 0xff290000 0x0 0x10000>;
 944                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
 945                 interrupt-names = "macirq";
 946
 947                 clocks = <&clk_mac>, <&clk_gates5 0>,
 948                          <&clk_gates5 1>, <&clk_gates5 2>,
 949                          <&clk_gates5 3>, <&clk_gates8 0>,
 950                          <&clk_gates8 1>;
 951                 clock-names = "clk_mac", "mac_clk_rx",
 952                               "mac_clk_tx", "clk_mac_ref",
 953                               "clk_mac_refout", "aclk_mac",
 954                               "pclk_mac";
 955
 956                 phy-mode = "rgmii";
 957                 pinctrl-names = "default";
 958                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
 959         };
 960
 961         gpu {
 962                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
 963                 reg = <0x0 0xffa30000 0x0 0x10000>;
 964                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 965                 interrupt-names = "GPU";
 966         };
 967
 968         iep_mmu {
 969                 dbgname = "iep";
 970                 compatible = "rockchip,iep_mmu";
 971                 reg = <0x0 0xff900800 0x0 0x100>;
 972                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 973                 interrupt-names = "iep_mmu";
 974         };
 975
 976         vip_mmu {
 977                 dbgname = "vip";
 978                 compatible = "rockchip,vip_mmu";
 979                 reg = <0x0 0xff950800 0x0 0x100>;
 980                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 981                 interrupt-names = "vip_mmu";
 982         };
 983
 984         vop_mmu {
 985                 dbgname = "vop";
 986                 compatible = "rockchip,vop_mmu";
 987                 reg = <0x0 0xff930300 0x0 0x100>;
 988                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 989                 interrupt-names = "vop_mmu";
 990         };
 991
 992         isp_mmu {
 993                 dbgname = "isp_mmu";
 994                 compatible = "rockchip,isp_mmu";
 995                 reg = <0x0 0xff914000 0x0 0x100>,
 996                 <0x0 0xff915000 0x0 0x100>;
 997                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 998                 interrupt-names = "isp_mmu";
 999         };
1000
1001         hdcp_mmu {
1002                 dbgname = "hdcp_mmu";
1003                 compatible = "rockchip,hdcp_mmu";
1004                 reg = <0x0 0xff940000 0x0 0x100>;
1005                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1006                 interrupt-names = "hdcp_mmu";
1007         };
1008
1009         hevc_mmu {
1010                 dbgname = "hevc";
1011                 compatible = "rockchip,hevc_mmu";
1012                 reg = <0x0 0xff9c0440 0x0 0x40>,                      /*need to fix*/
1013                           <0x0 0xff9c0480 0x0 0x40>;
1014                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1015                 interrupt-names = "hevc_mmu";
1016         };
1017
1018         vpu_mmu {
1019                 dbgname = "vpu";
1020                 compatible = "rockchip,vpu_mmu";
1021                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1022                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;       /*need to fix*/
1023                 interrupt-names = "vpu_mmu";
1024         };
1025
1026         rockchip_suspend {
1027                 rockchip,ctrbits = <
1028                         (0
1029                          |RKPM_CTR_PWR_DMNS
1030                          |RKPM_CTR_GTCLKS
1031                          |RKPM_CTR_PLLS
1032                          |RKPM_CTR_GPIOS
1033                         /*
1034                          |RKPM_CTR_SYSCLK_DIV
1035                          |RKPM_CTR_IDLEAUTO_MD
1036                          |RKPM_CTR_ARMOFF_LPMD
1037                         */
1038                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1039                         )
1040                         >;
1041                 rockchip,pmic-suspend_gpios = <
1042                                  /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1043                         >;
1044                 rockchip,pmic-resume_gpios = <
1045                                 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1046                         >;
1047         };
1048
1049         isp: isp@ff910000{
1050                 compatible = "rockchip,isp";
1051                 reg = <0x0 0xff910000 0x0 0x10000>;
1052                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1053                 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1054                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1055                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1056                 pinctrl-0 = <&cif_clkout>;
1057                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1058                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1059                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1060                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1061                 pinctrl-5 = <&cif_clkout>;
1062                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1063                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1064                 pinctrl-8 = <&isp_flash_trigger>;
1065                 rockchip,isp,mipiphy = <2>;
1066                 rockchip,isp,cifphy = <1>;
1067                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1068                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1069                 rockchip,isp,iommu_enable = <1>;
1070                 status = "okay";
1071         };
1072
1073         tsadc: tsadc@ff280000 {
1074                 compatible = "rockchip,tsadc";
1075                 reg = <0x0 0xff280000 0x0 0x100>;
1076                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1077                 #io-channel-cells = <1>;
1078                 io-channel-ranges;
1079                 clock-frequency = <10000>;
1080                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1081                 clock-names = "tsadc", "pclk_tsadc";
1082                 pinctrl-names = "default", "tsadc_int";
1083                 pinctrl-0 = <&tsadc_gpio>;
1084                 pinctrl-1 = <&tsadc_int>;
1085                 tsadc-ht-temp = <120>;
1086                 tsadc-ht-reset-cru = <1>;
1087                 tsadc-ht-pull-gpio = <0>;
1088                 status = "disabled";
1089         };
1090
1091         tsp: tsp@FF8B0000 {
1092                 compatible = "rockchip,rk3368-tsp";
1093                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1094                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1095                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1096                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1097                 interrupt-names = "irq_tsp";
1098                 // pinctrl-names = "default";
1099                 // pinctrl-0 = <&isp_hsadc>;
1100                 status = "okay";
1101         };
1102
1103         crypto: crypto@FF8A0000{
1104                 compatible = "rockchip,rk3368-crypto";
1105                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1106                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1107                 interrupt-names = "irq_crypto";
1108                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1109                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1110                 status = "okay";
1111         };
1112
1113         pinctrl: pinctrl {
1114                 compatible = "rockchip,rk3368-pinctrl";
1115                 rockchip,grf = <&grf>;
1116                 rockchip,pmu = <&pmu_grf>;
1117                 #address-cells = <2>;
1118                 #size-cells = <2>;
1119                 ranges;
1120
1121                 gpio0: gpio0@ff750000 {
1122                         compatible = "rockchip,gpio-bank";
1123                         reg =   <0x0 0xff750000 0x0 0x100>;
1124                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1125                         clocks = <&clk_gates23 4>;
1126
1127                         gpio-controller;
1128                         #gpio-cells = <2>;
1129
1130                         interrupt-controller;
1131                         #interrupt-cells = <2>;
1132                 };
1133
1134                 gpio1: gpio1@ff780000 {
1135                         compatible = "rockchip,gpio-bank";
1136                         reg = <0x0 0xff780000 0x0 0x100>;
1137                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1138                         clocks = <&clk_gates22 1>;
1139
1140                         gpio-controller;
1141                         #gpio-cells = <2>;
1142
1143                         interrupt-controller;
1144                         #interrupt-cells = <2>;
1145                 };
1146
1147                 gpio2: gpio2@ff790000 {
1148                         compatible = "rockchip,gpio-bank";
1149                         reg = <0x0 0xff790000 0x0 0x100>;
1150                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1151                         clocks = <&clk_gates22 2>;
1152
1153                         gpio-controller;
1154                         #gpio-cells = <2>;
1155
1156                         interrupt-controller;
1157                         #interrupt-cells = <2>;
1158                 };
1159
1160                 gpio3: gpio3@ff7a0000 {
1161                         compatible = "rockchip,gpio-bank";
1162                         reg = <0x0 0xff7a0000 0x0 0x100>;
1163                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1164                         clocks = <&clk_gates22 3>;
1165
1166                         gpio-controller;
1167                         #gpio-cells = <2>;
1168
1169                         interrupt-controller;
1170                         #interrupt-cells = <2>;
1171                 };
1172
1173                 pcfg_pull_up: pcfg-pull-up {
1174                         bias-pull-up;
1175                 };
1176
1177                 pcfg_pull_down: pcfg-pull-down {
1178                         bias-pull-down;
1179                 };
1180
1181                 pcfg_pull_none: pcfg-pull-none {
1182                         bias-disable;
1183                 };
1184
1185                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1186                         drive-strength = <8>;
1187                 };
1188
1189                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1190                         bias-pull-up;
1191                         drive-strength = <8>;
1192                 };
1193
1194                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1195                         drive-strength = <4>;
1196                 };
1197
1198                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1199                         bias-pull-up;
1200                         drive-strength = <4>;
1201                 };
1202
1203                 pcfg_output_high: pcfg-output-high {
1204                         output-high;
1205                 };
1206
1207                 pcfg_output_low: pcfg-output-low {
1208                         output-low;
1209                 };
1210
1211                 i2c0 {
1212                         i2c0_xfer: i2c0-xfer {
1213                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1214                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1215                         };
1216                         i2c0_gpio: i2c0-gpio {
1217                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1218                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1219                         };
1220                 };
1221
1222                 i2c1 {
1223                         i2c1_xfer: i2c1-xfer {
1224                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1225                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1226                         };
1227                         i2c1_gpio: i2c1-gpio {
1228                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1229                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1230                         };
1231                 };
1232
1233                 i2c2 {
1234                         i2c2_xfer: i2c2-xfer {
1235                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1236                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1237                         };
1238                         i2c2_gpio: i2c2-gpio {
1239                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1240                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1241             };
1242                 };
1243
1244                 i2c3 {
1245                         i2c3_xfer: i2c3-xfer {
1246                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1247                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1248                         };
1249                         i2c3_gpio: i2c3-gpio {
1250                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1251                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1252                         };
1253                 };
1254
1255                 i2c4 {
1256                         i2c4_xfer: i2c4-xfer {
1257                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1258                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1259                         };
1260                         i2c4_gpio: i2c4-gpio {
1261                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1262                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1263                         };
1264                 };
1265
1266                 i2c5 {
1267                         i2c5_xfer: i2c5-xfer {
1268                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1269                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1270                         };
1271                         i2c5_gpio: i2c5-gpio {
1272                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1273                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1274                         };
1275                 };
1276
1277                 uart0 {
1278                         uart0_xfer: uart0-xfer {
1279                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1280                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1281                         };
1282
1283                         uart0_cts: uart0-cts {
1284                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1285                         };
1286
1287                         uart0_rts: uart0-rts {
1288                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1289                         };
1290
1291                         uart0_rts_gpio: uart0-rts-gpio {
1292                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1293                         };
1294                 };
1295
1296                 uart1 {
1297                         uart1_xfer: uart1-xfer {
1298                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1299                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1300                         };
1301
1302                         uart1_cts: uart1-cts {
1303                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1304                         };
1305
1306                         uart1_rts: uart1-rts {
1307                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1308                         };
1309                 };
1310
1311                 uart2 {
1312                         uart2_xfer: uart2-xfer {
1313                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1314                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1315                         };
1316                 };
1317
1318                 uart3 {
1319                         uart3_xfer: uart3-xfer {
1320                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1321                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1322                         };
1323
1324                         uart3_cts: uart3-cts {
1325                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1326                         };
1327
1328                         uart3_rts: uart3-rts {
1329                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1330                         };
1331                 };
1332
1333                 uart4 {
1334                         uart4_xfer: uart4-xfer {
1335                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1336                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1337                         };
1338
1339                         uart4_cts: uart4-cts {
1340                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1341                         };
1342
1343                         uart4_rts: uart4-rts {
1344                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1345                         };
1346                 };
1347
1348                 spi0 {
1349                         spi0_clk: spi0-clk {
1350                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1351                         };
1352                         spi0_cs0: spi0-cs0 {
1353                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1354                         };
1355                         spi0_tx: spi0-tx {
1356                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1357                         };
1358                         spi0_rx: spi0-rx {
1359                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1360                         };
1361                         spi0_cs1: spi0-cs1 {
1362                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1363                         };
1364                 };
1365
1366                 spi1 {
1367                         spi1_clk: spi1-clk {
1368                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1369                         };
1370                         spi1_cs0: spi1-cs0 {
1371                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1372                         };
1373                         spi1_rx: spi1-rx {
1374                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1375                         };
1376                         spi1_tx: spi1-tx {
1377                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1378                         };
1379                 };
1380
1381                 spi2 {
1382                         spi2_clk: spi2-clk {
1383                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1384                         };
1385                         spi2_cs0: spi2-cs0 {
1386                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1387                         };
1388                         spi2_rx: spi2-rx {
1389                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1390                         };
1391                         spi2_tx: spi2-tx {
1392                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1393                         };
1394                 };
1395
1396                 i2s {
1397                         i2s_mclk: i2s-mclk {
1398                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1399                         };
1400
1401                         i2s_sclk:i2s-sclk {
1402                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1403                         };
1404
1405                         i2s_lrckrx:i2s-lrckrx {
1406                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1407                         };
1408
1409                         i2s_lrcktx:i2s-lrcktx {
1410                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1411                         };
1412
1413                         i2s_sdi:i2s-sdi {
1414                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1415                         };
1416
1417                         i2s_sdo0:i2s-sdo0 {
1418                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1419                         };
1420
1421                         i2s_sdo1:i2s-sdo1 {
1422                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1423                         };
1424
1425                         i2s_sdo2:i2s-sdo2 {
1426                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1427                         };
1428
1429                         i2s_sdo3:i2s-sdo3 {
1430                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1431                         };
1432
1433                         i2s_gpio: i2s-gpio {
1434                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1435                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1436                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1437                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1438                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1439                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1440                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1441                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1442                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1443                         };
1444                 };
1445
1446                 spdif {
1447                         spdif_tx: spdif-tx {
1448                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1449                         };
1450                 };
1451
1452                 sdmmc {
1453                         sdmmc_clk: sdmmc-clk {
1454                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1455                         };
1456
1457                         sdmmc_cmd: sdmmc-cmd {
1458                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1459                         };
1460
1461                         sdmmc_dectn: sdmmc-dectn {
1462                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1463                         };
1464
1465                         sdmmc_bus1: sdmmc-bus1 {
1466                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1467                         };
1468
1469                         sdmmc_bus4: sdmmc-bus4 {
1470                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1471                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1472                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1473                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1474                         };
1475
1476                         sdmmc_gpio: sdmmc-gpio {
1477                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1478                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1479                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1480                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1481                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1482                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1483                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1484                         };
1485                 };
1486
1487                 sdio0 {
1488                         sdio0_bus1: sdio0-bus1 {
1489                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1490                         };
1491
1492                         sdio0_bus4: sdio0-bus4 {
1493                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1494                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1495                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1496                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1497                         };
1498
1499                         sdio0_cmd: sdio0-cmd {
1500                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1501                         };
1502
1503                         sdio0_clk: sdio0-clk {
1504                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1505                         };
1506
1507                         sdio0_dectn: sdio0-dectn {
1508                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1509                         };
1510
1511                         sdio0_wrprt: sdio0-wrprt {
1512                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1513                         };
1514
1515                         sdio0_pwren: sdio0-pwren {
1516                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1517                         };
1518
1519                         sdio0_bkpwr: sdio0-bkpwr {
1520                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1521                         };
1522
1523                         sdio0_int: sdio0-int {
1524                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1525                         };
1526
1527                         sdio0_gpio: sdio0-gpio {
1528                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1529                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1530                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1531                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1532                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1533                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1534                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1535                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1536                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1537                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1538                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1539                         };
1540                 };
1541
1542                 emmc {
1543                         emmc_clk: emmc-clk {
1544                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1545                         };
1546
1547                         emmc_cmd: emmc-cmd {
1548                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1549                         };
1550
1551                         emmc_pwren: emmc-pwren {
1552                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1553                         };
1554
1555                         emmc_rstnout: emmc_rstnout {
1556                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1557                         };
1558
1559                         emmc_bus1: emmc-bus1 {
1560                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1561                         };
1562
1563                         emmc_bus4: emmc-bus4 {
1564                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1565                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1566                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1567                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1568                         };
1569                 };
1570
1571                 pwm0 {
1572                         pwm0_pin: pwm0-pin {
1573                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1574                         };
1575
1576                         vop_pwm_pin:vop-pwm {
1577                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1578                         };
1579                 };
1580
1581                 pwm1 {
1582                         pwm1_pin: pwm1-pin {
1583                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1584                         };
1585                 };
1586
1587                 pwm3 {
1588                         pwm3_pin: pwm3-pin {
1589                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1590                         };
1591                 };
1592
1593                 lcdc {
1594                         lcdc_lcdc: lcdc-lcdc {
1595                                 rockchip,pins =
1596                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1597                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1598                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1599                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1600                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1601                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1602                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1603                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1604                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1605                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1606                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1607                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1608                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1609                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1610                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1611                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1612                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1613                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1614                         };
1615
1616                         lcdc_gpio: lcdc-gpio {
1617                                 rockchip,pins =
1618                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1619                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1620                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1621                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1622                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1623                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1624                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1625                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1626                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1627                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1628                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1629                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1630                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1631                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1632                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1633                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1634                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1635                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1636                         };
1637                 };
1638
1639                 isp {
1640                         cif_clkout: cif-clkout {
1641                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1642                         };
1643
1644                         isp_dvp_d2d9: isp-dvp-d2d9 {
1645                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1646                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1647                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1648                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1649                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1650                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1651                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1652                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1653                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1654                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1655                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1656                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1657                         };
1658
1659                         isp_dvp_d0d1: isp-dvp-d0d1 {
1660                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1661                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1662                         };
1663
1664                         isp_dvp_d10d11:isp_d10d11       {
1665                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1666                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1667                         };
1668
1669                         isp_dvp_d0d7: isp-dvp-d0d7 {
1670                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1671                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1672                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1673                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1674                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1675                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1676                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1677                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1678                         };
1679
1680                         isp_shutter: isp-shutter {
1681                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1682                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1683                         };
1684
1685                         isp_flash_trigger: isp-flash-trigger {
1686                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1687                         };
1688
1689                         isp_prelight: isp-prelight {
1690                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1691                         };
1692
1693                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1694                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1695                         };
1696                 };
1697
1698                 gps {
1699                         gps_mag: gps-mag {
1700                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1701                         };
1702
1703                         gps_sig: gps-sig {
1704                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1705
1706                         };
1707
1708                         gps_rfclk: gps-rfclk {
1709                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1710                         };
1711                 };
1712
1713                 gmac {
1714                         mac_clk: mac-clk {
1715                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1716                         };
1717
1718                         mac_txpins: mac-txpins {
1719                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//TXD0
1720                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//TXD1
1721                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//TXD2
1722                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//TXD3
1723                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//TXEN
1724                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;//TXCLK
1725                         };
1726
1727                         mac_rxpins: mac-rxpins {
1728                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1729                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1730                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1731                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1732                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1733                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//RXER
1734                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1735                                                 <3 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;//COL
1736                         };
1737
1738                         mac_crs: mac-crs {
1739                                 rockchip,pins = <3 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>; //CRS
1740                         };
1741
1742                         mac_mdpins: mac-mdpins {
1743                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1744                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;//MDC
1745                         };
1746                 };
1747
1748                 tsadc_pin {
1749                         tsadc_int: tsadc-int {
1750                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1751                         };
1752                         tsadc_gpio: tsadc-gpio {
1753                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1754                         };
1755                 };
1756
1757                 hdmi_pin {
1758                         hdmi_cec: hdmi-cec {
1759                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1760                         };
1761                 };
1762
1763                 hdmi_i2c {
1764                         hdmii2c_xfer: hdmii2c-xfer {
1765                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
1766                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1767                         };
1768                 };
1769         };
1770 };