arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 idle-states {
  41                         entry-method = "arm,psci";
  42                         CPU_SLEEP_0: cpu-sleep-0 {
  43                                 compatible = "arm,idle-state";
  44                                 arm,psci-suspend-param = <0x0000000>;
  45                                 entry-latency-us = <10000000>;
  46                                 exit-latency-us = <10000000>;
  47                                 min-residency-us = <25000>;
  48                         };
  49                 };
  50
  51                 little0: cpu@100 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53", "arm,armv8";
  54                         reg = <0x0 0x100>;
  55                         enable-method = "psci";
  56                         cpu-idle-states = <&CPU_SLEEP_0>;
  57                 };
  58                 little1: cpu@101 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x101>;
  62                         enable-method = "psci";
  63                         cpu-idle-states = <&CPU_SLEEP_0>;
  64                 };
  65                 little2: cpu@102 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         reg = <0x0 0x102>;
  69                         enable-method = "psci";
  70                         cpu-idle-states = <&CPU_SLEEP_0>;
  71                 };
  72                 little3: cpu@103 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x103>;
  76                         enable-method = "psci";
  77                         cpu-idle-states = <&CPU_SLEEP_0>;
  78                 };
  79                 big0: cpu@0 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         reg = <0x0 0x0>;
  83                         enable-method = "psci";
  84                         cpu-idle-states = <&CPU_SLEEP_0>;
  85                 };
  86                 big1: cpu@1 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         reg = <0x0 0x1>;
  90                         enable-method = "psci";
  91                         cpu-idle-states = <&CPU_SLEEP_0>;
  92                 };
  93                 big2: cpu@2 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53", "arm,armv8";
  96                         reg = <0x0 0x2>;
  97                         enable-method = "psci";
  98                         cpu-idle-states = <&CPU_SLEEP_0>;
  99                 };
 100                 big3: cpu@3 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53", "arm,armv8";
 103                         reg = <0x0 0x3>;
 104                         enable-method = "psci";
 105                         cpu-idle-states = <&CPU_SLEEP_0>;
 106                 };
 107
 108                 cpu-map {
 109                         cluster0 {
 110                                 core0 {
 111                                         cpu = <&big0>;
 112                                 };
 113                                 core1 {
 114                                         cpu = <&big1>;
 115                                 };
 116                                 core2 {
 117                                         cpu = <&big2>;
 118                                 };
 119                                 core3 {
 120                                         cpu = <&big3>;
 121                                 };
 122                         };
 123                         cluster1 {
 124                                 core0 {
 125                                         cpu = <&little0>;
 126                                 };
 127                                 core1 {
 128                                         cpu = <&little1>;
 129                                 };
 130                                 core2 {
 131                                         cpu = <&little2>;
 132                                 };
 133                                 core3 {
 134                                         cpu = <&little3>;
 135                                 };
 136                         };
 137                 };
 138         };
 139
 140         psci {
 141                 compatible = "arm,psci-0.2";
 142                 method = "smc";
 143         };
 144
 145         gic: interrupt-controller@ffb70000 {
 146                 compatible = "arm,cortex-a15-gic";
 147                 #interrupt-cells = <3>;
 148                 #address-cells = <0>;
 149                 interrupt-controller;
 150                 reg = <0x0 0xffb71000 0 0x1000>,
 151                       <0x0 0xffb72000 0 0x1000>;
 152         };
 153
 154         pmu: syscon@ff730000 {
 155                 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
 156                 reg = <0x0 0xff730000 0x0 0x1000>;
 157         };
 158
 159         pmugrf: syscon@ff738000 {
 160                 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
 161                 reg = <0x0 0xff738000 0x0 0x1000>;
 162         };
 163
 164         sgrf: syscon@ff740000 {
 165                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 166                 reg = <0x0 0xff740000 0x0 0x1000>;
 167
 168         };
 169
 170         cru: syscon@ff760000 {
 171                 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
 172                 reg = <0x0 0xff760000 0x0 0x1000>;
 173         };
 174
 175         grf: syscon@ff770000 {
 176                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 177                 reg = <0x0 0xff770000 0x0 0x1000>;
 178         };
 179
 180         arm-pmu {
 181                 compatible = "arm,armv8-pmuv3";
 182                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 183                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 184                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 185                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 190         };
 191
 192         cpu_axi_bus: cpu_axi_bus {
 193                 compatible = "rockchip,cpu_axi_bus";
 194                 #address-cells = <2>;
 195                 #size-cells = <2>;
 196                 ranges;
 197
 198                 qos {
 199                         #address-cells = <2>;
 200                         #size-cells = <2>;
 201                         ranges;
 202
 203                         dmac {
 204                                 reg = <0x0 0xffa80000 0x0 0x20>;
 205                         };
 206                         crypto {
 207                                 reg = <0x0 0xffa80080 0x0 0x20>;
 208                         };
 209                         tsp {
 210                                 reg = <0x0 0xffa80280 0x0 0x20>;
 211                         };
 212                         bus_cpup {
 213                                 reg = <0x0 0xffa90000 0x0 0x20>;
 214                         };
 215                         cci_r {
 216                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 217                         };
 218                         cci_w {
 219                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 220                         };
 221                         peri {
 222                                 reg = <0x0 0xffab0000 0x0 0x20>;
 223                                 rockchip,priority = <2 2>;
 224                         };
 225                         iep {
 226                                 reg = <0x0 0xffad0000 0x0 0x20>;
 227                         };
 228                         isp_r0 {
 229                                 reg = <0x0 0xffad0080 0x0 0x20>;
 230                         };
 231                         isp_r1 {
 232                                 reg = <0x0 0xffad0100 0x0 0x20>;
 233                         };
 234                         isp_w0 {
 235                                 reg = <0x0 0xffad0180 0x0 0x20>;
 236                                 rockchip,priority = <2 2>;
 237                         };
 238                         isp_w1 {
 239                                 reg = <0x0 0xffad0200 0x0 0x20>;
 240                                 rockchip,priority = <2 2>;
 241                         };
 242                         vip {
 243                                 reg = <0x0 0xffad0280 0x0 0x20>;
 244                         };
 245                         vop {
 246                                 reg = <0x0 0xffad0300 0x0 0x20>;
 247                                 rockchip,priority = <2 2>;
 248                         };
 249                         rga_r {
 250                                 reg = <0x0 0xffad0380 0x0 0x20>;
 251                         };
 252                         rga_w {
 253                                 reg = <0x0 0xffad0400 0x0 0x20>;
 254                         };
 255                         hevc_r {
 256                                 reg = <0x0 0xffae0000 0x0 0x20>;
 257                         };
 258                         vpu_r {
 259                                 reg = <0x0 0xffae0100 0x0 0x20>;
 260                         };
 261                         vpu_w {
 262                                 reg = <0x0 0xffae0180 0x0 0x20>;
 263                         };
 264                         gpu {
 265                                 reg = <0x0 0xffaf0000 0x0 0x20>;
 266                         };
 267                 };
 268
 269                 msch {
 270                         #address-cells = <2>;
 271                         #size-cells = <2>;
 272                         ranges;
 273
 274                         msch {
 275                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 276                                 rockchip,read-latency = <0x34>;
 277                         };
 278                 };
 279         };
 280
 281         timer {
 282                 compatible = "arm,armv8-timer";
 283                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 284                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 285                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 286                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 287                 clock-frequency = <24000000>;
 288         };
 289
 290         timer@ff810000 {
 291                 compatible = "rockchip,timer";
 292                 reg = <0x0 0xff810000 0x0 0x20>;
 293                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 294                 rockchip,broadcast = <1>;
 295         };
 296
 297         sram: sram@ff8c0000 {
 298                 compatible = "mmio-sram";
 299                 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
 300                 map-exec;
 301         };
 302
 303         watchdog: wdt@ff800000 {
 304                 compatible = "rockchip,watch dog";
 305                 reg = <0x0 0xff800000 0x0 0x100>;
 306                 clocks = <&pclk_alive_pre>;
 307                 clock-names = "pclk_wdt";
 308                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 309                 rockchip,irq = <1>;
 310                 rockchip,timeout = <60>;
 311                 rockchip,atboot = <1>;
 312                 rockchip,debug = <0>;
 313                 status = "disabled";
 314         };
 315
 316         amba {
 317                 #address-cells = <2>;
 318                 #size-cells = <2>;
 319                 compatible = "arm,amba-bus";
 320                 interrupt-parent = <&gic>;
 321                 ranges;
 322
 323                 pdma0: pdma@ff600000 {
 324                         compatible = "arm,pl330", "arm,primecell";
 325                         reg = <0x0 0xff600000 0x0 0x4000>;
 326                         clocks = <&clk_gates12 11>;
 327                         clock-names = "apb_pclk";
 328                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 329                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 330                         #dma-cells = <1>;
 331
 332                 };
 333
 334                 pdma1: pdma@ff250000 {
 335                         compatible = "arm,pl330", "arm,primecell";
 336                         reg = <0x0 0xff250000 0x0 0x4000>;
 337                         clocks = <&clk_gates19 3>;
 338                         clock-names = "apb_pclk";
 339                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 340                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 341                         #dma-cells = <1>;
 342                 };
 343         };
 344
 345         reset: reset@ff760300{
 346                 compatible = "rockchip,reset";
 347                 reg = <0x0 0xff760300 0x0 0x38>;
 348                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 349                 #reset-cells = <1>;
 350         };
 351
 352         nandc0: nandc@ff400000 {
 353                 compatible = "rockchip,rk-nandc";
 354                 reg = <0x0 0xff400000 0x0 0x4000>;
 355                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 356                 nandc_id = <0>;
 357                 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
 358                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 359         };
 360
 361         nandc0reg: nandc0@ff400000 {
 362                 compatible = "rockchip,rk-nandc";
 363                 reg = <0x0 0xff400000 0x0 0x4000>;
 364         };
 365
 366         emmc: rksdmmc@ff0f0000 {
 367                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 368                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 369                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 370                 #address-cells = <1>;
 371                 #size-cells = <0>;
 372                 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
 373                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 374                 rockchip,grf = <&grf>;
 375                 num-slots = <1>;
 376                 fifo-depth = <0x100>;
 377                 bus-width = <8>;
 378         };
 379
 380         sdmmc: rksdmmc@ff0c0000 {
 381                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 382                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 383                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 pinctrl-names = "default", "idle", "udbg";
 387                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 388                 pinctrl-1 = <&sdmmc_gpio>;
 389                 pinctrl-2 = <&uart2_xfer &cpu_jtag &sdmmc_dectn>;
 390                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 391                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
 392                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 393                 rockchip,grf = <&grf>;
 394                 num-slots = <1>;
 395                 fifo-depth = <0x100>;
 396                 bus-width = <4>;
 397         };
 398
 399         sdio: rksdmmc@ff0d0000 {
 400                 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
 401                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 402                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 pinctrl-names = "default","idle";
 406                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 407                 pinctrl-1 = <&sdio0_gpio>;
 408                 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
 409                 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
 410                 rockchip,grf = <&grf>;
 411                 num-slots = <1>;
 412                 fifo-depth = <0x100>;
 413                 bus-width = <4>;
 414         };
 415
 416         spi0: spi@ff110000 {
 417                 compatible = "rockchip,rockchip-spi";
 418                 reg = <0x0 0xff110000 0x0 0x1000>;
 419                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422                 pinctrl-names = "default";
 423                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 424                 rockchip,spi-src-clk = <0>;
 425                 num-cs = <2>;
 426                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 427                 clock-names = "spi", "pclk_spi0";
 428                 //dmas = <&pdma1 11>, <&pdma1 12>;
 429                 //#dma-cells = <2>;
 430                 //dma-names = "tx", "rx";
 431                 status = "disabled";
 432         };
 433
 434         spi1: spi@ff120000 {
 435                 compatible = "rockchip,rockchip-spi";
 436                 reg = <0x0 0xff120000 0x0 0x1000>;
 437                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 pinctrl-names = "default";
 441                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 442                 rockchip,spi-src-clk = <1>;
 443                 num-cs = <1>;
 444                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 445                 clock-names = "spi", "pclk_spi1";
 446                 //dmas = <&pdma1 13>, <&pdma1 14>;
 447                 //#dma-cells = <2>;
 448                 //dma-names = "tx", "rx";
 449                 status = "disabled";
 450         };
 451
 452         spi2: spi@ff130000 {
 453                 compatible = "rockchip,rockchip-spi";
 454                 reg = <0x0 0xff130000 0x0 0x1000>;
 455                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 456                 #address-cells = <1>;
 457                 #size-cells = <0>;
 458                 pinctrl-names = "default";
 459                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 460                 rockchip,spi-src-clk = <2>;
 461                 num-cs = <1>;
 462                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 463                 clock-names = "spi", "pclk_spi2";
 464                 //dmas = <&pdma1 15>, <&pdma1 16>;
 465                 //#dma-cells = <2>;
 466                 //dma-names = "tx", "rx";
 467                 status = "disabled";
 468         };
 469
 470         uart_bt: serial@ff180000 {
 471                 compatible = "rockchip,serial";
 472                 reg = <0x0 0xff180000 0x0 0x100>;
 473                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 474                 clock-frequency = <24000000>;
 475                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 476                 clock-names = "sclk_uart", "pclk_uart";
 477                 reg-shift = <2>;
 478                 reg-io-width = <4>;
 479                 //dmas = <&pdma1 1>, <&pdma1 2>;
 480                 //#dma-cells = <2>;
 481                 pinctrl-names = "default";
 482                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 483                 status = "disabled";
 484         };
 485
 486         uart_bb: serial@ff190000 {
 487                 compatible = "rockchip,serial";
 488                 reg = <0x0 0xff190000 0x0 0x100>;
 489                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 490                 clock-frequency = <24000000>;
 491                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 492                 clock-names = "sclk_uart", "pclk_uart";
 493                 reg-shift = <2>;
 494                 reg-io-width = <4>;
 495                 //dmas = <&pdma1 3>, <&pdma1 4>;
 496                 //#dma-cells = <2>;
 497                 pinctrl-names = "default";
 498                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 499                 status = "disabled";
 500         };
 501
 502         uart_dbg: serial@ff690000 {
 503                 compatible = "rockchip,serial";
 504                 reg = <0x0 0xff690000 0x0 0x100>;
 505                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 506                 clock-frequency = <24000000>;
 507                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 508                 clock-names = "sclk_uart", "pclk_uart";
 509                 reg-shift = <2>;
 510                 reg-io-width = <4>;
 511                 //dmas = <&pdma0 4>, <&pdma0 5>;
 512                 //#dma-cells = <2>;
 513                 //pinctrl-names = "default";
 514                 //pinctrl-0 = <&uart2_xfer>;
 515                 status = "disabled";
 516         };
 517
 518         uart_gps: serial@ff1b0000 {
 519                 compatible = "rockchip,serial";
 520                 reg = <0x0 0xff1b0000 0x0 0x100>;
 521                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 522                 clock-frequency = <24000000>;
 523                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 524                 clock-names = "sclk_uart", "pclk_uart";
 525                 current-speed = <115200>;
 526                 reg-shift = <2>;
 527                 reg-io-width = <4>;
 528                 //dmas = <&pdma1 7>, <&pdma1 8>;
 529                 //#dma-cells = <2>;
 530                 pinctrl-names = "default";
 531                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 532                 status = "disabled";
 533         };
 534
 535         uart_exp: serial@ff1c0000 {
 536                 compatible = "rockchip,serial";
 537                 reg = <0x0 0xff1c0000 0x0 0x100>;
 538                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 539                 clock-frequency = <24000000>;
 540                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 541                 clock-names = "sclk_uart", "pclk_uart";
 542                 reg-shift = <2>;
 543                 reg-io-width = <4>;
 544                 //dmas = <&pdma1 9>, <&pdma1 10>;
 545                 //#dma-cells = <2>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 548                 status = "disabled";
 549         };
 550
 551         rockchip_clocks_init: clocks-init{
 552                 compatible = "rockchip,clocks-init";
 553                 rockchip,clocks-init-parent =
 554                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 555                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 556                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 557                         <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
 558                 rockchip,clocks-init-rate =
 559                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 560                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 561                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 562                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 563                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 564                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 565                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 566                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 567                         <&aclk_cci 600000000>,          <&clk_mac 125000000>,
 568                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 569                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 570                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 571                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 572                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 573                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 574                         <&clk_hevc_cabac 300000000>;
 575 /*
 576                 rockchip,clocks-uboot-has-init =
 577                         <&aclk_vio0>;
 578 */
 579         };
 580
 581         rockchip_clocks_enable: clocks-enable {
 582                 compatible = "rockchip,clocks-enable";
 583                 clocks =
 584                 <&pd_vio>,
 585                <&pd_video>,
 586                <&pd_gpu_0>,
 587                <&pd_gpu_1>,
 588
 589                         /*PLL*/
 590                         <&clk_apllb>,
 591                         <&clk_aplll>,
 592                         <&clk_dpll>,
 593                         <&clk_gpll>,
 594                         <&clk_cpll>,
 595
 596                         /*PD_CORE*/
 597                         <&clk_cs>,
 598                         <&clkin_trace>,
 599                         <&aclk_cci>,
 600
 601                         /*PD_BUS*/
 602                         <&aclk_bus>,
 603                         <&hclk_bus>,
 604                         <&pclk_bus>,
 605                         <&clk_gates12 12>,/*aclk_strc_sys*/
 606                         <&clk_gates12 6>,/*aclk_intmem1*/
 607                         <&clk_gates12 5>,/*aclk_intmem0*/
 608                         <&clk_gates12 4>,/*aclk_intmem*/
 609                         <&clk_gates13 9>,/*aclk_gic400*/
 610                         <&clk_gates12 9>,/*hclk_rom*/
 611
 612                         /*PD_ALIVE*/
 613                         <&clk_gates22 13>,/*pclk_timer1*/
 614                         <&clk_gates22 12>,/*pclk_timer0*/
 615                         <&clk_gates22 9>,/*pclk_alive_niu*/
 616                         <&clk_gates22 8>,/*pclk_grf*/
 617
 618                         /*PD_PMU*/
 619                         <&clk_gates23 5>,/*pclk_pmugrf*/
 620                         <&clk_gates23 3>,/*pclk_sgrf*/
 621                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 622                         <&clk_gates23 1>,/*pclk_intmem1*/
 623                         <&clk_gates23 0>,/*pclk_pmu*/
 624
 625                         /*PD_PERI*/
 626                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 627                         <&clk_gates20 8>,/*aclk_peri_niu*/
 628                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 629                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 630                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 631                         <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
 632         };
 633
 634         /* I2C_PMU */
 635         i2c0: i2c@ff650000 {
 636                 compatible = "rockchip,rk30-i2c";
 637                 reg = <0x0 0xff650000 0x0 0x1000>;
 638                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 639                 #address-cells = <1>;
 640                 #size-cells = <0>;
 641                 pinctrl-names = "default", "gpio";
 642                 pinctrl-0 = <&i2c0_xfer>;
 643                 pinctrl-1 = <&i2c0_gpio>;
 644                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 645                 clocks = <&clk_gates12 2>;
 646                 rockchip,check-idle = <1>;
 647                 status = "disabled";
 648         };
 649
 650         /* I2C_AUDIO */
 651         i2c1: i2c@ff660000 {
 652                 compatible = "rockchip,rk30-i2c";
 653                 reg = <0x0 0xff660000 0x0 0x1000>;
 654                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657                 pinctrl-names = "default", "gpio";
 658                 pinctrl-0 = <&i2c1_xfer>;
 659                 pinctrl-1 = <&i2c1_gpio>;
 660                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 661                 clocks = <&clk_gates12 3>;
 662                 rockchip,check-idle = <1>;
 663                 status = "disabled";
 664         };
 665
 666         /* I2C_SENSOR */
 667         i2c2: i2c@ff140000 {
 668                 compatible = "rockchip,rk30-i2c";
 669                 reg = <0x0 0xff140000 0x0 0x1000>;
 670                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 671                 #address-cells = <1>;
 672                 #size-cells = <0>;
 673                 pinctrl-names = "default", "gpio";
 674                 pinctrl-0 = <&i2c2_xfer>;
 675                 pinctrl-1 = <&i2c2_gpio>;
 676                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 677                 clocks = <&clk_gates19 11>;
 678                 rockchip,check-idle = <1>;
 679                 status = "disabled";
 680         };
 681
 682         /* I2C_CAM */
 683         i2c3: i2c@ff150000 {
 684                 compatible = "rockchip,rk30-i2c";
 685                 reg = <0x0 0xff150000 0x0 0x1000>;
 686                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 687                 #address-cells = <1>;
 688                 #size-cells = <0>;
 689                 pinctrl-names = "default", "gpio";
 690                 pinctrl-0 = <&i2c3_xfer>;
 691                 pinctrl-1 = <&i2c3_gpio>;
 692                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 693                 clocks = <&clk_gates19 12>;
 694                 rockchip,check-idle = <1>;
 695                 status = "disabled";
 696         };
 697
 698         /* I2C_TP */
 699         i2c4: i2c@ff160000 {
 700                 compatible = "rockchip,rk30-i2c";
 701                 reg = <0x0 0xff160000 0x0 0x1000>;
 702                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 703                 #address-cells = <1>;
 704                 #size-cells = <0>;
 705                 pinctrl-names = "default", "gpio";
 706                 pinctrl-0 = <&i2c4_xfer>;
 707                 pinctrl-1 = <&i2c4_gpio>;
 708                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 709                 clocks = <&clk_gates19 13>;
 710                 rockchip,check-idle = <1>;
 711                 status = "disabled";
 712         };
 713
 714         /* I2C_HDMI */
 715         i2c5: i2c@ff170000 {
 716                 compatible = "rockchip,rk30-i2c";
 717                 reg = <0x0 0xff170000 0x0 0x1000>;
 718                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 719                 #address-cells = <1>;
 720                 #size-cells = <0>;
 721                 pinctrl-names = "default", "gpio";
 722                 pinctrl-0 = <&i2c5_xfer>;
 723                 pinctrl-1 = <&i2c5_gpio>;
 724                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 725                 clocks = <&clk_gates19 14>;
 726                 rockchip,check-idle = <1>;
 727                 status = "disabled";
 728         };
 729
 730         fb: fb {
 731                 compatible = "rockchip,rk-fb";
 732                 rockchip,disp-mode = <NO_DUAL>;
 733         };
 734
 735
 736         rk_screen: rk_screen {
 737                 compatible = "rockchip,screen";
 738         };
 739
 740         dsihost0: mipi@ff960000{
 741                 compatible = "rockchip,rk3368-dsi";
 742                 rockchip,prop = <0>;
 743                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 744                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 745                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 746                 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>;
 747                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 748                 status = "okay";
 749         };
 750
 751         lvds: lvds@ff968000 {
 752                 compatible = "rockchip,rk3368-lvds";
 753                 rockchip,grf = <&grf>;
 754                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 755                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 756                 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
 757                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 758                 status = "disabled";
 759         };
 760
 761         edp: edp@ff970000 {
 762                 compatible = "rockchip,rk32-edp";
 763                 reg = <0x0 0xff970000 0x0 0x4000>;
 764                 rockchip,grf = <&grf>;
 765                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 766                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 767                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 768                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 769                 reset-names = "edp_24m", "edp_apb";
 770         };
 771
 772         hdmi: hdmi@ff980000 {
 773                 compatible = "rockchip,rk3368-hdmi";
 774                 reg = <0x0 0xff980000 0x0 0x20000>;
 775                 rockchip,grf = <&grf>;
 776                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 777                 pinctrl-names = "default", "gpio";
 778                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 779                 pinctrl-1 = <&i2c5_gpio>;
 780                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 781                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 782                 status = "disabled";
 783         };
 784
 785         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 786                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 787                 reg = <0x0 0xff978000 0x0 0x2000>;
 788                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 789                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 790                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 791                 status = "disabled";
 792         };
 793
 794         lcdc: lcdc@ff930000 {
 795                  compatible = "rockchip,rk3368-lcdc";
 796                  rockchip,grf = <&grf>;
 797                  rockchip,pmugrf = <&pmugrf>;
 798                  rockchip,prop = <PRMRY>;
 799                  rockchip,pwr18 = <0>;
 800                  rockchip,iommu-enabled = <0>;
 801                  reg = <0x0 0xff930000 0x0 0x10000>;
 802                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 803                 /*pinctrl-names = "default", "gpio";
 804                  *pinctrl-0 = <&lcdc_lcdc>;
 805                  *pinctrl-1 = <&lcdc_gpio>;
 806                  */
 807                  status = "disabled";
 808                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
 809                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
 810         };
 811
 812         adc: adc@ff100000 {
 813                 compatible = "rockchip,saradc";
 814                 reg = <0x0 0xff100000 0x0 0x100>;
 815                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 816                 #io-channel-cells = <1>;
 817                 io-channel-ranges;
 818                 rockchip,adc-vref = <1800>;
 819                 clock-frequency = <1000000>;
 820                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 821                 clock-names = "saradc", "pclk_saradc";
 822                 status = "disabled";
 823         };
 824
 825         rga@ff920000 {
 826                 compatible = "rockchip,rk3368-rga2";
 827                 reg = <0x0 0xff920000 0x0 0x1000>;
 828                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 829                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 830                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 831         };
 832
 833         i2s0: i2s0@ff898000 {
 834                 compatible = "rockchip-i2s";
 835                 reg = <0x0 0xff898000 0x0 0x1000>;
 836                 i2s-id = <0>;
 837                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 838                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 839                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 840                 dmas = <&pdma0 0>, <&pdma0 1>;
 841                 #dma-cells = <2>;
 842                 dma-names = "tx", "rx";
 843                 pinctrl-names = "default", "sleep";
 844                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 845                 pinctrl-1 = <&i2s_gpio>;
 846         };
 847
 848         i2s1: i2s1@ff890000 {
 849                 compatible = "rockchip-i2s";
 850                 reg = <0x0 0xff890000 0x0 0x1000>;
 851                 i2s-id = <1>;
 852                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 853                 clock-names = "i2s_clk", "i2s_hclk";
 854                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 855                 dmas = <&pdma0 6>, <&pdma0 7>;
 856                 #dma-cells = <2>;
 857                 dma-names = "tx", "rx";
 858         };
 859
 860         spdif: spdif@ff880000 {
 861                 compatible = "rockchip-spdif";
 862                 reg = <0x0 0xff880000 0x0 0x1000>;
 863                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 864                 clock-names = "spdif_mclk", "spdif_hclk";
 865                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 866                 dmas = <&pdma0 3>;
 867                 #dma-cells = <1>;
 868                 dma-names = "tx";
 869                 pinctrl-names = "default";
 870                 pinctrl-0 = <&spdif_tx>;
 871         };
 872
 873         pwm0: pwm@ff680000 {
 874                 compatible = "rockchip,rk-pwm";
 875                 reg = <0x0 0xff680000 0x0 0x10>;
 876                 #pwm-cells = <2>;
 877                 pinctrl-names = "default";
 878                 pinctrl-0 = <&pwm0_pin>;
 879                 clocks = <&clk_gates13 6>;
 880                 clock-names = "pclk_pwm";
 881                 status = "disabled";
 882         };
 883
 884         pwm1: pwm@ff680010 {
 885                 compatible = "rockchip,rk-pwm";
 886                 reg = <0x0 0xff680010 0x0 0x10>;
 887                 #pwm-cells = <2>;
 888                 pinctrl-names = "default";
 889                 pinctrl-0 = <&pwm1_pin>;
 890                 clocks = <&clk_gates13 6>;
 891                 clock-names = "pclk_pwm";
 892                 status = "disabled";
 893         };
 894
 895         pwm2: pwm@ff680020 {
 896                 compatible = "rockchip,rk-pwm";
 897                 reg = <0x0 0xff680020 0x0 0x10>;
 898                 #pwm-cells = <2>;
 899                 //pinctrl-names = "default";
 900                 //pinctrl-0 = <&pwm1_pin>;
 901                 clocks = <&clk_gates13 6>;
 902                 clock-names = "pclk_pwm";
 903                 status = "disabled";
 904         };
 905
 906         pwm3: pwm@ff680030 {
 907                 compatible = "rockchip,rk-pwm";
 908                 reg = <0x0 0xff680030 0x0 0x10>;
 909                 #pwm-cells = <2>;
 910                 pinctrl-names = "default";
 911                 pinctrl-0 = <&pwm3_pin>;
 912                 clocks = <&clk_gates13 6>;
 913                 clock-names = "pclk_pwm";
 914                 status = "disabled";
 915         };
 916
 917         remotectl: pwm@ff680030 {
 918                 compatible = "rockchip,remotectl-pwm";
 919                 reg = <0x0 0xff680030 0x0 0x50>;
 920                 #pwm-cells = <2>;
 921                 pinctrl-names = "default";
 922                 pinctrl-0 = <&pwm3_pin>;
 923                 clocks = <&clk_gates13 6>;
 924                 clock-names = "pclk_pwm";
 925                 dmas = <&pdma0 2>;
 926                 #dma-cells = <2>;
 927                 dma-names = "rx";
 928                 remote_pwm_id = <3>;
 929                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 930                 status = "disabled";
 931         };
 932
 933         voppwm: pwm@ff9301a0 {
 934                 compatible = "rockchip,vop-pwm";
 935                 reg = <0x0 0xff9301a0 0x0 0x10>;
 936                 #pwm-cells = <2>;
 937                 pinctrl-names = "default";
 938                 pinctrl-0 = <&vop_pwm_pin>;
 939                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
 940                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 941                 status = "disabled";
 942         };
 943
 944         pvtm {
 945                 compatible = "rockchip,rk3368-pvtm";
 946                 rockchip,grf = <&grf>;
 947                 rockchip,pmugrf = <&pmugrf>;
 948                 rockchip,pvtm-clk-out = <1>;
 949         };
 950
 951         cpufreq {
 952                 compatible = "rockchip,rk3368-cpufreq";
 953                 rockchip,grf = <&grf>;
 954         };
 955
 956         dvfs {
 957
 958                 vd_arm: vd_arm {
 959                         regulator_name = "vdd_arm";
 960                         suspend_volt = <1000>; //mV
 961                         pd_core {
 962                                 clk_core_b_dvfs_table: clk_core_b {
 963                                         operating-points = <
 964                                                 /* KHz    uV */
 965                                                 312000 1200000
 966                                                 504000 1200000
 967                                                 816000 1200000
 968                                                 1008000 1200000
 969                                                 >;
 970                                         status = "okay";
 971                                 };
 972                                 clk_core_l_dvfs_table: clk_core_l {
 973                                         operating-points = <
 974                                                 /* KHz    uV */
 975                                                 312000 1200000
 976                                                 504000 1200000
 977                                                 816000 1200000
 978                                                 1008000 1200000
 979                                                 >;
 980                                         status = "okay";
 981                                 };
 982                         };
 983                 };
 984
 985                 vd_logic: vd_logic {
 986                         regulator_name = "vdd_logic";
 987                         suspend_volt = <1000>; //mV
 988                         pd_ddr {
 989                                 clk_ddr_dvfs_table: clk_ddr {
 990                                         operating-points = <
 991                                                 /* KHz    uV */
 992                                                 200000 1200000
 993                                                 300000 1200000
 994                                                 400000 1200000
 995                                                 >;
 996                                         channel = <2>;
 997                                         status = "disabled";
 998                                 };
 999                         };
1000
1001                         pd_gpu {
1002                                 clk_gpu_dvfs_table: clk_gpu {
1003                                         operating-points = <
1004                                                 /* KHz    uV */
1005                                                 200000 1200000
1006                                                 300000 1200000
1007                                                 400000 1200000
1008                                                 >;
1009                                         channel = <1>;
1010                                         status = "okay";
1011                                         regu-mode-table = <
1012                                                 /*freq     mode*/
1013                                                 200000     4
1014                                                 0          3
1015                                         >;
1016                                         regu-mode-en = <0>;
1017                                 };
1018                         };
1019                 };
1020         };
1021
1022         ion {
1023                 compatible = "rockchip,ion";
1024                 #address-cells = <1>;
1025                 #size-cells = <0>;
1026
1027                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1028                         compatible = "rockchip,ion-heap";
1029                         rockchip,ion_heap = <4>;
1030                         reg = <0x00000000 0x08000000>; /* 512MB */
1031                 };
1032                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1033                         compatible = "rockchip,ion-heap";
1034                         rockchip,ion_heap = <0>;
1035                 };
1036         };
1037
1038         vpu: vpu_service {
1039                 compatible = "rockchip,vpu_sub";
1040                 iommu_enabled = <0>;
1041                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1042                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1043                 interrupt-names = "irq_enc", "irq_dec";
1044                 dev_mode = <0>;
1045                 name = "vpu_service";
1046         };
1047
1048         hevc: hevc_service {
1049                 compatible = "rockchip,hevc_sub";
1050                 iommu_enabled = <0>;
1051                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1052                 interrupt-names = "irq_dec";
1053                 dev_mode = <1>;
1054                 name = "hevc_service";
1055         };
1056
1057         vpu_combo: vpu_combo@ff9a0000 {
1058                 compatible = "rockchip,vpu_combo";
1059                 reg = <0x0 0xff9a0000 0x0 0x800>;
1060                 rockchip,grf = <&grf>;
1061                 subcnt = <2>;
1062                 rockchip,sub = <&vpu>, <&hevc>;
1063                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1064                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1065                 mode_bit = <12>;
1066                 mode_ctrl = <0x418>;
1067                 name = "vpu_combo";
1068                 status = "okay";
1069         };
1070
1071         iep: iep@ff900000 {
1072                 compatible = "rockchip,iep";
1073                 iommu_enabled = <0>;
1074                 reg = <0x0 0xff900000 0x0 0x800>;
1075                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1076                 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1077                 clock-names = "aclk_iep", "hclk_iep";
1078                 status = "okay";
1079         };
1080
1081         gmac: eth@ff290000 {
1082                 compatible = "rockchip,rk3368-gmac";
1083                 reg = <0x0 0xff290000 0x0 0x10000>;
1084                 rockchip,grf = <&grf>;
1085                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1086                 interrupt-names = "macirq";
1087
1088                 clocks = <&clk_mac>, <&clk_gates7 4>,
1089                          <&clk_gates7 5>, <&clk_gates7 6>,
1090                          <&clk_gates7 7>, <&clk_gates20 13>,
1091                          <&clk_gates20 14>;
1092                 clock-names = "clk_mac", "mac_clk_rx",
1093                               "mac_clk_tx", "clk_mac_ref",
1094                               "clk_mac_refout", "aclk_mac",
1095                               "pclk_mac";
1096
1097                 phy-mode = "rgmii";
1098                 pinctrl-names = "default";
1099                 pinctrl-0 = <&rgmii_pins>;
1100         };
1101
1102         gpu {
1103                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1104                 reg = <0x0 0xffa30000 0x0 0x10000>;
1105                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1106                 interrupt-names = "GPU";
1107         };
1108
1109         iep_mmu {
1110                 dbgname = "iep";
1111                 compatible = "rockchip,iep_mmu";
1112                 reg = <0x0 0xff900800 0x0 0x100>;
1113                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1114                 interrupt-names = "iep_mmu";
1115         };
1116
1117         vip_mmu {
1118                 dbgname = "vip";
1119                 compatible = "rockchip,vip_mmu";
1120                 reg = <0x0 0xff950800 0x0 0x100>;
1121                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1122                 interrupt-names = "vip_mmu";
1123         };
1124
1125         vop_mmu {
1126                 dbgname = "vop";
1127                 compatible = "rockchip,vopb_mmu";
1128                 reg = <0x0 0xff930300 0x0 0x100>;
1129                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1130                 interrupt-names = "vop_mmu";
1131         };
1132
1133         isp_mmu {
1134                 dbgname = "isp_mmu";
1135                 compatible = "rockchip,isp_mmu";
1136                 reg = <0x0 0xff914000 0x0 0x100>,
1137                 <0x0 0xff915000 0x0 0x100>;
1138                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1139                 interrupt-names = "isp_mmu";
1140         };
1141
1142         hdcp_mmu {
1143                 dbgname = "hdcp_mmu";
1144                 compatible = "rockchip,hdcp_mmu";
1145                 reg = <0x0 0xff940000 0x0 0x100>;
1146                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1147                 interrupt-names = "hdcp_mmu";
1148         };
1149
1150         hevc_mmu {
1151                 dbgname = "hevc";
1152                 compatible = "rockchip,hevc_mmu";
1153                 reg = <0x0 0xff9c0440 0x0 0x40>,                      /*need to fix*/
1154                           <0x0 0xff9c0480 0x0 0x40>;
1155                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1156                 interrupt-names = "hevc_mmu";
1157         };
1158
1159         vpu_mmu {
1160                 dbgname = "vpu";
1161                 compatible = "rockchip,vpu_mmu";
1162                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1163                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;       /*need to fix*/
1164                 interrupt-names = "vpu_mmu";
1165         };
1166
1167         rockchip_suspend {
1168                 rockchip,ctrbits = <
1169                         (0
1170                          |RKPM_CTR_PWR_DMNS
1171                          |RKPM_CTR_GTCLKS
1172                          |RKPM_CTR_PLLS
1173                          |RKPM_CTR_GPIOS
1174                         /*
1175                          |RKPM_CTR_SYSCLK_DIV
1176                          |RKPM_CTR_IDLEAUTO_MD
1177                          |RKPM_CTR_ARMOFF_LPMD
1178                         */
1179                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1180                         )
1181                         >;
1182                 rockchip,pmic-suspend_gpios = <
1183                                  /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1184                         >;
1185                 rockchip,pmic-resume_gpios = <
1186                                 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1187                         >;
1188         };
1189
1190         isp: isp@ff910000{
1191                 compatible = "rockchip,isp";
1192                 reg = <0x0 0xff910000 0x0 0x10000>;
1193                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1194                 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>,<&clk_gates16 0>;
1195                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "aclk_rga";
1196                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1197                 pinctrl-0 = <&cif_clkout>;
1198                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1199                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1200                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1201                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1202                 pinctrl-5 = <&cif_clkout>;
1203                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1204                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1205                 pinctrl-8 = <&isp_flash_trigger>;
1206                 rockchip,isp,mipiphy = <2>;
1207                 rockchip,isp,cifphy = <1>;
1208                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1209                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1210                 rockchip,grf = <&grf>;
1211                 rockchip,cru = <&cru>;
1212                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1213                 rockchip,isp,iommu_enable = <0>;
1214                 status = "okay";
1215         };
1216
1217         cif: cif@ff950000 {
1218                 compatible = "rockchip,cif";
1219                 reg = <0x0 0xff950000 0x0 0x10000>;
1220                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1221                 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1222                 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1223                 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1224                 pinctrl-names = "cif_pin_all";
1225                 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1226                 rockchip,grf = <&grf>;
1227                 rockchip,cru = <&cru>;
1228                 status = "okay";
1229         };
1230
1231 /*
1232         thermal-zones {
1233                 #include "rk3368-thermal.dtsi"
1234         };
1235 */
1236
1237         tsadc: tsadc@ff280000 {
1238                 compatible = "rockchip,rk3368-tsadc";
1239                 reg = <0x0 0xff280000 0x0 0x100>;
1240                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1241                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1242                 rockchip,grf = <&grf>;
1243                 rockchip,cru = <&cru>;
1244                 rockchip,pmu = <&pmu>;
1245                 clock-names = "tsadc", "apb_pclk";
1246                 clock-frequency = <32000>;
1247                 resets = <&reset RK3368_SRST_TSADC_P>;
1248                 reset-names = "tsadc-apb";
1249                 //pinctrl-names = "default";
1250                 //pinctrl-0 = <&tsadc_int>;
1251                 #thermal-sensor-cells = <1>;
1252                 hw-shut-temp = <120000>;
1253                 status = "disabled";
1254         };
1255
1256         tsp: tsp@FF8B0000 {
1257                 compatible = "rockchip,rk3368-tsp";
1258                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1259                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1260                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1261                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1262                 interrupt-names = "irq_tsp";
1263                 // pinctrl-names = "default";
1264                 // pinctrl-0 = <&isp_hsadc>;
1265                 status = "okay";
1266         };
1267
1268         crypto: crypto@FF8A0000{
1269                 compatible = "rockchip,rk3368-crypto";
1270                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1271                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1272                 interrupt-names = "irq_crypto";
1273                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1274                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1275                 status = "okay";
1276         };
1277
1278         dwc_control_usb: dwc-control-usb {
1279                 compatible = "rockchip,rk3368-dwc-control-usb";
1280                 rockchip,grf = <&grf>;
1281                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1282                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1283                 interrupt-names = "otg_id", "otg_bvalid",
1284                                   "otg_linestate", "host0_linestate";
1285                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1286                 clock-names = "hclk_usb_peri", "usbphy_480m";
1287                 //resets = <&reset RK3128_RST_USBPOR>;
1288                 //reset-names = "usbphy_por";
1289                 usb_bc{
1290                         compatible = "inno,phy";
1291                         regbase = &dwc_control_usb;
1292                         rk_usb,bvalid     = <0x4bc 23 1>;
1293                         rk_usb,iddig      = <0x4bc 26 1>;
1294                         rk_usb,vdmsrcen   = <0x718 12 1>;
1295                         rk_usb,vdpsrcen   = <0x718 11 1>;
1296                         rk_usb,rdmpden    = <0x718 10 1>;
1297                         rk_usb,idpsrcen   = <0x718  9 1>;
1298                         rk_usb,idmsinken  = <0x718  8 1>;
1299                         rk_usb,idpsinken  = <0x718  7 1>;
1300                         rk_usb,dpattach   = <0x4b8 31 1>;
1301                         rk_usb,cpdet      = <0x4b8 30 1>;
1302                         rk_usb,dcpattach  = <0x4b8 29 1>;
1303                 };
1304         };
1305
1306         usb0: usb@ff580000 {
1307                 compatible = "rockchip,rk3368_usb20_otg";
1308                 reg = <0x0 0xff580000 0x0 0x40000>;
1309                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1310                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1311                 clock-names = "clk_usbphy0", "hclk_otg";
1312                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1313                                 <&reset RK3368_SRST_USBOTGC0>;
1314                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1315                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1316                 rockchip,usb-mode = <0>;
1317         };
1318
1319         usb_ehci: usb@ff500000 {
1320                 compatible = "generic-ehci";
1321                 reg = <0x0 0xff500000 0x0 0x20000>;
1322                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1323                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1324                 clock-names = "clk_usbphy0", "hclk_ehci";
1325                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1326                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1327                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1328         };
1329
1330         usb_ohci: usb@ff520000 {
1331                 compatible = "generic-ohci";
1332                 reg = <0x0 0xff520000 0x0 0x20000>;
1333                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1334                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1335                 clock-names =  "clk_usbphy0", "hclk_ohci";
1336         };
1337
1338         usb_hsic: usb@ff5c0000 {
1339                 compatible = "rockchip,rk3288_rk_hsic_host";
1340                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1341                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1342 /*
1343                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1344                          <&hsicphy_12m>, <&usbphy_480m>,
1345                          <&otgphy1_480m>, <&otgphy2_480m>;
1346                 clock-names = "hsicphy_480m", "hclk_hsic",
1347                               "hsicphy_12m", "usbphy_480m",
1348                               "hsic_usbphy1", "hsic_usbphy2";
1349                 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1350                                 <&reset RK3288_SOFT_RST_HSICPHY>;
1351                 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1352 */
1353                 status = "disabled";
1354         };
1355
1356         pinctrl: pinctrl {
1357                 compatible = "rockchip,rk3368-pinctrl";
1358                 rockchip,grf = <&grf>;
1359                 rockchip,pmugrf = <&pmugrf>;
1360                 #address-cells = <2>;
1361                 #size-cells = <2>;
1362                 ranges;
1363
1364                 gpio0: gpio0@ff750000 {
1365                         compatible = "rockchip,gpio-bank";
1366                         reg =   <0x0 0xff750000 0x0 0x100>;
1367                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1368                         clocks = <&clk_gates23 4>;
1369
1370                         gpio-controller;
1371                         #gpio-cells = <2>;
1372
1373                         interrupt-controller;
1374                         #interrupt-cells = <2>;
1375                 };
1376
1377                 gpio1: gpio1@ff780000 {
1378                         compatible = "rockchip,gpio-bank";
1379                         reg = <0x0 0xff780000 0x0 0x100>;
1380                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1381                         clocks = <&clk_gates22 1>;
1382
1383                         gpio-controller;
1384                         #gpio-cells = <2>;
1385
1386                         interrupt-controller;
1387                         #interrupt-cells = <2>;
1388                 };
1389
1390                 gpio2: gpio2@ff790000 {
1391                         compatible = "rockchip,gpio-bank";
1392                         reg = <0x0 0xff790000 0x0 0x100>;
1393                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1394                         clocks = <&clk_gates22 2>;
1395
1396                         gpio-controller;
1397                         #gpio-cells = <2>;
1398
1399                         interrupt-controller;
1400                         #interrupt-cells = <2>;
1401                 };
1402
1403                 gpio3: gpio3@ff7a0000 {
1404                         compatible = "rockchip,gpio-bank";
1405                         reg = <0x0 0xff7a0000 0x0 0x100>;
1406                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1407                         clocks = <&clk_gates22 3>;
1408
1409                         gpio-controller;
1410                         #gpio-cells = <2>;
1411
1412                         interrupt-controller;
1413                         #interrupt-cells = <2>;
1414                 };
1415
1416                 pcfg_pull_up: pcfg-pull-up {
1417                         bias-pull-up;
1418                 };
1419
1420                 pcfg_pull_down: pcfg-pull-down {
1421                         bias-pull-down;
1422                 };
1423
1424                 pcfg_pull_none: pcfg-pull-none {
1425                         bias-disable;
1426                 };
1427
1428                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1429                         drive-strength = <8>;
1430                 };
1431
1432                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1433                         drive-strength = <12>;
1434                 };
1435
1436                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1437                         bias-pull-up;
1438                         drive-strength = <8>;
1439                 };
1440
1441                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1442                         drive-strength = <4>;
1443                 };
1444
1445                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1446                         bias-pull-up;
1447                         drive-strength = <4>;
1448                 };
1449
1450                 pcfg_output_high: pcfg-output-high {
1451                         output-high;
1452                 };
1453
1454                 pcfg_output_low: pcfg-output-low {
1455                         output-low;
1456                 };
1457
1458                 i2c0 {
1459                         i2c0_xfer: i2c0-xfer {
1460                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1461                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1462                         };
1463                         i2c0_gpio: i2c0-gpio {
1464                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1465                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1466                         };
1467                 };
1468
1469                 i2c1 {
1470                         i2c1_xfer: i2c1-xfer {
1471                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1472                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1473                         };
1474                         i2c1_gpio: i2c1-gpio {
1475                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1476                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1477                         };
1478                 };
1479
1480                 i2c2 {
1481                         i2c2_xfer: i2c2-xfer {
1482                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1483                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1484                         };
1485                         i2c2_gpio: i2c2-gpio {
1486                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1487                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1488             };
1489                 };
1490
1491                 i2c3 {
1492                         i2c3_xfer: i2c3-xfer {
1493                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1494                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1495                         };
1496                         i2c3_gpio: i2c3-gpio {
1497                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1498                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1499                         };
1500                 };
1501
1502                 i2c4 {
1503                         i2c4_xfer: i2c4-xfer {
1504                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1505                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1506                         };
1507                         i2c4_gpio: i2c4-gpio {
1508                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1509                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1510                         };
1511                 };
1512
1513                 i2c5 {
1514                         i2c5_xfer: i2c5-xfer {
1515                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1516                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1517                         };
1518                         i2c5_gpio: i2c5-gpio {
1519                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1520                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1521                         };
1522                 };
1523
1524                 uart0 {
1525                         uart0_xfer: uart0-xfer {
1526                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1527                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1528                         };
1529
1530                         uart0_cts: uart0-cts {
1531                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1532                         };
1533
1534                         uart0_rts: uart0-rts {
1535                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1536                         };
1537
1538                         uart0_rts_gpio: uart0-rts-gpio {
1539                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1540                         };
1541                 };
1542
1543                 uart1 {
1544                         uart1_xfer: uart1-xfer {
1545                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1546                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1547                         };
1548
1549                         uart1_cts: uart1-cts {
1550                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1551                         };
1552
1553                         uart1_rts: uart1-rts {
1554                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1555                         };
1556                 };
1557
1558                 uart2 {
1559                         uart2_xfer: uart2-xfer {
1560                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1561                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1562                         };
1563                 };
1564
1565                 uart3 {
1566                         uart3_xfer: uart3-xfer {
1567                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1568                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1569                         };
1570
1571                         uart3_cts: uart3-cts {
1572                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1573                         };
1574
1575                         uart3_rts: uart3-rts {
1576                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1577                         };
1578                 };
1579
1580                 uart4 {
1581                         uart4_xfer: uart4-xfer {
1582                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1583                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1584                         };
1585
1586                         uart4_cts: uart4-cts {
1587                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1588                         };
1589
1590                         uart4_rts: uart4-rts {
1591                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1592                         };
1593                 };
1594
1595                 spi0 {
1596                         spi0_clk: spi0-clk {
1597                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1598                         };
1599                         spi0_cs0: spi0-cs0 {
1600                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1601                         };
1602                         spi0_tx: spi0-tx {
1603                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1604                         };
1605                         spi0_rx: spi0-rx {
1606                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1607                         };
1608                         spi0_cs1: spi0-cs1 {
1609                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1610                         };
1611                 };
1612
1613                 spi1 {
1614                         spi1_clk: spi1-clk {
1615                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1616                         };
1617                         spi1_cs0: spi1-cs0 {
1618                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1619                         };
1620                         spi1_rx: spi1-rx {
1621                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1622                         };
1623                         spi1_tx: spi1-tx {
1624                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1625                         };
1626                 };
1627
1628                 spi2 {
1629                         spi2_clk: spi2-clk {
1630                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1631                         };
1632                         spi2_cs0: spi2-cs0 {
1633                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1634                         };
1635                         spi2_rx: spi2-rx {
1636                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1637                         };
1638                         spi2_tx: spi2-tx {
1639                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1640                         };
1641                 };
1642
1643                 i2s {
1644                         i2s_mclk: i2s-mclk {
1645                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1646                         };
1647
1648                         i2s_sclk:i2s-sclk {
1649                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1650                         };
1651
1652                         i2s_lrckrx:i2s-lrckrx {
1653                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1654                         };
1655
1656                         i2s_lrcktx:i2s-lrcktx {
1657                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1658                         };
1659
1660                         i2s_sdi:i2s-sdi {
1661                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1662                         };
1663
1664                         i2s_sdo0:i2s-sdo0 {
1665                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1666                         };
1667
1668                         i2s_sdo1:i2s-sdo1 {
1669                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1670                         };
1671
1672                         i2s_sdo2:i2s-sdo2 {
1673                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1674                         };
1675
1676                         i2s_sdo3:i2s-sdo3 {
1677                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1678                         };
1679
1680                         i2s_gpio: i2s-gpio {
1681                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1682                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1683                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1684                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1685                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1686                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1687                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1688                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1689                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1690                         };
1691                 };
1692
1693                 spdif {
1694                         spdif_tx: spdif-tx {
1695                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1696                         };
1697                 };
1698
1699                 sdmmc {
1700                         sdmmc_clk: sdmmc-clk {
1701                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1702                         };
1703
1704                         sdmmc_cmd: sdmmc-cmd {
1705                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1706                         };
1707
1708                         sdmmc_dectn: sdmmc-dectn {
1709                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1710                         };
1711
1712                         sdmmc_bus1: sdmmc-bus1 {
1713                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1714                         };
1715
1716                         sdmmc_bus4: sdmmc-bus4 {
1717                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1718                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1719                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1720                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1721                         };
1722
1723                         sdmmc_gpio: sdmmc-gpio {
1724                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1725                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1726                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1727                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1728                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1729                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1730                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1731                         };
1732                 };
1733
1734                 sdio0 {
1735                         sdio0_bus1: sdio0-bus1 {
1736                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1737                         };
1738
1739                         sdio0_bus4: sdio0-bus4 {
1740                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1741                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1742                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1743                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1744                         };
1745
1746                         sdio0_cmd: sdio0-cmd {
1747                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1748                         };
1749
1750                         sdio0_clk: sdio0-clk {
1751                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1752                         };
1753
1754                         sdio0_dectn: sdio0-dectn {
1755                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1756                         };
1757
1758                         sdio0_wrprt: sdio0-wrprt {
1759                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1760                         };
1761
1762                         sdio0_pwren: sdio0-pwren {
1763                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1764                         };
1765
1766                         sdio0_bkpwr: sdio0-bkpwr {
1767                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1768                         };
1769
1770                         sdio0_int: sdio0-int {
1771                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1772                         };
1773
1774                         sdio0_gpio: sdio0-gpio {
1775                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1776                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1777                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1778                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1779                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1780                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1781                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1782                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1783                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1784                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1785                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1786                         };
1787                 };
1788
1789                 emmc {
1790                         emmc_clk: emmc-clk {
1791                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1792                         };
1793
1794                         emmc_cmd: emmc-cmd {
1795                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1796                         };
1797
1798                         emmc_pwren: emmc-pwren {
1799                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1800                         };
1801
1802                         emmc_rstnout: emmc_rstnout {
1803                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1804                         };
1805
1806                         emmc_bus1: emmc-bus1 {
1807                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1808                         };
1809
1810                         emmc_bus4: emmc-bus4 {
1811                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1812                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1813                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1814                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1815                         };
1816                 };
1817
1818                 pwm0 {
1819                         pwm0_pin: pwm0-pin {
1820                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1821                         };
1822
1823                         vop_pwm_pin:vop-pwm {
1824                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1825                         };
1826                 };
1827
1828                 pwm1 {
1829                         pwm1_pin: pwm1-pin {
1830                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1831                         };
1832                 };
1833
1834                 pwm3 {
1835                         pwm3_pin: pwm3-pin {
1836                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1837                         };
1838                 };
1839
1840                 lcdc {
1841                         lcdc_lcdc: lcdc-lcdc {
1842                                 rockchip,pins =
1843                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1844                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1845                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1846                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1847                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1848                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1849                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1850                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1851                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1852                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1853                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1854                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1855                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1856                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1857                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1858                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1859                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1860                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1861                         };
1862
1863                         lcdc_gpio: lcdc-gpio {
1864                                 rockchip,pins =
1865                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1866                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1867                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1868                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1869                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1870                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1871                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1872                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1873                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1874                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1875                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1876                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1877                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1878                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1879                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1880                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1881                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1882                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1883                         };
1884                 };
1885
1886                 isp {
1887                         cif_clkout: cif-clkout {
1888                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1889                         };
1890
1891                         isp_dvp_d2d9: isp-dvp-d2d9 {
1892                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1893                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1894                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1895                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1896                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1897                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1898                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1899                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1900                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1901                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1902                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1903                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1904                         };
1905
1906                         isp_dvp_d0d1: isp-dvp-d0d1 {
1907                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1908                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1909                         };
1910
1911                         isp_dvp_d10d11:isp_d10d11       {
1912                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1913                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1914                         };
1915
1916                         isp_dvp_d0d7: isp-dvp-d0d7 {
1917                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1918                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1919                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1920                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1921                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1922                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1923                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1924                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1925                         };
1926
1927                         isp_shutter: isp-shutter {
1928                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1929                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1930                         };
1931
1932                         isp_flash_trigger: isp-flash-trigger {
1933                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1934                         };
1935
1936                         isp_prelight: isp-prelight {
1937                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1938                         };
1939
1940                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1941                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1942                         };
1943                 };
1944
1945                 gps {
1946                         gps_mag: gps-mag {
1947                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1948                         };
1949
1950                         gps_sig: gps-sig {
1951                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1952
1953                         };
1954
1955                         gps_rfclk: gps-rfclk {
1956                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1957                         };
1958                 };
1959
1960                 gmac {
1961                         rgmii_pins: rgmii-pins {
1962                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1963                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1964                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1965                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1966                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1967                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
1968                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
1969                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
1970                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1971                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1972                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1973                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1974                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1975                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1976                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
1977                         };
1978
1979                         rmii_pins: rmii-pins {
1980                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
1981                                                 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1982                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
1983                                                 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
1984                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
1985                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
1986                                                 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1987                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1988                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1989                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
1990                         };
1991                 };
1992
1993                 tsadc_pin {
1994                         tsadc_int: tsadc-int {
1995                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1996                         };
1997                         tsadc_gpio: tsadc-gpio {
1998                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1999                         };
2000                 };
2001
2002                 hdmi_pin {
2003                         hdmi_cec: hdmi-cec {
2004                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2005                         };
2006                 };
2007
2008                 hdmi_i2c {
2009                         hdmii2c_xfer: hdmii2c-xfer {
2010                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2011                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2012                         };
2013                 };
2014
2015                 cpu_jtag {
2016                         cpu_jtag: cpu-jtag {
2017                                 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2018                                                 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2019                         };
2020                 };
2021         };
2022
2023         reboot {
2024                 compatible = "rockchip,rk3368-reboot";
2025                 rockchip,cru = <&cru>;
2026                 rockchip,pmugrf = <&pmugrf>;
2027         };
2028 };