1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-pm.h>
3 #include <dt-bindings/pinctrl/rockchip.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/sensor-dev.h>
6 #include <dt-bindings/clock/rk_system_status.h>
8 #include "rk3368-clocks.dtsi"
11 compatible = "rockchip,rk3368";
13 rockchip,sram = <&sram>;
14 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a53", "arm,armv8";
44 enable-method = "psci";
48 compatible = "arm,cortex-a53", "arm,armv8";
50 enable-method = "psci";
54 compatible = "arm,cortex-a53", "arm,armv8";
56 enable-method = "psci";
60 compatible = "arm,cortex-a53", "arm,armv8";
62 enable-method = "psci";
66 compatible = "arm,cortex-a53", "arm,armv8";
68 enable-method = "psci";
72 compatible = "arm,cortex-a53", "arm,armv8";
74 enable-method = "psci";
78 compatible = "arm,cortex-a53", "arm,armv8";
80 enable-method = "psci";
84 compatible = "arm,cortex-a53", "arm,armv8";
86 enable-method = "psci";
122 compatible = "arm,psci";
124 cpu_on = <0xC4000003>;
127 gic: interrupt-controller@ffb70000 {
128 compatible = "arm,cortex-a15-gic";
129 #interrupt-cells = <3>;
130 #address-cells = <0>;
131 interrupt-controller;
132 reg = <0x0 0xffb71000 0 0x1000>,
133 <0x0 0xffb72000 0 0x1000>;
136 pmu_grf: syscon@ff738000 {
137 compatible = "rockchip,rk3388-pmu-grf", "syscon";
138 reg = <0x0 0xff738000 0x0 0x100>;
141 sgrf: syscon@ff740000 {
142 compatible = "rockchip,rk3388-sgrf", "syscon";
143 reg = <0x0 0xff740000 0x0 0x1000>;
147 grf: syscon@ff770000 {
148 compatible = "rockchip,rk3388-grf", "syscon";
149 reg = <0x0 0xff770000 0x0 0x1000>;
153 compatible = "arm,armv8-pmuv3";
154 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
164 cpu_axi_bus: cpu_axi_bus {
165 compatible = "rockchip,cpu_axi_bus";
166 #address-cells = <2>;
171 #address-cells = <2>;
176 reg = <0x0 0xffa80000 0x0 0x20>;
179 reg = <0x0 0xffa80080 0x0 0x20>;
182 reg = <0x0 0xffa90000 0x0 0x20>;
185 reg = <0x0 0xffaa0000 0x0 0x20>;
188 reg = <0x0 0xffaa0080 0x0 0x20>;
191 reg = <0x0 0xffab0000 0x0 0x20>;
194 reg = <0x0 0xffad0000 0x0 0x20>;
197 reg = <0x0 0xffad0080 0x0 0x20>;
200 reg = <0x0 0xffad0100 0x0 0x20>;
203 reg = <0x0 0xffad0180 0x0 0x20>;
204 rockchip,priority = <2 2>;
207 reg = <0x0 0xffad0200 0x0 0x20>;
208 rockchip,priority = <2 2>;
211 reg = <0x0 0xffad0280 0x0 0x20>;
214 reg = <0x0 0xffad0300 0x0 0x20>;
215 rockchip,priority = <2 2>;
218 reg = <0x0 0xffad0380 0x0 0x20>;
221 reg = <0x0 0xffad0400 0x0 0x20>;
224 reg = <0x0 0xffae0000 0x0 0x20>;
227 reg = <0x0 0xffae0080 0x0 0x20>;
230 reg = <0x0 0xffae0100 0x0 0x20>;
235 #address-cells = <2>;
240 reg = <0x0 0xffac0000 0x0 0x3c>;
241 rockchip,read-latency = <0x34>;
247 compatible = "arm,armv8-timer";
248 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
249 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
250 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
251 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
252 clock-frequency = <24000000>;
256 compatible = "rockchip,timer";
257 reg = <0x0 0xff810000 0x0 0x20>;
258 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
259 rockchip,broadcast = <1>;
262 sram: sram@ff8c0000 {
263 compatible = "mmio-sram";
264 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
268 watchdog: wdt@ff800000 {
269 compatible = "rockchip,watch dog";
270 reg = <0x0 0xff800000 0x0 0x100>;
271 clocks = <&pclk_alive_pre>;
272 clock-names = "pclk_wdt";
273 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
275 rockchip,timeout = <60>;
276 rockchip,atboot = <1>;
277 rockchip,debug = <0>;
282 #address-cells = <2>;
284 compatible = "arm,amba-bus";
285 interrupt-parent = <&gic>;
288 pdma0: pdma@ff600000 {
289 compatible = "arm,pl330", "arm,primecell";
290 reg = <0x0 0xff600000 0x0 0x4000>;
291 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
296 pdma1: pdma@ff250000 {
297 compatible = "arm,pl330", "arm,primecell";
298 reg = <0x0 0xff250000 0x0 0x4000>;
299 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
305 reset: reset@ff760300{
306 compatible = "rockchip,reset";
307 reg = <0x0 0xff760300 0x0 0x38>;
308 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
312 nandc0: nandc@ff400000 {
313 compatible = "rockchip,rk-nandc";
314 reg = <0x0 0xff400000 0x0 0x4000>;
315 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
318 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
321 nandc0reg: nandc0@ff400000 {
322 compatible = "rockchip,rk-nandc";
323 reg = <0x0 0xff400000 0x0 0x4000>;
326 emmc: rksdmmc@ff0f0000 {
327 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
328 reg = <0x0 0xff0f0000 0x0 0x4000>;
329 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
330 #address-cells = <1>;
332 clocks = <&clk_emmc>, <&clk_gates21 2>;
333 clock-names = "clk_mmc", "hclk_mmc";
335 fifo-depth = <0x100>;
339 sdmmc: rksdmmc@ff0c0000 {
340 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
341 reg = <0x0 0xff0c0000 0x0 0x4000>;
342 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
343 #address-cells = <1>;
345 pinctrl-names = "default", "idle";
346 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
347 pinctrl-1 = <&sdmmc_gpio>;
348 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
349 clocks = <&clk_sdmmc0>, <&clk_gates21 0>;
350 clock-names = "clk_mmc", "hclk_mmc";
352 fifo-depth = <0x100>;
356 sdio: rksdmmc@ff0d0000 {
357 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
358 reg = <0x0 0xff0d0000 0x0 0x4000>;
359 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
360 #address-cells = <1>;
362 pinctrl-names = "default","idle";
363 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
364 pinctrl-1 = <&sdio0_gpio>;
365 clocks = <&clk_sdio0>, <&clk_gates21 1>;
366 clock-names = "clk_mmc", "hclk_mmc";
368 fifo-depth = <0x100>;
373 compatible = "rockchip,rockchip-spi";
374 reg = <0x0 0xff110000 0x0 0x1000>;
375 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
376 #address-cells = <1>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
380 rockchip,spi-src-clk = <0>;
382 clocks =<&clk_spi0>, <&clk_gates19 4>;
383 clock-names = "spi", "pclk_spi0";
384 //dmas = <&pdma1 11>, <&pdma1 12>;
386 //dma-names = "tx", "rx";
391 compatible = "rockchip,rockchip-spi";
392 reg = <0x0 0xff120000 0x0 0x1000>;
393 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
394 #address-cells = <1>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
398 rockchip,spi-src-clk = <1>;
400 clocks = <&clk_spi1>, <&clk_gates19 5>;
401 clock-names = "spi", "pclk_spi1";
402 //dmas = <&pdma1 13>, <&pdma1 14>;
404 //dma-names = "tx", "rx";
409 compatible = "rockchip,rockchip-spi";
410 reg = <0x0 0xff130000 0x0 0x1000>;
411 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
412 #address-cells = <1>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
416 rockchip,spi-src-clk = <2>;
418 clocks = <&clk_spi2>, <&clk_gates19 6>;
419 clock-names = "spi", "pclk_spi2";
420 //dmas = <&pdma1 15>, <&pdma1 16>;
422 //dma-names = "tx", "rx";
426 uart_bt: serial@ff180000 {
427 compatible = "rockchip,serial";
428 reg = <0x0 0xff180000 0x0 0x100>;
429 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
430 clock-frequency = <24000000>;
431 clocks = <&clk_uart0>, <&clk_gates19 7>;
432 clock-names = "sclk_uart", "pclk_uart";
435 //dmas = <&pdma1 1>, <&pdma1 2>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
442 uart_bb: serial@ff190000 {
443 compatible = "rockchip,serial";
444 reg = <0x0 0xff190000 0x0 0x100>;
445 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
446 clock-frequency = <24000000>;
447 clocks = <&clk_uart1>, <&clk_gates19 8>;
448 clock-names = "sclk_uart", "pclk_uart";
451 //dmas = <&pdma1 3>, <&pdma1 4>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
458 uart_dbg: serial@ff690000 {
459 compatible = "rockchip,serial";
460 reg = <0x0 0xff690000 0x0 0x100>;
461 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
462 clock-frequency = <24000000>;
463 clocks = <&clk_uart2>, <&clk_gates13 5>;
464 clock-names = "sclk_uart", "pclk_uart";
467 //dmas = <&pdma0 4>, <&pdma0 5>;
469 //pinctrl-names = "default";
470 //pinctrl-0 = <&uart2_xfer>;
474 uart_gps: serial@ff1b0000 {
475 compatible = "rockchip,serial";
476 reg = <0x0 0xff1b0000 0x0 0x100>;
477 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
478 clock-frequency = <24000000>;
479 clocks = <&clk_uart3>, <&clk_gates19 9>;
480 clock-names = "sclk_uart", "pclk_uart";
481 current-speed = <115200>;
484 //dmas = <&pdma1 7>, <&pdma1 8>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
491 uart_exp: serial@ff1c0000 {
492 compatible = "rockchip,serial";
493 reg = <0x0 0xff1c0000 0x0 0x100>;
494 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
495 clock-frequency = <24000000>;
496 clocks = <&clk_uart4>, <&clk_gates19 10>;
497 clock-names = "sclk_uart", "pclk_uart";
500 //dmas = <&pdma1 9>, <&pdma1 10>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
507 rockchip_clocks_init: clocks-init{
508 compatible = "rockchip,clocks-init";
509 rockchip,clocks-init-parent =
510 <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
511 <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
512 <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
514 rockchip,clocks-init-rate =
515 <&clk_gpll 576000000>, <&clk_core_b 792000000>,
516 <&clk_core_l 600000000>, <&clk_cpll 400000000>,
517 /*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
518 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
519 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
520 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
521 <&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
522 <&clk_cs 300000000>, <&clkin_trace 300000000>,
523 <&aclk_cci 600000000>, <&clk_mac 50000000>,
524 <&aclk_vio0 400000000>, <&hclk_vio 100000000>,
525 <&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
526 <&clk_isp 400000000>, <&clk_edp 200000000>,
527 <&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
528 <&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
529 <&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
530 <&clk_hevc_cabac 300000000>;
532 rockchip,clocks-uboot-has-init =
537 rockchip_clocks_enable: clocks-enable {
538 compatible = "rockchip,clocks-enable";
555 <&clk_gates12 12>,/*aclk_strc_sys*/
556 <&clk_gates12 6>,/*aclk_intmem1*/
557 <&clk_gates12 5>,/*aclk_intmem0*/
558 <&clk_gates12 4>,/*aclk_intmem*/
559 <&clk_gates13 9>,/*aclk_gic400*/
562 <&clk_gates22 13>,/*pclk_timer1*/
563 <&clk_gates22 12>,/*pclk_timer0*/
564 <&clk_gates22 9>,/*pclk_alive_niu*/
565 <&clk_gates22 8>,/*pclk_grf*/
568 <&clk_gates23 5>,/*pclk_pmugrf*/
569 <&clk_gates23 3>,/*pclk_sgrf*/
570 <&clk_gates23 2>,/*pclk_pmu_noc*/
571 <&clk_gates23 1>,/*pclk_intmem1*/
572 <&clk_gates23 0>,/*pclk_pmu*/
575 <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
576 <&clk_gates20 8>,/*aclk_peri_niu*/
577 <&clk_gates21 4>,/*aclk_peri_mmu*/
578 <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
579 <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
580 <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
585 compatible = "rockchip,rk30-i2c";
586 reg = <0x0 0xff650000 0x0 0x1000>;
587 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
588 #address-cells = <1>;
590 pinctrl-names = "default", "gpio";
591 pinctrl-0 = <&i2c0_xfer>;
592 pinctrl-1 = <&i2c0_gpio>;
593 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
594 clocks = <&clk_gates12 2>;
595 rockchip,check-idle = <1>;
601 compatible = "rockchip,rk30-i2c";
602 reg = <0x0 0xff660000 0x0 0x1000>;
603 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
604 #address-cells = <1>;
606 pinctrl-names = "default", "gpio";
607 pinctrl-0 = <&i2c1_xfer>;
608 pinctrl-1 = <&i2c1_gpio>;
609 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
610 clocks = <&clk_gates12 3>;
611 rockchip,check-idle = <1>;
617 compatible = "rockchip,rk30-i2c";
618 reg = <0x0 0xff140000 0x0 0x1000>;
619 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
620 #address-cells = <1>;
622 pinctrl-names = "default", "gpio";
623 pinctrl-0 = <&i2c2_xfer>;
624 pinctrl-1 = <&i2c2_gpio>;
625 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
626 clocks = <&clk_gates19 11>;
627 rockchip,check-idle = <1>;
633 compatible = "rockchip,rk30-i2c";
634 reg = <0x0 0xff150000 0x0 0x1000>;
635 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
636 #address-cells = <1>;
638 pinctrl-names = "default", "gpio";
639 pinctrl-0 = <&i2c3_xfer>;
640 pinctrl-1 = <&i2c3_gpio>;
641 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
642 clocks = <&clk_gates19 12>;
643 rockchip,check-idle = <1>;
649 compatible = "rockchip,rk30-i2c";
650 reg = <0x0 0xff160000 0x0 0x1000>;
651 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
652 #address-cells = <1>;
654 pinctrl-names = "default", "gpio";
655 pinctrl-0 = <&i2c4_xfer>;
656 pinctrl-1 = <&i2c4_gpio>;
657 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
658 clocks = <&clk_gates19 13>;
659 rockchip,check-idle = <1>;
665 compatible = "rockchip,rk30-i2c";
666 reg = <0x0 0xff170000 0x0 0x1000>;
667 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
668 #address-cells = <1>;
670 pinctrl-names = "default", "gpio";
671 pinctrl-0 = <&i2c5_xfer>;
672 pinctrl-1 = <&i2c5_gpio>;
673 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
674 clocks = <&clk_gates19 14>;
675 rockchip,check-idle = <1>;
680 compatible = "rockchip,rk-fb";
681 rockchip,disp-mode = <NO_DUAL>;
685 rk_screen: rk_screen {
686 compatible = "rockchip,screen";
689 dsihost0: mipi@ff960000{
690 compatible = "rockchip,rk33x-dsi";
692 reg = <0xff960000 0x4000>, <0xff968000 0x4000>;
693 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
694 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&clk_gates4 14>, <&clk_gates17 3>, <&clk_gates22 10>;
696 clock-names = "clk_mipi_24m", "pclk_mipi_dsi_host", "pclk_mipi_dsi_phy";
700 lvds: lvds@ff968000 {
701 compatible = "rockchip,rk3368-lvds";
702 rockchip,grf = <&grf>;
703 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
704 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
705 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
706 clock-names = "pclk_lvds", "pclk_lvds_ctl";
711 compatible = "rockchip,rk32-edp";
712 reg = <0x0 0xff970000 0x0 0x4000>;
713 rockchip,grf = <&grf>;
714 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
716 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
717 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
718 reset-names = "edp_24m", "edp_apb";
721 hdmi: hdmi@ff980000 {
722 compatible = "rockchip,rk3368-hdmi";
723 reg = <0x0 0xff980000 0x0 0x20000>;
724 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
725 pinctrl-names = "default", "gpio";
726 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
727 pinctrl-1 = <&i2c5_gpio>;
728 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
729 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
733 hdmi_hdcp2: hdmi_hdcp2@ff978000 {
734 compatible = "rockchip,rk3368-hdmi-hdcp2";
735 reg = <0x0 0xff978000 0x0 0x2000>;
736 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
738 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
742 lcdc: lcdc@ff930000 {
743 compatible = "rockchip,rk3368-lcdc";
744 rockchip,grf = <&grf>;
745 rockchip,pmu = <&pmu_grf>;
746 rockchip,prop = <PRMRY>;
747 rockchip,pwr18 = <0>;
748 rockchip,iommu-enabled = <0>;
749 reg = <0x0 0xff930000 0x0 0x10000>;
750 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
751 /*pinctrl-names = "default", "gpio";
752 *pinctrl-0 = <&lcdc_lcdc>;
753 *pinctrl-1 = <&lcdc_gpio>;
756 clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
757 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
761 compatible = "rockchip,saradc";
762 reg = <0x0 0xff100000 0x0 0x100>;
763 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
764 #io-channel-cells = <1>;
766 rockchip,adc-vref = <1800>;
767 clock-frequency = <1000000>;
768 clocks = <&clk_saradc>, <&clk_gates19 15>;
769 clock-names = "saradc", "pclk_saradc";
774 compatible = "rockchip,rk3368-rga2";
775 reg = <0x0 0xff920000 0x0 0x1000>;
776 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
778 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
781 i2s0: i2s0@ff898000 {
782 compatible = "rockchip-i2s";
783 reg = <0x0 0xff898000 0x0 0x1000>;
785 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
786 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
787 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
788 dmas = <&pdma0 0>, <&pdma0 1>;
790 dma-names = "tx", "rx";
791 pinctrl-names = "default", "sleep";
792 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
793 pinctrl-1 = <&i2s_gpio>;
796 i2s1: i2s1@ff890000 {
797 compatible = "rockchip-i2s";
798 reg = <0x0 0xff890000 0x0 0x1000>;
800 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
801 clock-names = "i2s_clk", "i2s_hclk";
802 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
803 dmas = <&pdma0 6>, <&pdma0 7>;
805 dma-names = "tx", "rx";
808 spdif: spdif@ff880000 {
809 compatible = "rockchip-spdif";
810 reg = <0x0 0xff880000 0x0 0x1000>;
811 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
812 clock-names = "spdif_mclk", "spdif_hclk";
813 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
817 pinctrl-names = "default";
818 pinctrl-0 = <&spdif_tx>;
822 compatible = "rockchip,rk-pwm";
823 reg = <0x0 0xff680000 0x0 0x10>;
825 pinctrl-names = "default";
826 pinctrl-0 = <&pwm0_pin>;
827 clocks = <&clk_gates13 6>;
828 clock-names = "pclk_pwm";
833 compatible = "rockchip,rk-pwm";
834 reg = <0x0 0xff680010 0x0 0x10>;
836 pinctrl-names = "default";
837 pinctrl-0 = <&pwm1_pin>;
838 clocks = <&clk_gates13 6>;
839 clock-names = "pclk_pwm";
844 compatible = "rockchip,rk-pwm";
845 reg = <0x0 0xff680020 0x0 0x10>;
847 //pinctrl-names = "default";
848 //pinctrl-0 = <&pwm1_pin>;
849 clocks = <&clk_gates13 6>;
850 clock-names = "pclk_pwm";
855 compatible = "rockchip,rk-pwm";
856 reg = <0x0 0xff680030 0x0 0x10>;
858 pinctrl-names = "default";
859 pinctrl-0 = <&pwm3_pin>;
860 clocks = <&clk_gates13 6>;
861 clock-names = "pclk_pwm";
865 voppwm: pwm@ff9301a0 {
866 compatible = "rockchip,vop-pwm";
867 reg = <0x0 0xff9301a0 0x0 0x10>;
869 pinctrl-names = "default";
870 pinctrl-0 = <&vop_pwm_pin>;
871 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
872 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
879 regulator_name = "vdd_arm";
880 suspend_volt = <1000>; //mV
882 clk_core_dvfs_table: clk_core {
891 temp-limit-enable = <0>;
893 normal-temp-limit = <
894 /*delta-temp delta-freq*/
900 performance-temp-limit = <
916 regulator_name = "vdd_logic";
917 suspend_volt = <1000>; //mV
919 clk_ddr_dvfs_table: clk_ddr {
932 aclk_vio1_dvfs_table: aclk_vio1 {
944 regulator_name = "vdd_gpu";
945 suspend_volt = <1000>; //mV
947 clk_gpu_dvfs_table: clk_gpu {
968 compatible = "rockchip,ion";
969 #address-cells = <1>;
972 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
973 compatible = "rockchip,ion-heap";
974 rockchip,ion_heap = <4>;
975 reg = <0x00000000 0x08000000>; /* 512MB */
977 rockchip,ion-heap@0 { /* VMALLOC HEAP */
978 compatible = "rockchip,ion-heap";
979 rockchip,ion_heap = <0>;
983 vpu: vpu_service@ff9a0000 {
984 compatible = "vpu_service";
986 reg = <0x0 0xff9a0000 0x0 0x800>;
987 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
988 interrupt-names = "irq_enc", "irq_dec";
990 clocks = <&clk_vdpu>, <&hclk_vdpu>;
991 clock-names = "aclk_vcodec", "hclk_vcodec";
993 name = "vpu_service";
994 /* status = "disabled"; */
998 compatible = "rockchip,iep";
1000 reg = <0x0 0xff900000 0x0 0x800>;
1001 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1003 clock-names = "aclk_iep", "hclk_iep";
1007 gmac: eth@ff290000 {
1008 compatible = "rockchip,rk3368-gmac";
1009 reg = <0x0 0xff290000 0x0 0x10000>;
1010 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1011 interrupt-names = "macirq";
1013 clocks = <&clk_mac>, <&clk_gates5 0>,
1014 <&clk_gates5 1>, <&clk_gates5 2>,
1015 <&clk_gates5 3>, <&clk_gates8 0>,
1017 clock-names = "clk_mac", "mac_clk_rx",
1018 "mac_clk_tx", "clk_mac_ref",
1019 "clk_mac_refout", "aclk_mac",
1023 pinctrl-names = "default";
1024 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1028 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1029 reg = <0x0 0xffa30000 0x0 0x10000>;
1030 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1031 interrupt-names = "GPU";
1036 compatible = "rockchip,iep_mmu";
1037 reg = <0x0 0xff900800 0x0 0x100>;
1038 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1039 interrupt-names = "iep_mmu";
1044 compatible = "rockchip,vip_mmu";
1045 reg = <0x0 0xff950800 0x0 0x100>;
1046 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1047 interrupt-names = "vip_mmu";
1052 compatible = "rockchip,vop_mmu";
1053 reg = <0x0 0xff930300 0x0 0x100>;
1054 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1055 interrupt-names = "vop_mmu";
1059 dbgname = "isp_mmu";
1060 compatible = "rockchip,isp_mmu";
1061 reg = <0x0 0xff914000 0x0 0x100>,
1062 <0x0 0xff915000 0x0 0x100>;
1063 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1064 interrupt-names = "isp_mmu";
1068 dbgname = "hdcp_mmu";
1069 compatible = "rockchip,hdcp_mmu";
1070 reg = <0x0 0xff940000 0x0 0x100>;
1071 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1072 interrupt-names = "hdcp_mmu";
1077 compatible = "rockchip,hevc_mmu";
1078 reg = <0x0 0xff9c0440 0x0 0x40>, /*need to fix*/
1079 <0x0 0xff9c0480 0x0 0x40>;
1080 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1081 interrupt-names = "hevc_mmu";
1086 compatible = "rockchip,vpu_mmu";
1087 reg = <0x0 0xff9a0800 0x0 0x100>; /*need to fix*/
1088 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1089 interrupt-names = "vpu_mmu";
1093 rockchip,ctrbits = <
1100 |RKPM_CTR_SYSCLK_DIV
1101 |RKPM_CTR_IDLEAUTO_MD
1102 |RKPM_CTR_ARMOFF_LPMD
1104 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1107 rockchip,pmic-suspend_gpios = <
1108 /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1110 rockchip,pmic-resume_gpios = <
1111 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1116 compatible = "rockchip,isp";
1117 reg = <0x0 0xff910000 0x0 0x10000>;
1118 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1119 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1120 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1121 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1122 pinctrl-0 = <&cif_clkout>;
1123 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1124 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1125 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1126 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1127 pinctrl-5 = <&cif_clkout>;
1128 pinctrl-6 = <&cif_clkout &isp_prelight>;
1129 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1130 pinctrl-8 = <&isp_flash_trigger>;
1131 rockchip,isp,mipiphy = <2>;
1132 rockchip,isp,cifphy = <1>;
1133 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1134 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1135 rockchip,isp,iommu_enable = <1>;
1139 tsadc: tsadc@ff280000 {
1140 compatible = "rockchip,tsadc";
1141 reg = <0x0 0xff280000 0x0 0x100>;
1142 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1143 #io-channel-cells = <1>;
1145 clock-frequency = <10000>;
1146 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1147 clock-names = "tsadc", "pclk_tsadc";
1148 pinctrl-names = "default", "tsadc_int";
1149 pinctrl-0 = <&tsadc_gpio>;
1150 pinctrl-1 = <&tsadc_int>;
1151 tsadc-ht-temp = <120>;
1152 tsadc-ht-reset-cru = <1>;
1153 tsadc-ht-pull-gpio = <0>;
1154 status = "disabled";
1158 compatible = "rockchip,rk3368-tsp";
1159 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1160 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1161 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1162 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1163 interrupt-names = "irq_tsp";
1164 // pinctrl-names = "default";
1165 // pinctrl-0 = <&isp_hsadc>;
1169 crypto: crypto@FF8A0000{
1170 compatible = "rockchip,rk3368-crypto";
1171 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1172 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1173 interrupt-names = "irq_crypto";
1174 clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1175 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1178 dwc_control_usb: dwc-control-usb {
1179 compatible = "rockchip,rk3368-dwc-control-usb";
1180 rockchip,grf = <&grf>;
1181 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1182 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1183 interrupt-names = "otg_id", "otg_bvalid",
1184 "otg_linestate", "host0_linestate";
1185 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1186 clock-names = "hclk_usb_peri", "usbphy_480m";
1187 //resets = <&reset RK3128_RST_USBPOR>;
1188 //reset-names = "usbphy_por";
1190 compatible = "inno,phy";
1191 regbase = &dwc_control_usb;
1192 rk_usb,bvalid = <0x04b 23 1>;
1193 rk_usb,iddig = <0x04b 26 1>;
1194 rk_usb,vdmsrcen = <0x718 12 1>;
1195 rk_usb,vdpsrcen = <0x718 11 1>;
1196 rk_usb,rdmpden = <0x718 10 1>;
1197 rk_usb,idpsrcen = <0x718 9 1>;
1198 rk_usb,idmsinken = <0x718 8 1>;
1199 rk_usb,idpsinken = <0x718 7 1>;
1200 rk_usb,dpattach = <0x4b8 31 1>;
1201 rk_usb,cpdet = <0x4b8 30 1>;
1202 rk_usb,dcpattach = <0x4b8 29 1>;
1206 usb0: usb@ff580000 {
1207 compatible = "rockchip,rk3368_usb20_otg";
1208 reg = <0x0 0xff580000 0x0 0x40000>;
1209 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1211 clock-names = "clk_usbphy0", "hclk_otg";
1212 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1213 <&reset RK3368_SRST_USBOTGC0>;
1214 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1215 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1216 rockchip,usb-mode = <0>;
1219 usb_ehci: usb@ff500000 {
1220 compatible = "generic-ehci";
1221 reg = <0x0 0xff500000 0x0 0x20000>;
1222 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1223 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1224 clock-names = "clk_usbphy0", "hclk_ehci";
1225 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1226 // <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1227 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1230 usb_ohci: usb@ff520000 {
1231 compatible = "generic-ohci";
1232 reg = <0x0 0xff520000 0x0 0x20000>;
1233 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1234 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1235 clock-names = "clk_usbphy0", "hclk_ohci";
1238 usb_hsic: usb@ff5c0000 {
1239 compatible = "rockchip,rk3288_rk_hsic_host";
1240 reg = <0x0 0xff5c0000 0x0 0x40000>;
1241 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1243 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1244 <&hsicphy_12m>, <&usbphy_480m>,
1245 <&otgphy1_480m>, <&otgphy2_480m>;
1246 clock-names = "hsicphy_480m", "hclk_hsic",
1247 "hsicphy_12m", "usbphy_480m",
1248 "hsic_usbphy1", "hsic_usbphy2";
1249 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1250 <&reset RK3288_SOFT_RST_HSICPHY>;
1251 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1253 status = "disabled";
1257 compatible = "rockchip,rk3368-pinctrl";
1258 rockchip,grf = <&grf>;
1259 rockchip,pmu = <&pmu_grf>;
1260 #address-cells = <2>;
1264 gpio0: gpio0@ff750000 {
1265 compatible = "rockchip,gpio-bank";
1266 reg = <0x0 0xff750000 0x0 0x100>;
1267 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1268 clocks = <&clk_gates23 4>;
1273 interrupt-controller;
1274 #interrupt-cells = <2>;
1277 gpio1: gpio1@ff780000 {
1278 compatible = "rockchip,gpio-bank";
1279 reg = <0x0 0xff780000 0x0 0x100>;
1280 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1281 clocks = <&clk_gates22 1>;
1286 interrupt-controller;
1287 #interrupt-cells = <2>;
1290 gpio2: gpio2@ff790000 {
1291 compatible = "rockchip,gpio-bank";
1292 reg = <0x0 0xff790000 0x0 0x100>;
1293 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1294 clocks = <&clk_gates22 2>;
1299 interrupt-controller;
1300 #interrupt-cells = <2>;
1303 gpio3: gpio3@ff7a0000 {
1304 compatible = "rockchip,gpio-bank";
1305 reg = <0x0 0xff7a0000 0x0 0x100>;
1306 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1307 clocks = <&clk_gates22 3>;
1312 interrupt-controller;
1313 #interrupt-cells = <2>;
1316 pcfg_pull_up: pcfg-pull-up {
1320 pcfg_pull_down: pcfg-pull-down {
1324 pcfg_pull_none: pcfg-pull-none {
1328 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1329 drive-strength = <8>;
1332 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1334 drive-strength = <8>;
1337 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1338 drive-strength = <4>;
1341 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1343 drive-strength = <4>;
1346 pcfg_output_high: pcfg-output-high {
1350 pcfg_output_low: pcfg-output-low {
1355 i2c0_xfer: i2c0-xfer {
1356 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1357 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1359 i2c0_gpio: i2c0-gpio {
1360 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1361 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1366 i2c1_xfer: i2c1-xfer {
1367 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1368 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1370 i2c1_gpio: i2c1-gpio {
1371 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1372 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1377 i2c2_xfer: i2c2-xfer {
1378 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1379 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1381 i2c2_gpio: i2c2-gpio {
1382 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1383 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1388 i2c3_xfer: i2c3-xfer {
1389 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1390 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1392 i2c3_gpio: i2c3-gpio {
1393 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1394 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1399 i2c4_xfer: i2c4-xfer {
1400 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1401 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1403 i2c4_gpio: i2c4-gpio {
1404 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1405 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1410 i2c5_xfer: i2c5-xfer {
1411 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1412 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1414 i2c5_gpio: i2c5-gpio {
1415 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1416 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1421 uart0_xfer: uart0-xfer {
1422 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1423 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1426 uart0_cts: uart0-cts {
1427 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1430 uart0_rts: uart0-rts {
1431 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1434 uart0_rts_gpio: uart0-rts-gpio {
1435 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1440 uart1_xfer: uart1-xfer {
1441 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1442 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1445 uart1_cts: uart1-cts {
1446 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1449 uart1_rts: uart1-rts {
1450 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1455 uart2_xfer: uart2-xfer {
1456 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1457 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1462 uart3_xfer: uart3-xfer {
1463 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1464 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1467 uart3_cts: uart3-cts {
1468 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1471 uart3_rts: uart3-rts {
1472 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1477 uart4_xfer: uart4-xfer {
1478 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1479 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1482 uart4_cts: uart4-cts {
1483 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1486 uart4_rts: uart4-rts {
1487 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1492 spi0_clk: spi0-clk {
1493 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1495 spi0_cs0: spi0-cs0 {
1496 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1499 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1502 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1504 spi0_cs1: spi0-cs1 {
1505 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1510 spi1_clk: spi1-clk {
1511 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1513 spi1_cs0: spi1-cs0 {
1514 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1517 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1520 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1525 spi2_clk: spi2-clk {
1526 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1528 spi2_cs0: spi2-cs0 {
1529 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1532 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1535 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1540 i2s_mclk: i2s-mclk {
1541 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1545 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1548 i2s_lrckrx:i2s-lrckrx {
1549 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1552 i2s_lrcktx:i2s-lrcktx {
1553 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1557 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1561 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1565 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1569 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1573 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1576 i2s_gpio: i2s-gpio {
1577 rockchip,pins = <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,
1578 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1579 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1580 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1581 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1582 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1583 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1584 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1585 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1590 spdif_tx: spdif-tx {
1591 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1596 sdmmc_clk: sdmmc-clk {
1597 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1600 sdmmc_cmd: sdmmc-cmd {
1601 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1604 sdmmc_dectn: sdmmc-dectn {
1605 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1608 sdmmc_bus1: sdmmc-bus1 {
1609 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1612 sdmmc_bus4: sdmmc-bus4 {
1613 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1614 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1615 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1616 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1619 sdmmc_gpio: sdmmc-gpio {
1620 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1621 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1622 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1623 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1624 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1625 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1626 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1631 sdio0_bus1: sdio0-bus1 {
1632 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1635 sdio0_bus4: sdio0-bus4 {
1636 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1637 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1638 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1639 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1642 sdio0_cmd: sdio0-cmd {
1643 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1646 sdio0_clk: sdio0-clk {
1647 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1650 sdio0_dectn: sdio0-dectn {
1651 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1654 sdio0_wrprt: sdio0-wrprt {
1655 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1658 sdio0_pwren: sdio0-pwren {
1659 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1662 sdio0_bkpwr: sdio0-bkpwr {
1663 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1666 sdio0_int: sdio0-int {
1667 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1670 sdio0_gpio: sdio0-gpio {
1671 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1672 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1673 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1674 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1675 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1676 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1677 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1678 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1679 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1680 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1681 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1686 emmc_clk: emmc-clk {
1687 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1690 emmc_cmd: emmc-cmd {
1691 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1694 emmc_pwren: emmc-pwren {
1695 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1698 emmc_rstnout: emmc_rstnout {
1699 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1702 emmc_bus1: emmc-bus1 {
1703 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1706 emmc_bus4: emmc-bus4 {
1707 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1708 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1709 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1710 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1715 pwm0_pin: pwm0-pin {
1716 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1719 vop_pwm_pin:vop-pwm {
1720 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1725 pwm1_pin: pwm1-pin {
1726 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1731 pwm3_pin: pwm3-pin {
1732 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1737 lcdc_lcdc: lcdc-lcdc {
1739 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1740 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1741 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1742 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1743 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1744 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1745 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1746 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1747 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1748 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1749 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1750 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1751 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1752 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1753 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1754 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1755 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1756 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1759 lcdc_gpio: lcdc-gpio {
1761 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1762 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1763 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1764 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1765 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1766 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1767 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1768 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1769 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1770 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1771 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1772 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1773 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1774 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1775 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1776 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1777 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1778 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1783 cif_clkout: cif-clkout {
1784 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1787 isp_dvp_d2d9: isp-dvp-d2d9 {
1788 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1789 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1790 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1791 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1792 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1793 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1794 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1795 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1796 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1797 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1798 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1799 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1802 isp_dvp_d0d1: isp-dvp-d0d1 {
1803 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1804 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1807 isp_dvp_d10d11:isp_d10d11 {
1808 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1809 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1812 isp_dvp_d0d7: isp-dvp-d0d7 {
1813 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1814 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1815 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1816 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1817 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1818 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1819 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1820 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1823 isp_shutter: isp-shutter {
1824 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1825 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1828 isp_flash_trigger: isp-flash-trigger {
1829 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1832 isp_prelight: isp-prelight {
1833 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1836 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1837 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1843 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1847 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1851 gps_rfclk: gps-rfclk {
1852 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1858 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1861 mac_txpins: mac-txpins {
1862 rockchip,pins = <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//TXD0
1863 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//TXD1
1864 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//TXD2
1865 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//TXD3
1866 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//TXEN
1867 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;//TXCLK
1870 mac_rxpins: mac-rxpins {
1871 rockchip,pins = <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1872 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1873 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1874 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1875 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1876 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//RXER
1877 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1878 <3 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;//COL
1882 rockchip,pins = <3 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>; //CRS
1885 mac_mdpins: mac-mdpins {
1886 rockchip,pins = <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1887 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;//MDC
1892 tsadc_int: tsadc-int {
1893 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1895 tsadc_gpio: tsadc-gpio {
1896 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1901 hdmi_cec: hdmi-cec {
1902 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1907 hdmii2c_xfer: hdmii2c-xfer {
1908 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
1909 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;