arch/arm64/boot/dts/rk3368.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/pinctrl/rockchip.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/sensor-dev.h>
   6 #include <dt-bindings/clock/rk_system_status.h>
   7
   8 #include "rk3368-clocks.dtsi"
   9
  10 / {
  11         compatible = "rockchip,rk3368";
  12
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &uart_bt;
  20                 serial1 = &uart_bb;
  21                 serial2 = &uart_dbg;
  22                 serial3 = &uart_gps;
  23                 serial4 = &uart_exp;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &spi0;
  31                 spi1 = &spi1;
  32                 spi2 = &spi2;
  33                 lcdc = &lcdc;
  34         };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 big0: cpu@100 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53", "arm,armv8";
  43                         reg = <0x0 0x100>;
  44                         enable-method = "psci";
  45                 };
  46                 big1: cpu@101 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53", "arm,armv8";
  49                         reg = <0x0 0x101>;
  50                         enable-method = "psci";
  51                 };
  52                 big2: cpu@102 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a53", "arm,armv8";
  55                         reg = <0x0 0x102>;
  56                         enable-method = "psci";
  57                 };
  58                 big3: cpu@103 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         reg = <0x0 0x103>;
  62                         enable-method = "psci";
  63                 };
  64                 little0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53", "arm,armv8";
  67                         reg = <0x0 0x0>;
  68                         enable-method = "psci";
  69                 };
  70                 little1: cpu@1 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a53", "arm,armv8";
  73                         reg = <0x0 0x1>;
  74                         enable-method = "psci";
  75                 };
  76                 little2: cpu@2 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53", "arm,armv8";
  79                         reg = <0x0 0x2>;
  80                         enable-method = "psci";
  81                 };
  82                 little3: cpu@3 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53", "arm,armv8";
  85                         reg = <0x0 0x3>;
  86                         enable-method = "psci";
  87                 };
  88
  89                 cpu-map {
  90                         cluster0 {
  91                                 core0 {
  92                                         cpu = <&big0>;
  93                                 };
  94                                 core1 {
  95                                         cpu = <&big1>;
  96                                 };
  97                                 core2 {
  98                                         cpu = <&big2>;
  99                                 };
 100                                 core3 {
 101                                         cpu = <&big3>;
 102                                 };
 103                         };
 104                         cluster1 {
 105                                 core0 {
 106                                         cpu = <&little0>;
 107                                 };
 108                                 core1 {
 109                                         cpu = <&little1>;
 110                                 };
 111                                 core2 {
 112                                         cpu = <&little2>;
 113                                 };
 114                                 core3 {
 115                                         cpu = <&little3>;
 116                                 };
 117                         };
 118                 };
 119         };
 120
 121         psci {
 122                 compatible = "arm,psci";
 123                 method = "smc";
 124                 cpu_on = <0xC4000003>;
 125         };
 126
 127         gic: interrupt-controller@ffb70000 {
 128                 compatible = "arm,cortex-a15-gic";
 129                 #interrupt-cells = <3>;
 130                 #address-cells = <0>;
 131                 interrupt-controller;
 132                 reg = <0x0 0xffb71000 0 0x1000>,
 133                       <0x0 0xffb72000 0 0x1000>;
 134         };
 135
 136         pmu: syscon@ff730000 {
 137                 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
 138                 reg = <0x0 0xff730000 0x0 0x1000>;
 139         };
 140
 141         pmugrf: syscon@ff738000 {
 142                 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
 143                 reg = <0x0 0xff738000 0x0 0x1000>;
 144         };
 145
 146         sgrf: syscon@ff740000 {
 147                 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
 148                 reg = <0x0 0xff740000 0x0 0x1000>;
 149
 150         };
 151
 152         cru: syscon@ff760000 {
 153                 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
 154                 reg = <0x0 0xff760000 0x0 0x1000>;
 155         };
 156
 157         grf: syscon@ff770000 {
 158                 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
 159                 reg = <0x0 0xff770000 0x0 0x1000>;
 160         };
 161
 162         arm-pmu {
 163                 compatible = "arm,armv8-pmuv3";
 164                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 172         };
 173
 174         cpu_axi_bus: cpu_axi_bus {
 175                 compatible = "rockchip,cpu_axi_bus";
 176                 #address-cells = <2>;
 177                 #size-cells = <2>;
 178                 ranges;
 179
 180                 qos {
 181                         #address-cells = <2>;
 182                         #size-cells = <2>;
 183                         ranges;
 184
 185                         dmac {
 186                                 reg = <0x0 0xffa80000 0x0 0x20>;
 187                         };
 188                         crypto {
 189                                 reg = <0x0 0xffa80080 0x0 0x20>;
 190                         };
 191                         bus_cpup {
 192                                 reg = <0x0 0xffa90000 0x0 0x20>;
 193                         };
 194                         cci_r {
 195                                 reg = <0x0 0xffaa0000 0x0 0x20>;
 196                         };
 197                         cci_w {
 198                                 reg = <0x0 0xffaa0080 0x0 0x20>;
 199                         };
 200                         peri {
 201                                 reg = <0x0 0xffab0000 0x0 0x20>;
 202                         };
 203                         iep {
 204                                 reg = <0x0 0xffad0000 0x0 0x20>;
 205                         };
 206                         isp_r0 {
 207                                 reg = <0x0 0xffad0080 0x0 0x20>;
 208                         };
 209                         isp_r1 {
 210                                 reg = <0x0 0xffad0100 0x0 0x20>;
 211                         };
 212                         isp_w0 {
 213                                 reg = <0x0 0xffad0180 0x0 0x20>;
 214                                 rockchip,priority = <2 2>;
 215                         };
 216                         isp_w1 {
 217                                 reg = <0x0 0xffad0200 0x0 0x20>;
 218                                 rockchip,priority = <2 2>;
 219                         };
 220                         vip {
 221                                 reg = <0x0 0xffad0280 0x0 0x20>;
 222                         };
 223                         vop {
 224                                 reg = <0x0 0xffad0300 0x0 0x20>;
 225                                 rockchip,priority = <2 2>;
 226                         };
 227                         rga_r {
 228                                 reg = <0x0 0xffad0380 0x0 0x20>;
 229                         };
 230                         rga_w {
 231                                 reg = <0x0 0xffad0400 0x0 0x20>;
 232                         };
 233                         hevc_r {
 234                                 reg = <0x0 0xffae0000 0x0 0x20>;
 235                         };
 236                         vpu_r {
 237                                 reg = <0x0 0xffae0080 0x0 0x20>;
 238                         };
 239                         vpu_w {
 240                                 reg = <0x0 0xffae0100 0x0 0x20>;
 241                         };
 242                 };
 243
 244                 msch {
 245                         #address-cells = <2>;
 246                         #size-cells = <2>;
 247                         ranges;
 248
 249                         msch {
 250                                 reg = <0x0 0xffac0000 0x0 0x3c>;
 251                                 rockchip,read-latency = <0x34>;
 252                         };
 253                 };
 254         };
 255
 256         timer {
 257                 compatible = "arm,armv8-timer";
 258                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 259                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 260                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 261                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 262                 clock-frequency = <24000000>;
 263         };
 264
 265         timer@ff810000 {
 266                 compatible = "rockchip,timer";
 267                 reg = <0x0 0xff810000 0x0 0x20>;
 268                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 269                 rockchip,broadcast = <1>;
 270         };
 271
 272         sram: sram@ff8c0000 {
 273                 compatible = "mmio-sram";
 274                 reg = <0x0 0xff8c0000 0x0 0x10000>; /* 64k */
 275                 map-exec;
 276         };
 277
 278         watchdog: wdt@ff800000 {
 279                 compatible = "rockchip,watch dog";
 280                 reg = <0x0 0xff800000 0x0 0x100>;
 281                 clocks = <&pclk_alive_pre>;
 282                 clock-names = "pclk_wdt";
 283                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 284                 rockchip,irq = <1>;
 285                 rockchip,timeout = <60>;
 286                 rockchip,atboot = <1>;
 287                 rockchip,debug = <0>;
 288                 status = "disabled";
 289         };
 290
 291         amba {
 292                 #address-cells = <2>;
 293                 #size-cells = <2>;
 294                 compatible = "arm,amba-bus";
 295                 interrupt-parent = <&gic>;
 296                 ranges;
 297
 298                 pdma0: pdma@ff600000 {
 299                         compatible = "arm,pl330", "arm,primecell";
 300                         reg = <0x0 0xff600000 0x0 0x4000>;
 301                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 302                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 303                         #dma-cells = <1>;
 304                 };
 305
 306                 pdma1: pdma@ff250000 {
 307                         compatible = "arm,pl330", "arm,primecell";
 308                         reg = <0x0 0xff250000 0x0 0x4000>;
 309                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 310                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 311                         #dma-cells = <1>;
 312                 };
 313         };
 314
 315         reset: reset@ff760300{
 316                 compatible = "rockchip,reset";
 317                 reg = <0x0 0xff760300 0x0 0x38>;
 318                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 319                 #reset-cells = <1>;
 320         };
 321
 322         nandc0: nandc@ff400000 {
 323                 compatible = "rockchip,rk-nandc";
 324                 reg = <0x0 0xff400000 0x0 0x4000>;
 325                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 326                 nandc_id = <0>;
 327                 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
 328                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 329         };
 330
 331         nandc0reg: nandc0@ff400000 {
 332                 compatible = "rockchip,rk-nandc";
 333                 reg = <0x0 0xff400000 0x0 0x4000>;
 334         };
 335
 336         emmc: rksdmmc@ff0f0000 {
 337                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 338                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 339                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 clocks = <&clk_emmc>, <&clk_gates21 2>;
 343                 clock-names = "clk_mmc", "hclk_mmc";
 344                 num-slots = <1>;
 345                 fifo-depth = <0x100>;
 346                 bus-width = <8>;
 347         };
 348
 349         sdmmc: rksdmmc@ff0c0000 {
 350                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 351                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 352                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 pinctrl-names = "default", "idle";
 356                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 357                 pinctrl-1 = <&sdmmc_gpio>;
 358                 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 359                 clocks = <&clk_sdmmc0>, <&clk_gates21 0>;
 360                 clock-names = "clk_mmc", "hclk_mmc";
 361                 num-slots = <1>;
 362                 fifo-depth = <0x100>;
 363                 bus-width = <4>;
 364         };
 365
 366         sdio: rksdmmc@ff0d0000 {
 367                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 368                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 369                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 370                 #address-cells = <1>;
 371                 #size-cells = <0>;
 372                 pinctrl-names = "default","idle";
 373                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
 374                 pinctrl-1 = <&sdio0_gpio>;
 375                 clocks = <&clk_sdio0>, <&clk_gates21 1>;
 376                 clock-names = "clk_mmc", "hclk_mmc";
 377                 num-slots = <1>;
 378                 fifo-depth = <0x100>;
 379                 bus-width = <4>;
 380         };
 381
 382         spi0: spi@ff110000 {
 383                 compatible = "rockchip,rockchip-spi";
 384                 reg = <0x0 0xff110000 0x0 0x1000>;
 385                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 pinctrl-names = "default";
 389                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 390                 rockchip,spi-src-clk = <0>;
 391                 num-cs = <2>;
 392                 clocks =<&clk_spi0>, <&clk_gates19 4>;
 393                 clock-names = "spi", "pclk_spi0";
 394                 //dmas = <&pdma1 11>, <&pdma1 12>;
 395                 //#dma-cells = <2>;
 396                 //dma-names = "tx", "rx";
 397                 status = "disabled";
 398         };
 399
 400         spi1: spi@ff120000 {
 401                 compatible = "rockchip,rockchip-spi";
 402                 reg = <0x0 0xff120000 0x0 0x1000>;
 403                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 408                 rockchip,spi-src-clk = <1>;
 409                 num-cs = <1>;
 410                 clocks = <&clk_spi1>, <&clk_gates19 5>;
 411                 clock-names = "spi", "pclk_spi1";
 412                 //dmas = <&pdma1 13>, <&pdma1 14>;
 413                 //#dma-cells = <2>;
 414                 //dma-names = "tx", "rx";
 415                 status = "disabled";
 416         };
 417
 418         spi2: spi@ff130000 {
 419                 compatible = "rockchip,rockchip-spi";
 420                 reg = <0x0 0xff130000 0x0 0x1000>;
 421                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 422                 #address-cells = <1>;
 423                 #size-cells = <0>;
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 426                 rockchip,spi-src-clk = <2>;
 427                 num-cs = <1>;
 428                 clocks = <&clk_spi2>, <&clk_gates19 6>;
 429                 clock-names = "spi", "pclk_spi2";
 430                 //dmas = <&pdma1 15>, <&pdma1 16>;
 431                 //#dma-cells = <2>;
 432                 //dma-names = "tx", "rx";
 433                 status = "disabled";
 434         };
 435
 436         uart_bt: serial@ff180000 {
 437                 compatible = "rockchip,serial";
 438                 reg = <0x0 0xff180000 0x0 0x100>;
 439                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 440                 clock-frequency = <24000000>;
 441                 clocks = <&clk_uart0>, <&clk_gates19 7>;
 442                 clock-names = "sclk_uart", "pclk_uart";
 443                 reg-shift = <2>;
 444                 reg-io-width = <4>;
 445                 //dmas = <&pdma1 1>, <&pdma1 2>;
 446                 //#dma-cells = <2>;
 447                 pinctrl-names = "default";
 448                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 449                 status = "disabled";
 450         };
 451
 452         uart_bb: serial@ff190000 {
 453                 compatible = "rockchip,serial";
 454                 reg = <0x0 0xff190000 0x0 0x100>;
 455                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 456                 clock-frequency = <24000000>;
 457                 clocks = <&clk_uart1>, <&clk_gates19 8>;
 458                 clock-names = "sclk_uart", "pclk_uart";
 459                 reg-shift = <2>;
 460                 reg-io-width = <4>;
 461                 //dmas = <&pdma1 3>, <&pdma1 4>;
 462                 //#dma-cells = <2>;
 463                 pinctrl-names = "default";
 464                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 465                 status = "disabled";
 466         };
 467
 468         uart_dbg: serial@ff690000 {
 469                 compatible = "rockchip,serial";
 470                 reg = <0x0 0xff690000 0x0 0x100>;
 471                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 472                 clock-frequency = <24000000>;
 473                 clocks = <&clk_uart2>, <&clk_gates13 5>;
 474                 clock-names = "sclk_uart", "pclk_uart";
 475                 reg-shift = <2>;
 476                 reg-io-width = <4>;
 477                 //dmas = <&pdma0 4>, <&pdma0 5>;
 478                 //#dma-cells = <2>;
 479                 //pinctrl-names = "default";
 480                 //pinctrl-0 = <&uart2_xfer>;
 481                 status = "disabled";
 482         };
 483
 484         uart_gps: serial@ff1b0000 {
 485                 compatible = "rockchip,serial";
 486                 reg = <0x0 0xff1b0000 0x0 0x100>;
 487                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 488                 clock-frequency = <24000000>;
 489                 clocks = <&clk_uart3>, <&clk_gates19 9>;
 490                 clock-names = "sclk_uart", "pclk_uart";
 491                 current-speed = <115200>;
 492                 reg-shift = <2>;
 493                 reg-io-width = <4>;
 494                 //dmas = <&pdma1 7>, <&pdma1 8>;
 495                 //#dma-cells = <2>;
 496                 pinctrl-names = "default";
 497                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 498                 status = "disabled";
 499         };
 500
 501         uart_exp: serial@ff1c0000 {
 502                 compatible = "rockchip,serial";
 503                 reg = <0x0 0xff1c0000 0x0 0x100>;
 504                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 505                 clock-frequency = <24000000>;
 506                 clocks = <&clk_uart4>, <&clk_gates19 10>;
 507                 clock-names = "sclk_uart", "pclk_uart";
 508                 reg-shift = <2>;
 509                 reg-io-width = <4>;
 510                 //dmas = <&pdma1 9>, <&pdma1 10>;
 511                 //#dma-cells = <2>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 514                 status = "disabled";
 515         };
 516
 517         rockchip_clocks_init: clocks-init{
 518                 compatible = "rockchip,clocks-init";
 519                 rockchip,clocks-init-parent =
 520                         <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
 521                         <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
 522                         <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
 523                         <&clk_cs &clk_gpll>;
 524                 rockchip,clocks-init-rate =
 525                         <&clk_gpll 576000000>,          <&clk_core_b 792000000>,
 526                         <&clk_core_l 600000000>,        <&clk_cpll 400000000>,
 527                         /*<&clk_npll 500000000>,*/      <&aclk_bus 300000000>,
 528                         <&hclk_bus 150000000>,          <&pclk_bus 75000000>,
 529                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 530                         <&hclk_peri 150000000>,         <&pclk_peri 75000000>,
 531                         <&pclk_alive_pre 100000000>,    <&pclk_pmu_pre 100000000>,
 532                         <&clk_cs 300000000>,            <&clkin_trace 300000000>,
 533                         <&aclk_cci 600000000>,          <&clk_mac 50000000>,
 534                         <&aclk_vio0 400000000>,         <&hclk_vio 100000000>,
 535                         <&aclk_rga_pre 400000000>,      <&clk_rga 400000000>,
 536                         <&clk_isp 400000000>,           <&clk_edp 200000000>,
 537                         <&clk_gpu_core 400000000>,      <&aclk_gpu_mem 400000000>,
 538                         <&aclk_gpu_cfg 400000000>,      <&aclk_vepu 400000000>,
 539                         <&aclk_vdpu 400000000>,         <&clk_hevc_core 300000000>,
 540                         <&clk_hevc_cabac 300000000>;
 541 /*
 542                 rockchip,clocks-uboot-has-init =
 543                         <&aclk_vio0>;
 544 */
 545         };
 546
 547         rockchip_clocks_enable: clocks-enable {
 548                 compatible = "rockchip,clocks-enable";
 549                 clocks =
 550                         /*PLL*/
 551                         <&clk_apllb>,
 552                         <&clk_aplll>,
 553                         <&clk_dpll>,
 554                         <&clk_gpll>,
 555                         <&clk_cpll>,
 556
 557                         /*PD_CORE*/
 558                         <&clk_cs>,
 559                         <&clkin_trace>,
 560
 561                         /*PD_BUS*/
 562                         <&aclk_bus>,
 563                         <&hclk_bus>,
 564                         <&pclk_bus>,
 565                         <&clk_gates12 12>,/*aclk_strc_sys*/
 566                         <&clk_gates12 6>,/*aclk_intmem1*/
 567                         <&clk_gates12 5>,/*aclk_intmem0*/
 568                         <&clk_gates12 4>,/*aclk_intmem*/
 569                         <&clk_gates13 9>,/*aclk_gic400*/
 570
 571                         /*PD_ALIVE*/
 572                         <&clk_gates22 13>,/*pclk_timer1*/
 573                         <&clk_gates22 12>,/*pclk_timer0*/
 574                         <&clk_gates22 9>,/*pclk_alive_niu*/
 575                         <&clk_gates22 8>,/*pclk_grf*/
 576
 577                         /*PD_PMU*/
 578                         <&clk_gates23 5>,/*pclk_pmugrf*/
 579                         <&clk_gates23 3>,/*pclk_sgrf*/
 580                         <&clk_gates23 2>,/*pclk_pmu_noc*/
 581                         <&clk_gates23 1>,/*pclk_intmem1*/
 582                         <&clk_gates23 0>,/*pclk_pmu*/
 583
 584                         /*PD_PERI*/
 585                         <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
 586                         <&clk_gates20 8>,/*aclk_peri_niu*/
 587                         <&clk_gates21 4>,/*aclk_peri_mmu*/
 588                         <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
 589                         <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
 590                         <&clk_gates19 1>;/*pclk_peri_axi_matrix*/
 591         };
 592
 593         /* I2C_PMU */
 594         i2c0: i2c@ff650000 {
 595                 compatible = "rockchip,rk30-i2c";
 596                 reg = <0x0 0xff650000 0x0 0x1000>;
 597                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 598                 #address-cells = <1>;
 599                 #size-cells = <0>;
 600                 pinctrl-names = "default", "gpio";
 601                 pinctrl-0 = <&i2c0_xfer>;
 602                 pinctrl-1 = <&i2c0_gpio>;
 603                 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
 604                 clocks = <&clk_gates12 2>;
 605                 rockchip,check-idle = <1>;
 606                 status = "disabled";
 607         };
 608
 609         /* I2C_AUDIO */
 610         i2c1: i2c@ff660000 {
 611                 compatible = "rockchip,rk30-i2c";
 612                 reg = <0x0 0xff660000 0x0 0x1000>;
 613                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 614                 #address-cells = <1>;
 615                 #size-cells = <0>;
 616                 pinctrl-names = "default", "gpio";
 617                 pinctrl-0 = <&i2c1_xfer>;
 618                 pinctrl-1 = <&i2c1_gpio>;
 619                 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
 620                 clocks = <&clk_gates12 3>;
 621                 rockchip,check-idle = <1>;
 622                 status = "disabled";
 623         };
 624
 625         /* I2C_SENSOR */
 626         i2c2: i2c@ff140000 {
 627                 compatible = "rockchip,rk30-i2c";
 628                 reg = <0x0 0xff140000 0x0 0x1000>;
 629                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 630                 #address-cells = <1>;
 631                 #size-cells = <0>;
 632                 pinctrl-names = "default", "gpio";
 633                 pinctrl-0 = <&i2c2_xfer>;
 634                 pinctrl-1 = <&i2c2_gpio>;
 635                 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
 636                 clocks = <&clk_gates19 11>;
 637                 rockchip,check-idle = <1>;
 638                 status = "disabled";
 639         };
 640
 641         /* I2C_CAM */
 642         i2c3: i2c@ff150000 {
 643                 compatible = "rockchip,rk30-i2c";
 644                 reg = <0x0 0xff150000 0x0 0x1000>;
 645                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 646                 #address-cells = <1>;
 647                 #size-cells = <0>;
 648                 pinctrl-names = "default", "gpio";
 649                 pinctrl-0 = <&i2c3_xfer>;
 650                 pinctrl-1 = <&i2c3_gpio>;
 651                 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
 652                 clocks = <&clk_gates19 12>;
 653                 rockchip,check-idle = <1>;
 654                 status = "disabled";
 655         };
 656
 657         /* I2C_TP */
 658         i2c4: i2c@ff160000 {
 659                 compatible = "rockchip,rk30-i2c";
 660                 reg = <0x0 0xff160000 0x0 0x1000>;
 661                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 662                 #address-cells = <1>;
 663                 #size-cells = <0>;
 664                 pinctrl-names = "default", "gpio";
 665                 pinctrl-0 = <&i2c4_xfer>;
 666                 pinctrl-1 = <&i2c4_gpio>;
 667                 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
 668                 clocks = <&clk_gates19 13>;
 669                 rockchip,check-idle = <1>;
 670                 status = "disabled";
 671         };
 672
 673         /* I2C_HDMI */
 674         i2c5: i2c@ff170000 {
 675                 compatible = "rockchip,rk30-i2c";
 676                 reg = <0x0 0xff170000 0x0 0x1000>;
 677                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 678                 #address-cells = <1>;
 679                 #size-cells = <0>;
 680                 pinctrl-names = "default", "gpio";
 681                 pinctrl-0 = <&i2c5_xfer>;
 682                 pinctrl-1 = <&i2c5_gpio>;
 683                 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
 684                 clocks = <&clk_gates19 14>;
 685                 rockchip,check-idle = <1>;
 686                 status = "disabled";
 687         };
 688
 689         fb: fb {
 690                 compatible = "rockchip,rk-fb";
 691                 rockchip,disp-mode = <NO_DUAL>;
 692         };
 693
 694
 695         rk_screen: rk_screen {
 696                 compatible = "rockchip,screen";
 697         };
 698
 699         dsihost0: mipi@ff960000{
 700                 compatible = "rockchip,rk3368-dsi";
 701                 rockchip,prop = <0>;
 702                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 703                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 704                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 705                 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>;
 706                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 707                 status = "okay";
 708         };
 709
 710         lvds: lvds@ff968000 {
 711                 compatible = "rockchip,rk3368-lvds";
 712                 rockchip,grf = <&grf>;
 713                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
 714                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 715                 clocks = <&clk_gates22 10>, <&clk_gates17 3>;
 716                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 717                 status = "disabled";
 718         };
 719
 720         edp: edp@ff970000 {
 721                 compatible = "rockchip,rk32-edp";
 722                 reg = <0x0 0xff970000 0x0 0x4000>;
 723                 rockchip,grf = <&grf>;
 724                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 725                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
 726                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 727                 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
 728                 reset-names = "edp_24m", "edp_apb";
 729         };
 730
 731         hdmi: hdmi@ff980000 {
 732                 compatible = "rockchip,rk3368-hdmi";
 733                 reg = <0x0 0xff980000 0x0 0x20000>;
 734                 rockchip,grf = <&grf>;
 735                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 736                 pinctrl-names = "default", "gpio";
 737                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 738                 pinctrl-1 = <&i2c5_gpio>;
 739                 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
 740                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 741                 status = "disabled";
 742         };
 743
 744         hdmi_hdcp2: hdmi_hdcp2@ff978000 {
 745                 compatible = "rockchip,rk3368-hdmi-hdcp2";
 746                 reg = <0x0 0xff978000 0x0 0x2000>;
 747                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 748                 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
 749                 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
 750                 status = "disabled";
 751         };
 752
 753         lcdc: lcdc@ff930000 {
 754                  compatible = "rockchip,rk3368-lcdc";
 755                  rockchip,grf = <&grf>;
 756                  rockchip,pmugrf = <&pmugrf>;
 757                  rockchip,prop = <PRMRY>;
 758                  rockchip,pwr18 = <0>;
 759                  rockchip,iommu-enabled = <0>;
 760                  reg = <0x0 0xff930000 0x0 0x10000>;
 761                  interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 762                 /*pinctrl-names = "default", "gpio";
 763                  *pinctrl-0 = <&lcdc_lcdc>;
 764                  *pinctrl-1 = <&lcdc_gpio>;
 765                  */
 766                  status = "disabled";
 767                  clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
 768                  clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
 769         };
 770
 771         adc: adc@ff100000 {
 772                 compatible = "rockchip,saradc";
 773                 reg = <0x0 0xff100000 0x0 0x100>;
 774                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 775                 #io-channel-cells = <1>;
 776                 io-channel-ranges;
 777                 rockchip,adc-vref = <1800>;
 778                 clock-frequency = <1000000>;
 779                 clocks = <&clk_saradc>, <&clk_gates19 15>;
 780                 clock-names = "saradc", "pclk_saradc";
 781                 status = "disabled";
 782         };
 783
 784         rga@ff920000 {
 785                 compatible = "rockchip,rk3368-rga2";
 786                 reg = <0x0 0xff920000 0x0 0x1000>;
 787                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 788                 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
 789                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 790         };
 791
 792         i2s0: i2s0@ff898000 {
 793                 compatible = "rockchip-i2s";
 794                 reg = <0x0 0xff898000 0x0 0x1000>;
 795                 i2s-id = <0>;
 796                 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
 797                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 798                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 799                 dmas = <&pdma0 0>, <&pdma0 1>;
 800                 #dma-cells = <2>;
 801                 dma-names = "tx", "rx";
 802                 pinctrl-names = "default", "sleep";
 803                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 804                 pinctrl-1 = <&i2s_gpio>;
 805         };
 806
 807         i2s1: i2s1@ff890000 {
 808                 compatible = "rockchip-i2s";
 809                 reg = <0x0 0xff890000 0x0 0x1000>;
 810                 i2s-id = <1>;
 811                 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
 812                 clock-names = "i2s_clk", "i2s_hclk";
 813                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 814                 dmas = <&pdma0 6>, <&pdma0 7>;
 815                 #dma-cells = <2>;
 816                 dma-names = "tx", "rx";
 817         };
 818
 819         spdif: spdif@ff880000 {
 820                 compatible = "rockchip-spdif";
 821                 reg = <0x0 0xff880000 0x0 0x1000>;
 822                 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
 823                 clock-names = "spdif_mclk", "spdif_hclk";
 824                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 825                 dmas = <&pdma0 3>;
 826                 #dma-cells = <1>;
 827                 dma-names = "tx";
 828                 pinctrl-names = "default";
 829                 pinctrl-0 = <&spdif_tx>;
 830         };
 831
 832         pwm0: pwm@ff680000 {
 833                 compatible = "rockchip,rk-pwm";
 834                 reg = <0x0 0xff680000 0x0 0x10>;
 835                 #pwm-cells = <2>;
 836                 pinctrl-names = "default";
 837                 pinctrl-0 = <&pwm0_pin>;
 838                 clocks = <&clk_gates13 6>;
 839                 clock-names = "pclk_pwm";
 840                 status = "disabled";
 841         };
 842
 843         pwm1: pwm@ff680010 {
 844                 compatible = "rockchip,rk-pwm";
 845                 reg = <0x0 0xff680010 0x0 0x10>;
 846                 #pwm-cells = <2>;
 847                 pinctrl-names = "default";
 848                 pinctrl-0 = <&pwm1_pin>;
 849                 clocks = <&clk_gates13 6>;
 850                 clock-names = "pclk_pwm";
 851                 status = "disabled";
 852         };
 853
 854         pwm2: pwm@ff680020 {
 855                 compatible = "rockchip,rk-pwm";
 856                 reg = <0x0 0xff680020 0x0 0x10>;
 857                 #pwm-cells = <2>;
 858                 //pinctrl-names = "default";
 859                 //pinctrl-0 = <&pwm1_pin>;
 860                 clocks = <&clk_gates13 6>;
 861                 clock-names = "pclk_pwm";
 862                 status = "disabled";
 863         };
 864
 865         pwm3: pwm@ff680030 {
 866                 compatible = "rockchip,rk-pwm";
 867                 reg = <0x0 0xff680030 0x0 0x10>;
 868                 #pwm-cells = <2>;
 869                 pinctrl-names = "default";
 870                 pinctrl-0 = <&pwm3_pin>;
 871                 clocks = <&clk_gates13 6>;
 872                 clock-names = "pclk_pwm";
 873                 status = "disabled";
 874         };
 875
 876         remotectl: pwm@ff680030 {
 877                 compatible = "rockchip,remotectl-pwm";
 878                 reg = <0x0 0xff680030 0x0 0x50>;
 879                 #pwm-cells = <2>;
 880                 pinctrl-names = "default";
 881                 pinctrl-0 = <&pwm3_pin>;
 882                 clocks = <&clk_gates13 6>;
 883                 clock-names = "pclk_pwm";
 884                 dmas = <&pdma0 2>;
 885                 #dma-cells = <2>;
 886                 dma-names = "rx";
 887                 remote_pwm_id = <3>;
 888                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 889                 status = "disabled";
 890         };
 891
 892         voppwm: pwm@ff9301a0 {
 893                 compatible = "rockchip,vop-pwm";
 894                 reg = <0x0 0xff9301a0 0x0 0x10>;
 895                 #pwm-cells = <2>;
 896                 pinctrl-names = "default";
 897                 pinctrl-0 = <&vop_pwm_pin>;
 898                 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
 899                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 900                 status = "disabled";
 901         };
 902
 903         pvtm {
 904                 compatible = "rockchip,rk3368-pvtm";
 905                 rockchip,grf = <&grf>;
 906         };
 907
 908         cpufreq {
 909                 compatible = "rockchip,rk3368-cpufreq";
 910                 rockchip,grf = <&grf>;
 911         };
 912
 913         dvfs {
 914
 915                 vd_arm: vd_arm {
 916                         regulator_name = "vdd_arm";
 917                         suspend_volt = <1000>; //mV
 918                         pd_core {
 919                                 clk_core_b_dvfs_table: clk_core_b {
 920                                         operating-points = <
 921                                                 /* KHz    uV */
 922                                                 312000 1200000
 923                                                 504000 1200000
 924                                                 816000 1200000
 925                                                 1008000 1200000
 926                                                 >;
 927                                         status = "okay";
 928                                 };
 929                                 clk_core_l_dvfs_table: clk_core_l {
 930                                         operating-points = <
 931                                                 /* KHz    uV */
 932                                                 312000 1200000
 933                                                 504000 1200000
 934                                                 816000 1200000
 935                                                 1008000 1200000
 936                                                 >;
 937                                         status = "okay";
 938                                 };
 939                         };
 940                 };
 941
 942                 vd_logic: vd_logic {
 943                         regulator_name = "vdd_logic";
 944                         suspend_volt = <1000>; //mV
 945                         pd_ddr {
 946                                 clk_ddr_dvfs_table: clk_ddr {
 947                                         operating-points = <
 948                                                 /* KHz    uV */
 949                                                 200000 1200000
 950                                                 300000 1200000
 951                                                 400000 1200000
 952                                                 >;
 953                                         channel = <2>;
 954                                         status = "disabled";
 955                                 };
 956                         };
 957
 958                         pd_gpu {
 959                                 clk_gpu_dvfs_table: clk_gpu {
 960                                         operating-points = <
 961                                                 /* KHz    uV */
 962                                                 200000 1200000
 963                                                 300000 1200000
 964                                                 400000 1200000
 965                                                 >;
 966                                         channel = <1>;
 967                                         status = "okay";
 968                                         regu-mode-table = <
 969                                                 /*freq     mode*/
 970                                                 200000     4
 971                                                 0          3
 972                                         >;
 973                                         regu-mode-en = <0>;
 974                                 };
 975                         };
 976                 };
 977         };
 978
 979         ion {
 980                 compatible = "rockchip,ion";
 981                 #address-cells = <1>;
 982                 #size-cells = <0>;
 983
 984                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
 985                         compatible = "rockchip,ion-heap";
 986                         rockchip,ion_heap = <4>;
 987                         reg = <0x00000000 0x08000000>; /* 512MB */
 988                 };
 989                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
 990                         compatible = "rockchip,ion-heap";
 991                         rockchip,ion_heap = <0>;
 992                 };
 993         };
 994
 995         vpu: vpu_service {
 996                 compatible = "rockchip,vpu_sub";
 997                 iommu_enabled = <0>;
 998                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 999                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1000                 interrupt-names = "irq_enc", "irq_dec";
1001                 dev_mode = <0>;
1002                 name = "vpu_service";
1003         };
1004
1005         hevc: hevc_service {
1006                 compatible = "rockchip,hevc_sub";
1007                 iommu_enabled = <0>;
1008                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1009                 interrupts-names = "irq_dec";
1010                 dev_mode = <1>;
1011                 name = "hevc_service";
1012         };
1013
1014         vpu_combo: vpu_combo@ff9a0000 {
1015                 compatible = "rockchip,vpu_combo";
1016                 reg = <0x0 0xff9a0000 0x0 0x800>;
1017                 rockchip,grf = <&grf>;
1018                 subcnt = <2>;
1019                 rockchip,sub = <&vpu>, <&hevc>;
1020                 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1021                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1022                 mode_bit = <12>;
1023                 mode_ctrl = <0x418>;
1024                 name = "vpu_combo";
1025                 status = "okay";
1026         };
1027
1028         iep: iep@ff900000 {
1029                 compatible = "rockchip,iep";
1030                 iommu_enabled = <0>;
1031                 reg = <0x0 0xff900000 0x0 0x800>;
1032                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1033                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1034                 clock-names = "aclk_iep", "hclk_iep";
1035                 status = "okay";
1036         };
1037
1038         gmac: eth@ff290000 {
1039                 compatible = "rockchip,rk3368-gmac";
1040                 reg = <0x0 0xff290000 0x0 0x10000>;
1041                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1042                 interrupt-names = "macirq";
1043
1044                 clocks = <&clk_mac>, <&clk_gates5 0>,
1045                          <&clk_gates5 1>, <&clk_gates5 2>,
1046                          <&clk_gates5 3>, <&clk_gates8 0>,
1047                          <&clk_gates8 1>;
1048                 clock-names = "clk_mac", "mac_clk_rx",
1049                               "mac_clk_tx", "clk_mac_ref",
1050                               "clk_mac_refout", "aclk_mac",
1051                               "pclk_mac";
1052
1053                 phy-mode = "rgmii";
1054                 pinctrl-names = "default";
1055                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1056         };
1057
1058         gpu {
1059                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1060                 reg = <0x0 0xffa30000 0x0 0x10000>;
1061                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1062                 interrupt-names = "GPU";
1063         };
1064
1065         iep_mmu {
1066                 dbgname = "iep";
1067                 compatible = "rockchip,iep_mmu";
1068                 reg = <0x0 0xff900800 0x0 0x100>;
1069                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1070                 interrupt-names = "iep_mmu";
1071         };
1072
1073         vip_mmu {
1074                 dbgname = "vip";
1075                 compatible = "rockchip,vip_mmu";
1076                 reg = <0x0 0xff950800 0x0 0x100>;
1077                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1078                 interrupt-names = "vip_mmu";
1079         };
1080
1081         vop_mmu {
1082                 dbgname = "vop";
1083                 compatible = "rockchip,vop_mmu";
1084                 reg = <0x0 0xff930300 0x0 0x100>;
1085                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1086                 interrupt-names = "vop_mmu";
1087         };
1088
1089         isp_mmu {
1090                 dbgname = "isp_mmu";
1091                 compatible = "rockchip,isp_mmu";
1092                 reg = <0x0 0xff914000 0x0 0x100>,
1093                 <0x0 0xff915000 0x0 0x100>;
1094                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1095                 interrupt-names = "isp_mmu";
1096         };
1097
1098         hdcp_mmu {
1099                 dbgname = "hdcp_mmu";
1100                 compatible = "rockchip,hdcp_mmu";
1101                 reg = <0x0 0xff940000 0x0 0x100>;
1102                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1103                 interrupt-names = "hdcp_mmu";
1104         };
1105
1106         hevc_mmu {
1107                 dbgname = "hevc";
1108                 compatible = "rockchip,hevc_mmu";
1109                 reg = <0x0 0xff9c0440 0x0 0x40>,                      /*need to fix*/
1110                           <0x0 0xff9c0480 0x0 0x40>;
1111                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;        /*need to fix*/
1112                 interrupt-names = "hevc_mmu";
1113         };
1114
1115         vpu_mmu {
1116                 dbgname = "vpu";
1117                 compatible = "rockchip,vpu_mmu";
1118                 reg = <0x0 0xff9a0800 0x0 0x100>;                    /*need to fix*/
1119                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;       /*need to fix*/
1120                 interrupt-names = "vpu_mmu";
1121         };
1122
1123         rockchip_suspend {
1124                 rockchip,ctrbits = <
1125                         (0
1126                          |RKPM_CTR_PWR_DMNS
1127                          |RKPM_CTR_GTCLKS
1128                          |RKPM_CTR_PLLS
1129                          |RKPM_CTR_GPIOS
1130                         /*
1131                          |RKPM_CTR_SYSCLK_DIV
1132                          |RKPM_CTR_IDLEAUTO_MD
1133                          |RKPM_CTR_ARMOFF_LPMD
1134                         */
1135                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1136                         )
1137                         >;
1138                 rockchip,pmic-suspend_gpios = <
1139                                  /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1140                         >;
1141                 rockchip,pmic-resume_gpios = <
1142                                 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1143                         >;
1144         };
1145
1146         isp: isp@ff910000{
1147                 compatible = "rockchip,isp";
1148                 reg = <0x0 0xff910000 0x0 0x10000>;
1149                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1150                 clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
1151                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
1152                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1153                 pinctrl-0 = <&cif_clkout>;
1154                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1155                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1156                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1157                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1158                 pinctrl-5 = <&cif_clkout>;
1159                 pinctrl-6 = <&cif_clkout &isp_prelight>;
1160                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1161                 pinctrl-8 = <&isp_flash_trigger>;
1162                 rockchip,isp,mipiphy = <2>;
1163                 rockchip,isp,cifphy = <1>;
1164                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1165                 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1166                 rockchip,isp,iommu_enable = <1>;
1167                 status = "okay";
1168         };
1169
1170         tsadc: tsadc@ff280000 {
1171                 compatible = "rockchip,tsadc";
1172                 reg = <0x0 0xff280000 0x0 0x100>;
1173                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1174                 #io-channel-cells = <1>;
1175                 io-channel-ranges;
1176                 clock-frequency = <10000>;
1177                 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1178                 clock-names = "tsadc", "pclk_tsadc";
1179                 pinctrl-names = "default", "tsadc_int";
1180                 pinctrl-0 = <&tsadc_gpio>;
1181                 pinctrl-1 = <&tsadc_int>;
1182                 tsadc-ht-temp = <120>;
1183                 tsadc-ht-reset-cru = <1>;
1184                 tsadc-ht-pull-gpio = <0>;
1185                 status = "disabled";
1186         };
1187
1188         tsp: tsp@FF8B0000 {
1189                 compatible = "rockchip,rk3368-tsp";
1190                 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1191                 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1192                 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1193                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1194                 interrupt-names = "irq_tsp";
1195                 // pinctrl-names = "default";
1196                 // pinctrl-0 = <&isp_hsadc>;
1197                 status = "okay";
1198         };
1199
1200         crypto: crypto@FF8A0000{
1201                 compatible = "rockchip,rk3368-crypto";
1202                 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1203                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1204                 interrupt-names = "irq_crypto";
1205                         clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1206                 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1207                 status = "okay";
1208         };
1209
1210         dwc_control_usb: dwc-control-usb {
1211                 compatible = "rockchip,rk3368-dwc-control-usb";
1212                 rockchip,grf = <&grf>;
1213                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1214                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1215                 interrupt-names = "otg_id", "otg_bvalid",
1216                                   "otg_linestate", "host0_linestate";
1217                 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1218                 clock-names = "hclk_usb_peri", "usbphy_480m";
1219                 //resets = <&reset RK3128_RST_USBPOR>;
1220                 //reset-names = "usbphy_por";
1221                 usb_bc{
1222                         compatible = "inno,phy";
1223                         regbase = &dwc_control_usb;
1224                         rk_usb,bvalid     = <0x4bc 23 1>;
1225                         rk_usb,iddig      = <0x4bc 26 1>;
1226                         rk_usb,vdmsrcen   = <0x718 12 1>;
1227                         rk_usb,vdpsrcen   = <0x718 11 1>;
1228                         rk_usb,rdmpden    = <0x718 10 1>;
1229                         rk_usb,idpsrcen   = <0x718  9 1>;
1230                         rk_usb,idmsinken  = <0x718  8 1>;
1231                         rk_usb,idpsinken  = <0x718  7 1>;
1232                         rk_usb,dpattach   = <0x4b8 31 1>;
1233                         rk_usb,cpdet      = <0x4b8 30 1>;
1234                         rk_usb,dcpattach  = <0x4b8 29 1>;
1235                 };
1236         };
1237
1238         usb0: usb@ff580000 {
1239                 compatible = "rockchip,rk3368_usb20_otg";
1240                 reg = <0x0 0xff580000 0x0 0x40000>;
1241                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1242                 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1243                 clock-names = "clk_usbphy0", "hclk_otg";
1244                 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1245                                 <&reset RK3368_SRST_USBOTGC0>;
1246                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1247                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1248                 rockchip,usb-mode = <0>;
1249         };
1250
1251         usb_ehci: usb@ff500000 {
1252                 compatible = "generic-ehci";
1253                 reg = <0x0 0xff500000 0x0 0x20000>;
1254                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1255                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1256                 clock-names = "clk_usbphy0", "hclk_ehci";
1257                 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1258                 //              <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1259                 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1260         };
1261
1262         usb_ohci: usb@ff520000 {
1263                 compatible = "generic-ohci";
1264                 reg = <0x0 0xff520000 0x0 0x20000>;
1265                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1266                 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1267                 clock-names =  "clk_usbphy0", "hclk_ohci";
1268         };
1269
1270         usb_hsic: usb@ff5c0000 {
1271                 compatible = "rockchip,rk3288_rk_hsic_host";
1272                 reg = <0x0 0xff5c0000 0x0 0x40000>;
1273                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1274 /*
1275                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1276                          <&hsicphy_12m>, <&usbphy_480m>,
1277                          <&otgphy1_480m>, <&otgphy2_480m>;
1278                 clock-names = "hsicphy_480m", "hclk_hsic",
1279                               "hsicphy_12m", "usbphy_480m",
1280                               "hsic_usbphy1", "hsic_usbphy2";
1281                 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1282                                 <&reset RK3288_SOFT_RST_HSICPHY>;
1283                 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1284 */
1285                 status = "disabled";
1286         };
1287
1288         pinctrl: pinctrl {
1289                 compatible = "rockchip,rk3368-pinctrl";
1290                 rockchip,grf = <&grf>;
1291                 rockchip,pmugrf = <&pmugrf>;
1292                 #address-cells = <2>;
1293                 #size-cells = <2>;
1294                 ranges;
1295
1296                 gpio0: gpio0@ff750000 {
1297                         compatible = "rockchip,gpio-bank";
1298                         reg =   <0x0 0xff750000 0x0 0x100>;
1299                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1300                         clocks = <&clk_gates23 4>;
1301
1302                         gpio-controller;
1303                         #gpio-cells = <2>;
1304
1305                         interrupt-controller;
1306                         #interrupt-cells = <2>;
1307                 };
1308
1309                 gpio1: gpio1@ff780000 {
1310                         compatible = "rockchip,gpio-bank";
1311                         reg = <0x0 0xff780000 0x0 0x100>;
1312                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1313                         clocks = <&clk_gates22 1>;
1314
1315                         gpio-controller;
1316                         #gpio-cells = <2>;
1317
1318                         interrupt-controller;
1319                         #interrupt-cells = <2>;
1320                 };
1321
1322                 gpio2: gpio2@ff790000 {
1323                         compatible = "rockchip,gpio-bank";
1324                         reg = <0x0 0xff790000 0x0 0x100>;
1325                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1326                         clocks = <&clk_gates22 2>;
1327
1328                         gpio-controller;
1329                         #gpio-cells = <2>;
1330
1331                         interrupt-controller;
1332                         #interrupt-cells = <2>;
1333                 };
1334
1335                 gpio3: gpio3@ff7a0000 {
1336                         compatible = "rockchip,gpio-bank";
1337                         reg = <0x0 0xff7a0000 0x0 0x100>;
1338                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1339                         clocks = <&clk_gates22 3>;
1340
1341                         gpio-controller;
1342                         #gpio-cells = <2>;
1343
1344                         interrupt-controller;
1345                         #interrupt-cells = <2>;
1346                 };
1347
1348                 pcfg_pull_up: pcfg-pull-up {
1349                         bias-pull-up;
1350                 };
1351
1352                 pcfg_pull_down: pcfg-pull-down {
1353                         bias-pull-down;
1354                 };
1355
1356                 pcfg_pull_none: pcfg-pull-none {
1357                         bias-disable;
1358                 };
1359
1360                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1361                         drive-strength = <8>;
1362                 };
1363
1364                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1365                         bias-pull-up;
1366                         drive-strength = <8>;
1367                 };
1368
1369                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1370                         drive-strength = <4>;
1371                 };
1372
1373                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1374                         bias-pull-up;
1375                         drive-strength = <4>;
1376                 };
1377
1378                 pcfg_output_high: pcfg-output-high {
1379                         output-high;
1380                 };
1381
1382                 pcfg_output_low: pcfg-output-low {
1383                         output-low;
1384                 };
1385
1386                 i2c0 {
1387                         i2c0_xfer: i2c0-xfer {
1388                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1389                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1390                         };
1391                         i2c0_gpio: i2c0-gpio {
1392                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1393                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1394                         };
1395                 };
1396
1397                 i2c1 {
1398                         i2c1_xfer: i2c1-xfer {
1399                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1400                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1401                         };
1402                         i2c1_gpio: i2c1-gpio {
1403                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1404                                                 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1405                         };
1406                 };
1407
1408                 i2c2 {
1409                         i2c2_xfer: i2c2-xfer {
1410                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1411                                                 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1412                         };
1413                         i2c2_gpio: i2c2-gpio {
1414                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1415                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1416             };
1417                 };
1418
1419                 i2c3 {
1420                         i2c3_xfer: i2c3-xfer {
1421                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1422                                                 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1423                         };
1424                         i2c3_gpio: i2c3-gpio {
1425                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1426                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1427                         };
1428                 };
1429
1430                 i2c4 {
1431                         i2c4_xfer: i2c4-xfer {
1432                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1433                                                 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1434                         };
1435                         i2c4_gpio: i2c4-gpio {
1436                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1437                                                 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1438                         };
1439                 };
1440
1441                 i2c5 {
1442                         i2c5_xfer: i2c5-xfer {
1443                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1444                                                 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1445                         };
1446                         i2c5_gpio: i2c5-gpio {
1447                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1448                                                 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1449                         };
1450                 };
1451
1452                 uart0 {
1453                         uart0_xfer: uart0-xfer {
1454                                 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1455                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1456                         };
1457
1458                         uart0_cts: uart0-cts {
1459                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1460                         };
1461
1462                         uart0_rts: uart0-rts {
1463                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1464                         };
1465
1466                         uart0_rts_gpio: uart0-rts-gpio {
1467                                 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1468                         };
1469                 };
1470
1471                 uart1 {
1472                         uart1_xfer: uart1-xfer {
1473                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1474                                                 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1475                         };
1476
1477                         uart1_cts: uart1-cts {
1478                                 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1479                         };
1480
1481                         uart1_rts: uart1-rts {
1482                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1483                         };
1484                 };
1485
1486                 uart2 {
1487                         uart2_xfer: uart2-xfer {
1488                                 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1489                                                 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1490                         };
1491                 };
1492
1493                 uart3 {
1494                         uart3_xfer: uart3-xfer {
1495                                 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1496                                                 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1497                         };
1498
1499                         uart3_cts: uart3-cts {
1500                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1501                         };
1502
1503                         uart3_rts: uart3-rts {
1504                                 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1505                         };
1506                 };
1507
1508                 uart4 {
1509                         uart4_xfer: uart4-xfer {
1510                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1511                                                 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1512                         };
1513
1514                         uart4_cts: uart4-cts {
1515                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1516                         };
1517
1518                         uart4_rts: uart4-rts {
1519                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1520                         };
1521                 };
1522
1523                 spi0 {
1524                         spi0_clk: spi0-clk {
1525                                 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1526                         };
1527                         spi0_cs0: spi0-cs0 {
1528                                 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1529                         };
1530                         spi0_tx: spi0-tx {
1531                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1532                         };
1533                         spi0_rx: spi0-rx {
1534                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1535                         };
1536                         spi0_cs1: spi0-cs1 {
1537                                 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1538                         };
1539                 };
1540
1541                 spi1 {
1542                         spi1_clk: spi1-clk {
1543                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1544                         };
1545                         spi1_cs0: spi1-cs0 {
1546                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1547                         };
1548                         spi1_rx: spi1-rx {
1549                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1550                         };
1551                         spi1_tx: spi1-tx {
1552                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1553                         };
1554                 };
1555
1556                 spi2 {
1557                         spi2_clk: spi2-clk {
1558                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1559                         };
1560                         spi2_cs0: spi2-cs0 {
1561                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1562                         };
1563                         spi2_rx: spi2-rx {
1564                                 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1565                         };
1566                         spi2_tx: spi2-tx {
1567                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1568                         };
1569                 };
1570
1571                 i2s {
1572                         i2s_mclk: i2s-mclk {
1573                                 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1574                         };
1575
1576                         i2s_sclk:i2s-sclk {
1577                                 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1578                         };
1579
1580                         i2s_lrckrx:i2s-lrckrx {
1581                                 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1582                         };
1583
1584                         i2s_lrcktx:i2s-lrcktx {
1585                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1586                         };
1587
1588                         i2s_sdi:i2s-sdi {
1589                                 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1590                         };
1591
1592                         i2s_sdo0:i2s-sdo0 {
1593                                 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1594                         };
1595
1596                         i2s_sdo1:i2s-sdo1 {
1597                                 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1598                         };
1599
1600                         i2s_sdo2:i2s-sdo2 {
1601                                 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1602                         };
1603
1604                         i2s_sdo3:i2s-sdo3 {
1605                                 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1606                         };
1607
1608                         i2s_gpio: i2s-gpio {
1609                                 rockchip,pins = <2 GPIO_C4  RK_FUNC_GPIO &pcfg_pull_none>,
1610                                                 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1611                                                 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1612                                                 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1613                                                 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1614                                                 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1615                                                 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1616                                                 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1617                                                 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1618                         };
1619                 };
1620
1621                 spdif {
1622                         spdif_tx: spdif-tx {
1623                                 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1624                         };
1625                 };
1626
1627                 sdmmc {
1628                         sdmmc_clk: sdmmc-clk {
1629                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1630                         };
1631
1632                         sdmmc_cmd: sdmmc-cmd {
1633                                 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1634                         };
1635
1636                         sdmmc_dectn: sdmmc-dectn {
1637                                 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1638                         };
1639
1640                         sdmmc_bus1: sdmmc-bus1 {
1641                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1642                         };
1643
1644                         sdmmc_bus4: sdmmc-bus4 {
1645                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1646                                                 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1647                                                 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1648                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1649                         };
1650
1651                         sdmmc_gpio: sdmmc-gpio {
1652                                 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1653                                                 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1654                                                 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1655                                                 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1656                                                 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1657                                                 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1658                                                 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1659                         };
1660                 };
1661
1662                 sdio0 {
1663                         sdio0_bus1: sdio0-bus1 {
1664                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1665                         };
1666
1667                         sdio0_bus4: sdio0-bus4 {
1668                                 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1669                                                 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1670                                                 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1671                                                 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1672                         };
1673
1674                         sdio0_cmd: sdio0-cmd {
1675                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1676                         };
1677
1678                         sdio0_clk: sdio0-clk {
1679                                 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1680                         };
1681
1682                         sdio0_dectn: sdio0-dectn {
1683                                 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1684                         };
1685
1686                         sdio0_wrprt: sdio0-wrprt {
1687                                 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1688                         };
1689
1690                         sdio0_pwren: sdio0-pwren {
1691                                 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1692                         };
1693
1694                         sdio0_bkpwr: sdio0-bkpwr {
1695                                 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1696                         };
1697
1698                         sdio0_int: sdio0-int {
1699                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1700                         };
1701
1702                         sdio0_gpio: sdio0-gpio {
1703                                 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1704                                                 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1705                                                 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1706                                                 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1707                                                 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1708                                                 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1709                                                 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1710                                                 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1711                                                 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1712                                                 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1713                                                 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1714                         };
1715                 };
1716
1717                 emmc {
1718                         emmc_clk: emmc-clk {
1719                                 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1720                         };
1721
1722                         emmc_cmd: emmc-cmd {
1723                                 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1724                         };
1725
1726                         emmc_pwren: emmc-pwren {
1727                                 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1728                         };
1729
1730                         emmc_rstnout: emmc_rstnout {
1731                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1732                         };
1733
1734                         emmc_bus1: emmc-bus1 {
1735                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1736                         };
1737
1738                         emmc_bus4: emmc-bus4 {
1739                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1740                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1741                                                 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1742                                                 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1743                         };
1744                 };
1745
1746                 pwm0 {
1747                         pwm0_pin: pwm0-pin {
1748                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1749                         };
1750
1751                         vop_pwm_pin:vop-pwm {
1752                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1753                         };
1754                 };
1755
1756                 pwm1 {
1757                         pwm1_pin: pwm1-pin {
1758                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1759                         };
1760                 };
1761
1762                 pwm3 {
1763                         pwm3_pin: pwm3-pin {
1764                                 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1765                         };
1766                 };
1767
1768                 lcdc {
1769                         lcdc_lcdc: lcdc-lcdc {
1770                                 rockchip,pins =
1771                                                 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1772                                                 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1773                                                 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1774                                                 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1775                                                 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1776                                                 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1777                                                 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1778                                                 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1779                                                 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1780                                                 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1781                                                 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1782                                                 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1783                                                 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1784                                                 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1785                                                 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1786                                                 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1787                                                 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1788                                                 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1789                         };
1790
1791                         lcdc_gpio: lcdc-gpio {
1792                                 rockchip,pins =
1793                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1794                                                 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1795                                                 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1796                                                 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1797                                                 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1798                                                 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1799                                                 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1800                                                 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1801                                                 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1802                                                 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1803                                                 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1804                                                 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1805                                                 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1806                                                 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1807                                                 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1808                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1809                                                 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1810                                                 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1811                         };
1812                 };
1813
1814                 isp {
1815                         cif_clkout: cif-clkout {
1816                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1817                         };
1818
1819                         isp_dvp_d2d9: isp-dvp-d2d9 {
1820                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1821                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1822                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1823                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1824                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1825                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1826                                                 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1827                                                 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1828                                                 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1829                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1830                                                 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1831                                                 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1832                         };
1833
1834                         isp_dvp_d0d1: isp-dvp-d0d1 {
1835                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1836                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1837                         };
1838
1839                         isp_dvp_d10d11:isp_d10d11       {
1840                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1841                                                 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1842                         };
1843
1844                         isp_dvp_d0d7: isp-dvp-d0d7 {
1845                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1846                                                 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1847                                                 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1848                                                 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1849                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1850                                                 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1851                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1852                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1853                         };
1854
1855                         isp_shutter: isp-shutter {
1856                                 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1857                                                 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1858                         };
1859
1860                         isp_flash_trigger: isp-flash-trigger {
1861                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1862                         };
1863
1864                         isp_prelight: isp-prelight {
1865                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1866                         };
1867
1868                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1869                                 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1870                         };
1871                 };
1872
1873                 gps {
1874                         gps_mag: gps-mag {
1875                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
1876                         };
1877
1878                         gps_sig: gps-sig {
1879                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
1880
1881                         };
1882
1883                         gps_rfclk: gps-rfclk {
1884                                 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
1885                         };
1886                 };
1887
1888                 gmac {
1889                         mac_clk: mac-clk {
1890                                 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1891                         };
1892
1893                         mac_txpins: mac-txpins {
1894                                 rockchip,pins = <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//TXD0
1895                                                 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//TXD1
1896                                                 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//TXD2
1897                                                 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//TXD3
1898                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//TXEN
1899                                                 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;//TXCLK
1900                         };
1901
1902                         mac_rxpins: mac-rxpins {
1903                                 rockchip,pins = <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
1904                                                 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
1905                                                 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
1906                                                 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
1907                                                 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
1908                                                 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//RXER
1909                                                 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
1910                                                 <3 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;//COL
1911                         };
1912
1913                         mac_crs: mac-crs {
1914                                 rockchip,pins = <3 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>; //CRS
1915                         };
1916
1917                         mac_mdpins: mac-mdpins {
1918                                 rockchip,pins = <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
1919                                                 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;//MDC
1920                         };
1921                 };
1922
1923                 tsadc_pin {
1924                         tsadc_int: tsadc-int {
1925                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
1926                         };
1927                         tsadc_gpio: tsadc-gpio {
1928                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
1929                         };
1930                 };
1931
1932                 hdmi_pin {
1933                         hdmi_cec: hdmi-cec {
1934                                 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1935                         };
1936                 };
1937
1938                 hdmi_i2c {
1939                         hdmii2c_xfer: hdmii2c-xfer {
1940                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
1941                                                 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1942                         };
1943                 };
1944         };
1945
1946         reboot {
1947                 compatible = "rockchip,rk3368-reboot";
1948                 rockchip,cru = <&cru>;
1949                 rockchip,pmugrf = <&pmugrf>;
1950         };
1951 };