2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3328-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/soc/rockchip_boot-mode.h>
51 compatible = "rockchip,rk3328";
53 interrupt-parent = <&gic>;
73 compatible = "arm,cortex-a53", "arm,armv8";
75 enable-method = "psci";
76 // clocks = <&cru ARMCLK>;
77 operating-points-v2 = <&cpu0_opp_table>;
81 compatible = "arm,cortex-a53", "arm,armv8";
83 enable-method = "psci";
87 compatible = "arm,cortex-a53", "arm,armv8";
89 enable-method = "psci";
93 compatible = "arm,cortex-a53", "arm,armv8";
95 enable-method = "psci";
99 cpu0_opp_table: opp_table0 {
100 compatible = "operating-points-v2";
104 opp-hz = /bits/ 64 <408000000>;
105 opp-microvolt = <950000>;
106 clock-latency-ns = <40000>;
110 opp-hz = /bits/ 64 <600000000>;
111 opp-microvolt = <950000>;
112 clock-latency-ns = <40000>;
115 opp-hz = /bits/ 64 <816000000>;
116 opp-microvolt = <1000000>;
117 clock-latency-ns = <40000>;
120 opp-hz = /bits/ 64 <1008000000>;
121 opp-microvolt = <1100000>;
122 clock-latency-ns = <40000>;
125 opp-hz = /bits/ 64 <1200000000>;
126 opp-microvolt = <1225000>;
127 clock-latency-ns = <40000>;
130 opp-hz = /bits/ 64 <1296000000>;
131 opp-microvolt = <1300000>;
132 clock-latency-ns = <40000>;
137 compatible = "arm,cortex-a53-pmu";
138 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
142 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
146 compatible = "arm,psci-1.0";
151 compatible = "arm,armv8-timer";
152 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
153 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
154 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
155 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
159 compatible = "fixed-clock";
161 clock-frequency = <24000000>;
162 clock-output-names = "xin24m";
166 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
167 reg = <0x0 0xff000000 0x0 0x1000>;
168 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
170 clock-names = "i2s_clk", "i2s_hclk";
171 dmas = <&dmac 11>, <&dmac 12>;
173 dma-names = "tx", "rx";
178 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
179 reg = <0x0 0xff010000 0x0 0x1000>;
180 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
182 clock-names = "i2s_clk", "i2s_hclk";
183 dmas = <&dmac 14>, <&dmac 15>;
185 dma-names = "tx", "rx";
190 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
191 reg = <0x0 0xff020000 0x0 0x1000>;
192 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
193 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
194 clock-names = "i2s_clk", "i2s_hclk";
195 dmas = <&dmac 0>, <&dmac 1>;
197 dma-names = "tx", "rx";
198 pinctrl-names = "default", "sleep";
199 pinctrl-0 = <&i2s2m0_mclk
205 pinctrl-1 = <&i2s2m0_sleep>;
209 spdif: spdif@ff030000 {
210 compatible = "rockchip,rk3328-spdif";
211 reg = <0x0 0xff030000 0x0 0x1000>;
212 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
214 clock-names = "mclk", "hclk";
218 pinctrl-names = "default";
219 pinctrl-0 = <&spdifm2_tx>;
223 grf: syscon@ff100000 {
224 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
225 reg = <0x0 0xff100000 0x0 0x1000>;
226 #address-cells = <1>;
229 io_domains: io-domains {
230 compatible = "rockchip,rk3328-io-voltage-domain";
235 compatible = "syscon-reboot-mode";
237 mode-bootloader = <BOOT_LOADER>;
238 mode-charge = <BOOT_CHARGING>;
239 mode-fastboot = <BOOT_FASTBOOT>;
240 mode-loader = <BOOT_LOADER>;
241 mode-normal = <BOOT_NORMAL>;
242 mode-recovery = <BOOT_RECOVERY>;
243 mode-ums = <BOOT_UMS>;
247 uart0: serial@ff110000 {
248 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
249 reg = <0x0 0xff110000 0x0 0x100>;
250 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
252 clock-names = "baudclk", "apb_pclk";
255 dmas = <&dmac 2>, <&dmac 3>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
262 uart1: serial@ff120000 {
263 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
264 reg = <0x0 0xff120000 0x0 0x100>;
265 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
267 clock-names = "sclk_uart", "pclk_uart";
270 dmas = <&dmac 4>, <&dmac 5>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
277 uart2: serial@ff130000 {
278 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
279 reg = <0x0 0xff130000 0x0 0x100>;
280 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
282 clock-names = "baudclk", "apb_pclk";
285 dmas = <&dmac 6>, <&dmac 7>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&uart2m1_xfer>;
292 pmu: power-management@ff140000 {
293 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
294 reg = <0x0 0xff140000 0x0 0x1000>;
298 compatible = "rockchip,rk3328-i2c";
299 reg = <0x0 0xff150000 0x0 0x1000>;
300 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
301 #address-cells = <1>;
303 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
304 clock-names = "i2c", "pclk";
305 pinctrl-names = "default";
306 pinctrl-0 = <&i2c0_xfer>;
311 compatible = "rockchip,rk3328-i2c";
312 reg = <0x0 0xff160000 0x0 0x1000>;
313 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>;
316 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
317 clock-names = "i2c", "pclk";
318 pinctrl-names = "default";
319 pinctrl-0 = <&i2c1_xfer>;
324 compatible = "rockchip,rk3328-i2c";
325 reg = <0x0 0xff170000 0x0 0x1000>;
326 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
327 #address-cells = <1>;
329 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
330 clock-names = "i2c", "pclk";
331 pinctrl-names = "default";
332 pinctrl-0 = <&i2c2_xfer>;
337 compatible = "rockchip,rk3328-i2c";
338 reg = <0x0 0xff180000 0x0 0x1000>;
339 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
340 #address-cells = <1>;
342 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
343 clock-names = "i2c", "pclk";
344 pinctrl-names = "default";
345 pinctrl-0 = <&i2c3_xfer>;
350 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
351 reg = <0x0 0xff190000 0x0 0x1000>;
352 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>;
355 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
356 clock-names = "spiclk", "apb_pclk";
357 dmas = <&dmac 8>, <&dmac 9>;
359 dma-names = "tx", "rx";
360 pinctrl-names = "default";
361 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
365 wdt: watchdog@ff1a0000 {
366 compatible = "snps,dw-wdt";
367 reg = <0x0 0xff1a0000 0x0 0x100>;
368 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
373 compatible = "simple-bus";
374 #address-cells = <2>;
378 dmac: dmac@ff1f0000 {
379 compatible = "arm,pl330", "arm,primecell";
380 reg = <0x0 0xff1f0000 0x0 0x4000>;
381 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&cru ACLK_DMAC>;
384 clock-names = "apb_pclk";
389 saradc: saradc@ff280000 {
390 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
391 reg = <0x0 0xff280000 0x0 0x100>;
392 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
393 #io-channel-cells = <1>;
394 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
395 clock-names = "saradc", "apb_pclk";
396 resets = <&cru SRST_SARADC_P>;
397 reset-names = "saradc-apb";
401 cru: clock-controller@ff440000 {
402 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
403 reg = <0x0 0xff440000 0x0 0x1000>;
404 rockchip,grf = <&grf>;
408 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
409 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
410 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
411 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
412 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
413 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
414 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
415 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
416 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
417 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
418 <&cru SCLK_WIFI>, <&cru ARMCLK>,
419 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
420 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
421 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
422 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
423 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
424 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
425 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
426 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
427 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
428 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
429 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
430 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
431 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
432 assigned-clock-parents =
433 <&cru HDMIPHY>, <&cru PLL_APLL>,
434 <&cru PLL_GPLL>, <&xin24m>,
435 <&xin24m>, <&xin24m>;
436 assigned-clock-rates =
439 <24000000>, <24000000>,
440 <15000000>, <15000000>,
441 <100000000>, <100000000>,
442 <100000000>, <100000000>,
443 <50000000>, <100000000>,
444 <100000000>, <100000000>,
445 <50000000>, <50000000>,
446 <50000000>, <50000000>,
447 <24000000>, <600000000>,
448 <491520000>, <1200000000>,
449 <150000000>, <75000000>,
450 <75000000>, <150000000>,
451 <75000000>, <75000000>,
452 <300000000>, <100000000>,
453 <300000000>, <200000000>,
454 <400000000>, <500000000>,
455 <200000000>, <300000000>,
456 <300000000>, <250000000>,
457 <200000000>, <100000000>,
458 <24000000>, <100000000>,
459 <150000000>, <50000000>,
463 gic: interrupt-controller@ffb70000 {
464 compatible = "arm,gic-400";
465 #interrupt-cells = <3>;
466 #address-cells = <0>;
467 interrupt-controller;
468 reg = <0x0 0xff811000 0 0x1000>,
469 <0x0 0xff812000 0 0x2000>,
470 <0x0 0xff814000 0 0x2000>,
471 <0x0 0xff816000 0 0x2000>;
472 interrupts = <GIC_PPI 9
473 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
477 compatible = "rockchip,rk3328-pinctrl";
478 rockchip,grf = <&grf>;
479 #address-cells = <2>;
483 gpio0: gpio0@ff210000 {
484 compatible = "rockchip,gpio-bank";
485 reg = <0x0 0xff210000 0x0 0x100>;
486 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&cru PCLK_GPIO0>;
492 interrupt-controller;
493 #interrupt-cells = <2>;
496 gpio1: gpio1@ff220000 {
497 compatible = "rockchip,gpio-bank";
498 reg = <0x0 0xff220000 0x0 0x100>;
499 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&cru PCLK_GPIO1>;
505 interrupt-controller;
506 #interrupt-cells = <2>;
509 gpio2: gpio2@ff230000 {
510 compatible = "rockchip,gpio-bank";
511 reg = <0x0 0xff230000 0x0 0x100>;
512 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&cru PCLK_GPIO2>;
518 interrupt-controller;
519 #interrupt-cells = <2>;
522 gpio3: gpio3@ff240000 {
523 compatible = "rockchip,gpio-bank";
524 reg = <0x0 0xff240000 0x0 0x100>;
525 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&cru PCLK_GPIO3>;
531 interrupt-controller;
532 #interrupt-cells = <2>;
535 pcfg_pull_up: pcfg-pull-up {
539 pcfg_pull_down: pcfg-pull-down {
543 pcfg_pull_none: pcfg-pull-none {
547 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
549 drive-strength = <2>;
552 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
554 drive-strength = <2>;
557 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
559 drive-strength = <4>;
562 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
564 drive-strength = <4>;
567 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
569 drive-strength = <4>;
572 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
574 drive-strength = <8>;
577 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
579 drive-strength = <8>;
582 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
584 drive-strength = <12>;
587 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
589 drive-strength = <12>;
592 pcfg_output_high: pcfg-output-high {
596 pcfg_output_low: pcfg-output-low {
600 pcfg_input_high: pcfg-input-high {
605 pcfg_input: pcfg-input {
610 i2c0_xfer: i2c0-xfer {
612 <2 24 RK_FUNC_1 &pcfg_pull_none>,
613 <2 25 RK_FUNC_1 &pcfg_pull_none>;
618 i2c1_xfer: i2c1-xfer {
620 <2 4 RK_FUNC_2 &pcfg_pull_none>,
621 <2 5 RK_FUNC_2 &pcfg_pull_none>;
626 i2c2_xfer: i2c2-xfer {
628 <2 13 RK_FUNC_1 &pcfg_pull_none>,
629 <2 14 RK_FUNC_1 &pcfg_pull_none>;
634 i2c3_xfer: i2c3-xfer {
636 <0 5 RK_FUNC_2 &pcfg_pull_none>,
637 <0 6 RK_FUNC_2 &pcfg_pull_none>;
639 i2c3_gpio: i2c3-gpio {
641 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
642 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
647 hdmii2c_xfer: hdmii2c-xfer {
649 <0 5 RK_FUNC_1 &pcfg_pull_none>,
650 <0 6 RK_FUNC_1 &pcfg_pull_none>;
655 uart0_xfer: uart0-xfer {
657 <1 9 RK_FUNC_1 &pcfg_pull_up>,
658 <1 8 RK_FUNC_1 &pcfg_pull_none>;
661 uart0_cts: uart0-cts {
663 <1 11 RK_FUNC_1 &pcfg_pull_none>;
666 uart0_rts: uart0-rts {
668 <1 10 RK_FUNC_1 &pcfg_pull_none>;
671 uart0_rts_gpio: uart0-rts-gpio {
673 <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
678 uart1_xfer: uart1-xfer {
680 <3 4 RK_FUNC_4 &pcfg_pull_up>,
681 <3 6 RK_FUNC_4 &pcfg_pull_none>;
684 uart1_cts: uart1-cts {
686 <3 7 RK_FUNC_4 &pcfg_pull_none>;
689 uart1_rts: uart1-rts {
691 <3 5 RK_FUNC_4 &pcfg_pull_none>;
694 uart1_rts_gpio: uart1-rts-gpio {
696 <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
701 uart2m0_xfer: uart2m0-xfer {
703 <1 0 RK_FUNC_2 &pcfg_pull_up>,
704 <1 1 RK_FUNC_2 &pcfg_pull_none>;
709 uart2m1_xfer: uart2m1-xfer {
711 <2 0 RK_FUNC_1 &pcfg_pull_up>,
712 <2 1 RK_FUNC_1 &pcfg_pull_none>;
717 spi0m0_clk: spi0m0-clk {
719 <2 8 RK_FUNC_1 &pcfg_pull_up>;
722 spi0m0_cs0: spi0m0-cs0 {
724 <2 11 RK_FUNC_1 &pcfg_pull_up>;
727 spi0m0_tx: spi0m0-tx {
729 <2 9 RK_FUNC_1 &pcfg_pull_up>;
732 spi0m0_rx: spi0m0-rx {
734 <2 10 RK_FUNC_1 &pcfg_pull_up>;
737 spi0m0_cs1: spi0m0-cs1 {
739 <2 12 RK_FUNC_1 &pcfg_pull_up>;
744 spi0m1_clk: spi0m1-clk {
746 <3 23 RK_FUNC_2 &pcfg_pull_up>;
749 spi0m1_cs0: spi0m1-cs0 {
751 <3 26 RK_FUNC_2 &pcfg_pull_up>;
754 spi0m1_tx: spi0m1-tx {
756 <3 25 RK_FUNC_2 &pcfg_pull_up>;
759 spi0m1_rx: spi0m1-rx {
761 <3 24 RK_FUNC_2 &pcfg_pull_up>;
764 spi0m1_cs1: spi0m1-cs1 {
766 <3 27 RK_FUNC_2 &pcfg_pull_up>;
771 spi0m2_clk: spi0m2-clk {
773 <3 0 RK_FUNC_4 &pcfg_pull_up>;
776 spi0m2_cs0: spi0m2-cs0 {
778 <3 8 RK_FUNC_3 &pcfg_pull_up>;
781 spi0m2_tx: spi0m2-tx {
783 <3 1 RK_FUNC_4 &pcfg_pull_up>;
786 spi0m2_rx: spi0m2-rx {
788 <3 2 RK_FUNC_4 &pcfg_pull_up>;
793 i2s1_mclk: i2s1-mclk {
795 <2 15 RK_FUNC_1 &pcfg_pull_none>;
798 i2s1_sclk: i2s1-sclk {
800 <2 18 RK_FUNC_1 &pcfg_pull_none>;
803 i2s1_lrckrx: i2s1-lrckrx {
805 <2 16 RK_FUNC_1 &pcfg_pull_none>;
808 i2s1_lrcktx: i2s1-lrcktx {
810 <2 17 RK_FUNC_1 &pcfg_pull_none>;
815 <2 19 RK_FUNC_1 &pcfg_pull_none>;
820 <2 23 RK_FUNC_1 &pcfg_pull_none>;
823 i2s1_sdio1: i2s1-sdio1 {
825 <2 20 RK_FUNC_1 &pcfg_pull_none>;
828 i2s1_sdio2: i2s1-sdio2 {
830 <2 21 RK_FUNC_1 &pcfg_pull_none>;
833 i2s1_sdio3: i2s1-sdio3 {
835 <2 22 RK_FUNC_1 &pcfg_pull_none>;
838 i2s1_sleep: i2s1-sleep {
840 <2 15 RK_FUNC_GPIO &pcfg_input_high>,
841 <2 16 RK_FUNC_GPIO &pcfg_input_high>,
842 <2 17 RK_FUNC_GPIO &pcfg_input_high>,
843 <2 18 RK_FUNC_GPIO &pcfg_input_high>,
844 <2 19 RK_FUNC_GPIO &pcfg_input_high>,
845 <2 20 RK_FUNC_GPIO &pcfg_input_high>,
846 <2 21 RK_FUNC_GPIO &pcfg_input_high>,
847 <2 22 RK_FUNC_GPIO &pcfg_input_high>,
848 <2 23 RK_FUNC_GPIO &pcfg_input_high>;
853 i2s2m0_mclk: i2s2m0-mclk {
855 <1 21 RK_FUNC_1 &pcfg_pull_none>;
858 i2s2m0_sclk: i2s2m0-sclk {
860 <1 22 RK_FUNC_1 &pcfg_pull_none>;
863 i2s2m0_lrckrx: i2s2m0-lrckrx {
865 <1 26 RK_FUNC_1 &pcfg_pull_none>;
868 i2s2m0_lrcktx: i2s2m0-lrcktx {
870 <1 23 RK_FUNC_1 &pcfg_pull_none>;
873 i2s2m0_sdi: i2s2m0-sdi {
875 <1 24 RK_FUNC_1 &pcfg_pull_none>;
878 i2s2m0_sdo: i2s2m0-sdo {
880 <1 25 RK_FUNC_1 &pcfg_pull_none>;
883 i2s2m0_sleep: i2s2m0-sleep {
885 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
886 <1 22 RK_FUNC_GPIO &pcfg_input_high>,
887 <1 26 RK_FUNC_GPIO &pcfg_input_high>,
888 <1 23 RK_FUNC_GPIO &pcfg_input_high>,
889 <1 24 RK_FUNC_GPIO &pcfg_input_high>,
890 <1 25 RK_FUNC_GPIO &pcfg_input_high>;
895 i2s2m1_mclk: i2s2m1-mclk {
897 <1 21 RK_FUNC_1 &pcfg_pull_none>;
900 i2s2m1_sclk: i2s2m1-sclk {
902 <3 0 RK_FUNC_6 &pcfg_pull_none>;
905 i2s2m1_lrckrx: i2sm1-lrckrx {
907 <3 8 RK_FUNC_6 &pcfg_pull_none>;
910 i2s2m1_lrcktx: i2s2m1-lrcktx {
912 <3 8 RK_FUNC_4 &pcfg_pull_none>;
915 i2s2m1_sdi: i2s2m1-sdi {
917 <3 2 RK_FUNC_6 &pcfg_pull_none>;
920 i2s2m1_sdo: i2s2m1-sdo {
922 <3 1 RK_FUNC_6 &pcfg_pull_none>;
925 i2s2m1_sleep: i2s2m1-sleep {
927 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
928 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
929 <3 8 RK_FUNC_GPIO &pcfg_input_high>,
930 <3 2 RK_FUNC_GPIO &pcfg_input_high>,
931 <3 1 RK_FUNC_GPIO &pcfg_input_high>;
936 spdifm0_tx: spdifm0-tx {
938 <0 27 RK_FUNC_1 &pcfg_pull_none>;
943 spdifm1_tx: spdifm1-tx {
945 <2 17 RK_FUNC_2 &pcfg_pull_none>;
950 spdifm2_tx: spdifm2-tx {
952 <0 2 RK_FUNC_2 &pcfg_pull_none>;
957 sdmmc0m0_pwren: sdmmc0m0-pwren {
959 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
962 sdmmc0m0_gpio: sdmmc0m0-gpio {
964 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
969 sdmmc0m1_pwren: sdmmc0m1-pwren {
971 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
974 sdmmc0m1_gpio: sdmmc0m1-gpio {
976 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
981 sdmmc0_clk: sdmmc0-clk {
983 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
986 sdmmc0_cmd: sdmmc0-cmd {
988 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
991 sdmmc0_dectn: sdmmc0-dectn {
993 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
996 sdmmc0_wrprt: sdmmc0-wrprt {
998 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1001 sdmmc0_bus1: sdmmc0-bus1 {
1003 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1006 sdmmc0_bus4: sdmmc0-bus4 {
1008 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1009 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1010 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1011 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1014 sdmmc0_gpio: sdmmc0-gpio {
1016 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1017 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1018 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1019 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1020 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1021 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1022 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1023 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1028 sdmmc0ext_clk: sdmmc0ext-clk {
1030 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1033 sdmmc0ext_cmd: sdmmc0ext-cmd {
1035 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1038 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1040 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1043 sdmmc0ext_dectn: sdmmc0ext-dectn {
1045 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1048 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1050 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1053 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1055 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1056 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1057 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1058 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1061 sdmmc0ext_gpio: sdmmc0ext-gpio {
1063 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1064 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1065 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1066 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1067 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1068 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1069 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1070 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1075 sdmmc1_clk: sdmmc1-clk {
1077 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1080 sdmmc1_cmd: sdmmc1-cmd {
1082 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1085 sdmmc1_pwren: sdmmc1-pwren {
1087 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1090 sdmmc1_wrprt: sdmmc1-wrprt {
1092 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1095 sdmmc1_dectn: sdmmc1-dectn {
1097 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1100 sdmmc1_bus1: sdmmc1-bus1 {
1102 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1105 sdmmc1_bus4: sdmmc1-bus4 {
1107 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1108 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1109 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1110 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1113 sdmmc1_gpio: sdmmc1-gpio {
1115 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1116 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1117 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1118 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1119 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1120 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1121 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1122 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1123 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1128 emmc_clk: emmc-clk {
1130 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1133 emmc_cmd: emmc-cmd {
1135 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1138 emmc_pwren: emmc-pwren {
1140 <3 22 RK_FUNC_2 &pcfg_pull_none>;
1143 emmc_rstnout: emmc-rstnout {
1145 <3 20 RK_FUNC_2 &pcfg_pull_none>;
1148 emmc_bus1: emmc-bus1 {
1150 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1153 emmc_bus4: emmc-bus4 {
1155 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1156 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1157 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1158 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1161 emmc_bus8: emmc-bus8 {
1163 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1164 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1165 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1166 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1167 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1168 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1169 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1170 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1175 pwm0_pin: pwm0-pin {
1177 <2 4 RK_FUNC_1 &pcfg_pull_none>;
1182 pwm1_pin: pwm1-pin {
1184 <2 5 RK_FUNC_1 &pcfg_pull_none>;
1189 pwm2_pin: pwm2-pin {
1191 <2 6 RK_FUNC_1 &pcfg_pull_none>;
1196 pwmir_pin: pwmir-pin {
1198 <2 2 RK_FUNC_1 &pcfg_pull_none>;
1203 rgmiim0_pins: rgmiim0-pins {
1206 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1208 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1210 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1212 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1214 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1216 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1218 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1220 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1222 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1224 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1226 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1228 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1230 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1232 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1234 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1237 rmiim0_pins: rmiim0-pins {
1240 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1242 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1244 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1246 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1248 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1250 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1252 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1254 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1256 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1258 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1263 rgmiim1_pins: rgmiim1-pins {
1266 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1268 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1270 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1272 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1274 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1276 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1278 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1280 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1282 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1284 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1286 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1288 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1290 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1292 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1294 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1297 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1299 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1301 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1303 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1305 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1307 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1309 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1312 rmiim1_pins: rmiim1-pins {
1315 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1317 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1319 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1321 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1323 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1325 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1327 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1329 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1331 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1333 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1336 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1338 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1340 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1342 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1344 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1346 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1351 fephyled_speed100: fephyled-speed100 {
1353 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1356 fephyled_speed10: fephyled-speed10 {
1358 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1361 fephyled_duplex: fephyled-duplex {
1363 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1366 fephyled_rxm0: fephyled-rxm0 {
1368 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1371 fephyled_txm0: fephyled-txm0 {
1373 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1376 fephyled_linkm0: fephyled-linkm0 {
1378 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1381 fephyled_rxm1: fephyled-rxm1 {
1383 <2 25 RK_FUNC_2 &pcfg_pull_none>;
1386 fephyled_txm1: fephyled-txm1 {
1388 <2 25 RK_FUNC_3 &pcfg_pull_none>;
1391 fephyled_linkm1: fephyled-linkm1 {
1393 <2 24 RK_FUNC_2 &pcfg_pull_none>;
1398 tsadc_int: tsadc-int {
1400 <2 13 RK_FUNC_2 &pcfg_pull_none>;
1402 tsadc_gpio: tsadc-gpio {
1404 <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1409 hdmi_cec: hdmi-cec {
1411 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1414 hdmi_hpd: hdmi-hpd {
1416 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1421 dvp_d2d9_m0:dvp-d2d9-m0 {
1424 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1426 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1428 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1430 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1432 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1434 <3 9 RK_FUNC_2 &pcfg_pull_none>,
1436 <3 10 RK_FUNC_2 &pcfg_pull_none>,
1438 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1440 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1442 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1444 <3 3 RK_FUNC_2 &pcfg_pull_none>,
1446 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1451 dvp_d2d9_m1:dvp-d2d9-m1 {
1454 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1456 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1458 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1460 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1462 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1464 <2 16 RK_FUNC_4 &pcfg_pull_none>,
1466 <2 17 RK_FUNC_4 &pcfg_pull_none>,
1468 <2 18 RK_FUNC_4 &pcfg_pull_none>,
1470 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1472 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1474 <2 15 RK_FUNC_4 &pcfg_pull_none>,
1476 <3 2 RK_FUNC_2 &pcfg_pull_none>;