2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3328-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49 #include <dt-bindings/power/rk3328-power.h>
52 compatible = "rockchip,rk3328";
54 interrupt-parent = <&gic>;
74 compatible = "arm,cortex-a53", "arm,armv8";
76 enable-method = "psci";
77 // clocks = <&cru ARMCLK>;
78 operating-points-v2 = <&cpu0_opp_table>;
82 compatible = "arm,cortex-a53", "arm,armv8";
84 enable-method = "psci";
88 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
94 compatible = "arm,cortex-a53", "arm,armv8";
96 enable-method = "psci";
100 cpu0_opp_table: opp_table0 {
101 compatible = "operating-points-v2";
105 opp-hz = /bits/ 64 <408000000>;
106 opp-microvolt = <950000>;
107 clock-latency-ns = <40000>;
111 opp-hz = /bits/ 64 <600000000>;
112 opp-microvolt = <950000>;
113 clock-latency-ns = <40000>;
116 opp-hz = /bits/ 64 <816000000>;
117 opp-microvolt = <1000000>;
118 clock-latency-ns = <40000>;
121 opp-hz = /bits/ 64 <1008000000>;
122 opp-microvolt = <1100000>;
123 clock-latency-ns = <40000>;
126 opp-hz = /bits/ 64 <1200000000>;
127 opp-microvolt = <1225000>;
128 clock-latency-ns = <40000>;
131 opp-hz = /bits/ 64 <1296000000>;
132 opp-microvolt = <1300000>;
133 clock-latency-ns = <40000>;
138 compatible = "arm,cortex-a53-pmu";
139 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
143 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
147 compatible = "arm,psci-1.0";
152 compatible = "arm,armv8-timer";
153 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
154 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
155 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
156 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
160 compatible = "fixed-clock";
162 clock-frequency = <24000000>;
163 clock-output-names = "xin24m";
167 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
168 reg = <0x0 0xff000000 0x0 0x1000>;
169 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
171 clock-names = "i2s_clk", "i2s_hclk";
172 dmas = <&dmac 11>, <&dmac 12>;
174 dma-names = "tx", "rx";
179 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
180 reg = <0x0 0xff010000 0x0 0x1000>;
181 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
183 clock-names = "i2s_clk", "i2s_hclk";
184 dmas = <&dmac 14>, <&dmac 15>;
186 dma-names = "tx", "rx";
191 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
192 reg = <0x0 0xff020000 0x0 0x1000>;
193 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
195 clock-names = "i2s_clk", "i2s_hclk";
196 dmas = <&dmac 0>, <&dmac 1>;
198 dma-names = "tx", "rx";
199 pinctrl-names = "default", "sleep";
200 pinctrl-0 = <&i2s2m0_mclk
206 pinctrl-1 = <&i2s2m0_sleep>;
210 spdif: spdif@ff030000 {
211 compatible = "rockchip,rk3328-spdif";
212 reg = <0x0 0xff030000 0x0 0x1000>;
213 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
215 clock-names = "mclk", "hclk";
219 pinctrl-names = "default";
220 pinctrl-0 = <&spdifm2_tx>;
224 grf: syscon@ff100000 {
225 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
226 reg = <0x0 0xff100000 0x0 0x1000>;
227 #address-cells = <1>;
230 io_domains: io-domains {
231 compatible = "rockchip,rk3328-io-voltage-domain";
235 power: power-controller {
236 compatible = "rockchip,rk3328-power-controller";
237 #power-domain-cells = <1>;
238 #address-cells = <1>;
242 pd_hevc@RK3328_PD_HEVC {
243 reg = <RK3328_PD_HEVC>;
245 pd_video@RK3328_PD_VIDEO {
246 reg = <RK3328_PD_VIDEO>;
248 pd_vpu@RK3328_PD_VPU {
249 reg = <RK3328_PD_VPU>;
254 compatible = "syscon-reboot-mode";
256 mode-bootloader = <BOOT_BL_DOWNLOAD>;
257 mode-charge = <BOOT_CHARGING>;
258 mode-fastboot = <BOOT_FASTBOOT>;
259 mode-loader = <BOOT_BL_DOWNLOAD>;
260 mode-normal = <BOOT_NORMAL>;
261 mode-recovery = <BOOT_RECOVERY>;
262 mode-ums = <BOOT_UMS>;
266 uart0: serial@ff110000 {
267 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
268 reg = <0x0 0xff110000 0x0 0x100>;
269 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
271 clock-names = "baudclk", "apb_pclk";
274 dmas = <&dmac 2>, <&dmac 3>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
281 uart1: serial@ff120000 {
282 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
283 reg = <0x0 0xff120000 0x0 0x100>;
284 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
286 clock-names = "sclk_uart", "pclk_uart";
289 dmas = <&dmac 4>, <&dmac 5>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
296 uart2: serial@ff130000 {
297 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
298 reg = <0x0 0xff130000 0x0 0x100>;
299 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
301 clock-names = "baudclk", "apb_pclk";
304 dmas = <&dmac 6>, <&dmac 7>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&uart2m1_xfer>;
311 pmu: power-management@ff140000 {
312 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
313 reg = <0x0 0xff140000 0x0 0x1000>;
317 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
318 reg = <0x0 0xff150000 0x0 0x1000>;
319 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>;
322 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
323 clock-names = "i2c", "pclk";
324 pinctrl-names = "default";
325 pinctrl-0 = <&i2c0_xfer>;
330 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
331 reg = <0x0 0xff160000 0x0 0x1000>;
332 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
333 #address-cells = <1>;
335 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
336 clock-names = "i2c", "pclk";
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2c1_xfer>;
343 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
344 reg = <0x0 0xff170000 0x0 0x1000>;
345 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
348 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
349 clock-names = "i2c", "pclk";
350 pinctrl-names = "default";
351 pinctrl-0 = <&i2c2_xfer>;
356 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
357 reg = <0x0 0xff180000 0x0 0x1000>;
358 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
361 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
362 clock-names = "i2c", "pclk";
363 pinctrl-names = "default";
364 pinctrl-0 = <&i2c3_xfer>;
369 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
370 reg = <0x0 0xff190000 0x0 0x1000>;
371 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
372 #address-cells = <1>;
374 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
375 clock-names = "spiclk", "apb_pclk";
376 dmas = <&dmac 8>, <&dmac 9>;
378 dma-names = "tx", "rx";
379 pinctrl-names = "default";
380 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
384 wdt: watchdog@ff1a0000 {
385 compatible = "snps,dw-wdt";
386 reg = <0x0 0xff1a0000 0x0 0x100>;
387 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
392 compatible = "simple-bus";
393 #address-cells = <2>;
397 dmac: dmac@ff1f0000 {
398 compatible = "arm,pl330", "arm,primecell";
399 reg = <0x0 0xff1f0000 0x0 0x4000>;
400 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&cru ACLK_DMAC>;
403 clock-names = "apb_pclk";
408 saradc: saradc@ff280000 {
409 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
410 reg = <0x0 0xff280000 0x0 0x100>;
411 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
412 #io-channel-cells = <1>;
413 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
414 clock-names = "saradc", "apb_pclk";
415 resets = <&cru SRST_SARADC_P>;
416 reset-names = "saradc-apb";
420 cru: clock-controller@ff440000 {
421 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
422 reg = <0x0 0xff440000 0x0 0x1000>;
423 rockchip,grf = <&grf>;
427 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
428 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
429 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
430 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
431 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
432 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
433 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
434 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
435 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
436 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
437 <&cru SCLK_WIFI>, <&cru ARMCLK>,
438 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
439 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
440 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
441 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
442 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
443 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
444 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
445 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
446 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
447 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
448 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
449 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
450 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
451 assigned-clock-parents =
452 <&cru HDMIPHY>, <&cru PLL_APLL>,
453 <&cru PLL_GPLL>, <&xin24m>,
454 <&xin24m>, <&xin24m>;
455 assigned-clock-rates =
458 <24000000>, <24000000>,
459 <15000000>, <15000000>,
460 <100000000>, <100000000>,
461 <100000000>, <100000000>,
462 <50000000>, <100000000>,
463 <100000000>, <100000000>,
464 <50000000>, <50000000>,
465 <50000000>, <50000000>,
466 <24000000>, <600000000>,
467 <491520000>, <1200000000>,
468 <150000000>, <75000000>,
469 <75000000>, <150000000>,
470 <75000000>, <75000000>,
471 <300000000>, <100000000>,
472 <300000000>, <200000000>,
473 <400000000>, <500000000>,
474 <200000000>, <300000000>,
475 <300000000>, <250000000>,
476 <200000000>, <100000000>,
477 <24000000>, <100000000>,
478 <150000000>, <50000000>,
482 usb2phy_grf: syscon@ff450000 {
483 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
485 reg = <0x0 0xff450000 0x0 0x10000>;
486 #address-cells = <1>;
489 u2phy: usb2-phy@100 {
490 compatible = "rockchip,rk3328-usb2phy";
493 clock-names = "phyclk";
495 assigned-clocks = <&cru USB480M>;
496 assigned-clock-parents = <&u2phy>;
497 clock-output-names = "usb480m_phy";
500 u2phy_host: host-port {
502 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
503 interrupt-names = "linestate";
509 usb3phy_grf: syscon@ff460000 {
510 compatible = "rockchip,usb3phy-grf", "syscon";
511 reg = <0x0 0xff460000 0x0 0x1000>;
514 u3phy: usb3-phy@ff470000 {
515 compatible = "rockchip,rk3328-u3phy";
516 reg = <0x0 0xff470000 0x0 0x0>;
517 rockchip,u3phygrf = <&usb3phy_grf>;
518 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
519 interrupt-names = "linestate";
520 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
521 clock-names = "u3phy-otg", "u3phy-pipe";
522 resets = <&cru SRST_USB3PHY_U2>,
523 <&cru SRST_USB3PHY_U3>,
524 <&cru SRST_USB3PHY_PIPE>,
525 <&cru SRST_USB3OTG_UTMI>,
526 <&cru SRST_USB3PHY_OTG_P>,
527 <&cru SRST_USB3PHY_PIPE_P>;
528 reset-names = "u3phy-u2-por", "u3phy-u3-por",
529 "u3phy-pipe-mac", "u3phy-utmi-mac",
530 "u3phy-utmi-apb", "u3phy-pipe-apb";
531 #address-cells = <2>;
536 u3phy_utmi: utmi@ff470000 {
537 reg = <0x0 0xff470000 0x0 0x8000>;
542 u3phy_pipe: pipe@ff478000 {
543 reg = <0x0 0xff478000 0x0 0x8000>;
549 sdmmc: rksdmmc@ff500000 {
550 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
551 reg = <0x0 0xff500000 0x0 0x4000>;
552 clock-freq-min-max = <400000 150000000>;
553 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
554 clock-names = "biu", "ciu";
555 fifo-depth = <0x100>;
556 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
560 sdio: dwmmc@ff510000 {
561 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
562 reg = <0x0 0xff510000 0x0 0x4000>;
563 clock-freq-min-max = <400000 150000000>;
564 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
565 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
566 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
567 fifo-depth = <0x100>;
568 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
572 emmc: rksdmmc@ff520000 {
573 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
574 reg = <0x0 0xff520000 0x0 0x4000>;
575 clock-freq-min-max = <400000 150000000>;
576 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
577 clock-names = "biu", "ciu";
578 fifo-depth = <0x100>;
579 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
583 gmac2io: eth@ff540000 {
584 compatible = "rockchip,rk3328-gmac";
585 reg = <0x0 0xff540000 0x0 0x10000>;
586 rockchip,grf = <&grf>;
587 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
588 interrupt-names = "macirq";
589 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
590 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
591 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
593 clock-names = "stmmaceth", "mac_clk_rx",
594 "mac_clk_tx", "clk_mac_ref",
595 "clk_mac_refout", "aclk_mac",
597 resets = <&cru SRST_GMAC2IO_A>;
598 reset-names = "stmmaceth";
602 usb20_otg: usb@ff580000 {
603 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
605 reg = <0x0 0xff580000 0x0 0x40000>;
606 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
608 clock-names = "otg", "otg_pmu";
610 g-np-tx-fifo-size = <16>;
611 g-rx-fifo-size = <275>;
612 g-tx-fifo-size = <256 128 128 64 64 32>;
617 usb_host0_ehci: usb@ff5c0000 {
618 compatible = "generic-ehci";
619 reg = <0x0 0xff5c0000 0x0 0x10000>;
620 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
623 clock-names = "usbhost", "arbiter", "utmi";
624 phys = <&u2phy_host>;
629 usb_host0_ohci: usb@ff5d0000 {
630 compatible = "generic-ohci";
631 reg = <0x0 0xff5d0000 0x0 0x10000>;
632 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
635 clock-names = "usbhost", "arbiter", "utmi";
636 phys = <&u2phy_host>;
641 sdmmc_ext: rksdmmc@ff5f0000 {
642 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
643 reg = <0x0 0xff5f0000 0x0 0x4000>;
644 clock-freq-min-max = <400000 150000000>;
645 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
646 clock-names = "biu", "ciu";
647 fifo-depth = <0x100>;
648 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
652 usbdrd3: usb@ff600000 {
653 compatible = "rockchip,rk3328-dwc3";
654 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
656 clock-names = "ref_clk", "suspend_clk",
658 #address-cells = <2>;
663 usbdrd_dwc3: dwc3@ff600000 {
664 compatible = "snps,dwc3";
665 reg = <0x0 0xff600000 0x0 0x100000>;
666 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
668 phys = <&u3phy_utmi>, <&u3phy_pipe>;
669 phy-names = "usb2-phy", "usb3-phy";
670 phy_type = "utmi_wide";
671 snps,dis_enblslpm_quirk;
672 snps,dis-u2-freeclk-exists-quirk;
673 snps,dis_u2_susphy_quirk;
674 snps,dis_u3_susphy_quirk;
675 snps,dis-del-phy-power-chg-quirk;
680 gic: interrupt-controller@ff811000 {
681 compatible = "arm,gic-400";
682 #interrupt-cells = <3>;
683 #address-cells = <0>;
684 interrupt-controller;
685 reg = <0x0 0xff811000 0 0x1000>,
686 <0x0 0xff812000 0 0x2000>,
687 <0x0 0xff814000 0 0x2000>,
688 <0x0 0xff816000 0 0x2000>;
689 interrupts = <GIC_PPI 9
690 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
694 compatible = "rockchip,rk3328-pinctrl";
695 rockchip,grf = <&grf>;
696 #address-cells = <2>;
700 gpio0: gpio0@ff210000 {
701 compatible = "rockchip,gpio-bank";
702 reg = <0x0 0xff210000 0x0 0x100>;
703 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&cru PCLK_GPIO0>;
709 interrupt-controller;
710 #interrupt-cells = <2>;
713 gpio1: gpio1@ff220000 {
714 compatible = "rockchip,gpio-bank";
715 reg = <0x0 0xff220000 0x0 0x100>;
716 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&cru PCLK_GPIO1>;
722 interrupt-controller;
723 #interrupt-cells = <2>;
726 gpio2: gpio2@ff230000 {
727 compatible = "rockchip,gpio-bank";
728 reg = <0x0 0xff230000 0x0 0x100>;
729 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&cru PCLK_GPIO2>;
735 interrupt-controller;
736 #interrupt-cells = <2>;
739 gpio3: gpio3@ff240000 {
740 compatible = "rockchip,gpio-bank";
741 reg = <0x0 0xff240000 0x0 0x100>;
742 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&cru PCLK_GPIO3>;
748 interrupt-controller;
749 #interrupt-cells = <2>;
752 pcfg_pull_up: pcfg-pull-up {
756 pcfg_pull_down: pcfg-pull-down {
760 pcfg_pull_none: pcfg-pull-none {
764 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
766 drive-strength = <2>;
769 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
771 drive-strength = <2>;
774 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
776 drive-strength = <4>;
779 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
781 drive-strength = <4>;
784 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
786 drive-strength = <4>;
789 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
791 drive-strength = <8>;
794 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
796 drive-strength = <8>;
799 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
801 drive-strength = <12>;
804 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
806 drive-strength = <12>;
809 pcfg_output_high: pcfg-output-high {
813 pcfg_output_low: pcfg-output-low {
817 pcfg_input_high: pcfg-input-high {
822 pcfg_input: pcfg-input {
827 i2c0_xfer: i2c0-xfer {
829 <2 24 RK_FUNC_1 &pcfg_pull_none>,
830 <2 25 RK_FUNC_1 &pcfg_pull_none>;
835 i2c1_xfer: i2c1-xfer {
837 <2 4 RK_FUNC_2 &pcfg_pull_none>,
838 <2 5 RK_FUNC_2 &pcfg_pull_none>;
843 i2c2_xfer: i2c2-xfer {
845 <2 13 RK_FUNC_1 &pcfg_pull_none>,
846 <2 14 RK_FUNC_1 &pcfg_pull_none>;
851 i2c3_xfer: i2c3-xfer {
853 <0 5 RK_FUNC_2 &pcfg_pull_none>,
854 <0 6 RK_FUNC_2 &pcfg_pull_none>;
856 i2c3_gpio: i2c3-gpio {
858 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
859 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
864 hdmii2c_xfer: hdmii2c-xfer {
866 <0 5 RK_FUNC_1 &pcfg_pull_none>,
867 <0 6 RK_FUNC_1 &pcfg_pull_none>;
872 uart0_xfer: uart0-xfer {
874 <1 9 RK_FUNC_1 &pcfg_pull_up>,
875 <1 8 RK_FUNC_1 &pcfg_pull_none>;
878 uart0_cts: uart0-cts {
880 <1 11 RK_FUNC_1 &pcfg_pull_none>;
883 uart0_rts: uart0-rts {
885 <1 10 RK_FUNC_1 &pcfg_pull_none>;
888 uart0_rts_gpio: uart0-rts-gpio {
890 <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
895 uart1_xfer: uart1-xfer {
897 <3 4 RK_FUNC_4 &pcfg_pull_up>,
898 <3 6 RK_FUNC_4 &pcfg_pull_none>;
901 uart1_cts: uart1-cts {
903 <3 7 RK_FUNC_4 &pcfg_pull_none>;
906 uart1_rts: uart1-rts {
908 <3 5 RK_FUNC_4 &pcfg_pull_none>;
911 uart1_rts_gpio: uart1-rts-gpio {
913 <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
918 uart2m0_xfer: uart2m0-xfer {
920 <1 0 RK_FUNC_2 &pcfg_pull_up>,
921 <1 1 RK_FUNC_2 &pcfg_pull_none>;
926 uart2m1_xfer: uart2m1-xfer {
928 <2 0 RK_FUNC_1 &pcfg_pull_up>,
929 <2 1 RK_FUNC_1 &pcfg_pull_none>;
934 spi0m0_clk: spi0m0-clk {
936 <2 8 RK_FUNC_1 &pcfg_pull_up>;
939 spi0m0_cs0: spi0m0-cs0 {
941 <2 11 RK_FUNC_1 &pcfg_pull_up>;
944 spi0m0_tx: spi0m0-tx {
946 <2 9 RK_FUNC_1 &pcfg_pull_up>;
949 spi0m0_rx: spi0m0-rx {
951 <2 10 RK_FUNC_1 &pcfg_pull_up>;
954 spi0m0_cs1: spi0m0-cs1 {
956 <2 12 RK_FUNC_1 &pcfg_pull_up>;
961 spi0m1_clk: spi0m1-clk {
963 <3 23 RK_FUNC_2 &pcfg_pull_up>;
966 spi0m1_cs0: spi0m1-cs0 {
968 <3 26 RK_FUNC_2 &pcfg_pull_up>;
971 spi0m1_tx: spi0m1-tx {
973 <3 25 RK_FUNC_2 &pcfg_pull_up>;
976 spi0m1_rx: spi0m1-rx {
978 <3 24 RK_FUNC_2 &pcfg_pull_up>;
981 spi0m1_cs1: spi0m1-cs1 {
983 <3 27 RK_FUNC_2 &pcfg_pull_up>;
988 spi0m2_clk: spi0m2-clk {
990 <3 0 RK_FUNC_4 &pcfg_pull_up>;
993 spi0m2_cs0: spi0m2-cs0 {
995 <3 8 RK_FUNC_3 &pcfg_pull_up>;
998 spi0m2_tx: spi0m2-tx {
1000 <3 1 RK_FUNC_4 &pcfg_pull_up>;
1003 spi0m2_rx: spi0m2-rx {
1005 <3 2 RK_FUNC_4 &pcfg_pull_up>;
1010 i2s1_mclk: i2s1-mclk {
1012 <2 15 RK_FUNC_1 &pcfg_pull_none>;
1015 i2s1_sclk: i2s1-sclk {
1017 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1020 i2s1_lrckrx: i2s1-lrckrx {
1022 <2 16 RK_FUNC_1 &pcfg_pull_none>;
1025 i2s1_lrcktx: i2s1-lrcktx {
1027 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1030 i2s1_sdi: i2s1-sdi {
1032 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1035 i2s1_sdo: i2s1-sdo {
1037 <2 23 RK_FUNC_1 &pcfg_pull_none>;
1040 i2s1_sdio1: i2s1-sdio1 {
1042 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1045 i2s1_sdio2: i2s1-sdio2 {
1047 <2 21 RK_FUNC_1 &pcfg_pull_none>;
1050 i2s1_sdio3: i2s1-sdio3 {
1052 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1055 i2s1_sleep: i2s1-sleep {
1057 <2 15 RK_FUNC_GPIO &pcfg_input_high>,
1058 <2 16 RK_FUNC_GPIO &pcfg_input_high>,
1059 <2 17 RK_FUNC_GPIO &pcfg_input_high>,
1060 <2 18 RK_FUNC_GPIO &pcfg_input_high>,
1061 <2 19 RK_FUNC_GPIO &pcfg_input_high>,
1062 <2 20 RK_FUNC_GPIO &pcfg_input_high>,
1063 <2 21 RK_FUNC_GPIO &pcfg_input_high>,
1064 <2 22 RK_FUNC_GPIO &pcfg_input_high>,
1065 <2 23 RK_FUNC_GPIO &pcfg_input_high>;
1070 i2s2m0_mclk: i2s2m0-mclk {
1072 <1 21 RK_FUNC_1 &pcfg_pull_none>;
1075 i2s2m0_sclk: i2s2m0-sclk {
1077 <1 22 RK_FUNC_1 &pcfg_pull_none>;
1080 i2s2m0_lrckrx: i2s2m0-lrckrx {
1082 <1 26 RK_FUNC_1 &pcfg_pull_none>;
1085 i2s2m0_lrcktx: i2s2m0-lrcktx {
1087 <1 23 RK_FUNC_1 &pcfg_pull_none>;
1090 i2s2m0_sdi: i2s2m0-sdi {
1092 <1 24 RK_FUNC_1 &pcfg_pull_none>;
1095 i2s2m0_sdo: i2s2m0-sdo {
1097 <1 25 RK_FUNC_1 &pcfg_pull_none>;
1100 i2s2m0_sleep: i2s2m0-sleep {
1102 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1103 <1 22 RK_FUNC_GPIO &pcfg_input_high>,
1104 <1 26 RK_FUNC_GPIO &pcfg_input_high>,
1105 <1 23 RK_FUNC_GPIO &pcfg_input_high>,
1106 <1 24 RK_FUNC_GPIO &pcfg_input_high>,
1107 <1 25 RK_FUNC_GPIO &pcfg_input_high>;
1112 i2s2m1_mclk: i2s2m1-mclk {
1114 <1 21 RK_FUNC_1 &pcfg_pull_none>;
1117 i2s2m1_sclk: i2s2m1-sclk {
1119 <3 0 RK_FUNC_6 &pcfg_pull_none>;
1122 i2s2m1_lrckrx: i2sm1-lrckrx {
1124 <3 8 RK_FUNC_6 &pcfg_pull_none>;
1127 i2s2m1_lrcktx: i2s2m1-lrcktx {
1129 <3 8 RK_FUNC_4 &pcfg_pull_none>;
1132 i2s2m1_sdi: i2s2m1-sdi {
1134 <3 2 RK_FUNC_6 &pcfg_pull_none>;
1137 i2s2m1_sdo: i2s2m1-sdo {
1139 <3 1 RK_FUNC_6 &pcfg_pull_none>;
1142 i2s2m1_sleep: i2s2m1-sleep {
1144 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1145 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
1146 <3 8 RK_FUNC_GPIO &pcfg_input_high>,
1147 <3 2 RK_FUNC_GPIO &pcfg_input_high>,
1148 <3 1 RK_FUNC_GPIO &pcfg_input_high>;
1153 spdifm0_tx: spdifm0-tx {
1155 <0 27 RK_FUNC_1 &pcfg_pull_none>;
1160 spdifm1_tx: spdifm1-tx {
1162 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1167 spdifm2_tx: spdifm2-tx {
1169 <0 2 RK_FUNC_2 &pcfg_pull_none>;
1174 sdmmc0m0_pwren: sdmmc0m0-pwren {
1176 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1179 sdmmc0m0_gpio: sdmmc0m0-gpio {
1181 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1186 sdmmc0m1_pwren: sdmmc0m1-pwren {
1188 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1191 sdmmc0m1_gpio: sdmmc0m1-gpio {
1193 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1198 sdmmc0_clk: sdmmc0-clk {
1200 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1203 sdmmc0_cmd: sdmmc0-cmd {
1205 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1208 sdmmc0_dectn: sdmmc0-dectn {
1210 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1213 sdmmc0_wrprt: sdmmc0-wrprt {
1215 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1218 sdmmc0_bus1: sdmmc0-bus1 {
1220 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1223 sdmmc0_bus4: sdmmc0-bus4 {
1225 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1226 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1227 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1228 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1231 sdmmc0_gpio: sdmmc0-gpio {
1233 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1234 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1235 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1236 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1237 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1238 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1239 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1240 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1245 sdmmc0ext_clk: sdmmc0ext-clk {
1247 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1250 sdmmc0ext_cmd: sdmmc0ext-cmd {
1252 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1255 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1257 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1260 sdmmc0ext_dectn: sdmmc0ext-dectn {
1262 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1265 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1267 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1270 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1272 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1273 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1274 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1275 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1278 sdmmc0ext_gpio: sdmmc0ext-gpio {
1280 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1281 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1282 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1283 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1284 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1285 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1286 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1287 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1292 sdmmc1_clk: sdmmc1-clk {
1294 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1297 sdmmc1_cmd: sdmmc1-cmd {
1299 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1302 sdmmc1_pwren: sdmmc1-pwren {
1304 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1307 sdmmc1_wrprt: sdmmc1-wrprt {
1309 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1312 sdmmc1_dectn: sdmmc1-dectn {
1314 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1317 sdmmc1_bus1: sdmmc1-bus1 {
1319 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1322 sdmmc1_bus4: sdmmc1-bus4 {
1324 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1325 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1326 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1327 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1330 sdmmc1_gpio: sdmmc1-gpio {
1332 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1333 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1334 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1335 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1336 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1337 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1338 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1339 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1340 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1345 emmc_clk: emmc-clk {
1347 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1350 emmc_cmd: emmc-cmd {
1352 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1355 emmc_pwren: emmc-pwren {
1357 <3 22 RK_FUNC_2 &pcfg_pull_none>;
1360 emmc_rstnout: emmc-rstnout {
1362 <3 20 RK_FUNC_2 &pcfg_pull_none>;
1365 emmc_bus1: emmc-bus1 {
1367 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1370 emmc_bus4: emmc-bus4 {
1372 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1373 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1374 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1375 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1378 emmc_bus8: emmc-bus8 {
1380 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1381 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1382 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1383 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1384 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1385 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1386 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1387 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1392 pwm0_pin: pwm0-pin {
1394 <2 4 RK_FUNC_1 &pcfg_pull_none>;
1399 pwm1_pin: pwm1-pin {
1401 <2 5 RK_FUNC_1 &pcfg_pull_none>;
1406 pwm2_pin: pwm2-pin {
1408 <2 6 RK_FUNC_1 &pcfg_pull_none>;
1413 pwmir_pin: pwmir-pin {
1415 <2 2 RK_FUNC_1 &pcfg_pull_none>;
1420 rgmiim0_pins: rgmiim0-pins {
1423 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1425 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1427 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1429 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1431 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1433 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1435 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1437 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1439 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1441 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1443 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1445 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1447 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1449 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1451 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1454 rmiim0_pins: rmiim0-pins {
1457 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1459 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1461 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1463 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1465 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1467 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1469 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1471 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1473 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1475 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1480 rgmiim1_pins: rgmiim1-pins {
1483 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1485 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1487 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1489 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1491 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1493 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1495 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1497 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1499 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1501 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1503 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1505 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1507 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1509 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1511 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1514 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1516 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1518 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1520 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1522 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1524 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1526 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1529 rmiim1_pins: rmiim1-pins {
1532 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1534 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1536 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1538 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1540 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1542 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1544 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1546 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1548 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1550 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1553 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1555 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1557 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1559 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1561 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1563 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1568 fephyled_speed100: fephyled-speed100 {
1570 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1573 fephyled_speed10: fephyled-speed10 {
1575 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1578 fephyled_duplex: fephyled-duplex {
1580 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1583 fephyled_rxm0: fephyled-rxm0 {
1585 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1588 fephyled_txm0: fephyled-txm0 {
1590 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1593 fephyled_linkm0: fephyled-linkm0 {
1595 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1598 fephyled_rxm1: fephyled-rxm1 {
1600 <2 25 RK_FUNC_2 &pcfg_pull_none>;
1603 fephyled_txm1: fephyled-txm1 {
1605 <2 25 RK_FUNC_3 &pcfg_pull_none>;
1608 fephyled_linkm1: fephyled-linkm1 {
1610 <2 24 RK_FUNC_2 &pcfg_pull_none>;
1615 tsadc_int: tsadc-int {
1617 <2 13 RK_FUNC_2 &pcfg_pull_none>;
1619 tsadc_gpio: tsadc-gpio {
1621 <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1626 hdmi_cec: hdmi-cec {
1628 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1631 hdmi_hpd: hdmi-hpd {
1633 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1638 dvp_d2d9_m0:dvp-d2d9-m0 {
1641 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1643 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1645 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1647 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1649 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1651 <3 9 RK_FUNC_2 &pcfg_pull_none>,
1653 <3 10 RK_FUNC_2 &pcfg_pull_none>,
1655 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1657 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1659 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1661 <3 3 RK_FUNC_2 &pcfg_pull_none>,
1663 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1668 dvp_d2d9_m1:dvp-d2d9-m1 {
1671 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1673 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1675 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1677 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1679 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1681 <2 16 RK_FUNC_4 &pcfg_pull_none>,
1683 <2 17 RK_FUNC_4 &pcfg_pull_none>,
1685 <2 18 RK_FUNC_4 &pcfg_pull_none>,
1687 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1689 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1691 <2 15 RK_FUNC_4 &pcfg_pull_none>,
1693 <3 2 RK_FUNC_2 &pcfg_pull_none>;