arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/power/rk3328-power.h>
  50
  51 / {
  52         compatible = "rockchip,rk3328";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 serial0 = &uart0;
  60                 serial1 = &uart1;
  61                 serial2 = &uart2;
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66         };
  67
  68         cpus {
  69                 #address-cells = <2>;
  70                 #size-cells = <0>;
  71
  72                 cpu0: cpu@0 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x0>;
  76                         enable-method = "psci";
  77                         clocks = <&cru ARMCLK>;
  78                         operating-points-v2 = <&cpu0_opp_table>;
  79                 };
  80                 cpu1: cpu@1 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53", "arm,armv8";
  83                         reg = <0x0 0x1>;
  84                         enable-method = "psci";
  85                         operating-points-v2 = <&cpu0_opp_table>;
  86                 };
  87                 cpu2: cpu@2 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a53", "arm,armv8";
  90                         reg = <0x0 0x2>;
  91                         enable-method = "psci";
  92                         operating-points-v2 = <&cpu0_opp_table>;
  93                 };
  94                 cpu3: cpu@3 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a53", "arm,armv8";
  97                         reg = <0x0 0x3>;
  98                         enable-method = "psci";
  99                         operating-points-v2 = <&cpu0_opp_table>;
 100                 };
 101         };
 102
 103         cpu0_opp_table: opp_table0 {
 104                 compatible = "operating-points-v2";
 105                 opp-shared;
 106
 107                 opp@408000000 {
 108                         opp-hz = /bits/ 64 <408000000>;
 109                         opp-microvolt = <950000>;
 110                         clock-latency-ns = <40000>;
 111                         opp-suspend;
 112                 };
 113                 opp@600000000 {
 114                         opp-hz = /bits/ 64 <600000000>;
 115                         opp-microvolt = <950000>;
 116                         clock-latency-ns = <40000>;
 117                 };
 118                 opp@816000000 {
 119                         opp-hz = /bits/ 64 <816000000>;
 120                         opp-microvolt = <1000000>;
 121                         clock-latency-ns = <40000>;
 122                 };
 123                 opp@1008000000 {
 124                         opp-hz = /bits/ 64 <1008000000>;
 125                         opp-microvolt = <1100000>;
 126                         clock-latency-ns = <40000>;
 127                 };
 128                 opp@1200000000 {
 129                         opp-hz = /bits/ 64 <1200000000>;
 130                         opp-microvolt = <1225000>;
 131                         clock-latency-ns = <40000>;
 132                 };
 133                 opp@1296000000 {
 134                         opp-hz = /bits/ 64 <1296000000>;
 135                         opp-microvolt = <1300000>;
 136                         clock-latency-ns = <40000>;
 137                 };
 138         };
 139
 140         arm-pmu {
 141                 compatible = "arm,cortex-a53-pmu";
 142                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 143                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 144                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 146                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 147         };
 148
 149         psci {
 150                 compatible = "arm,psci-1.0";
 151                 method = "smc";
 152         };
 153
 154         timer {
 155                 compatible = "arm,armv8-timer";
 156                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 157                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 158                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 159                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 160         };
 161
 162         xin24m: xin24m {
 163                 compatible = "fixed-clock";
 164                 #clock-cells = <0>;
 165                 clock-frequency = <24000000>;
 166                 clock-output-names = "xin24m";
 167         };
 168
 169         i2s0: i2s@ff000000 {
 170                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 171                 reg = <0x0 0xff000000 0x0 0x1000>;
 172                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 173                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 174                 clock-names = "i2s_clk", "i2s_hclk";
 175                 dmas = <&dmac 11>, <&dmac 12>;
 176                 #dma-cells = <2>;
 177                 dma-names = "tx", "rx";
 178                 status = "disabled";
 179         };
 180
 181         i2s1: i2s@ff010000 {
 182                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 183                 reg = <0x0 0xff010000 0x0 0x1000>;
 184                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 185                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 186                 clock-names = "i2s_clk", "i2s_hclk";
 187                 dmas = <&dmac 14>, <&dmac 15>;
 188                 #dma-cells = <2>;
 189                 dma-names = "tx", "rx";
 190                 status = "disabled";
 191         };
 192
 193         i2s2: i2s@ff020000 {
 194                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 195                 reg = <0x0 0xff020000 0x0 0x1000>;
 196                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 197                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 198                 clock-names = "i2s_clk", "i2s_hclk";
 199                 dmas = <&dmac 0>, <&dmac 1>;
 200                 #dma-cells = <2>;
 201                 dma-names = "tx", "rx";
 202                 pinctrl-names = "default", "sleep";
 203                 pinctrl-0 = <&i2s2m0_mclk
 204                              &i2s2m0_sclk
 205                              &i2s2m0_lrcktx
 206                              &i2s2m0_lrckrx
 207                              &i2s2m0_sdo
 208                              &i2s2m0_sdi>;
 209                 pinctrl-1 = <&i2s2m0_sleep>;
 210                 status = "disabled";
 211         };
 212
 213         spdif: spdif@ff030000 {
 214                 compatible = "rockchip,rk3328-spdif";
 215                 reg = <0x0 0xff030000 0x0 0x1000>;
 216                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 217                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 218                 clock-names = "mclk", "hclk";
 219                 dmas = <&dmac 10>;
 220                 #dma-cells = <1>;
 221                 dma-names = "tx";
 222                 pinctrl-names = "default";
 223                 pinctrl-0 = <&spdifm2_tx>;
 224                 status = "disabled";
 225         };
 226
 227         grf: syscon@ff100000 {
 228                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 229                 reg = <0x0 0xff100000 0x0 0x1000>;
 230                 #address-cells = <1>;
 231                 #size-cells = <1>;
 232
 233                 io_domains: io-domains {
 234                         compatible = "rockchip,rk3328-io-voltage-domain";
 235                         status = "disabled";
 236                 };
 237
 238                 power: power-controller {
 239                         compatible = "rockchip,rk3328-power-controller";
 240                         #power-domain-cells = <1>;
 241                         #address-cells = <1>;
 242                         #size-cells = <0>;
 243                         status = "disabled";
 244
 245                         pd_hevc@RK3328_PD_HEVC {
 246                                 reg = <RK3328_PD_HEVC>;
 247                         };
 248                         pd_video@RK3328_PD_VIDEO {
 249                                 reg = <RK3328_PD_VIDEO>;
 250                         };
 251                         pd_vpu@RK3328_PD_VPU {
 252                                 reg = <RK3328_PD_VPU>;
 253                         };
 254                 };
 255
 256                 reboot-mode {
 257                         compatible = "syscon-reboot-mode";
 258                         offset = <0x5c8>;
 259                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 260                         mode-charge = <BOOT_CHARGING>;
 261                         mode-fastboot = <BOOT_FASTBOOT>;
 262                         mode-loader = <BOOT_BL_DOWNLOAD>;
 263                         mode-normal = <BOOT_NORMAL>;
 264                         mode-recovery = <BOOT_RECOVERY>;
 265                         mode-ums = <BOOT_UMS>;
 266                 };
 267         };
 268
 269         uart0: serial@ff110000 {
 270                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 271                 reg = <0x0 0xff110000 0x0 0x100>;
 272                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 273                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 274                 clock-names = "baudclk", "apb_pclk";
 275                 reg-shift = <2>;
 276                 reg-io-width = <4>;
 277                 dmas = <&dmac 2>, <&dmac 3>;
 278                 #dma-cells = <2>;
 279                 pinctrl-names = "default";
 280                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 281                 status = "disabled";
 282         };
 283
 284         uart1: serial@ff120000 {
 285                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 286                 reg = <0x0 0xff120000 0x0 0x100>;
 287                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 288                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 289                 clock-names = "sclk_uart", "pclk_uart";
 290                 reg-shift = <2>;
 291                 reg-io-width = <4>;
 292                 dmas = <&dmac 4>, <&dmac 5>;
 293                 #dma-cells = <2>;
 294                 pinctrl-names = "default";
 295                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 296                 status = "disabled";
 297         };
 298
 299         uart2: serial@ff130000 {
 300                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 301                 reg = <0x0 0xff130000 0x0 0x100>;
 302                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 303                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 304                 clock-names = "baudclk", "apb_pclk";
 305                 reg-shift = <2>;
 306                 reg-io-width = <4>;
 307                 dmas = <&dmac 6>, <&dmac 7>;
 308                 #dma-cells = <2>;
 309                 pinctrl-names = "default";
 310                 pinctrl-0 = <&uart2m1_xfer>;
 311                 status = "disabled";
 312         };
 313
 314         pmu: power-management@ff140000 {
 315                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 316                 reg = <0x0 0xff140000 0x0 0x1000>;
 317         };
 318
 319         i2c0: i2c@ff150000 {
 320                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 321                 reg = <0x0 0xff150000 0x0 0x1000>;
 322                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 326                 clock-names = "i2c", "pclk";
 327                 pinctrl-names = "default";
 328                 pinctrl-0 = <&i2c0_xfer>;
 329                 status = "disabled";
 330         };
 331
 332         i2c1: i2c@ff160000 {
 333                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 334                 reg = <0x0 0xff160000 0x0 0x1000>;
 335                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 336                 #address-cells = <1>;
 337                 #size-cells = <0>;
 338                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 339                 clock-names = "i2c", "pclk";
 340                 pinctrl-names = "default";
 341                 pinctrl-0 = <&i2c1_xfer>;
 342                 status = "disabled";
 343         };
 344
 345         i2c2: i2c@ff170000 {
 346                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 347                 reg = <0x0 0xff170000 0x0 0x1000>;
 348                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 349                 #address-cells = <1>;
 350                 #size-cells = <0>;
 351                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 352                 clock-names = "i2c", "pclk";
 353                 pinctrl-names = "default";
 354                 pinctrl-0 = <&i2c2_xfer>;
 355                 status = "disabled";
 356         };
 357
 358         i2c3: i2c@ff180000 {
 359                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 360                 reg = <0x0 0xff180000 0x0 0x1000>;
 361                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 365                 clock-names = "i2c", "pclk";
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&i2c3_xfer>;
 368                 status = "disabled";
 369         };
 370
 371         spi0: spi@ff190000 {
 372                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 373                 reg = <0x0 0xff190000 0x0 0x1000>;
 374                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 378                 clock-names = "spiclk", "apb_pclk";
 379                 dmas = <&dmac 8>, <&dmac 9>;
 380                 #dma-cells = <2>;
 381                 dma-names = "tx", "rx";
 382                 pinctrl-names = "default";
 383                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 384                 status = "disabled";
 385         };
 386
 387         wdt: watchdog@ff1a0000 {
 388                 compatible = "snps,dw-wdt";
 389                 reg = <0x0 0xff1a0000 0x0 0x100>;
 390                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 391                 status = "disabled";
 392         };
 393
 394         pwm0: pwm@ff1b0000 {
 395                 compatible = "rockchip,rk3328-pwm";
 396                 reg = <0x0 0xff1b0000 0x0 0x10>;
 397                 #pwm-cells = <3>;
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&pwm0_pin>;
 400                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 401                 clock-names = "pwm", "pclk";
 402                 status = "disabled";
 403         };
 404
 405         pwm1: pwm@ff1b0010 {
 406                 compatible = "rockchip,rk3328-pwm";
 407                 reg = <0x0 0xff1b0010 0x0 0x10>;
 408                 #pwm-cells = <3>;
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&pwm1_pin>;
 411                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 412                 clock-names = "pwm", "pclk";
 413                 status = "disabled";
 414         };
 415
 416         pwm2: pwm@ff1b0020 {
 417                 compatible = "rockchip,rk3328-pwm";
 418                 reg = <0x0 0xff1b0020 0x0 0x10>;
 419                 #pwm-cells = <3>;
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&pwm2_pin>;
 422                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 423                 clock-names = "pwm", "pclk";
 424                 status = "disabled";
 425         };
 426
 427         pwm3: pwm@ff1b0030 {
 428                 compatible = "rockchip,rk3328-pwm";
 429                 reg = <0x0 0xff1b0030 0x0 0x10>;
 430                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 431                 #pwm-cells = <3>;
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&pwmir_pin>;
 434                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 435                 clock-names = "pwm", "pclk";
 436                 status = "disabled";
 437         };
 438
 439         amba {
 440                 compatible = "simple-bus";
 441                 #address-cells = <2>;
 442                 #size-cells = <2>;
 443                 ranges;
 444
 445                 dmac: dmac@ff1f0000 {
 446                         compatible = "arm,pl330", "arm,primecell";
 447                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 448                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 449                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 450                         clocks = <&cru ACLK_DMAC>;
 451                         clock-names = "apb_pclk";
 452                         #dma-cells = <1>;
 453                 };
 454         };
 455
 456         saradc: saradc@ff280000 {
 457                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 458                 reg = <0x0 0xff280000 0x0 0x100>;
 459                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 460                 #io-channel-cells = <1>;
 461                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 462                 clock-names = "saradc", "apb_pclk";
 463                 resets = <&cru SRST_SARADC_P>;
 464                 reset-names = "saradc-apb";
 465                 status = "disabled";
 466         };
 467
 468         cru: clock-controller@ff440000 {
 469                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 470                 reg = <0x0 0xff440000 0x0 0x1000>;
 471                 rockchip,grf = <&grf>;
 472                 #clock-cells = <1>;
 473                 #reset-cells = <1>;
 474                 assigned-clocks =
 475                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 476                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 477                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 478                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 479                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 480                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 481                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 482                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 483                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 484                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 485                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 486                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 487                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 488                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 489                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 490                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 491                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 492                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 493                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 494                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 495                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 496                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 497                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 498                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 499                 assigned-clock-parents =
 500                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 501                         <&cru PLL_GPLL>, <&xin24m>,
 502                         <&xin24m>, <&xin24m>;
 503                 assigned-clock-rates =
 504                         <0>, <61440000>,
 505                         <0>, <24000000>,
 506                         <24000000>, <24000000>,
 507                         <15000000>, <15000000>,
 508                         <100000000>, <100000000>,
 509                         <100000000>, <100000000>,
 510                         <50000000>, <100000000>,
 511                         <100000000>, <100000000>,
 512                         <50000000>, <50000000>,
 513                         <50000000>, <50000000>,
 514                         <24000000>, <600000000>,
 515                         <491520000>, <1200000000>,
 516                         <150000000>, <75000000>,
 517                         <75000000>, <150000000>,
 518                         <75000000>, <75000000>,
 519                         <300000000>, <100000000>,
 520                         <300000000>, <200000000>,
 521                         <400000000>, <500000000>,
 522                         <200000000>, <300000000>,
 523                         <300000000>, <250000000>,
 524                         <200000000>, <100000000>,
 525                         <24000000>, <100000000>,
 526                         <150000000>, <50000000>,
 527                         <32768>, <32768>;
 528         };
 529
 530         usb2phy_grf: syscon@ff450000 {
 531                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 532                              "simple-mfd";
 533                 reg = <0x0 0xff450000 0x0 0x10000>;
 534                 #address-cells = <1>;
 535                 #size-cells = <1>;
 536
 537                 u2phy: usb2-phy@100 {
 538                         compatible = "rockchip,rk3328-usb2phy";
 539                         reg = <0x100 0x10>;
 540                         clocks = <&xin24m>;
 541                         clock-names = "phyclk";
 542                         #clock-cells = <0>;
 543                         assigned-clocks = <&cru USB480M>;
 544                         assigned-clock-parents = <&u2phy>;
 545                         clock-output-names = "usb480m_phy";
 546                         status = "disabled";
 547
 548                         u2phy_host: host-port {
 549                                 #phy-cells = <0>;
 550                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 551                                 interrupt-names = "linestate";
 552                                 status = "disabled";
 553                         };
 554
 555                         u2phy_otg: otg-port {
 556                                 #phy-cells = <0>;
 557                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 558                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 559                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 560                                 interrupt-names = "otg-bvalid", "otg-id",
 561                                                   "linestate";
 562                                 status = "disabled";
 563                         };
 564                 };
 565         };
 566
 567         usb3phy_grf: syscon@ff460000 {
 568                 compatible = "rockchip,usb3phy-grf", "syscon";
 569                 reg = <0x0 0xff460000 0x0 0x1000>;
 570         };
 571
 572         u3phy: usb3-phy@ff470000 {
 573                 compatible = "rockchip,rk3328-u3phy";
 574                 reg = <0x0 0xff470000 0x0 0x0>;
 575                 rockchip,u3phygrf = <&usb3phy_grf>;
 576                 rockchip,grf = <&grf>;
 577                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 578                 interrupt-names = "linestate";
 579                 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
 580                 clock-names = "u3phy-otg", "u3phy-pipe";
 581                 resets = <&cru SRST_USB3PHY_U2>,
 582                          <&cru SRST_USB3PHY_U3>,
 583                          <&cru SRST_USB3PHY_PIPE>,
 584                          <&cru SRST_USB3OTG_UTMI>,
 585                          <&cru SRST_USB3PHY_OTG_P>,
 586                          <&cru SRST_USB3PHY_PIPE_P>;
 587                 reset-names = "u3phy-u2-por", "u3phy-u3-por",
 588                               "u3phy-pipe-mac", "u3phy-utmi-mac",
 589                               "u3phy-utmi-apb", "u3phy-pipe-apb";
 590                 #address-cells = <2>;
 591                 #size-cells = <2>;
 592                 ranges;
 593                 status = "disabled";
 594
 595                 u3phy_utmi: utmi@ff470000 {
 596                         reg = <0x0 0xff470000 0x0 0x8000>;
 597                         #phy-cells = <0>;
 598                         status = "disabled";
 599                 };
 600
 601                 u3phy_pipe: pipe@ff478000 {
 602                         reg = <0x0 0xff478000 0x0 0x8000>;
 603                         #phy-cells = <0>;
 604                         status = "disabled";
 605                 };
 606         };
 607
 608         sdmmc: rksdmmc@ff500000 {
 609                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 610                 reg = <0x0 0xff500000 0x0 0x4000>;
 611                 clock-freq-min-max = <400000 150000000>;
 612                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 613                 clock-names = "biu", "ciu";
 614                 fifo-depth = <0x100>;
 615                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 616                 status = "disabled";
 617         };
 618
 619         sdio: dwmmc@ff510000 {
 620                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 621                 reg = <0x0 0xff510000 0x0 0x4000>;
 622                 clock-freq-min-max = <400000 150000000>;
 623                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 624                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 625                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 626                 fifo-depth = <0x100>;
 627                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 628                 status = "disabled";
 629         };
 630
 631         emmc: rksdmmc@ff520000 {
 632                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 633                 reg = <0x0 0xff520000 0x0 0x4000>;
 634                 clock-freq-min-max = <400000 150000000>;
 635                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 636                 clock-names = "biu", "ciu";
 637                 fifo-depth = <0x100>;
 638                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 639                 status = "disabled";
 640         };
 641
 642         gmac2io: eth@ff540000 {
 643                 compatible = "rockchip,rk3328-gmac";
 644                 reg = <0x0 0xff540000 0x0 0x10000>;
 645                 rockchip,grf = <&grf>;
 646                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 647                 interrupt-names = "macirq";
 648                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 649                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 650                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 651                          <&cru PCLK_MAC2IO>;
 652                 clock-names = "stmmaceth", "mac_clk_rx",
 653                               "mac_clk_tx", "clk_mac_ref",
 654                               "clk_mac_refout", "aclk_mac",
 655                               "pclk_mac";
 656                 resets = <&cru SRST_GMAC2IO_A>;
 657                 reset-names = "stmmaceth";
 658                 status = "disabled";
 659         };
 660
 661         usb20_otg: usb@ff580000 {
 662                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 663                              "snps,dwc2";
 664                 reg = <0x0 0xff580000 0x0 0x40000>;
 665                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 666                 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
 667                 clock-names = "otg", "otg_pmu";
 668                 dr_mode = "otg";
 669                 g-np-tx-fifo-size = <16>;
 670                 g-rx-fifo-size = <275>;
 671                 g-tx-fifo-size = <256 128 128 64 64 32>;
 672                 g-use-dma;
 673                 phys = <&u2phy_otg>;
 674                 phy-names = "usb2-phy";
 675                 status = "disabled";
 676         };
 677
 678         usb_host0_ehci: usb@ff5c0000 {
 679                 compatible = "generic-ehci";
 680                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 681                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 682                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 683                          <&u2phy>;
 684                 clock-names = "usbhost", "arbiter", "utmi";
 685                 phys = <&u2phy_host>;
 686                 phy-names = "usb";
 687                 status = "disabled";
 688         };
 689
 690         usb_host0_ohci: usb@ff5d0000 {
 691                 compatible = "generic-ohci";
 692                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 693                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 694                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 695                          <&u2phy>;
 696                 clock-names = "usbhost", "arbiter", "utmi";
 697                 phys = <&u2phy_host>;
 698                 phy-names = "usb";
 699                 status = "disabled";
 700         };
 701
 702         sdmmc_ext: rksdmmc@ff5f0000 {
 703                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 704                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 705                 clock-freq-min-max = <400000 150000000>;
 706                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 707                 clock-names = "biu", "ciu";
 708                 fifo-depth = <0x100>;
 709                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 710                 status = "disabled";
 711         };
 712
 713         usbdrd3: usb@ff600000 {
 714                 compatible = "rockchip,rk3328-dwc3";
 715                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
 716                          <&cru ACLK_USB3OTG>;
 717                 clock-names = "ref_clk", "suspend_clk",
 718                               "bus_clk";
 719                 #address-cells = <2>;
 720                 #size-cells = <2>;
 721                 ranges;
 722                 status = "disabled";
 723
 724                 usbdrd_dwc3: dwc3@ff600000 {
 725                         compatible = "snps,dwc3";
 726                         reg = <0x0 0xff600000 0x0 0x100000>;
 727                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 728                         dr_mode = "host";
 729                         phys = <&u3phy_utmi>, <&u3phy_pipe>;
 730                         phy-names = "usb2-phy", "usb3-phy";
 731                         phy_type = "utmi_wide";
 732                         snps,dis_enblslpm_quirk;
 733                         snps,dis-u2-freeclk-exists-quirk;
 734                         snps,dis_u2_susphy_quirk;
 735                         snps,dis-u3-autosuspend-quirk;
 736                         snps,dis_u3_susphy_quirk;
 737                         snps,dis-del-phy-power-chg-quirk;
 738                         status = "disabled";
 739                 };
 740         };
 741
 742         gic: interrupt-controller@ff811000 {
 743                 compatible = "arm,gic-400";
 744                 #interrupt-cells = <3>;
 745                 #address-cells = <0>;
 746                 interrupt-controller;
 747                 reg = <0x0 0xff811000 0 0x1000>,
 748                       <0x0 0xff812000 0 0x2000>,
 749                       <0x0 0xff814000 0 0x2000>,
 750                       <0x0 0xff816000 0 0x2000>;
 751                 interrupts = <GIC_PPI 9
 752                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 753         };
 754
 755         pinctrl: pinctrl {
 756                 compatible = "rockchip,rk3328-pinctrl";
 757                 rockchip,grf = <&grf>;
 758                 #address-cells = <2>;
 759                 #size-cells = <2>;
 760                 ranges;
 761
 762                 gpio0: gpio0@ff210000 {
 763                         compatible = "rockchip,gpio-bank";
 764                         reg = <0x0 0xff210000 0x0 0x100>;
 765                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 766                         clocks = <&cru PCLK_GPIO0>;
 767
 768                         gpio-controller;
 769                         #gpio-cells = <2>;
 770
 771                         interrupt-controller;
 772                         #interrupt-cells = <2>;
 773                 };
 774
 775                 gpio1: gpio1@ff220000 {
 776                         compatible = "rockchip,gpio-bank";
 777                         reg = <0x0 0xff220000 0x0 0x100>;
 778                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 779                         clocks = <&cru PCLK_GPIO1>;
 780
 781                         gpio-controller;
 782                         #gpio-cells = <2>;
 783
 784                         interrupt-controller;
 785                         #interrupt-cells = <2>;
 786                 };
 787
 788                 gpio2: gpio2@ff230000 {
 789                         compatible = "rockchip,gpio-bank";
 790                         reg = <0x0 0xff230000 0x0 0x100>;
 791                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 792                         clocks = <&cru PCLK_GPIO2>;
 793
 794                         gpio-controller;
 795                         #gpio-cells = <2>;
 796
 797                         interrupt-controller;
 798                         #interrupt-cells = <2>;
 799                 };
 800
 801                 gpio3: gpio3@ff240000 {
 802                         compatible = "rockchip,gpio-bank";
 803                         reg = <0x0 0xff240000 0x0 0x100>;
 804                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 805                         clocks = <&cru PCLK_GPIO3>;
 806
 807                         gpio-controller;
 808                         #gpio-cells = <2>;
 809
 810                         interrupt-controller;
 811                         #interrupt-cells = <2>;
 812                 };
 813
 814                 pcfg_pull_up: pcfg-pull-up {
 815                         bias-pull-up;
 816                 };
 817
 818                 pcfg_pull_down: pcfg-pull-down {
 819                         bias-pull-down;
 820                 };
 821
 822                 pcfg_pull_none: pcfg-pull-none {
 823                         bias-disable;
 824                 };
 825
 826                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 827                         bias-disable;
 828                         drive-strength = <2>;
 829                 };
 830
 831                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 832                         bias-pull-up;
 833                         drive-strength = <2>;
 834                 };
 835
 836                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 837                         bias-pull-up;
 838                         drive-strength = <4>;
 839                 };
 840
 841                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 842                         bias-disable;
 843                         drive-strength = <4>;
 844                 };
 845
 846                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 847                         bias-pull-down;
 848                         drive-strength = <4>;
 849                 };
 850
 851                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 852                         bias-disable;
 853                         drive-strength = <8>;
 854                 };
 855
 856                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 857                         bias-pull-up;
 858                         drive-strength = <8>;
 859                 };
 860
 861                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 862                         bias-disable;
 863                         drive-strength = <12>;
 864                 };
 865
 866                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 867                         bias-pull-up;
 868                         drive-strength = <12>;
 869                 };
 870
 871                 pcfg_output_high: pcfg-output-high {
 872                         output-high;
 873                 };
 874
 875                 pcfg_output_low: pcfg-output-low {
 876                         output-low;
 877                 };
 878
 879                 pcfg_input_high: pcfg-input-high {
 880                         bias-pull-up;
 881                         input-enable;
 882                 };
 883
 884                 pcfg_input: pcfg-input {
 885                         input-enable;
 886                 };
 887
 888                 i2c0 {
 889                         i2c0_xfer: i2c0-xfer {
 890                                 rockchip,pins =
 891                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 892                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 893                         };
 894                 };
 895
 896                 i2c1 {
 897                         i2c1_xfer: i2c1-xfer {
 898                                 rockchip,pins =
 899                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 900                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 901                         };
 902                 };
 903
 904                 i2c2 {
 905                         i2c2_xfer: i2c2-xfer {
 906                                 rockchip,pins =
 907                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 908                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 909                         };
 910                 };
 911
 912                 i2c3 {
 913                         i2c3_xfer: i2c3-xfer {
 914                                 rockchip,pins =
 915                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 916                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 917                         };
 918                         i2c3_gpio: i2c3-gpio {
 919                                 rockchip,pins =
 920                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 921                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 922                         };
 923                 };
 924
 925                 hdmi_i2c {
 926                         hdmii2c_xfer: hdmii2c-xfer {
 927                                 rockchip,pins =
 928                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 929                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 930                         };
 931                 };
 932
 933                 uart0 {
 934                         uart0_xfer: uart0-xfer {
 935                                 rockchip,pins =
 936                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
 937                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 938                         };
 939
 940                         uart0_cts: uart0-cts {
 941                                 rockchip,pins =
 942                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 943                         };
 944
 945                         uart0_rts: uart0-rts {
 946                                 rockchip,pins =
 947                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
 948                         };
 949
 950                         uart0_rts_gpio: uart0-rts-gpio {
 951                                 rockchip,pins =
 952                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
 953                         };
 954                 };
 955
 956                 uart1 {
 957                         uart1_xfer: uart1-xfer {
 958                                 rockchip,pins =
 959                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
 960                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
 961                         };
 962
 963                         uart1_cts: uart1-cts {
 964                                 rockchip,pins =
 965                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
 966                         };
 967
 968                         uart1_rts: uart1-rts {
 969                                 rockchip,pins =
 970                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
 971                         };
 972
 973                         uart1_rts_gpio: uart1-rts-gpio {
 974                                 rockchip,pins =
 975                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
 976                         };
 977                 };
 978
 979                 uart2-0 {
 980                         uart2m0_xfer: uart2m0-xfer {
 981                                 rockchip,pins =
 982                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
 983                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
 984                         };
 985                 };
 986
 987                 uart2-1 {
 988                         uart2m1_xfer: uart2m1-xfer {
 989                                 rockchip,pins =
 990                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
 991                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
 992                         };
 993                 };
 994
 995                 spi0-0 {
 996                         spi0m0_clk: spi0m0-clk {
 997                                 rockchip,pins =
 998                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
 999                         };
1000
1001                         spi0m0_cs0: spi0m0-cs0 {
1002                                 rockchip,pins =
1003                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1004                         };
1005
1006                         spi0m0_tx: spi0m0-tx {
1007                                 rockchip,pins =
1008                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1009                         };
1010
1011                         spi0m0_rx: spi0m0-rx {
1012                                 rockchip,pins =
1013                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1014                         };
1015
1016                         spi0m0_cs1: spi0m0-cs1 {
1017                                 rockchip,pins =
1018                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1019                         };
1020                 };
1021
1022                 spi0-1 {
1023                         spi0m1_clk: spi0m1-clk {
1024                                 rockchip,pins =
1025                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
1026                         };
1027
1028                         spi0m1_cs0: spi0m1-cs0 {
1029                                 rockchip,pins =
1030                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
1031                         };
1032
1033                         spi0m1_tx: spi0m1-tx {
1034                                 rockchip,pins =
1035                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
1036                         };
1037
1038                         spi0m1_rx: spi0m1-rx {
1039                                 rockchip,pins =
1040                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
1041                         };
1042
1043                         spi0m1_cs1: spi0m1-cs1 {
1044                                 rockchip,pins =
1045                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
1046                         };
1047                 };
1048
1049                 spi0-2 {
1050                         spi0m2_clk: spi0m2-clk {
1051                                 rockchip,pins =
1052                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
1053                         };
1054
1055                         spi0m2_cs0: spi0m2-cs0 {
1056                                 rockchip,pins =
1057                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
1058                         };
1059
1060                         spi0m2_tx: spi0m2-tx {
1061                                 rockchip,pins =
1062                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
1063                         };
1064
1065                         spi0m2_rx: spi0m2-rx {
1066                                 rockchip,pins =
1067                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
1068                         };
1069                 };
1070
1071                 i2s1 {
1072                         i2s1_mclk: i2s1-mclk {
1073                                 rockchip,pins =
1074                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
1075                         };
1076
1077                         i2s1_sclk: i2s1-sclk {
1078                                 rockchip,pins =
1079                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1080                         };
1081
1082                         i2s1_lrckrx: i2s1-lrckrx {
1083                                 rockchip,pins =
1084                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
1085                         };
1086
1087                         i2s1_lrcktx: i2s1-lrcktx {
1088                                 rockchip,pins =
1089                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1090                         };
1091
1092                         i2s1_sdi: i2s1-sdi {
1093                                 rockchip,pins =
1094                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1095                         };
1096
1097                         i2s1_sdo: i2s1-sdo {
1098                                 rockchip,pins =
1099                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
1100                         };
1101
1102                         i2s1_sdio1: i2s1-sdio1 {
1103                                 rockchip,pins =
1104                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
1105                         };
1106
1107                         i2s1_sdio2: i2s1-sdio2 {
1108                                 rockchip,pins =
1109                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
1110                         };
1111
1112                         i2s1_sdio3: i2s1-sdio3 {
1113                                 rockchip,pins =
1114                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
1115                         };
1116
1117                         i2s1_sleep: i2s1-sleep {
1118                                 rockchip,pins =
1119                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
1120                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
1121                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
1122                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
1123                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
1124                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
1125                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
1126                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
1127                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
1128                         };
1129                 };
1130
1131                 i2s2-0 {
1132                         i2s2m0_mclk: i2s2m0-mclk {
1133                                 rockchip,pins =
1134                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1135                         };
1136
1137                         i2s2m0_sclk: i2s2m0-sclk {
1138                                 rockchip,pins =
1139                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
1140                         };
1141
1142                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1143                                 rockchip,pins =
1144                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
1145                         };
1146
1147                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1148                                 rockchip,pins =
1149                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
1150                         };
1151
1152                         i2s2m0_sdi: i2s2m0-sdi {
1153                                 rockchip,pins =
1154                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
1155                         };
1156
1157                         i2s2m0_sdo: i2s2m0-sdo {
1158                                 rockchip,pins =
1159                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
1160                         };
1161
1162                         i2s2m0_sleep: i2s2m0-sleep {
1163                                 rockchip,pins =
1164                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1165                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
1166                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
1167                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
1168                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
1169                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
1170                         };
1171                 };
1172
1173                 i2s2-1 {
1174                         i2s2m1_mclk: i2s2m1-mclk {
1175                                 rockchip,pins =
1176                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1177                         };
1178
1179                         i2s2m1_sclk: i2s2m1-sclk {
1180                                 rockchip,pins =
1181                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
1182                         };
1183
1184                         i2s2m1_lrckrx: i2sm1-lrckrx {
1185                                 rockchip,pins =
1186                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
1187                         };
1188
1189                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1190                                 rockchip,pins =
1191                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
1192                         };
1193
1194                         i2s2m1_sdi: i2s2m1-sdi {
1195                                 rockchip,pins =
1196                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
1197                         };
1198
1199                         i2s2m1_sdo: i2s2m1-sdo {
1200                                 rockchip,pins =
1201                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
1202                         };
1203
1204                         i2s2m1_sleep: i2s2m1-sleep {
1205                                 rockchip,pins =
1206                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1207                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
1208                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
1209                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
1210                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
1211                         };
1212                 };
1213
1214                 spdif-0 {
1215                         spdifm0_tx: spdifm0-tx {
1216                                 rockchip,pins =
1217                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
1218                         };
1219                 };
1220
1221                 spdif-1 {
1222                         spdifm1_tx: spdifm1-tx {
1223                                 rockchip,pins =
1224                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1225                         };
1226                 };
1227
1228                 spdif-2 {
1229                         spdifm2_tx: spdifm2-tx {
1230                                 rockchip,pins =
1231                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
1232                         };
1233                 };
1234
1235                 sdmmc0-0 {
1236                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1237                                 rockchip,pins =
1238                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1239                         };
1240
1241                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1242                                 rockchip,pins =
1243                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1244                         };
1245                 };
1246
1247                 sdmmc0-1 {
1248                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1249                                 rockchip,pins =
1250                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1251                         };
1252
1253                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1254                                 rockchip,pins =
1255                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1256                         };
1257                 };
1258
1259                 sdmmc0 {
1260                         sdmmc0_clk: sdmmc0-clk {
1261                                 rockchip,pins =
1262                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1263                         };
1264
1265                         sdmmc0_cmd: sdmmc0-cmd {
1266                                 rockchip,pins =
1267                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1268                         };
1269
1270                         sdmmc0_dectn: sdmmc0-dectn {
1271                                 rockchip,pins =
1272                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1273                         };
1274
1275                         sdmmc0_wrprt: sdmmc0-wrprt {
1276                                 rockchip,pins =
1277                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1278                         };
1279
1280                         sdmmc0_bus1: sdmmc0-bus1 {
1281                                 rockchip,pins =
1282                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1283                         };
1284
1285                         sdmmc0_bus4: sdmmc0-bus4 {
1286                                 rockchip,pins =
1287                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1288                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1289                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1290                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1291                         };
1292
1293                         sdmmc0_gpio: sdmmc0-gpio {
1294                                 rockchip,pins =
1295                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1296                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1297                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1298                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1299                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1300                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1301                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1302                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1303                         };
1304                 };
1305
1306                 sdmmc0ext {
1307                         sdmmc0ext_clk: sdmmc0ext-clk {
1308                                 rockchip,pins =
1309                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1310                         };
1311
1312                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1313                                 rockchip,pins =
1314                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1315                         };
1316
1317                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1318                                 rockchip,pins =
1319                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1320                         };
1321
1322                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1323                                 rockchip,pins =
1324                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1325                         };
1326
1327                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1328                                 rockchip,pins =
1329                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1330                         };
1331
1332                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1333                                 rockchip,pins =
1334                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1335                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1336                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1337                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1338                         };
1339
1340                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1341                                 rockchip,pins =
1342                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1343                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1344                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1345                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1346                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1347                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1348                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1349                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1350                         };
1351                 };
1352
1353                 sdmmc1 {
1354                         sdmmc1_clk: sdmmc1-clk {
1355                                 rockchip,pins =
1356                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1357                         };
1358
1359                         sdmmc1_cmd: sdmmc1-cmd {
1360                                 rockchip,pins =
1361                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1362                         };
1363
1364                         sdmmc1_pwren: sdmmc1-pwren {
1365                                 rockchip,pins =
1366                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1367                         };
1368
1369                         sdmmc1_wrprt: sdmmc1-wrprt {
1370                                 rockchip,pins =
1371                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1372                         };
1373
1374                         sdmmc1_dectn: sdmmc1-dectn {
1375                                 rockchip,pins =
1376                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1377                         };
1378
1379                         sdmmc1_bus1: sdmmc1-bus1 {
1380                                 rockchip,pins =
1381                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1382                         };
1383
1384                         sdmmc1_bus4: sdmmc1-bus4 {
1385                                 rockchip,pins =
1386                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1387                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1388                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1389                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1390                         };
1391
1392                         sdmmc1_gpio: sdmmc1-gpio {
1393                                 rockchip,pins =
1394                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1395                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1396                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1397                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1398                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1399                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1400                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1401                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1402                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1403                         };
1404                 };
1405
1406                 emmc {
1407                         emmc_clk: emmc-clk {
1408                                 rockchip,pins =
1409                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1410                         };
1411
1412                         emmc_cmd: emmc-cmd {
1413                                 rockchip,pins =
1414                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1415                         };
1416
1417                         emmc_pwren: emmc-pwren {
1418                                 rockchip,pins =
1419                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1420                         };
1421
1422                         emmc_rstnout: emmc-rstnout {
1423                                 rockchip,pins =
1424                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1425                         };
1426
1427                         emmc_bus1: emmc-bus1 {
1428                                 rockchip,pins =
1429                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1430                         };
1431
1432                         emmc_bus4: emmc-bus4 {
1433                                 rockchip,pins =
1434                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1435                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1436                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1437                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1438                         };
1439
1440                         emmc_bus8: emmc-bus8 {
1441                                 rockchip,pins =
1442                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1443                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1444                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1445                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1446                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1447                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1448                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1449                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1450                         };
1451                 };
1452
1453                 pwm0 {
1454                         pwm0_pin: pwm0-pin {
1455                                 rockchip,pins =
1456                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1457                         };
1458                 };
1459
1460                 pwm1 {
1461                         pwm1_pin: pwm1-pin {
1462                                 rockchip,pins =
1463                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1464                         };
1465                 };
1466
1467                 pwm2 {
1468                         pwm2_pin: pwm2-pin {
1469                                 rockchip,pins =
1470                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1471                         };
1472                 };
1473
1474                 pwmir {
1475                         pwmir_pin: pwmir-pin {
1476                                 rockchip,pins =
1477                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1478                         };
1479                 };
1480
1481                 gmac-0 {
1482                         rgmiim0_pins: rgmiim0-pins {
1483                                 rockchip,pins =
1484                                         /* mac_txclk */
1485                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1486                                         /* mac_rxclk */
1487                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1488                                         /* mac_mdio */
1489                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1490                                         /* mac_txen */
1491                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1492                                         /* mac_clk */
1493                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1494                                         /* mac_rxdv */
1495                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1496                                         /* mac_mdc */
1497                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1498                                         /* mac_rxd1 */
1499                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1500                                         /* mac_rxd0 */
1501                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1502                                         /* mac_txd1 */
1503                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1504                                         /* mac_txd0 */
1505                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1506                                         /* mac_rxd3 */
1507                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1508                                         /* mac_rxd2 */
1509                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1510                                         /* mac_txd3 */
1511                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1512                                         /* mac_txd2 */
1513                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1514                         };
1515
1516                         rmiim0_pins: rmiim0-pins {
1517                                 rockchip,pins =
1518                                         /* mac_mdio */
1519                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1520                                         /* mac_txen */
1521                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1522                                         /* mac_clk */
1523                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1524                                         /* mac_rxer */
1525                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1526                                         /* mac_rxdv */
1527                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1528                                         /* mac_mdc */
1529                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1530                                         /* mac_rxd1 */
1531                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1532                                         /* mac_rxd0 */
1533                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1534                                         /* mac_txd1 */
1535                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1536                                         /* mac_txd0 */
1537                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1538                         };
1539                 };
1540
1541                 gmac-1 {
1542                         rgmiim1_pins: rgmiim1-pins {
1543                                 rockchip,pins =
1544                                         /* mac_txclk */
1545                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1546                                         /* mac_rxclk */
1547                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1548                                         /* mac_mdio */
1549                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1550                                         /* mac_txen */
1551                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1552                                         /* mac_clk */
1553                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1554                                         /* mac_rxdv */
1555                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1556                                         /* mac_mdc */
1557                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1558                                         /* mac_rxd1 */
1559                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1560                                         /* mac_rxd0 */
1561                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1562                                         /* mac_txd1 */
1563                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1564                                         /* mac_txd0 */
1565                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1566                                         /* mac_rxd3 */
1567                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1568                                         /* mac_rxd2 */
1569                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1570                                         /* mac_txd3 */
1571                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1572                                         /* mac_txd2 */
1573                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1574
1575                                         /* mac_txclk */
1576                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1577                                         /* mac_txen */
1578                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1579                                         /* mac_clk */
1580                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1581                                         /* mac_txd1 */
1582                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1583                                         /* mac_txd0 */
1584                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1585                                         /* mac_txd3 */
1586                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1587                                         /* mac_txd2 */
1588                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1589                         };
1590
1591                         rmiim1_pins: rmiim1-pins {
1592                                 rockchip,pins =
1593                                         /* mac_mdio */
1594                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1595                                         /* mac_txen */
1596                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1597                                         /* mac_clk */
1598                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1599                                         /* mac_rxer */
1600                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1601                                         /* mac_rxdv */
1602                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1603                                         /* mac_mdc */
1604                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1605                                         /* mac_rxd1 */
1606                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1607                                         /* mac_rxd0 */
1608                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1609                                         /* mac_txd1 */
1610                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1611                                         /* mac_txd0 */
1612                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1613
1614                                         /* mac_mdio */
1615                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1616                                         /* mac_txen */
1617                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1618                                         /* mac_clk */
1619                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1620                                         /* mac_mdc */
1621                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1622                                         /* mac_txd1 */
1623                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1624                                         /* mac_txd0 */
1625                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1626                         };
1627                 };
1628
1629                 gmac2phy {
1630                         fephyled_speed100: fephyled-speed100 {
1631                                 rockchip,pins =
1632                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1633                         };
1634
1635                         fephyled_speed10: fephyled-speed10 {
1636                                 rockchip,pins =
1637                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1638                         };
1639
1640                         fephyled_duplex: fephyled-duplex {
1641                                 rockchip,pins =
1642                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1643                         };
1644
1645                         fephyled_rxm0: fephyled-rxm0 {
1646                                 rockchip,pins =
1647                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1648                         };
1649
1650                         fephyled_txm0: fephyled-txm0 {
1651                                 rockchip,pins =
1652                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1653                         };
1654
1655                         fephyled_linkm0: fephyled-linkm0 {
1656                                 rockchip,pins =
1657                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1658                         };
1659
1660                         fephyled_rxm1: fephyled-rxm1 {
1661                                 rockchip,pins =
1662                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1663                         };
1664
1665                         fephyled_txm1: fephyled-txm1 {
1666                                 rockchip,pins =
1667                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1668                         };
1669
1670                         fephyled_linkm1: fephyled-linkm1 {
1671                                 rockchip,pins =
1672                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1673                         };
1674                 };
1675
1676                 tsadc_pin {
1677                         tsadc_int: tsadc-int {
1678                                 rockchip,pins =
1679                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1680                         };
1681                         tsadc_gpio: tsadc-gpio {
1682                                 rockchip,pins =
1683                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1684                         };
1685                 };
1686
1687                 hdmi_pin {
1688                         hdmi_cec: hdmi-cec {
1689                                 rockchip,pins =
1690                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1691                         };
1692
1693                         hdmi_hpd: hdmi-hpd {
1694                                 rockchip,pins =
1695                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1696                         };
1697                 };
1698
1699                 cif-0 {
1700                         dvp_d2d9_m0:dvp-d2d9-m0 {
1701                                 rockchip,pins =
1702                                         /* cif_d0 */
1703                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1704                                         /* cif_d1 */
1705                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1706                                         /* cif_d2 */
1707                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1708                                         /* cif_d3 */
1709                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1710                                         /* cif_d4 */
1711                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1712                                         /* cif_d5m0 */
1713                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1714                                         /* cif_d6m0 */
1715                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1716                                         /* cif_d7m0 */
1717                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1718                                         /* cif_href */
1719                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1720                                         /* cif_vsync */
1721                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1722                                         /* cif_clkoutm0 */
1723                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1724                                         /* cif_clkin */
1725                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1726                         };
1727                 };
1728
1729                 cif-1 {
1730                         dvp_d2d9_m1:dvp-d2d9-m1 {
1731                                 rockchip,pins =
1732                                         /* cif_d0 */
1733                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1734                                         /* cif_d1 */
1735                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1736                                         /* cif_d2 */
1737                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1738                                         /* cif_d3 */
1739                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1740                                         /* cif_d4 */
1741                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1742                                         /* cif_d5m1 */
1743                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1744                                         /* cif_d6m1 */
1745                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1746                                         /* cif_d7m1 */
1747                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1748                                         /* cif_href */
1749                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1750                                         /* cif_vsync */
1751                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1752                                         /* cif_clkoutm1 */
1753                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1754                                         /* cif_clkin */
1755                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1756                         };
1757                 };
1758         };
1759 };