arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/power/rk3328-power.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3328";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67         };
  68
  69         cpus {
  70                 #address-cells = <2>;
  71                 #size-cells = <0>;
  72
  73                 cpu0: cpu@0 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53", "arm,armv8";
  76                         reg = <0x0 0x0>;
  77                         enable-method = "psci";
  78                         clocks = <&cru ARMCLK>;
  79                         #cooling-cells = <2>; /* min followed by max */
  80                         dynamic-power-coefficient = <120>;
  81                         operating-points-v2 = <&cpu0_opp_table>;
  82                 };
  83                 cpu1: cpu@1 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53", "arm,armv8";
  86                         reg = <0x0 0x1>;
  87                         enable-method = "psci";
  88                         operating-points-v2 = <&cpu0_opp_table>;
  89                 };
  90                 cpu2: cpu@2 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a53", "arm,armv8";
  93                         reg = <0x0 0x2>;
  94                         enable-method = "psci";
  95                         operating-points-v2 = <&cpu0_opp_table>;
  96                 };
  97                 cpu3: cpu@3 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a53", "arm,armv8";
 100                         reg = <0x0 0x3>;
 101                         enable-method = "psci";
 102                         operating-points-v2 = <&cpu0_opp_table>;
 103                 };
 104         };
 105
 106         cpu0_opp_table: opp_table0 {
 107                 compatible = "operating-points-v2";
 108                 opp-shared;
 109
 110                 opp@408000000 {
 111                         opp-hz = /bits/ 64 <408000000>;
 112                         opp-microvolt = <950000>;
 113                         clock-latency-ns = <40000>;
 114                         opp-suspend;
 115                 };
 116                 opp@600000000 {
 117                         opp-hz = /bits/ 64 <600000000>;
 118                         opp-microvolt = <950000>;
 119                         clock-latency-ns = <40000>;
 120                 };
 121                 opp@816000000 {
 122                         opp-hz = /bits/ 64 <816000000>;
 123                         opp-microvolt = <1000000>;
 124                         clock-latency-ns = <40000>;
 125                 };
 126                 opp@1008000000 {
 127                         opp-hz = /bits/ 64 <1008000000>;
 128                         opp-microvolt = <1100000>;
 129                         clock-latency-ns = <40000>;
 130                 };
 131                 opp@1200000000 {
 132                         opp-hz = /bits/ 64 <1200000000>;
 133                         opp-microvolt = <1225000>;
 134                         clock-latency-ns = <40000>;
 135                 };
 136                 opp@1296000000 {
 137                         opp-hz = /bits/ 64 <1296000000>;
 138                         opp-microvolt = <1300000>;
 139                         clock-latency-ns = <40000>;
 140                 };
 141         };
 142
 143         arm-pmu {
 144                 compatible = "arm,cortex-a53-pmu";
 145                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 149                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 150         };
 151
 152         psci {
 153                 compatible = "arm,psci-1.0";
 154                 method = "smc";
 155         };
 156
 157         timer {
 158                 compatible = "arm,armv8-timer";
 159                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 160                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 161                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 162                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 163         };
 164
 165         xin24m: xin24m {
 166                 compatible = "fixed-clock";
 167                 #clock-cells = <0>;
 168                 clock-frequency = <24000000>;
 169                 clock-output-names = "xin24m";
 170         };
 171
 172         i2s0: i2s@ff000000 {
 173                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 174                 reg = <0x0 0xff000000 0x0 0x1000>;
 175                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 177                 clock-names = "i2s_clk", "i2s_hclk";
 178                 dmas = <&dmac 11>, <&dmac 12>;
 179                 #dma-cells = <2>;
 180                 dma-names = "tx", "rx";
 181                 status = "disabled";
 182         };
 183
 184         i2s1: i2s@ff010000 {
 185                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 186                 reg = <0x0 0xff010000 0x0 0x1000>;
 187                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 189                 clock-names = "i2s_clk", "i2s_hclk";
 190                 dmas = <&dmac 14>, <&dmac 15>;
 191                 #dma-cells = <2>;
 192                 dma-names = "tx", "rx";
 193                 status = "disabled";
 194         };
 195
 196         i2s2: i2s@ff020000 {
 197                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 198                 reg = <0x0 0xff020000 0x0 0x1000>;
 199                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 201                 clock-names = "i2s_clk", "i2s_hclk";
 202                 dmas = <&dmac 0>, <&dmac 1>;
 203                 #dma-cells = <2>;
 204                 dma-names = "tx", "rx";
 205                 pinctrl-names = "default", "sleep";
 206                 pinctrl-0 = <&i2s2m0_mclk
 207                              &i2s2m0_sclk
 208                              &i2s2m0_lrcktx
 209                              &i2s2m0_lrckrx
 210                              &i2s2m0_sdo
 211                              &i2s2m0_sdi>;
 212                 pinctrl-1 = <&i2s2m0_sleep>;
 213                 status = "disabled";
 214         };
 215
 216         spdif: spdif@ff030000 {
 217                 compatible = "rockchip,rk3328-spdif";
 218                 reg = <0x0 0xff030000 0x0 0x1000>;
 219                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 221                 clock-names = "mclk", "hclk";
 222                 dmas = <&dmac 10>;
 223                 #dma-cells = <1>;
 224                 dma-names = "tx";
 225                 pinctrl-names = "default";
 226                 pinctrl-0 = <&spdifm2_tx>;
 227                 status = "disabled";
 228         };
 229
 230         grf: syscon@ff100000 {
 231                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 232                 reg = <0x0 0xff100000 0x0 0x1000>;
 233                 #address-cells = <1>;
 234                 #size-cells = <1>;
 235
 236                 io_domains: io-domains {
 237                         compatible = "rockchip,rk3328-io-voltage-domain";
 238                         status = "disabled";
 239                 };
 240
 241                 power: power-controller {
 242                         compatible = "rockchip,rk3328-power-controller";
 243                         #power-domain-cells = <1>;
 244                         #address-cells = <1>;
 245                         #size-cells = <0>;
 246                         status = "disabled";
 247
 248                         pd_hevc@RK3328_PD_HEVC {
 249                                 reg = <RK3328_PD_HEVC>;
 250                         };
 251                         pd_video@RK3328_PD_VIDEO {
 252                                 reg = <RK3328_PD_VIDEO>;
 253                         };
 254                         pd_vpu@RK3328_PD_VPU {
 255                                 reg = <RK3328_PD_VPU>;
 256                         };
 257                 };
 258
 259                 reboot-mode {
 260                         compatible = "syscon-reboot-mode";
 261                         offset = <0x5c8>;
 262                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 263                         mode-charge = <BOOT_CHARGING>;
 264                         mode-fastboot = <BOOT_FASTBOOT>;
 265                         mode-loader = <BOOT_BL_DOWNLOAD>;
 266                         mode-normal = <BOOT_NORMAL>;
 267                         mode-recovery = <BOOT_RECOVERY>;
 268                         mode-ums = <BOOT_UMS>;
 269                 };
 270         };
 271
 272         thermal-zones {
 273                 soc_thermal: soc-thermal {
 274                         polling-delay-passive = <20>; /* milliseconds */
 275                         polling-delay = <1000>; /* milliseconds */
 276                         sustainable-power = <1000>; /* milliwatts */
 277
 278                         thermal-sensors = <&tsadc 0>;
 279
 280                         trips {
 281                                 threshold: trip-point@0 {
 282                                         temperature = <70000>; /* millicelsius */
 283                                         hysteresis = <2000>; /* millicelsius */
 284                                         type = "passive";
 285                                 };
 286                                 target: trip-point@1 {
 287                                         temperature = <85000>; /* millicelsius */
 288                                         hysteresis = <2000>; /* millicelsius */
 289                                         type = "passive";
 290                                 };
 291                                 soc_crit: soc-crit {
 292                                         temperature = <95000>; /* millicelsius */
 293                                         hysteresis = <2000>; /* millicelsius */
 294                                         type = "critical";
 295                                 };
 296                         };
 297
 298                         cooling-maps {
 299                                 map0 {
 300                                         trip = <&target>;
 301                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 302                                         contribution = <4096>;
 303                                 };
 304                         };
 305                 };
 306
 307         };
 308
 309         tsadc: tsadc@ff250000 {
 310                 compatible = "rockchip,rk3328-tsadc";
 311                 reg = <0x0 0xff250000 0x0 0x100>;
 312                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
 313                 rockchip,grf = <&grf>;
 314                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 315                 clock-names = "tsadc", "apb_pclk";
 316                 assigned-clocks = <&cru SCLK_TSADC>;
 317                 assigned-clock-rates = <50000>;
 318                 resets = <&cru SRST_TSADC>;
 319                 reset-names = "tsadc-apb";
 320                 pinctrl-names = "init", "default", "sleep";
 321                 pinctrl-0 = <&otp_gpio>;
 322                 pinctrl-1 = <&otp_out>;
 323                 pinctrl-2 = <&otp_gpio>;
 324                 #thermal-sensor-cells = <1>;
 325                 rockchip,hw-tshut-temp = <100000>;
 326                 status = "disabled";
 327         };
 328
 329         uart0: serial@ff110000 {
 330                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 331                 reg = <0x0 0xff110000 0x0 0x100>;
 332                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 333                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 334                 clock-names = "baudclk", "apb_pclk";
 335                 reg-shift = <2>;
 336                 reg-io-width = <4>;
 337                 dmas = <&dmac 2>, <&dmac 3>;
 338                 #dma-cells = <2>;
 339                 pinctrl-names = "default";
 340                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 341                 status = "disabled";
 342         };
 343
 344         uart1: serial@ff120000 {
 345                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 346                 reg = <0x0 0xff120000 0x0 0x100>;
 347                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 348                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 349                 clock-names = "sclk_uart", "pclk_uart";
 350                 reg-shift = <2>;
 351                 reg-io-width = <4>;
 352                 dmas = <&dmac 4>, <&dmac 5>;
 353                 #dma-cells = <2>;
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 356                 status = "disabled";
 357         };
 358
 359         uart2: serial@ff130000 {
 360                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 361                 reg = <0x0 0xff130000 0x0 0x100>;
 362                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 364                 clock-names = "baudclk", "apb_pclk";
 365                 reg-shift = <2>;
 366                 reg-io-width = <4>;
 367                 dmas = <&dmac 6>, <&dmac 7>;
 368                 #dma-cells = <2>;
 369                 pinctrl-names = "default";
 370                 pinctrl-0 = <&uart2m1_xfer>;
 371                 status = "disabled";
 372         };
 373
 374         pmu: power-management@ff140000 {
 375                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 376                 reg = <0x0 0xff140000 0x0 0x1000>;
 377         };
 378
 379         i2c0: i2c@ff150000 {
 380                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 381                 reg = <0x0 0xff150000 0x0 0x1000>;
 382                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 383                 #address-cells = <1>;
 384                 #size-cells = <0>;
 385                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 386                 clock-names = "i2c", "pclk";
 387                 pinctrl-names = "default";
 388                 pinctrl-0 = <&i2c0_xfer>;
 389                 status = "disabled";
 390         };
 391
 392         i2c1: i2c@ff160000 {
 393                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 394                 reg = <0x0 0xff160000 0x0 0x1000>;
 395                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 396                 #address-cells = <1>;
 397                 #size-cells = <0>;
 398                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 399                 clock-names = "i2c", "pclk";
 400                 pinctrl-names = "default";
 401                 pinctrl-0 = <&i2c1_xfer>;
 402                 status = "disabled";
 403         };
 404
 405         i2c2: i2c@ff170000 {
 406                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 407                 reg = <0x0 0xff170000 0x0 0x1000>;
 408                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 409                 #address-cells = <1>;
 410                 #size-cells = <0>;
 411                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 412                 clock-names = "i2c", "pclk";
 413                 pinctrl-names = "default";
 414                 pinctrl-0 = <&i2c2_xfer>;
 415                 status = "disabled";
 416         };
 417
 418         i2c3: i2c@ff180000 {
 419                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 420                 reg = <0x0 0xff180000 0x0 0x1000>;
 421                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 422                 #address-cells = <1>;
 423                 #size-cells = <0>;
 424                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 425                 clock-names = "i2c", "pclk";
 426                 pinctrl-names = "default";
 427                 pinctrl-0 = <&i2c3_xfer>;
 428                 status = "disabled";
 429         };
 430
 431         spi0: spi@ff190000 {
 432                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 433                 reg = <0x0 0xff190000 0x0 0x1000>;
 434                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 435                 #address-cells = <1>;
 436                 #size-cells = <0>;
 437                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 438                 clock-names = "spiclk", "apb_pclk";
 439                 dmas = <&dmac 8>, <&dmac 9>;
 440                 #dma-cells = <2>;
 441                 dma-names = "tx", "rx";
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 444                 status = "disabled";
 445         };
 446
 447         wdt: watchdog@ff1a0000 {
 448                 compatible = "snps,dw-wdt";
 449                 reg = <0x0 0xff1a0000 0x0 0x100>;
 450                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 451                 status = "disabled";
 452         };
 453
 454         pwm0: pwm@ff1b0000 {
 455                 compatible = "rockchip,rk3328-pwm";
 456                 reg = <0x0 0xff1b0000 0x0 0x10>;
 457                 #pwm-cells = <3>;
 458                 pinctrl-names = "default";
 459                 pinctrl-0 = <&pwm0_pin>;
 460                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 461                 clock-names = "pwm", "pclk";
 462                 status = "disabled";
 463         };
 464
 465         pwm1: pwm@ff1b0010 {
 466                 compatible = "rockchip,rk3328-pwm";
 467                 reg = <0x0 0xff1b0010 0x0 0x10>;
 468                 #pwm-cells = <3>;
 469                 pinctrl-names = "default";
 470                 pinctrl-0 = <&pwm1_pin>;
 471                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 472                 clock-names = "pwm", "pclk";
 473                 status = "disabled";
 474         };
 475
 476         pwm2: pwm@ff1b0020 {
 477                 compatible = "rockchip,rk3328-pwm";
 478                 reg = <0x0 0xff1b0020 0x0 0x10>;
 479                 #pwm-cells = <3>;
 480                 pinctrl-names = "default";
 481                 pinctrl-0 = <&pwm2_pin>;
 482                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 483                 clock-names = "pwm", "pclk";
 484                 status = "disabled";
 485         };
 486
 487         pwm3: pwm@ff1b0030 {
 488                 compatible = "rockchip,rk3328-pwm";
 489                 reg = <0x0 0xff1b0030 0x0 0x10>;
 490                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 491                 #pwm-cells = <3>;
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&pwmir_pin>;
 494                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 495                 clock-names = "pwm", "pclk";
 496                 status = "disabled";
 497         };
 498
 499         amba {
 500                 compatible = "simple-bus";
 501                 #address-cells = <2>;
 502                 #size-cells = <2>;
 503                 ranges;
 504
 505                 dmac: dmac@ff1f0000 {
 506                         compatible = "arm,pl330", "arm,primecell";
 507                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 508                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 509                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 510                         clocks = <&cru ACLK_DMAC>;
 511                         clock-names = "apb_pclk";
 512                         #dma-cells = <1>;
 513                 };
 514         };
 515
 516         saradc: saradc@ff280000 {
 517                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 518                 reg = <0x0 0xff280000 0x0 0x100>;
 519                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 520                 #io-channel-cells = <1>;
 521                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 522                 clock-names = "saradc", "apb_pclk";
 523                 resets = <&cru SRST_SARADC_P>;
 524                 reset-names = "saradc-apb";
 525                 status = "disabled";
 526         };
 527
 528         cru: clock-controller@ff440000 {
 529                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 530                 reg = <0x0 0xff440000 0x0 0x1000>;
 531                 rockchip,grf = <&grf>;
 532                 #clock-cells = <1>;
 533                 #reset-cells = <1>;
 534                 assigned-clocks =
 535                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 536                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 537                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 538                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 539                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 540                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 541                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 542                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 543                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 544                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 545                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 546                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 547                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 548                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 549                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 550                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 551                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 552                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 553                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 554                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 555                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 556                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 557                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 558                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 559                 assigned-clock-parents =
 560                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 561                         <&cru PLL_GPLL>, <&xin24m>,
 562                         <&xin24m>, <&xin24m>;
 563                 assigned-clock-rates =
 564                         <0>, <61440000>,
 565                         <0>, <24000000>,
 566                         <24000000>, <24000000>,
 567                         <15000000>, <15000000>,
 568                         <100000000>, <100000000>,
 569                         <100000000>, <100000000>,
 570                         <50000000>, <100000000>,
 571                         <100000000>, <100000000>,
 572                         <50000000>, <50000000>,
 573                         <50000000>, <50000000>,
 574                         <24000000>, <600000000>,
 575                         <491520000>, <1200000000>,
 576                         <150000000>, <75000000>,
 577                         <75000000>, <150000000>,
 578                         <75000000>, <75000000>,
 579                         <300000000>, <100000000>,
 580                         <300000000>, <200000000>,
 581                         <400000000>, <500000000>,
 582                         <200000000>, <300000000>,
 583                         <300000000>, <250000000>,
 584                         <200000000>, <100000000>,
 585                         <24000000>, <100000000>,
 586                         <150000000>, <50000000>,
 587                         <32768>, <32768>;
 588         };
 589
 590         usb2phy_grf: syscon@ff450000 {
 591                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 592                              "simple-mfd";
 593                 reg = <0x0 0xff450000 0x0 0x10000>;
 594                 #address-cells = <1>;
 595                 #size-cells = <1>;
 596
 597                 u2phy: usb2-phy@100 {
 598                         compatible = "rockchip,rk3328-usb2phy";
 599                         reg = <0x100 0x10>;
 600                         clocks = <&xin24m>;
 601                         clock-names = "phyclk";
 602                         #clock-cells = <0>;
 603                         assigned-clocks = <&cru USB480M>;
 604                         assigned-clock-parents = <&u2phy>;
 605                         clock-output-names = "usb480m_phy";
 606                         status = "disabled";
 607
 608                         u2phy_host: host-port {
 609                                 #phy-cells = <0>;
 610                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 611                                 interrupt-names = "linestate";
 612                                 status = "disabled";
 613                         };
 614
 615                         u2phy_otg: otg-port {
 616                                 #phy-cells = <0>;
 617                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 618                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 619                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 620                                 interrupt-names = "otg-bvalid", "otg-id",
 621                                                   "linestate";
 622                                 status = "disabled";
 623                         };
 624                 };
 625         };
 626
 627         usb3phy_grf: syscon@ff460000 {
 628                 compatible = "rockchip,usb3phy-grf", "syscon";
 629                 reg = <0x0 0xff460000 0x0 0x1000>;
 630         };
 631
 632         u3phy: usb3-phy@ff470000 {
 633                 compatible = "rockchip,rk3328-u3phy";
 634                 reg = <0x0 0xff470000 0x0 0x0>;
 635                 rockchip,u3phygrf = <&usb3phy_grf>;
 636                 rockchip,grf = <&grf>;
 637                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 638                 interrupt-names = "linestate";
 639                 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
 640                 clock-names = "u3phy-otg", "u3phy-pipe";
 641                 resets = <&cru SRST_USB3PHY_U2>,
 642                          <&cru SRST_USB3PHY_U3>,
 643                          <&cru SRST_USB3PHY_PIPE>,
 644                          <&cru SRST_USB3OTG_UTMI>,
 645                          <&cru SRST_USB3PHY_OTG_P>,
 646                          <&cru SRST_USB3PHY_PIPE_P>;
 647                 reset-names = "u3phy-u2-por", "u3phy-u3-por",
 648                               "u3phy-pipe-mac", "u3phy-utmi-mac",
 649                               "u3phy-utmi-apb", "u3phy-pipe-apb";
 650                 #address-cells = <2>;
 651                 #size-cells = <2>;
 652                 ranges;
 653                 status = "disabled";
 654
 655                 u3phy_utmi: utmi@ff470000 {
 656                         reg = <0x0 0xff470000 0x0 0x8000>;
 657                         #phy-cells = <0>;
 658                         status = "disabled";
 659                 };
 660
 661                 u3phy_pipe: pipe@ff478000 {
 662                         reg = <0x0 0xff478000 0x0 0x8000>;
 663                         #phy-cells = <0>;
 664                         status = "disabled";
 665                 };
 666         };
 667
 668         sdmmc: rksdmmc@ff500000 {
 669                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 670                 reg = <0x0 0xff500000 0x0 0x4000>;
 671                 clock-freq-min-max = <400000 150000000>;
 672                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 673                 clock-names = "biu", "ciu";
 674                 fifo-depth = <0x100>;
 675                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 676                 status = "disabled";
 677         };
 678
 679         sdio: dwmmc@ff510000 {
 680                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 681                 reg = <0x0 0xff510000 0x0 0x4000>;
 682                 clock-freq-min-max = <400000 150000000>;
 683                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 684                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 685                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 686                 fifo-depth = <0x100>;
 687                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 688                 status = "disabled";
 689         };
 690
 691         emmc: rksdmmc@ff520000 {
 692                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 693                 reg = <0x0 0xff520000 0x0 0x4000>;
 694                 clock-freq-min-max = <400000 150000000>;
 695                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 696                 clock-names = "biu", "ciu";
 697                 fifo-depth = <0x100>;
 698                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 699                 status = "disabled";
 700         };
 701
 702         gmac2io: eth@ff540000 {
 703                 compatible = "rockchip,rk3328-gmac";
 704                 reg = <0x0 0xff540000 0x0 0x10000>;
 705                 rockchip,grf = <&grf>;
 706                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 707                 interrupt-names = "macirq";
 708                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 709                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 710                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 711                          <&cru PCLK_MAC2IO>;
 712                 clock-names = "stmmaceth", "mac_clk_rx",
 713                               "mac_clk_tx", "clk_mac_ref",
 714                               "clk_mac_refout", "aclk_mac",
 715                               "pclk_mac";
 716                 resets = <&cru SRST_GMAC2IO_A>;
 717                 reset-names = "stmmaceth";
 718                 status = "disabled";
 719         };
 720
 721         usb20_otg: usb@ff580000 {
 722                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 723                              "snps,dwc2";
 724                 reg = <0x0 0xff580000 0x0 0x40000>;
 725                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 726                 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
 727                 clock-names = "otg", "otg_pmu";
 728                 dr_mode = "otg";
 729                 g-np-tx-fifo-size = <16>;
 730                 g-rx-fifo-size = <275>;
 731                 g-tx-fifo-size = <256 128 128 64 64 32>;
 732                 g-use-dma;
 733                 phys = <&u2phy_otg>;
 734                 phy-names = "usb2-phy";
 735                 status = "disabled";
 736         };
 737
 738         usb_host0_ehci: usb@ff5c0000 {
 739                 compatible = "generic-ehci";
 740                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 741                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 742                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 743                          <&u2phy>;
 744                 clock-names = "usbhost", "arbiter", "utmi";
 745                 phys = <&u2phy_host>;
 746                 phy-names = "usb";
 747                 status = "disabled";
 748         };
 749
 750         usb_host0_ohci: usb@ff5d0000 {
 751                 compatible = "generic-ohci";
 752                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 753                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 754                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 755                          <&u2phy>;
 756                 clock-names = "usbhost", "arbiter", "utmi";
 757                 phys = <&u2phy_host>;
 758                 phy-names = "usb";
 759                 status = "disabled";
 760         };
 761
 762         sdmmc_ext: rksdmmc@ff5f0000 {
 763                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 764                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 765                 clock-freq-min-max = <400000 150000000>;
 766                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 767                 clock-names = "biu", "ciu";
 768                 fifo-depth = <0x100>;
 769                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 770                 status = "disabled";
 771         };
 772
 773         usbdrd3: usb@ff600000 {
 774                 compatible = "rockchip,rk3328-dwc3";
 775                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
 776                          <&cru ACLK_USB3OTG>;
 777                 clock-names = "ref_clk", "suspend_clk",
 778                               "bus_clk";
 779                 #address-cells = <2>;
 780                 #size-cells = <2>;
 781                 ranges;
 782                 status = "disabled";
 783
 784                 usbdrd_dwc3: dwc3@ff600000 {
 785                         compatible = "snps,dwc3";
 786                         reg = <0x0 0xff600000 0x0 0x100000>;
 787                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 788                         dr_mode = "host";
 789                         phys = <&u3phy_utmi>, <&u3phy_pipe>;
 790                         phy-names = "usb2-phy", "usb3-phy";
 791                         phy_type = "utmi_wide";
 792                         snps,dis_enblslpm_quirk;
 793                         snps,dis-u2-freeclk-exists-quirk;
 794                         snps,dis_u2_susphy_quirk;
 795                         snps,dis-u3-autosuspend-quirk;
 796                         snps,dis_u3_susphy_quirk;
 797                         snps,dis-del-phy-power-chg-quirk;
 798                         status = "disabled";
 799                 };
 800         };
 801
 802         gic: interrupt-controller@ff811000 {
 803                 compatible = "arm,gic-400";
 804                 #interrupt-cells = <3>;
 805                 #address-cells = <0>;
 806                 interrupt-controller;
 807                 reg = <0x0 0xff811000 0 0x1000>,
 808                       <0x0 0xff812000 0 0x2000>,
 809                       <0x0 0xff814000 0 0x2000>,
 810                       <0x0 0xff816000 0 0x2000>;
 811                 interrupts = <GIC_PPI 9
 812                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 813         };
 814
 815         pinctrl: pinctrl {
 816                 compatible = "rockchip,rk3328-pinctrl";
 817                 rockchip,grf = <&grf>;
 818                 #address-cells = <2>;
 819                 #size-cells = <2>;
 820                 ranges;
 821
 822                 gpio0: gpio0@ff210000 {
 823                         compatible = "rockchip,gpio-bank";
 824                         reg = <0x0 0xff210000 0x0 0x100>;
 825                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 826                         clocks = <&cru PCLK_GPIO0>;
 827
 828                         gpio-controller;
 829                         #gpio-cells = <2>;
 830
 831                         interrupt-controller;
 832                         #interrupt-cells = <2>;
 833                 };
 834
 835                 gpio1: gpio1@ff220000 {
 836                         compatible = "rockchip,gpio-bank";
 837                         reg = <0x0 0xff220000 0x0 0x100>;
 838                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 839                         clocks = <&cru PCLK_GPIO1>;
 840
 841                         gpio-controller;
 842                         #gpio-cells = <2>;
 843
 844                         interrupt-controller;
 845                         #interrupt-cells = <2>;
 846                 };
 847
 848                 gpio2: gpio2@ff230000 {
 849                         compatible = "rockchip,gpio-bank";
 850                         reg = <0x0 0xff230000 0x0 0x100>;
 851                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 852                         clocks = <&cru PCLK_GPIO2>;
 853
 854                         gpio-controller;
 855                         #gpio-cells = <2>;
 856
 857                         interrupt-controller;
 858                         #interrupt-cells = <2>;
 859                 };
 860
 861                 gpio3: gpio3@ff240000 {
 862                         compatible = "rockchip,gpio-bank";
 863                         reg = <0x0 0xff240000 0x0 0x100>;
 864                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 865                         clocks = <&cru PCLK_GPIO3>;
 866
 867                         gpio-controller;
 868                         #gpio-cells = <2>;
 869
 870                         interrupt-controller;
 871                         #interrupt-cells = <2>;
 872                 };
 873
 874                 pcfg_pull_up: pcfg-pull-up {
 875                         bias-pull-up;
 876                 };
 877
 878                 pcfg_pull_down: pcfg-pull-down {
 879                         bias-pull-down;
 880                 };
 881
 882                 pcfg_pull_none: pcfg-pull-none {
 883                         bias-disable;
 884                 };
 885
 886                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 887                         bias-disable;
 888                         drive-strength = <2>;
 889                 };
 890
 891                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 892                         bias-pull-up;
 893                         drive-strength = <2>;
 894                 };
 895
 896                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 897                         bias-pull-up;
 898                         drive-strength = <4>;
 899                 };
 900
 901                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 902                         bias-disable;
 903                         drive-strength = <4>;
 904                 };
 905
 906                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 907                         bias-pull-down;
 908                         drive-strength = <4>;
 909                 };
 910
 911                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 912                         bias-disable;
 913                         drive-strength = <8>;
 914                 };
 915
 916                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 917                         bias-pull-up;
 918                         drive-strength = <8>;
 919                 };
 920
 921                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 922                         bias-disable;
 923                         drive-strength = <12>;
 924                 };
 925
 926                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 927                         bias-pull-up;
 928                         drive-strength = <12>;
 929                 };
 930
 931                 pcfg_output_high: pcfg-output-high {
 932                         output-high;
 933                 };
 934
 935                 pcfg_output_low: pcfg-output-low {
 936                         output-low;
 937                 };
 938
 939                 pcfg_input_high: pcfg-input-high {
 940                         bias-pull-up;
 941                         input-enable;
 942                 };
 943
 944                 pcfg_input: pcfg-input {
 945                         input-enable;
 946                 };
 947
 948                 i2c0 {
 949                         i2c0_xfer: i2c0-xfer {
 950                                 rockchip,pins =
 951                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 952                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 953                         };
 954                 };
 955
 956                 i2c1 {
 957                         i2c1_xfer: i2c1-xfer {
 958                                 rockchip,pins =
 959                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 960                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 961                         };
 962                 };
 963
 964                 i2c2 {
 965                         i2c2_xfer: i2c2-xfer {
 966                                 rockchip,pins =
 967                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 968                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 969                         };
 970                 };
 971
 972                 i2c3 {
 973                         i2c3_xfer: i2c3-xfer {
 974                                 rockchip,pins =
 975                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 976                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 977                         };
 978                         i2c3_gpio: i2c3-gpio {
 979                                 rockchip,pins =
 980                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 981                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 982                         };
 983                 };
 984
 985                 hdmi_i2c {
 986                         hdmii2c_xfer: hdmii2c-xfer {
 987                                 rockchip,pins =
 988                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 989                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 990                         };
 991                 };
 992
 993                 tsadc {
 994                         otp_gpio: otp-gpio {
 995                                 rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
 996                         };
 997
 998                         otp_out: otp-out {
 999                                 rockchip,pins = <2 13 RK_FUNC_1 &pcfg_pull_none>;
1000                         };
1001                 };
1002
1003                 uart0 {
1004                         uart0_xfer: uart0-xfer {
1005                                 rockchip,pins =
1006                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
1007                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1008                         };
1009
1010                         uart0_cts: uart0-cts {
1011                                 rockchip,pins =
1012                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1013                         };
1014
1015                         uart0_rts: uart0-rts {
1016                                 rockchip,pins =
1017                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
1018                         };
1019
1020                         uart0_rts_gpio: uart0-rts-gpio {
1021                                 rockchip,pins =
1022                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
1023                         };
1024                 };
1025
1026                 uart1 {
1027                         uart1_xfer: uart1-xfer {
1028                                 rockchip,pins =
1029                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
1030                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
1031                         };
1032
1033                         uart1_cts: uart1-cts {
1034                                 rockchip,pins =
1035                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
1036                         };
1037
1038                         uart1_rts: uart1-rts {
1039                                 rockchip,pins =
1040                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
1041                         };
1042
1043                         uart1_rts_gpio: uart1-rts-gpio {
1044                                 rockchip,pins =
1045                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
1046                         };
1047                 };
1048
1049                 uart2-0 {
1050                         uart2m0_xfer: uart2m0-xfer {
1051                                 rockchip,pins =
1052                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
1053                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
1054                         };
1055                 };
1056
1057                 uart2-1 {
1058                         uart2m1_xfer: uart2m1-xfer {
1059                                 rockchip,pins =
1060                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
1061                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
1062                         };
1063                 };
1064
1065                 spi0-0 {
1066                         spi0m0_clk: spi0m0-clk {
1067                                 rockchip,pins =
1068                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
1069                         };
1070
1071                         spi0m0_cs0: spi0m0-cs0 {
1072                                 rockchip,pins =
1073                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1074                         };
1075
1076                         spi0m0_tx: spi0m0-tx {
1077                                 rockchip,pins =
1078                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1079                         };
1080
1081                         spi0m0_rx: spi0m0-rx {
1082                                 rockchip,pins =
1083                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1084                         };
1085
1086                         spi0m0_cs1: spi0m0-cs1 {
1087                                 rockchip,pins =
1088                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1089                         };
1090                 };
1091
1092                 spi0-1 {
1093                         spi0m1_clk: spi0m1-clk {
1094                                 rockchip,pins =
1095                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
1096                         };
1097
1098                         spi0m1_cs0: spi0m1-cs0 {
1099                                 rockchip,pins =
1100                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
1101                         };
1102
1103                         spi0m1_tx: spi0m1-tx {
1104                                 rockchip,pins =
1105                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
1106                         };
1107
1108                         spi0m1_rx: spi0m1-rx {
1109                                 rockchip,pins =
1110                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
1111                         };
1112
1113                         spi0m1_cs1: spi0m1-cs1 {
1114                                 rockchip,pins =
1115                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
1116                         };
1117                 };
1118
1119                 spi0-2 {
1120                         spi0m2_clk: spi0m2-clk {
1121                                 rockchip,pins =
1122                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
1123                         };
1124
1125                         spi0m2_cs0: spi0m2-cs0 {
1126                                 rockchip,pins =
1127                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
1128                         };
1129
1130                         spi0m2_tx: spi0m2-tx {
1131                                 rockchip,pins =
1132                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
1133                         };
1134
1135                         spi0m2_rx: spi0m2-rx {
1136                                 rockchip,pins =
1137                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
1138                         };
1139                 };
1140
1141                 i2s1 {
1142                         i2s1_mclk: i2s1-mclk {
1143                                 rockchip,pins =
1144                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
1145                         };
1146
1147                         i2s1_sclk: i2s1-sclk {
1148                                 rockchip,pins =
1149                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1150                         };
1151
1152                         i2s1_lrckrx: i2s1-lrckrx {
1153                                 rockchip,pins =
1154                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
1155                         };
1156
1157                         i2s1_lrcktx: i2s1-lrcktx {
1158                                 rockchip,pins =
1159                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1160                         };
1161
1162                         i2s1_sdi: i2s1-sdi {
1163                                 rockchip,pins =
1164                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1165                         };
1166
1167                         i2s1_sdo: i2s1-sdo {
1168                                 rockchip,pins =
1169                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
1170                         };
1171
1172                         i2s1_sdio1: i2s1-sdio1 {
1173                                 rockchip,pins =
1174                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
1175                         };
1176
1177                         i2s1_sdio2: i2s1-sdio2 {
1178                                 rockchip,pins =
1179                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
1180                         };
1181
1182                         i2s1_sdio3: i2s1-sdio3 {
1183                                 rockchip,pins =
1184                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
1185                         };
1186
1187                         i2s1_sleep: i2s1-sleep {
1188                                 rockchip,pins =
1189                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
1190                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
1191                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
1192                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
1193                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
1194                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
1195                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
1196                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
1197                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
1198                         };
1199                 };
1200
1201                 i2s2-0 {
1202                         i2s2m0_mclk: i2s2m0-mclk {
1203                                 rockchip,pins =
1204                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1205                         };
1206
1207                         i2s2m0_sclk: i2s2m0-sclk {
1208                                 rockchip,pins =
1209                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
1210                         };
1211
1212                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1213                                 rockchip,pins =
1214                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
1215                         };
1216
1217                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1218                                 rockchip,pins =
1219                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
1220                         };
1221
1222                         i2s2m0_sdi: i2s2m0-sdi {
1223                                 rockchip,pins =
1224                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
1225                         };
1226
1227                         i2s2m0_sdo: i2s2m0-sdo {
1228                                 rockchip,pins =
1229                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
1230                         };
1231
1232                         i2s2m0_sleep: i2s2m0-sleep {
1233                                 rockchip,pins =
1234                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1235                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
1236                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
1237                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
1238                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
1239                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
1240                         };
1241                 };
1242
1243                 i2s2-1 {
1244                         i2s2m1_mclk: i2s2m1-mclk {
1245                                 rockchip,pins =
1246                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1247                         };
1248
1249                         i2s2m1_sclk: i2s2m1-sclk {
1250                                 rockchip,pins =
1251                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
1252                         };
1253
1254                         i2s2m1_lrckrx: i2sm1-lrckrx {
1255                                 rockchip,pins =
1256                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
1257                         };
1258
1259                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1260                                 rockchip,pins =
1261                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
1262                         };
1263
1264                         i2s2m1_sdi: i2s2m1-sdi {
1265                                 rockchip,pins =
1266                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
1267                         };
1268
1269                         i2s2m1_sdo: i2s2m1-sdo {
1270                                 rockchip,pins =
1271                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
1272                         };
1273
1274                         i2s2m1_sleep: i2s2m1-sleep {
1275                                 rockchip,pins =
1276                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1277                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
1278                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
1279                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
1280                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
1281                         };
1282                 };
1283
1284                 spdif-0 {
1285                         spdifm0_tx: spdifm0-tx {
1286                                 rockchip,pins =
1287                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
1288                         };
1289                 };
1290
1291                 spdif-1 {
1292                         spdifm1_tx: spdifm1-tx {
1293                                 rockchip,pins =
1294                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1295                         };
1296                 };
1297
1298                 spdif-2 {
1299                         spdifm2_tx: spdifm2-tx {
1300                                 rockchip,pins =
1301                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
1302                         };
1303                 };
1304
1305                 sdmmc0-0 {
1306                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1307                                 rockchip,pins =
1308                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1309                         };
1310
1311                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1312                                 rockchip,pins =
1313                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1314                         };
1315                 };
1316
1317                 sdmmc0-1 {
1318                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1319                                 rockchip,pins =
1320                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1321                         };
1322
1323                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1324                                 rockchip,pins =
1325                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1326                         };
1327                 };
1328
1329                 sdmmc0 {
1330                         sdmmc0_clk: sdmmc0-clk {
1331                                 rockchip,pins =
1332                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1333                         };
1334
1335                         sdmmc0_cmd: sdmmc0-cmd {
1336                                 rockchip,pins =
1337                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1338                         };
1339
1340                         sdmmc0_dectn: sdmmc0-dectn {
1341                                 rockchip,pins =
1342                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1343                         };
1344
1345                         sdmmc0_wrprt: sdmmc0-wrprt {
1346                                 rockchip,pins =
1347                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1348                         };
1349
1350                         sdmmc0_bus1: sdmmc0-bus1 {
1351                                 rockchip,pins =
1352                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1353                         };
1354
1355                         sdmmc0_bus4: sdmmc0-bus4 {
1356                                 rockchip,pins =
1357                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1358                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1359                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1360                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1361                         };
1362
1363                         sdmmc0_gpio: sdmmc0-gpio {
1364                                 rockchip,pins =
1365                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1366                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1367                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1368                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1369                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1370                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1371                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1372                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1373                         };
1374                 };
1375
1376                 sdmmc0ext {
1377                         sdmmc0ext_clk: sdmmc0ext-clk {
1378                                 rockchip,pins =
1379                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1380                         };
1381
1382                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1383                                 rockchip,pins =
1384                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1385                         };
1386
1387                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1388                                 rockchip,pins =
1389                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1390                         };
1391
1392                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1393                                 rockchip,pins =
1394                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1395                         };
1396
1397                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1398                                 rockchip,pins =
1399                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1400                         };
1401
1402                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1403                                 rockchip,pins =
1404                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1405                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1406                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1407                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1408                         };
1409
1410                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1411                                 rockchip,pins =
1412                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1413                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1414                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1415                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1416                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1417                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1418                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1419                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1420                         };
1421                 };
1422
1423                 sdmmc1 {
1424                         sdmmc1_clk: sdmmc1-clk {
1425                                 rockchip,pins =
1426                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1427                         };
1428
1429                         sdmmc1_cmd: sdmmc1-cmd {
1430                                 rockchip,pins =
1431                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1432                         };
1433
1434                         sdmmc1_pwren: sdmmc1-pwren {
1435                                 rockchip,pins =
1436                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1437                         };
1438
1439                         sdmmc1_wrprt: sdmmc1-wrprt {
1440                                 rockchip,pins =
1441                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1442                         };
1443
1444                         sdmmc1_dectn: sdmmc1-dectn {
1445                                 rockchip,pins =
1446                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1447                         };
1448
1449                         sdmmc1_bus1: sdmmc1-bus1 {
1450                                 rockchip,pins =
1451                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1452                         };
1453
1454                         sdmmc1_bus4: sdmmc1-bus4 {
1455                                 rockchip,pins =
1456                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1457                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1458                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1459                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1460                         };
1461
1462                         sdmmc1_gpio: sdmmc1-gpio {
1463                                 rockchip,pins =
1464                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1465                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1466                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1467                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1468                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1469                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1470                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1471                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1472                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1473                         };
1474                 };
1475
1476                 emmc {
1477                         emmc_clk: emmc-clk {
1478                                 rockchip,pins =
1479                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1480                         };
1481
1482                         emmc_cmd: emmc-cmd {
1483                                 rockchip,pins =
1484                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1485                         };
1486
1487                         emmc_pwren: emmc-pwren {
1488                                 rockchip,pins =
1489                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1490                         };
1491
1492                         emmc_rstnout: emmc-rstnout {
1493                                 rockchip,pins =
1494                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1495                         };
1496
1497                         emmc_bus1: emmc-bus1 {
1498                                 rockchip,pins =
1499                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1500                         };
1501
1502                         emmc_bus4: emmc-bus4 {
1503                                 rockchip,pins =
1504                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1505                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1506                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1507                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1508                         };
1509
1510                         emmc_bus8: emmc-bus8 {
1511                                 rockchip,pins =
1512                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1513                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1514                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1515                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1516                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1517                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1518                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1519                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1520                         };
1521                 };
1522
1523                 pwm0 {
1524                         pwm0_pin: pwm0-pin {
1525                                 rockchip,pins =
1526                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1527                         };
1528                 };
1529
1530                 pwm1 {
1531                         pwm1_pin: pwm1-pin {
1532                                 rockchip,pins =
1533                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1534                         };
1535                 };
1536
1537                 pwm2 {
1538                         pwm2_pin: pwm2-pin {
1539                                 rockchip,pins =
1540                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1541                         };
1542                 };
1543
1544                 pwmir {
1545                         pwmir_pin: pwmir-pin {
1546                                 rockchip,pins =
1547                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1548                         };
1549                 };
1550
1551                 gmac-0 {
1552                         rgmiim0_pins: rgmiim0-pins {
1553                                 rockchip,pins =
1554                                         /* mac_txclk */
1555                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1556                                         /* mac_rxclk */
1557                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1558                                         /* mac_mdio */
1559                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1560                                         /* mac_txen */
1561                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1562                                         /* mac_clk */
1563                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1564                                         /* mac_rxdv */
1565                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1566                                         /* mac_mdc */
1567                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1568                                         /* mac_rxd1 */
1569                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1570                                         /* mac_rxd0 */
1571                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1572                                         /* mac_txd1 */
1573                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1574                                         /* mac_txd0 */
1575                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1576                                         /* mac_rxd3 */
1577                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1578                                         /* mac_rxd2 */
1579                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1580                                         /* mac_txd3 */
1581                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1582                                         /* mac_txd2 */
1583                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1584                         };
1585
1586                         rmiim0_pins: rmiim0-pins {
1587                                 rockchip,pins =
1588                                         /* mac_mdio */
1589                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1590                                         /* mac_txen */
1591                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1592                                         /* mac_clk */
1593                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1594                                         /* mac_rxer */
1595                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1596                                         /* mac_rxdv */
1597                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1598                                         /* mac_mdc */
1599                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1600                                         /* mac_rxd1 */
1601                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1602                                         /* mac_rxd0 */
1603                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1604                                         /* mac_txd1 */
1605                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1606                                         /* mac_txd0 */
1607                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1608                         };
1609                 };
1610
1611                 gmac-1 {
1612                         rgmiim1_pins: rgmiim1-pins {
1613                                 rockchip,pins =
1614                                         /* mac_txclk */
1615                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1616                                         /* mac_rxclk */
1617                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1618                                         /* mac_mdio */
1619                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1620                                         /* mac_txen */
1621                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1622                                         /* mac_clk */
1623                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1624                                         /* mac_rxdv */
1625                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1626                                         /* mac_mdc */
1627                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1628                                         /* mac_rxd1 */
1629                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1630                                         /* mac_rxd0 */
1631                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1632                                         /* mac_txd1 */
1633                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1634                                         /* mac_txd0 */
1635                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1636                                         /* mac_rxd3 */
1637                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1638                                         /* mac_rxd2 */
1639                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1640                                         /* mac_txd3 */
1641                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1642                                         /* mac_txd2 */
1643                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1644
1645                                         /* mac_txclk */
1646                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1647                                         /* mac_txen */
1648                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1649                                         /* mac_clk */
1650                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1651                                         /* mac_txd1 */
1652                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1653                                         /* mac_txd0 */
1654                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1655                                         /* mac_txd3 */
1656                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1657                                         /* mac_txd2 */
1658                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1659                         };
1660
1661                         rmiim1_pins: rmiim1-pins {
1662                                 rockchip,pins =
1663                                         /* mac_mdio */
1664                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1665                                         /* mac_txen */
1666                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1667                                         /* mac_clk */
1668                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1669                                         /* mac_rxer */
1670                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1671                                         /* mac_rxdv */
1672                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1673                                         /* mac_mdc */
1674                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1675                                         /* mac_rxd1 */
1676                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1677                                         /* mac_rxd0 */
1678                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1679                                         /* mac_txd1 */
1680                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1681                                         /* mac_txd0 */
1682                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1683
1684                                         /* mac_mdio */
1685                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1686                                         /* mac_txen */
1687                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1688                                         /* mac_clk */
1689                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1690                                         /* mac_mdc */
1691                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1692                                         /* mac_txd1 */
1693                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1694                                         /* mac_txd0 */
1695                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1696                         };
1697                 };
1698
1699                 gmac2phy {
1700                         fephyled_speed100: fephyled-speed100 {
1701                                 rockchip,pins =
1702                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1703                         };
1704
1705                         fephyled_speed10: fephyled-speed10 {
1706                                 rockchip,pins =
1707                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1708                         };
1709
1710                         fephyled_duplex: fephyled-duplex {
1711                                 rockchip,pins =
1712                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1713                         };
1714
1715                         fephyled_rxm0: fephyled-rxm0 {
1716                                 rockchip,pins =
1717                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1718                         };
1719
1720                         fephyled_txm0: fephyled-txm0 {
1721                                 rockchip,pins =
1722                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1723                         };
1724
1725                         fephyled_linkm0: fephyled-linkm0 {
1726                                 rockchip,pins =
1727                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1728                         };
1729
1730                         fephyled_rxm1: fephyled-rxm1 {
1731                                 rockchip,pins =
1732                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1733                         };
1734
1735                         fephyled_txm1: fephyled-txm1 {
1736                                 rockchip,pins =
1737                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1738                         };
1739
1740                         fephyled_linkm1: fephyled-linkm1 {
1741                                 rockchip,pins =
1742                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1743                         };
1744                 };
1745
1746                 tsadc_pin {
1747                         tsadc_int: tsadc-int {
1748                                 rockchip,pins =
1749                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1750                         };
1751                         tsadc_gpio: tsadc-gpio {
1752                                 rockchip,pins =
1753                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1754                         };
1755                 };
1756
1757                 hdmi_pin {
1758                         hdmi_cec: hdmi-cec {
1759                                 rockchip,pins =
1760                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1761                         };
1762
1763                         hdmi_hpd: hdmi-hpd {
1764                                 rockchip,pins =
1765                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1766                         };
1767                 };
1768
1769                 cif-0 {
1770                         dvp_d2d9_m0:dvp-d2d9-m0 {
1771                                 rockchip,pins =
1772                                         /* cif_d0 */
1773                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1774                                         /* cif_d1 */
1775                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1776                                         /* cif_d2 */
1777                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1778                                         /* cif_d3 */
1779                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1780                                         /* cif_d4 */
1781                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1782                                         /* cif_d5m0 */
1783                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1784                                         /* cif_d6m0 */
1785                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1786                                         /* cif_d7m0 */
1787                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1788                                         /* cif_href */
1789                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1790                                         /* cif_vsync */
1791                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1792                                         /* cif_clkoutm0 */
1793                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1794                                         /* cif_clkin */
1795                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1796                         };
1797                 };
1798
1799                 cif-1 {
1800                         dvp_d2d9_m1:dvp-d2d9-m1 {
1801                                 rockchip,pins =
1802                                         /* cif_d0 */
1803                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1804                                         /* cif_d1 */
1805                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1806                                         /* cif_d2 */
1807                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1808                                         /* cif_d3 */
1809                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1810                                         /* cif_d4 */
1811                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1812                                         /* cif_d5m1 */
1813                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1814                                         /* cif_d6m1 */
1815                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1816                                         /* cif_d7m1 */
1817                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1818                                         /* cif_href */
1819                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1820                                         /* cif_vsync */
1821                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1822                                         /* cif_clkoutm1 */
1823                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1824                                         /* cif_clkin */
1825                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1826                         };
1827                 };
1828         };
1829 };