2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3366-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/power/rk3366-power.h>
50 #include <dt-bindings/soc/rockchip_boot-mode.h>
53 compatible = "rockchip,rk3366";
54 interrupt-parent = <&gic>;
73 #address-cells = <0x2>;
78 compatible = "arm,cortex-a53","arm,armv8";
80 enable-method = "psci";
81 clocks = <&cru ARMCLK>;
82 operating-points-v2 = <&cpu0_opp_table>;
87 compatible = "arm,cortex-a53","arm,armv8";
89 enable-method = "psci";
90 operating-points-v2 = <&cpu0_opp_table>;
95 compatible = "arm,cortex-a53","arm,armv8";
97 enable-method = "psci";
98 operating-points-v2 = <&cpu0_opp_table>;
103 compatible = "arm,cortex-a53","arm,armv8";
105 enable-method = "psci";
106 operating-points-v2 = <&cpu0_opp_table>;
110 cpu0_opp_table: opp_table0 {
111 compatible = "operating-points-v2";
115 opp-hz = /bits/ 64 <408000000>;
116 opp-microvolt = <1200000>;
117 clock-latency-ns = <40000>;
121 opp-hz = /bits/ 64 <600000000>;
122 opp-microvolt = <1200000>;
125 opp-hz = /bits/ 64 <816000000>;
126 opp-microvolt = <1200000>;
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1200000>;
133 opp-hz = /bits/ 64 <1200000000>;
134 opp-microvolt = <1200000>;
139 compatible = "arm,psci-1.0";
144 compatible = "arm,armv8-timer";
145 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
152 compatible = "fixed-clock";
154 clock-frequency = <24000000>;
155 clock-output-names = "xin24m";
158 gic: interrupt-controller@ffb71000 {
159 compatible = "arm,gic-400";
160 interrupt-controller;
161 #interrupt-cells = <3>;
162 #address-cells = <0>;
164 reg = <0x0 0xffb71000 0x0 0x1000>,
165 <0x0 0xffb72000 0x0 0x1000>,
166 <0x0 0xffb74000 0x0 0x2000>,
167 <0x0 0xffb76000 0x0 0x2000>;
168 interrupts = <GIC_PPI 9
169 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
172 nandc0: nandc@ff0c0000 {
173 compatible = "rockchip,rk-nandc";
174 reg = <0x0 0xff0c0000 0x0 0x4000>;
175 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
178 clock-names = "clk_nandc", "hclk_nandc";
182 saradc: saradc@ff100000 {
183 compatible = "rockchip,saradc";
184 reg = <0x0 0xff100000 0x0 0x100>;
185 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
186 #io-channel-cells = <1>;
187 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
188 clock-names = "saradc", "apb_pclk";
193 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
194 reg = <0x0 0xff110000 0x0 0x1000>;
195 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
196 clock-names = "spiclk", "apb_pclk";
197 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
200 #address-cells = <1>;
206 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
207 reg = <0x0 0xff120000 0x0 0x1000>;
208 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
209 clock-names = "spiclk", "apb_pclk";
210 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
213 #address-cells = <1>;
218 sdmmc: rksdmmc@ff400000 {
219 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
220 clock-freq-min-max = <400000 150000000>;
221 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
222 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
223 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
224 fifo-depth = <0x100>;
225 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
226 reg = <0x0 0xff400000 0x0 0x4000>;
230 sdio: rksdmmc@ff410000 {
231 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
232 clock-freq-min-max = <400000 150000000>;
233 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
234 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
235 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
236 fifo-depth = <0x100>;
237 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
238 reg = <0x0 0xff410000 0x0 0x4000>;
242 emmc: rksdmmc@ff420000 {
243 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
244 clock-freq-min-max = <400000 150000000>;
245 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
246 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
247 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
248 fifo-depth = <0x100>;
249 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
250 reg = <0x0 0xff420000 0x0 0x4000>;
255 compatible = "rockchip,rk3366-gmac";
256 reg = <0x0 0xff440000 0x0 0x10000>;
257 rockchip,grf = <&grf>;
258 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
259 interrupt-names = "macirq";
260 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
261 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
262 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
264 clock-names = "stmmaceth", "mac_clk_rx",
265 "mac_clk_tx", "clk_mac_ref",
266 "clk_mac_refout", "aclk_mac",
268 resets = <&cru SRST_MAC>;
269 reset-names = "stmmaceth";
274 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
275 reg = <0x0 0xff728000 0x0 0x1000>;
276 clocks = <&cru PCLK_I2C0>;
278 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&i2c0_xfer>;
281 #address-cells = <1>;
287 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
288 reg = <0x0 0xff140000 0x0 0x1000>;
289 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
290 #address-cells = <1>;
293 clocks = <&cru PCLK_I2C2>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&i2c2_xfer>;
300 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
301 reg = <0x0 0xff150000 0x0 0x1000>;
302 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
303 #address-cells = <1>;
306 clocks = <&cru PCLK_I2C3>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&i2c3_xfer>;
313 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
314 reg = <0x0 0xff160000 0x0 0x1000>;
315 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
316 #address-cells = <1>;
319 clocks = <&cru PCLK_I2C4>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&i2c4_xfer>;
326 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
327 reg = <0x0 0xff170000 0x0 0x1000>;
328 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
329 #address-cells = <1>;
332 clocks = <&cru PCLK_I2C5>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&i2c5_xfer>;
338 uart0: serial@ff180000 {
339 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
340 reg = <0x0 0xff180000 0x0 0x100>;
341 clock-frequency = <24000000>;
342 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
343 clock-names = "baudclk", "apb_pclk";
344 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
352 uart3: serial@ff1b0000 {
353 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
354 reg = <0x0 0xff1b0000 0x0 0x100>;
355 clock-frequency = <24000000>;
356 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
357 clock-names = "baudclk", "apb_pclk";
358 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
366 usb_host0_echi: usb@ff480000 {
367 compatible = "generic-ehci";
368 reg = <0x0 0xff480000 0x0 0x20000>;
369 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
371 clock-names = "sclk_otgphy0", "hclk_host0";
375 usb_host0_ohci: usb@ff4a0000 {
376 compatible = "generic-ohci";
377 reg = <0x0 0xff4a0000 0x0 0x20000>;
378 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
380 clock-names = "sclk_otgphy0", "hclk_host0";
384 usb_otg: usb@ff4c0000 {
385 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
387 reg = <0x0 0xff4c0000 0x0 0x40000>;
388 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&cru HCLK_OTG>;
392 g-np-tx-fifo-size = <16>;
393 g-rx-fifo-size = <275>;
394 g-tx-fifo-size = <256 128 128 64 64 32>;
400 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
401 reg = <0x0 0xff660000 0x0 0x1000>;
402 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
403 #address-cells = <1>;
406 clocks = <&cru PCLK_I2C1>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&i2c1_xfer>;
413 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
414 reg = <0x0 0xff680000 0x0 0x10>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&pwm0_pin>;
418 clocks = <&cru PCLK_RKPWM>;
424 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
425 reg = <0x0 0xff680010 0x0 0x10>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&pwm1_pin>;
429 clocks = <&cru PCLK_RKPWM>;
435 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
436 reg = <0x0 0xff680020 0x0 0x10>;
438 clocks = <&cru PCLK_RKPWM>;
444 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
445 reg = <0x0 0xff680030 0x0 0x10>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&pwm3_t2_pin>;
449 clocks = <&cru PCLK_RKPWM>;
454 uart2: serial@ff690000 {
455 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
456 reg = <0x0 0xff690000 0x0 0x100>;
457 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
459 clock-names = "baudclk", "apb_pclk";
462 pinctrl-names = "default";
463 pinctrl-0 = <&uart2_t1_xfer>;
467 pmu: power-management@ff730000 {
468 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
469 reg = <0x0 0xff730000 0x0 0x1000>;
471 power: power-controller {
473 compatible = "rockchip,rk3366-power-controller";
474 #power-domain-cells = <1>;
475 #address-cells = <1>;
479 * Note: Although SCLK_* are the working clocks
480 * of device without including on the NOC, needed for
483 * The clocks on the which NOC:
484 * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
485 * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
486 * ACLK_ISP is on ACLK_ISP_NIU.
487 * ACLK_HDCP is on ACLK_HDCP_NIU.
488 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
490 * Which clock are device clocks:
492 * *_IEP IEP:Image Enhancement Processor
493 * *_ISP ISP:Image Signal Processing
494 * *_VOP* VOP:Visual Output Processor
501 reg = <RK3366_PD_VIO>;
502 clocks = <&cru ACLK_IEP>,
506 <&cru ACLK_VOP_FULL>,
507 <&cru ACLK_VOP_LITE>,
509 <&cru DCLK_VOP_FULL>,
510 <&cru DCLK_VOP_LITE>,
514 <&cru HCLK_VOP_FULL>,
515 <&cru HCLK_VOP_LITE>,
516 <&cru HCLK_VIO_HDCPMMU>,
517 <&cru PCLK_HDMI_CTRL>,
519 <&cru PCLK_MIPI_DSI0>,
520 <&cru SCLK_VOP_FULL_PWM>,
524 <&cru SCLK_HDMI_CEC>,
525 <&cru SCLK_HDMI_HDCP>;
529 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
530 * (video endecoder & decoder) clocks that on the
531 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
534 reg = <RK3366_PD_VPU>;
535 clocks = <&cru ACLK_VIDEO>,
540 * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
541 * (video decoder) clocks that on the
542 * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
545 reg = <RK3366_PD_RKVDEC>;
546 clocks = <&cru ACLK_RKVDEC>,
551 reg = <RK3366_PD_VIDEO>;
552 clocks = <&cru ACLK_VIDEO>,
556 <&cru SCLK_HEVC_CABAC>,
557 <&cru SCLK_HEVC_CORE>;
561 * Note: ACLK_GPU is the GPU clock,
562 * and on the ACLK_GPU_NIU (NOC).
565 reg = <RK3366_PD_GPU>;
566 clocks = <&cru ACLK_GPU>;
571 pmugrf: syscon@ff738000 {
572 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
573 reg = <0x0 0xff738000 0x0 0x1000>;
576 compatible = "syscon-reboot-mode";
578 mode-normal = <BOOT_NORMAL>;
579 mode-recovery = <BOOT_RECOVERY>;
580 mode-fastboot = <BOOT_FASTBOOT>;
581 mode-loader = <BOOT_LOADER>;
586 compatible = "arm,amba-bus";
587 #address-cells = <2>;
591 dmac_peri: dma-controller@ff250000 {
592 compatible = "arm,pl330", "arm,primecell";
593 reg = <0x0 0xff250000 0x0 0x4000>;
594 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&cru ACLK_DMAC_PERI>;
598 clock-names = "apb_pclk";
601 dmac_bus: dma-controller@ff600000 {
602 compatible = "arm,pl330", "arm,primecell";
603 reg = <0x0 0xff600000 0x0 0x4000>;
604 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&cru ACLK_DMAC_BUS>;
608 clock-names = "apb_pclk";
612 cru: clock-controller@ff760000 {
613 compatible = "rockchip,rk3366-cru";
614 reg = <0x0 0xff760000 0x0 0x1000>;
615 rockchip,grf = <&grf>;
619 <&cru PLL_CPLL>, <&cru PLL_GPLL>,
620 <&cru PLL_NPLL>, <&cru PLL_MPLL>,
621 <&cru PLL_WPLL>, <&cru PLL_BPLL>,
622 <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
623 <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
624 assigned-clock-rates =
625 <750000000>, <576000000>,
626 <594000000>, <594000000>,
627 <480000000>, <520000000>,
628 <375000000>, <288000000>,
629 <100000000>, <100000000>;
632 grf: syscon@ff770000 {
633 compatible = "rockchip,rk3366-grf", "syscon";
634 reg = <0x0 0xff770000 0x0 0x1000>;
637 spdif: spdif@ff880000 {
638 compatible = "rockchip,rk3366-spdif";
639 reg = <0x0 0xff880000 0x0 0x1000>;
640 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
641 dmas = <&dmac_bus 3>;
643 clock-names = "hclk", "mclk";
644 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
645 pinctrl-names = "default";
646 pinctrl-0 = <&spdif_bus>;
650 i2s_2ch: i2s-2ch@ff890000 {
651 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
652 reg = <0x0 0xff890000 0x0 0x1000>;
653 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
654 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
655 dma-names = "tx", "rx";
656 clock-names = "i2s_hclk", "i2s_clk";
657 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
661 i2s_8ch: i2s-8ch@ff898000 {
662 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
663 reg = <0x0 0xff898000 0x0 0x1000>;
664 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
665 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
666 dma-names = "tx", "rx";
667 clock-names = "i2s_hclk", "i2s_clk";
668 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
669 pinctrl-names = "default";
670 pinctrl-0 = <&i2s_8ch_bus>;
675 compatible = "rockchip,rk-fb";
676 rockchip,disp-mode = <DUAL>;
681 compatible = "rockchip,screen";
685 vop_lite: vop@ff8f0000 {
686 compatible = "rockchip,rk3366-lcdc-lite";
687 rockchip,grf = <&grf>;
688 rockchip,pwr18 = <0>;
689 rockchip,iommu-enabled = <1>;
690 reg = <0x0 0xff8f0000 0x0 0x1000>;
691 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
693 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
694 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
695 reset-names = "axi", "ahb", "dclk";
701 compatible = "rockchip,vopl_mmu";
702 reg = <0x0 0xff8f0f00 0x0 0x100>;
703 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
704 interrupt-names = "vopl_mmu";
709 compatible = "rockchip,rga2";
711 reg = <0x0 0xff920000 0x0 0x1000>;
712 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
714 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
718 vop_big: vop@ff930000 {
719 compatible = "rockchip,rk3366-lcdc-big";
720 rockchip,grf = <&grf>;
721 rockchip,prop = <PRMRY>;
722 rockchip,pwr18 = <0>;
723 rockchip,iommu-enabled = <1>;
724 reg = <0x0 0xff930000 0x0 0x23f0>;
725 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
727 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
728 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
729 reset-names = "axi", "ahb", "dclk";
735 compatible = "rockchip,vopb_mmu";
736 reg = <0x0 0xff932400 0x0 0x100>;
737 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
738 interrupt-names = "vop_mmu";
742 dsihost0: mipi@ff960000 {
743 compatible = "rockchip,rk3368-dsi";
745 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
746 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
747 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
749 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
753 lvds: lvds@ff968000 {
754 compatible = "rockchip,rk3366-lvds";
755 rockchip,grf = <&grf>;
756 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
757 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
758 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
759 clock-names = "pclk_lvds", "pclk_lvds_ctl";
763 hdmi: hdmi@ff980000 {
764 compatible = "rockchip,rk3366-hdmi";
765 reg = <0x0 0xff980000 0x0 0x20000>;
766 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&cru PCLK_HDMI_CTRL>,
769 <&cru SCLK_HDMI_HDCP>,
770 <&cru SCLK_HDMI_CEC>,
772 clock-names = "pclk_hdmi",
776 resets = <&cru SRST_HDMI>;
777 reset-names = "hdmi";
778 pinctrl-names = "default", "gpio";
779 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
780 pinctrl-1 = <&i2c5_gpio>;
785 compatible = "rockchip,rk3366-pinctrl";
786 rockchip,grf = <&grf>;
787 rockchip,pmu = <&pmugrf>;
788 #address-cells = <0x2>;
792 gpio0: gpio0@ff750000 {
793 compatible = "rockchip,gpio-bank";
794 reg = <0x0 0xff750000 0x0 0x100>;
795 clocks = <&cru PCLK_GPIO0>;
796 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
801 interrupt-controller;
802 #interrupt-cells = <0x2>;
805 gpio1: gpio1@ff780000 {
806 compatible = "rockchip,gpio-bank";
807 reg = <0x0 0xff758000 0x0 0x100>;
808 clocks = <&cru PCLK_GPIO1>;
809 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
814 interrupt-controller;
815 #interrupt-cells = <0x2>;
818 gpio2: gpio2@ff790000 {
819 compatible = "rockchip,gpio-bank";
820 reg = <0x0 0xff790000 0x0 0x100>;
821 clocks = <&cru PCLK_GPIO2>;
822 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
827 interrupt-controller;
828 #interrupt-cells = <0x2>;
831 gpio3: gpio3@ff7a0000 {
832 compatible = "rockchip,gpio-bank";
833 reg = <0x0 0xff7a0000 0x0 0x100>;
834 clocks = <&cru PCLK_GPIO3>;
835 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
840 interrupt-controller;
841 #interrupt-cells = <0x2>;
844 gpio4: gpio4@ff7b0000 {
845 compatible = "rockchip,gpio-bank";
846 reg = <0x0 0xff7b0000 0x0 0x100>;
847 clocks = <&cru PCLK_GPIO4>;
848 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
853 interrupt-controller;
854 #interrupt-cells = <0x2>;
857 gpio5: gpio5@ff7c0000 {
858 compatible = "rockchip,gpio-bank";
859 reg = <0x0 0xff7c0000 0x0 0x100>;
860 clocks = <&cru PCLK_GPIO5>;
861 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
866 interrupt-controller;
867 #interrupt-cells = <0x2>;
870 pcfg_pull_up: pcfg-pull-up {
874 pcfg_pull_down: pcfg-pull-down {
878 pcfg_pull_none: pcfg-pull-none {
882 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
884 drive-strength = <12>;
890 <3 4 RK_FUNC_2 &pcfg_pull_none>;
895 <2 26 RK_FUNC_2 &pcfg_pull_up>;
900 <2 27 RK_FUNC_2 &pcfg_pull_up>;
903 emmc_bus1: emmc-bus1 {
905 <2 18 RK_FUNC_2 &pcfg_pull_up>;
908 emmc_bus4: emmc-bus4 {
910 <2 18 RK_FUNC_2 &pcfg_pull_up>,
911 <2 19 RK_FUNC_2 &pcfg_pull_up>,
912 <2 20 RK_FUNC_2 &pcfg_pull_up>,
913 <2 21 RK_FUNC_2 &pcfg_pull_up>;
916 emmc_bus8: emmc-bus8 {
918 <2 18 RK_FUNC_2 &pcfg_pull_up>,
919 <2 19 RK_FUNC_2 &pcfg_pull_up>,
920 <2 20 RK_FUNC_2 &pcfg_pull_up>,
921 <2 21 RK_FUNC_2 &pcfg_pull_up>,
922 <2 22 RK_FUNC_2 &pcfg_pull_up>,
923 <2 23 RK_FUNC_2 &pcfg_pull_up>,
924 <2 24 RK_FUNC_2 &pcfg_pull_up>,
925 <2 25 RK_FUNC_2 &pcfg_pull_up>;
931 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
934 sdmmc_bus1: sdmmc-bus1 {
935 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
938 sdmmc_bus4: sdmmc-bus4 {
939 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
940 <5 1 RK_FUNC_1 &pcfg_pull_up>,
941 <5 2 RK_FUNC_1 &pcfg_pull_up>,
942 <5 3 RK_FUNC_1 &pcfg_pull_up>;
945 sdmmc_clk: sdmmc-clk {
946 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
949 sdmmc_cmd: sdmmc-cmd {
950 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
955 sdio_bus1: sdio-bus1 {
956 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
959 sdio_bus4: sdio-bus4 {
960 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
961 <3 13 RK_FUNC_1 &pcfg_pull_up>,
962 <3 14 RK_FUNC_1 &pcfg_pull_up>,
963 <3 15 RK_FUNC_1 &pcfg_pull_up>;
967 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
971 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
975 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
979 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
983 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
987 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
992 hdmii2c_xfer: hdmii2c-xfer {
994 <5 13 RK_FUNC_2 &pcfg_pull_none>,
995 <5 14 RK_FUNC_2 &pcfg_pull_none>;
1000 hdmi_cec: hdmi-cec {
1002 <5 12 RK_FUNC_1 &pcfg_pull_none>;
1007 i2c0_xfer: i2c0-xfer {
1009 <0 3 RK_FUNC_1 &pcfg_pull_none>,
1010 <0 4 RK_FUNC_1 &pcfg_pull_none>;
1015 i2c1_xfer: i2c1-xfer {
1017 <4 25 RK_FUNC_1 &pcfg_pull_none>,
1018 <4 26 RK_FUNC_1 &pcfg_pull_none>;
1023 i2c2_xfer: i2c2-xfer {
1025 <5 15 RK_FUNC_2 &pcfg_pull_none>,
1026 <5 16 RK_FUNC_2 &pcfg_pull_none>;
1031 i2c3_xfer: i2c3-xfer {
1033 <2 16 RK_FUNC_2 &pcfg_pull_none>,
1034 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1039 i2c4_xfer: i2c4-xfer {
1041 <5 8 RK_FUNC_1 &pcfg_pull_none>,
1042 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1047 i2c5_xfer: i2c5-xfer {
1049 <5 13 RK_FUNC_1 &pcfg_pull_none>,
1050 <5 14 RK_FUNC_1 &pcfg_pull_none>;
1052 i2c5_gpio: i2c5-gpio {
1054 <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1055 <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1060 i2s_8ch_bus: i2s-8ch-bus {
1062 <4 16 RK_FUNC_1 &pcfg_pull_none>,
1063 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1064 <4 18 RK_FUNC_1 &pcfg_pull_none>,
1065 <4 19 RK_FUNC_1 &pcfg_pull_none>,
1066 <4 20 RK_FUNC_1 &pcfg_pull_none>,
1067 <4 21 RK_FUNC_1 &pcfg_pull_none>,
1068 <4 22 RK_FUNC_1 &pcfg_pull_none>,
1069 <4 23 RK_FUNC_1 &pcfg_pull_none>,
1070 <4 24 RK_FUNC_1 &pcfg_pull_none>;
1075 spdif_bus: spdif-bus {
1077 <5 19 RK_FUNC_1 &pcfg_pull_none>;
1082 spi0_clk: spi0-clk {
1084 <2 29 RK_FUNC_2 &pcfg_pull_up>;
1086 spi0_cs0: spi0-cs0 {
1088 <2 24 RK_FUNC_3 &pcfg_pull_up>;
1090 spi0_cs1: spi0-cs1 {
1092 <2 25 RK_FUNC_3 &pcfg_pull_up>;
1096 <2 23 RK_FUNC_3 &pcfg_pull_up>;
1100 <2 22 RK_FUNC_3 &pcfg_pull_up>;
1105 spi1_clk: spi1-clk {
1107 <2 4 RK_FUNC_3 &pcfg_pull_up>;
1109 spi1_cs0: spi1-cs0 {
1111 <2 5 RK_FUNC_3 &pcfg_pull_up>;
1115 <2 6 RK_FUNC_3 &pcfg_pull_up>;
1119 <2 7 RK_FUNC_3 &pcfg_pull_up>;
1124 uart0_xfer: uart0-xfer {
1126 <3 8 RK_FUNC_1 &pcfg_pull_up>,
1127 <3 9 RK_FUNC_1 &pcfg_pull_none>;
1130 uart0_cts: uart0-cts {
1132 <3 10 RK_FUNC_1 &pcfg_pull_none>;
1135 uart0_rts: uart0-rts {
1137 <3 11 RK_FUNC_1 &pcfg_pull_none>;
1142 uart2_t0_xfer: uart2_t0-xfer {
1144 <0 22 RK_FUNC_1 &pcfg_pull_up>,
1145 <0 21 RK_FUNC_1 &pcfg_pull_none>;
1147 /* no rts / cts for uart2 */
1151 uart2_t1_xfer: uart2_t1-xfer {
1153 <5 0 RK_FUNC_2 &pcfg_pull_up>,
1154 <5 1 RK_FUNC_2 &pcfg_pull_none>;
1156 /* no rts / cts for uart2 */
1160 uart2_t2_xfer: uart2_t2-xfer {
1162 <5 14 RK_FUNC_3 &pcfg_pull_up>,
1163 <5 13 RK_FUNC_3 &pcfg_pull_none>;
1165 /* no rts / cts for uart2 */
1169 uart3_xfer: uart3-xfer {
1171 <5 15 RK_FUNC_1 &pcfg_pull_up>,
1172 <5 16 RK_FUNC_1 &pcfg_pull_none>;
1175 uart3_cts: uart3-cts {
1177 <5 17 RK_FUNC_1 &pcfg_pull_none>;
1180 uart3_rts: uart3-rts {
1182 <5 18 RK_FUNC_1 &pcfg_pull_none>;
1187 pwm0_pin: pwm0-pin {
1189 <0 8 RK_FUNC_1 &pcfg_pull_none>;
1194 pwm1_pin: pwm1-pin {
1196 <1 6 RK_FUNC_2 &pcfg_pull_none>;
1201 pwm2_t0_pin: pwm2_t0-pin {
1203 <2 15 RK_FUNC_3 &pcfg_pull_none>;
1208 pwm2_t1_pin: pwm2_t1-pin {
1210 <5 17 RK_FUNC_2 &pcfg_pull_none>;
1215 pwm3_t0_pin: pwm3_t0-pin {
1217 <1 0 RK_FUNC_2 &pcfg_pull_none>;
1222 pwm3_t1_pin: pwm3_t1-pin {
1224 <0 21 RK_FUNC_2 &pcfg_pull_none>;
1229 pwm3_t2_pin: pwm3_t2-pin {
1231 <5 18 RK_FUNC_2 &pcfg_pull_none>;
1236 lcdc_lcdc: lcdc-lcdc {
1238 <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1239 <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1240 <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1241 <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1242 <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1243 <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1244 <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1245 <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1246 <1 0 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1247 <1 1 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1248 <1 2 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1249 <1 3 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1250 <1 4 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1251 <1 5 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1252 <1 6 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1253 <1 7 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1254 <1 8 RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1255 <1 9 RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1258 lcdc_gpio: lcdc-gpio {
1260 <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1261 <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1262 <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1263 <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1264 <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1265 <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1266 <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1267 <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1268 <1 0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1269 <1 1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1270 <1 2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1271 <1 3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1272 <1 4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1273 <1 5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1274 <1 6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1275 <1 7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1276 <1 8 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1277 <1 9 RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1282 rgmii_pins: rgmii-pins {
1285 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1287 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1289 <2 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1291 <2 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1293 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1295 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1297 <2 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1299 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1301 <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1303 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1305 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1307 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1309 <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1311 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1313 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1315 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1317 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1320 rmii_pins: rmii-pins {
1323 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1325 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1327 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1329 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1331 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1333 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1335 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1337 <2 12 RK_FUNC_1 &pcfg_pull_none>,
1339 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1341 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1343 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1345 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1350 eth_phy_pwr: eth-phy-pwr {
1352 <0 25 RK_FUNC_GPIO &pcfg_pull_none>;