arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/mipi_dsi.h>
  49 #include <dt-bindings/power/rk3366-power.h>
  50 #include <dt-bindings/soc/rockchip,boot-mode.h>
  51 #include <dt-bindings/thermal/thermal.h>
  52 #include <dt-bindings/display/drm_mipi_dsi.h>
  53 #include <dt-bindings/display/media-bus-format.h>
  54
  55 / {
  56         compatible = "rockchip,rk3366";
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 serial0 = &uart0;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73         };
  74
  75         cpus {
  76                 #address-cells = <0x2>;
  77                 #size-cells = <0x0>;
  78
  79                 cpu0: cpu@0 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53","arm,armv8";
  82                         reg = <0x0 0x0>;
  83                         enable-method = "psci";
  84                         clocks = <&cru ARMCLK>;
  85                         operating-points-v2 = <&cpu0_opp_table>;
  86                         cpu-idle-states = <&cpu_sleep>;
  87                         #cooling-cells = <2>; /* min followed by max */
  88                         dynamic-power-coefficient = <166>;
  89                 };
  90
  91                 cpu1: cpu@1 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a53","arm,armv8";
  94                         reg = <0x0 0x1>;
  95                         enable-method = "psci";
  96                         operating-points-v2 = <&cpu0_opp_table>;
  97                         cpu-idle-states = <&cpu_sleep>;
  98                 };
  99
 100                 cpu2: cpu@2 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53","arm,armv8";
 103                         reg = <0x0 0x2>;
 104                         enable-method = "psci";
 105                         operating-points-v2 = <&cpu0_opp_table>;
 106                         cpu-idle-states = <&cpu_sleep>;
 107                 };
 108
 109                 cpu3: cpu@3 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53","arm,armv8";
 112                         reg = <0x0 0x3>;
 113                         enable-method = "psci";
 114                         operating-points-v2 = <&cpu0_opp_table>;
 115                         cpu-idle-states = <&cpu_sleep>;
 116                 };
 117
 118                 idle-states {
 119                         entry-method = "psci";
 120                         cpu_sleep: cpu-sleep-0 {
 121                                 compatible = "arm,idle-state";
 122                                 local-timer-stop;
 123                                 arm,psci-suspend-param = <0x0010000>;
 124                                 entry-latency-us = <350>;
 125                                 exit-latency-us = <600>;
 126                                 min-residency-us = <1150>;
 127                         };
 128                 };
 129         };
 130
 131         cpu0_opp_table: opp_table0 {
 132                 compatible = "operating-points-v2";
 133                 opp-shared;
 134
 135                 nvmem-cells = <&cpu_leakage>;
 136                 nvmem-cell-names = "cpu_leakage";
 137
 138                 opp-408000000 {
 139                         opp-hz = /bits/ 64 <408000000>;
 140                         opp-microvolt = <950000>;
 141                         clock-latency-ns = <40000>;
 142                         opp-suspend;
 143                 };
 144                 opp-600000000 {
 145                         opp-hz = /bits/ 64 <600000000>;
 146                         opp-microvolt = <950000>;
 147                 };
 148                 opp-816000000 {
 149                         opp-hz = /bits/ 64 <816000000>;
 150                         opp-microvolt = <1000000>;
 151                 };
 152                 opp-1008000000 {
 153                         opp-hz = /bits/ 64 <1008000000>;
 154                         opp-microvolt = <1075000>;
 155                 };
 156                 opp-1200000000 {
 157                         opp-hz = /bits/ 64 <1200000000>;
 158                         opp-microvolt = <1175000>;
 159                 };
 160                 opp-1296000000 {
 161                         opp-hz = /bits/ 64 <1296000000>;
 162                         opp-microvolt = <1250000>;
 163                 };
 164         };
 165
 166         psci {
 167                 compatible = "arm,psci-1.0";
 168                 method = "smc";
 169         };
 170
 171         timer {
 172                 compatible = "arm,armv8-timer";
 173                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 174                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 175                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 176                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 177         };
 178
 179         arm-pmu {
 180                 compatible = "arm,cortex-a53-pmu";
 181                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 182                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 183                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 184                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 185                 interrupt-affinity = <&cpu0>,
 186                                      <&cpu1>,
 187                                      <&cpu2>,
 188                                      <&cpu3>;
 189         };
 190
 191         xin24m: xin24m {
 192                 compatible = "fixed-clock";
 193                 #clock-cells = <0>;
 194                 clock-frequency = <24000000>;
 195                 clock-output-names = "xin24m";
 196         };
 197
 198         gic: interrupt-controller@ffb71000 {
 199                 compatible = "arm,gic-400";
 200                 interrupt-controller;
 201                 #interrupt-cells = <3>;
 202                 #address-cells = <0>;
 203
 204                 reg = <0x0 0xffb71000 0x0 0x1000>,
 205                       <0x0 0xffb72000 0x0 0x1000>,
 206                       <0x0 0xffb74000 0x0 0x2000>,
 207                       <0x0 0xffb76000 0x0 0x2000>;
 208                 interrupts = <GIC_PPI 9
 209                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 210         };
 211
 212         nandc0: nandc@ff0c0000 {
 213                 compatible = "rockchip,rk-nandc";
 214                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 215                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 216                 nandc_id = <0>;
 217                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 218                 clock-names = "clk_nandc", "hclk_nandc";
 219                 status = "disabled";
 220         };
 221
 222         saradc: saradc@ff100000 {
 223                 compatible = "rockchip,saradc";
 224                 reg = <0x0 0xff100000 0x0 0x100>;
 225                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 226                 #io-channel-cells = <1>;
 227                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 228                 clock-names = "saradc", "apb_pclk";
 229                 status = "disabled";
 230         };
 231
 232         spi0: spi@ff110000 {
 233                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 234                 reg = <0x0 0xff110000 0x0 0x1000>;
 235                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 236                 clock-names = "spiclk", "apb_pclk";
 237                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 238                 pinctrl-names = "default";
 239                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 240                 #address-cells = <1>;
 241                 #size-cells = <0>;
 242                 status = "disabled";
 243         };
 244
 245         spi1: spi@ff120000 {
 246                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 247                 reg = <0x0 0xff120000 0x0 0x1000>;
 248                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 249                 clock-names = "spiclk", "apb_pclk";
 250                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 251                 pinctrl-names = "default";
 252                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 253                 #address-cells = <1>;
 254                 #size-cells = <0>;
 255                 status = "disabled";
 256         };
 257
 258         scr: rkscr@ff1d0000 {
 259                 compatible = "rockchip-scr";
 260                 reg = <0x0 0xff1d0000 0x0 0x10000>;
 261                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 262                 #address-cells = <1>;
 263                 #size-cells = <0>;
 264                 pinctrl-names = "default";
 265                 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
 266                 clocks = <&cru PCLK_SIM>;
 267                 clock-names = "g_pclk_sim_card";
 268                 status = "disabled";
 269         };
 270
 271         thermal-zones {
 272                 soc_thermal: soc-thermal {
 273                         polling-delay-passive = <100>; /* milliseconds */
 274                         polling-delay = <1000>; /* milliseconds */
 275                         sustainable-power = <1600>; /* milliwatts */
 276
 277                         thermal-sensors = <&tsadc 0>;
 278
 279                         trips {
 280                                 threshold: trip-point@0 {
 281                                         temperature = <70000>; /* millicelsius */
 282                                         hysteresis = <2000>; /* millicelsius */
 283                                         type = "passive";
 284                                 };
 285                                 target: trip-point@1 {
 286                                         temperature = <85000>; /* millicelsius */
 287                                         hysteresis = <2000>; /* millicelsius */
 288                                         type = "passive";
 289                                 };
 290                                 soc_crit: soc-crit {
 291                                         temperature = <95000>; /* millicelsius */
 292                                         hysteresis = <2000>; /* millicelsius */
 293                                         type = "critical";
 294                                 };
 295                         };
 296
 297                         cooling-maps {
 298                                 map0 {
 299                                         trip = <&target>;
 300                                         cooling-device =
 301                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 302                                 };
 303                                 map1 {
 304                                         trip = <&target>;
 305                                         cooling-device =
 306                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 307                                 };
 308                         };
 309                 };
 310
 311                 gpu_thermal: gpu-thermal {
 312                         polling-delay-passive = <100>; /* milliseconds */
 313                         polling-delay = <1000>; /* milliseconds */
 314
 315                         thermal-sensors = <&tsadc 1>;
 316                 };
 317         };
 318
 319         tsadc: tsadc@ff260000 {
 320                 compatible = "rockchip,rk3366-tsadc";
 321                 reg = <0x0 0xff260000 0x0 0x100>;
 322                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 323                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 324                 clock-names = "tsadc", "apb_pclk";
 325                 resets = <&cru SRST_TSADC>;
 326                 reset-names = "tsadc-apb";
 327                 pinctrl-names = "default";
 328                 pinctrl-0 = <&tsadc_gpio>;
 329                 #thermal-sensor-cells = <1>;
 330                 rockchip,hw-tshut-temp = <95000>;
 331                 status = "disabled";
 332         };
 333
 334         sdmmc: dwmmc@ff400000 {
 335                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 336                 clock-freq-min-max = <400000 150000000>;
 337                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 338                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 339                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 340                 fifo-depth = <0x100>;
 341                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 342                 reg = <0x0 0xff400000 0x0 0x4000>;
 343                 status = "disabled";
 344         };
 345
 346         sdio: dwmmc@ff410000 {
 347                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 348                 clock-freq-min-max = <400000 150000000>;
 349                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 350                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 351                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 352                 fifo-depth = <0x100>;
 353                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 354                 reg = <0x0 0xff410000 0x0 0x4000>;
 355                 status = "disabled";
 356         };
 357
 358         emmc: dwmmc@ff420000 {
 359                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 360                 clock-freq-min-max = <400000 150000000>;
 361                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 362                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 363                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 364                 fifo-depth = <0x100>;
 365                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 366                 reg = <0x0 0xff420000 0x0 0x4000>;
 367                 status = "disabled";
 368         };
 369
 370         gmac: eth@ff440000 {
 371                 compatible = "rockchip,rk3366-gmac";
 372                 reg = <0x0 0xff440000 0x0 0x10000>;
 373                 rockchip,grf = <&grf>;
 374                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 375                 interrupt-names = "macirq";
 376                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 377                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 378                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 379                          <&cru PCLK_GMAC>;
 380                 clock-names = "stmmaceth", "mac_clk_rx",
 381                               "mac_clk_tx", "clk_mac_ref",
 382                               "clk_mac_refout", "aclk_mac",
 383                               "pclk_mac";
 384                 resets = <&cru SRST_MAC>;
 385                 reset-names = "stmmaceth";
 386                 status = "disabled";
 387         };
 388
 389         i2c0: i2c@ff650000 {
 390                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 391                 reg = <0x0 0xff728000 0x0 0x1000>;
 392                 clocks = <&cru PCLK_I2C0>;
 393                 clock-names = "i2c";
 394                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&i2c0_xfer>;
 397                 #address-cells = <1>;
 398                 #size-cells = <0>;
 399                 status = "disabled";
 400         };
 401
 402         i2c2: i2c@ff140000 {
 403                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 404                 reg = <0x0 0xff140000 0x0 0x1000>;
 405                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 clock-names = "i2c";
 409                 clocks = <&cru PCLK_I2C2>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&i2c2_xfer>;
 412                 status = "disabled";
 413         };
 414
 415         i2c3: i2c@ff150000 {
 416                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 417                 reg = <0x0 0xff150000 0x0 0x1000>;
 418                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 419                 #address-cells = <1>;
 420                 #size-cells = <0>;
 421                 clock-names = "i2c";
 422                 clocks = <&cru PCLK_I2C3>;
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&i2c3_xfer>;
 425                 status = "disabled";
 426         };
 427
 428         i2c4: i2c@ff160000 {
 429                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 430                 reg = <0x0 0xff160000 0x0 0x1000>;
 431                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 432                 #address-cells = <1>;
 433                 #size-cells = <0>;
 434                 clock-names = "i2c";
 435                 clocks = <&cru PCLK_I2C4>;
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&i2c4_xfer>;
 438                 status = "disabled";
 439         };
 440
 441         i2c5: i2c@ff170000 {
 442                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 443                 reg = <0x0 0xff170000 0x0 0x1000>;
 444                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 445                 #address-cells = <1>;
 446                 #size-cells = <0>;
 447                 clock-names = "i2c";
 448                 clocks = <&cru PCLK_I2C5>;
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&i2c5_xfer>;
 451                 status = "disabled";
 452         };
 453
 454         uart0: serial@ff180000 {
 455                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 456                 reg = <0x0 0xff180000 0x0 0x100>;
 457                 clock-frequency = <24000000>;
 458                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 459                 clock-names = "baudclk", "apb_pclk";
 460                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 461                 reg-shift = <2>;
 462                 reg-io-width = <4>;
 463                 pinctrl-names = "default";
 464                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 465                 status = "disabled";
 466         };
 467
 468         uart3: serial@ff1b0000 {
 469                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 470                 reg = <0x0 0xff1b0000 0x0 0x100>;
 471                 clock-frequency = <24000000>;
 472                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 473                 clock-names = "baudclk", "apb_pclk";
 474                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 475                 reg-shift = <2>;
 476                 reg-io-width = <4>;
 477                 pinctrl-names = "default";
 478                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 479                 status = "disabled";
 480         };
 481
 482         usb_host0_ehci: usb@ff480000 {
 483                 compatible = "generic-ehci";
 484                 reg = <0x0 0xff480000 0x0 0x20000>;
 485                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 486                 clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
 487                 clock-names = "usbphy_480m", "hclk_host0";
 488                 phys = <&u2phy_host>;
 489                 phy-names = "usb";
 490                 status = "disabled";
 491         };
 492
 493         usb_host0_ohci: usb@ff4a0000 {
 494                 compatible = "generic-ohci";
 495                 reg = <0x0 0xff4a0000 0x0 0x20000>;
 496                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 497                 clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
 498                 clock-names = "usbphy_480m", "hclk_host0";
 499                 phys = <&u2phy_host>;
 500                 phy-names = "usb";
 501                 status = "disabled";
 502         };
 503
 504         usb_otg: usb@ff4c0000 {
 505                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 506                              "snps,dwc2";
 507                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 508                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 509                 clocks = <&cru HCLK_OTG>;
 510                 clock-names = "otg";
 511                 dr_mode = "otg";
 512                 g-np-tx-fifo-size = <16>;
 513                 g-rx-fifo-size = <275>;
 514                 g-tx-fifo-size = <256 128 128 64 64 32>;
 515                 g-use-dma;
 516                 status = "disabled";
 517         };
 518
 519         i2c1: i2c@ff660000 {
 520                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 521                 reg = <0x0 0xff660000 0x0 0x1000>;
 522                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 523                 #address-cells = <1>;
 524                 #size-cells = <0>;
 525                 clock-names = "i2c";
 526                 clocks = <&cru PCLK_I2C1>;
 527                 pinctrl-names = "default";
 528                 pinctrl-0 = <&i2c1_xfer>;
 529                 status = "disabled";
 530         };
 531
 532         efuse: efuse@ff670000 {
 533                 compatible = "rockchip,rk3366-efuse";
 534                 reg = <0x0 0xff670000 0x0 0x20>;
 535                 #address-cells = <1>;
 536                 #size-cells = <1>;
 537                 clocks = <&cru PCLK_EFUSE_256>;
 538                 clock-names = "pclk_efuse";
 539
 540                 /* Data cells */
 541                 cpu_leakage: cpu-leakage {
 542                         reg = <0x17 0x1>;
 543                 };
 544                 gpu_leakage: gpu-leakage {
 545                         reg = <0x18 0x1>;
 546                 };
 547                 logic_leakage: logic-leakage {
 548                         reg = <0x19 0x1>;
 549                 };
 550                 wafer_info: wafer-info {
 551                         reg = <0x1c 0x1>;
 552                 };
 553         };
 554
 555         pwm0: pwm@ff680000 {
 556                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 557                 reg = <0x0 0xff680000 0x0 0x10>;
 558                 #pwm-cells = <3>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&pwm0_pin>;
 561                 clocks = <&cru PCLK_RKPWM>;
 562                 clock-names = "pwm";
 563                 status = "disabled";
 564         };
 565
 566         pwm1: pwm@ff680010 {
 567                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 568                 reg = <0x0 0xff680010 0x0 0x10>;
 569                 #pwm-cells = <3>;
 570                 pinctrl-names = "default";
 571                 pinctrl-0 = <&pwm1_pin>;
 572                 clocks = <&cru PCLK_RKPWM>;
 573                 clock-names = "pwm";
 574                 status = "disabled";
 575         };
 576
 577         pwm2: pwm@ff680020 {
 578                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 579                 reg = <0x0 0xff680020 0x0 0x10>;
 580                 #pwm-cells = <3>;
 581                 clocks = <&cru PCLK_RKPWM>;
 582                 clock-names = "pwm";
 583                 status = "disabled";
 584         };
 585
 586         pwm3: pwm@ff680030 {
 587                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 588                 reg = <0x0 0xff680030 0x0 0x10>;
 589                 #pwm-cells = <3>;
 590                 pinctrl-names = "default";
 591                 pinctrl-0 = <&pwm3_t2_pin>;
 592                 clocks = <&cru PCLK_RKPWM>;
 593                 clock-names = "pwm";
 594                 status = "disabled";
 595         };
 596
 597         uart2: serial@ff690000 {
 598                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 599                 reg = <0x0 0xff690000 0x0 0x100>;
 600                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 601                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 602                 clock-names = "baudclk", "apb_pclk";
 603                 reg-shift = <2>;
 604                 reg-io-width = <4>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&uart2_t1_xfer>;
 607                 status = "disabled";
 608         };
 609
 610         pmu: power-management@ff730000 {
 611                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 612                 reg = <0x0 0xff730000 0x0 0x1000>;
 613
 614                 power: power-controller {
 615                         compatible = "rockchip,rk3366-power-controller";
 616                         #power-domain-cells = <1>;
 617                         #address-cells = <1>;
 618                         #size-cells = <0>;
 619
 620                         /*
 621                          * Note: Although SCLK_* are the working clocks
 622                          * of device without including on the NOC, needed for
 623                          * synchronous reset.
 624                          *
 625                          * The clocks on the which NOC:
 626                          * ACLK_IEP/ACLK_VOP_FULL are on ACLK_VIO0_NOC.
 627                          * ACLK_RGA/ACLK_VOP_LITE are on ACLK_VIO1_NOC.
 628                          * ACLK_ISP is on ACLK_ISP_NOC.
 629                          * ACLK_HDCP is on ACLK_HDCP_NOC.
 630                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NOC.
 631                          *
 632                          * Which clock are device clocks:
 633                          *      clocks          devices
 634                          *      *_IEP           IEP:Image Enhancement Processor
 635                          *      *_ISP           ISP:Image Signal Processing
 636                          *      *_VOP*          VOP:Visual Output Processor
 637                          *      *_RGA           RGA
 638                          *      *_DPHY*         LVDS
 639                          *      *_HDMI          HDMI
 640                          *      *_MIPI_*        MIPI/LVDS
 641                          */
 642                         pd_vio@RK3366_PD_VIO {
 643                                 reg = <RK3366_PD_VIO>;
 644                                 clocks = <&cru ACLK_IEP>,
 645                                          <&cru ACLK_ISP>,
 646                                          <&cru ACLK_RGA>,
 647                                          <&cru ACLK_HDCP>,
 648                                          <&cru ACLK_VOP_FULL>,
 649                                          <&cru ACLK_VOP_LITE>,
 650                                          <&cru ACLK_VOP_IEP>,
 651                                          <&cru DCLK_VOP_FULL>,
 652                                          <&cru DCLK_VOP_LITE>,
 653                                          <&cru HCLK_IEP>,
 654                                          <&cru HCLK_ISP>,
 655                                          <&cru HCLK_RGA>,
 656                                          <&cru HCLK_VOP_FULL>,
 657                                          <&cru HCLK_VOP_LITE>,
 658                                          <&cru HCLK_VIO_HDCPMMU>,
 659                                          <&cru PCLK_DPHYTX>,
 660                                          <&cru PCLK_HDMI_CTRL>,
 661                                          <&cru PCLK_HDCP>,
 662                                          <&cru PCLK_MIPI_DSI0>,
 663                                          <&cru SCLK_VOP_FULL_PWM>,
 664                                          <&cru SCLK_HDCP>,
 665                                          <&cru SCLK_ISP>,
 666                                          <&cru SCLK_RGA>,
 667                                          <&cru SCLK_HDMI_CEC>,
 668                                          <&cru SCLK_HDMI_HDCP>;
 669                         };
 670
 671                         /*
 672                          * Note: ACLK_VCODEC/HCLK_VCODEC are VPU clocks
 673                          * that on the ACLK_VCODEC_NOC and
 674                          * HCLK_VCODEC_NOC.
 675                          */
 676                         pd_vpu@RK3366_PD_VPU {
 677                                 reg = <RK3366_PD_VPU>;
 678                                 clocks = <&cru ACLK_VIDEO>,
 679                                          <&cru HCLK_VIDEO>;
 680                         };
 681
 682                         /*
 683                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 684                          * clocks that on the ACLK_RKVDEC_NOC and
 685                          * HCLK_RKVDEC_NOC.
 686                          */
 687                         pd_rkvdec@RK3366_PD_RKVDEC {
 688                                 reg = <RK3366_PD_RKVDEC>;
 689                                 clocks = <&cru ACLK_RKVDEC>,
 690                                          <&cru HCLK_RKVDEC>,
 691                                          <&cru SCLK_HEVC_CABAC>,
 692                                          <&cru SCLK_HEVC_CORE>;
 693                         };
 694
 695                         /*
 696                          * Note: ACLK_GPU is the GPU clock
 697                          * that on the ACLK_GPU_NOC.
 698                          */
 699                         pd_gpu@RK3366_PD_GPU {
 700                                 reg = <RK3366_PD_GPU>;
 701                                 clocks = <&cru ACLK_GPU>;
 702                         };
 703                 };
 704         };
 705
 706         pmugrf: syscon@ff738000 {
 707                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 708                 reg = <0x0 0xff738000 0x0 0x1000>;
 709
 710                 reboot-mode {
 711                         compatible = "syscon-reboot-mode";
 712                         offset = <0x200>;
 713                         mode-normal = <BOOT_NORMAL>;
 714                         mode-recovery = <BOOT_RECOVERY>;
 715                         mode-fastboot = <BOOT_FASTBOOT>;
 716                         mode-loader = <BOOT_BL_DOWNLOAD>;
 717                 };
 718
 719                 pmu_pvtm: pmu-pvtm {
 720                         compatible = "rockchip,rk3366-pmu-pvtm";
 721                         clocks = <&cru SCLK_PVTM_PMU>;
 722                         clock-names = "pmu";
 723                         status = "disabled";
 724                 };
 725         };
 726
 727         amba {
 728                 compatible = "arm,amba-bus";
 729                 #address-cells = <2>;
 730                 #size-cells = <2>;
 731                 ranges;
 732
 733                 dmac_peri: dma-controller@ff250000 {
 734                         compatible = "arm,pl330", "arm,primecell";
 735                         reg = <0x0 0xff250000 0x0 0x4000>;
 736                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 737                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 738                         #dma-cells = <1>;
 739                         clocks = <&cru ACLK_DMAC_PERI>;
 740                         clock-names = "apb_pclk";
 741                         peripherals-req-type-burst;
 742                 };
 743
 744                 dmac_bus: dma-controller@ff600000 {
 745                         compatible = "arm,pl330", "arm,primecell";
 746                         reg = <0x0 0xff600000 0x0 0x4000>;
 747                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 748                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 749                         #dma-cells = <1>;
 750                         clocks = <&cru ACLK_DMAC_BUS>;
 751                         clock-names = "apb_pclk";
 752                         peripherals-req-type-burst;
 753                 };
 754         };
 755
 756         cru: clock-controller@ff760000 {
 757                 compatible = "rockchip,rk3366-cru";
 758                 reg = <0x0 0xff760000 0x0 0x1000>;
 759                 rockchip,grf = <&grf>;
 760                 #clock-cells = <1>;
 761                 #reset-cells = <1>;
 762                 assigned-clocks =
 763                         <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
 764                         <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
 765                         <&cru SCLK_I2S_8CH_SRC>, <&cru SCLK_I2S_2CH_SRC>,
 766                         <&cru SCLK_SPDIF_8CH_SRC>,
 767                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 768                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 769                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 770                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 771                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
 772                         <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
 773                         <&cru ACLK_PERI1>;
 774                 assigned-clock-rates =
 775                         <0>, <0>,
 776                         <0>, <0>,
 777                         <0>, <0>,
 778                         <0>,
 779                         <750000000>, <576000000>,
 780                         <594000000>, <594000000>,
 781                         <960000000>, <520000000>,
 782                         <375000000>, <288000000>,
 783                         <100000000>, <100000000>,
 784                         <288000000>, <288000000>,
 785                         <144000000>;
 786                 assigned-clock-parents =
 787                         <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
 788                         <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>,
 789                         <&cru PLL_GPLL>, <&cru PLL_GPLL>,
 790                         <&cru PLL_GPLL>;
 791         };
 792
 793         grf: syscon@ff770000 {
 794                 compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd";
 795                 reg = <0x0 0xff770000 0x0 0x1000>;
 796                 #address-cells = <1>;
 797                 #size-cells = <1>;
 798
 799                 u2phy: usb2-phy@700 {
 800                         compatible = "rockchip,rk3366-usb2phy";
 801                         reg = <0x700 0x2c>;
 802                         clocks = <&cru SCLK_OTG_PHY0>;
 803                         clock-names = "phyclk";
 804                         #clock-cells = <0>;
 805                         clock-output-names = "sclk_otgphy0_480m";
 806
 807                         u2phy_host: host-port {
 808                                 #phy-cells = <0>;
 809                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 810                                 interrupt-names = "linestate";
 811                                 status = "okay";
 812                         };
 813                 };
 814
 815                 pvtm: pvtm {
 816                         compatible = "rockchip,rk3366-pvtm";
 817                         clocks = <&cru SCLK_PVTM_CORE>, <&cru SCLK_PVTM_GPU>;
 818                         clock-names = "core", "gpu";
 819                         status = "disabled";
 820                 };
 821         };
 822
 823         wdt: watchdog@ff800000 {
 824                 compatible = "snps,dw-wdt";
 825                 reg = <0x0 0xff800000 0x0 0x100>;
 826                 clocks = <&cru PCLK_WDT>;
 827                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 828                 status = "disabled";
 829         };
 830
 831         rktimer: rktimer@ff810000 {
 832                 compatible = "rockchip,rk3288-timer";
 833                 reg = <0x0 0xff810000 0x0 0x1000>;
 834                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
 835                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER0>;
 836                 clock-names = "pclk", "timer";
 837         };
 838
 839         spdif: spdif@ff880000 {
 840                 compatible = "rockchip,rk3366-spdif";
 841                 reg = <0x0 0xff880000 0x0 0x1000>;
 842                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 843                 dmas = <&dmac_bus 3>;
 844                 dma-names = "tx";
 845                 clock-names = "mclk", "hclk";
 846                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 847                 pinctrl-names = "default";
 848                 pinctrl-0 = <&spdif_bus>;
 849                 status = "disabled";
 850         };
 851
 852         i2s_2ch: i2s-2ch@ff890000 {
 853                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 854                 reg = <0x0 0xff890000 0x0 0x1000>;
 855                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 856                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 857                 dma-names = "tx", "rx";
 858                 clock-names = "i2s_clk", "i2s_hclk";
 859                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 860                 status = "disabled";
 861         };
 862
 863         i2s_8ch: i2s-8ch@ff898000 {
 864                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 865                 reg = <0x0 0xff898000 0x0 0x1000>;
 866                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 867                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 868                 dma-names = "tx", "rx";
 869                 clock-names = "i2s_clk", "i2s_hclk";
 870                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 871                 pinctrl-names = "default";
 872                 pinctrl-0 = <&i2s_8ch_bus>;
 873                 status = "disabled";
 874         };
 875
 876         display_subsystem: display-subsystem {
 877                 compatible = "rockchip,display-subsystem";
 878                 ports = <&vopb_out>, <&vopl_out>;
 879                 status = "disabled";
 880         };
 881
 882         vopl: vop@ff8f0000 {
 883                 compatible = "rockchip,rk3366-vop-lit";
 884                 reg = <0x0 0xff8f0000 0x0 0x900>;
 885                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 886                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>,
 887                          <&cru HCLK_VOP_LITE>;
 888                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 889                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>,
 890                          <&cru SRST_VOP1_AHB>;
 891                 reset-names = "axi", "ahb", "dclk";
 892                 power-domains = <&power RK3366_PD_VIO>;
 893                 iommus = <&vopl_mmu>;
 894                 status = "disabled";
 895
 896                 vopl_out: port {
 897                         #address-cells = <1>;
 898                         #size-cells = <0>;
 899
 900                         vopl_out_dsi: endpoint@0 {
 901                                 reg = <0>;
 902                                 remote-endpoint = <&dsi_in_vopl>;
 903                         };
 904
 905                         vopl_out_lvds: endpoint@1 {
 906                                 reg = <1>;
 907                                 remote-endpoint = <&lvds_in_vopl>;
 908                         };
 909                 };
 910         };
 911
 912         vopl_mmu: iommu@ff8f0f00 {
 913                 compatible = "rockchip,iommu";
 914                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 915                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>;
 916                 interrupt-names = "vopl_mmu";
 917                 clocks = <&cru ACLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 918                 clock-names = "aclk", "hclk";
 919                 power-domains = <&power RK3366_PD_VIO>;
 920                 #iommu-cells = <0>;
 921                 status = "disabled";
 922         };
 923
 924         iep: iep@ff900000 {
 925                 compatible = "rockchip,iep";
 926                 iommu_enabled = <1>;
 927                 iommus = <&iep_mmu>;
 928                 reg = <0x0 0xff900000 0x0 0x800>;
 929                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 930                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 931                 clock-names = "aclk_iep", "hclk_iep";
 932                 power-domains = <&power RK3366_PD_VIO>;
 933                 allocator = <1>;
 934                 version = <2>;
 935                 status = "disabled";
 936         };
 937
 938         iep_mmu: iommu@ff900800 {
 939                 compatible = "rockchip,iommu";
 940                 reg = <0x0 0xff900800 0x0 0x100>;
 941                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 942                 interrupt-names = "iep_mmu";
 943                 power-domains = <&power RK3366_PD_VIO>;
 944                 #iommu-cells = <0>;
 945                 status = "disabled";
 946         };
 947
 948         rga: rga@ff920000 {
 949                 compatible = "rockchip,rga2";
 950                 dev_mode = <1>;
 951                 reg = <0x0 0xff920000 0x0 0x1000>;
 952                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 953                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 954                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 955                 power-domains = <&power RK3366_PD_VIO>;
 956                 status = "disabled";
 957         };
 958
 959         vopb: vop@ff930000 {
 960                 compatible = "rockchip,rk3366-vop";
 961                 reg = <0x0 0xff930000 0x0 0x1ffc>;
 962                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 963                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>,
 964                          <&cru HCLK_VOP_FULL>;
 965                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 966                 power-domains = <&power RK3366_PD_VIO>;
 967                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>,
 968                          <&cru SRST_VOP0_AHB>;
 969                 reset-names = "axi", "ahb", "dclk";
 970                 iommus = <&vopb_mmu>;
 971                 status = "disabled";
 972
 973                 vopb_out: port {
 974                         #address-cells = <1>;
 975                         #size-cells = <0>;
 976
 977                         vopb_out_dsi: endpoint@0 {
 978                                 reg = <0>;
 979                                 remote-endpoint = <&dsi_in_vopb>;
 980                         };
 981
 982                         vopb_out_lvds: endpoint@1 {
 983                                 reg = <1>;
 984                                 remote-endpoint = <&lvds_in_vopb>;
 985                         };
 986
 987                         vopb_out_hdmi: endpoint@2 {
 988                                 reg = <2>;
 989                                 remote-endpoint = <&hdmi_in_vopb>;
 990                         };
 991                 };
 992         };
 993
 994         vopb_mmu: iommu@ff932400 {
 995                 compatible = "rockchip,iommu";
 996                 reg = <0x0 0xff932400 0x0 0x100>;
 997                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
 998                 interrupt-names = "vop_mmu";
 999                 clocks = <&cru ACLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
1000                 clock-names = "aclk", "hclk";
1001                 power-domains = <&power RK3366_PD_VIO>;
1002                 #iommu-cells = <0>;
1003                 status = "disabled";
1004         };
1005
1006         dsi: dsi@ff960000 {
1007                 compatible = "rockchip,rk3366-mipi-dsi";
1008                 reg = <0x0 0xff960000 0x0 0x4000>;
1009                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1010                 clocks = <&cru PCLK_MIPI_DSI0>;
1011                 clock-names = "pclk";
1012                 resets = <&cru SRST_MIPIDSI0>;
1013                 reset-names = "apb";
1014                 phys = <&mipi_dphy>;
1015                 phy-names = "mipi_dphy";
1016                 power-domains = <&power RK3366_PD_VIO>;
1017                 rockchip,grf = <&grf>;
1018                 #address-cells = <1>;
1019                 #size-cells = <0>;
1020                 status = "disabled";
1021
1022                 ports {
1023                         port {
1024                                 #address-cells = <1>;
1025                                 #size-cells = <0>;
1026
1027                                 dsi_in_vopb: endpoint@0 {
1028                                         reg = <0>;
1029                                         remote-endpoint = <&vopb_out_dsi>;
1030                                 };
1031                                 dsi_in_vopl: endpoint@1 {
1032                                         reg = <1>;
1033                                         remote-endpoint = <&vopl_out_dsi>;
1034                                 };
1035                         };
1036                 };
1037         };
1038
1039         mipi_dphy: mipi-dphy@ff968000 {
1040                 compatible = "rockchip,rk3366-mipi-dphy";
1041                 reg = <0x0 0xff968000 0x0 0x4000>;
1042                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>;
1043                 clock-names = "ref", "pclk";
1044                 resets = <&cru SRST_MIPIDPHYTX>;
1045                 reset-names = "apb";
1046                 #phy-cells = <0>;
1047                 status = "disabled";
1048         };
1049
1050         lvds: lvds@ff968000 {
1051                 compatible = "rockchip,rk3366-lvds";
1052                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1053                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1054                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
1055                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1056                 power-domains = <&power RK3366_PD_VIO>;
1057                 pinctrl-names = "lcdc", "gpio";
1058                 pinctrl-0 = <&lcdc_lcdc>;
1059                 pinctrl-1 = <&lcdc_gpio>;
1060                 rockchip,grf = <&grf>;
1061                 status = "disabled";
1062
1063                 ports {
1064                         #address-cells = <1>;
1065                         #size-cells = <0>;
1066
1067                         port@0 {
1068                                 reg = <0>;
1069                                 #address-cells = <1>;
1070                                 #size-cells = <0>;
1071
1072                                 lvds_in_vopb: endpoint@0 {
1073                                         reg = <0>;
1074                                         remote-endpoint = <&vopb_out_lvds>;
1075                                 };
1076                                 lvds_in_vopl: endpoint@1 {
1077                                         reg = <1>;
1078                                         remote-endpoint = <&vopl_out_lvds>;
1079                                 };
1080                         };
1081                 };
1082
1083         };
1084
1085         hdmi: hdmi@ff980000 {
1086                 compatible = "rockchip,rk3366-dw-hdmi";
1087                 reg = <0x0 0xff980000 0x0 0x20000>;
1088                 reg-io-width = <4>;
1089                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1090                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1091                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>,
1092                          <&cru SCLK_HDMI_CEC>, <&cru DCLK_HDMIPHY>;
1093                 clock-names = "iahb", "isfr", "cec", "dclk";
1094                 pinctrl-names = "default";
1095                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1096                 resets = <&cru SRST_HDMI>;
1097                 reset-names = "hdmi";
1098                 //power-domains = <&power RK3366_PD_VIO>;
1099                 rockchip,grf = <&grf>;
1100                 status = "disabled";
1101
1102                 ports {
1103                         port {
1104                                 #address-cells = <1>;
1105                                 #size-cells = <0>;
1106
1107                                 hdmi_in_vopb: endpoint@0 {
1108                                         reg = <0>;
1109                                         remote-endpoint = <&vopb_out_hdmi>;
1110                                 };
1111                         };
1112                 };
1113         };
1114
1115         vpu: vpu_service@ff9a0000 {
1116                 compatible = "rockchip,vpu_service";
1117                 rockchip,grf = <&grf>;
1118                 iommu_enabled = <1>;
1119                 iommus = <&vpu_mmu>;
1120                 reg = <0x0 0xff9a0000 0x0 0x800>;
1121                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1122                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1123                 interrupt-names = "irq_dec", "irq_enc";
1124                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1125                 clock-names = "aclk_vcodec", "hclk_vcodec";
1126                 power-domains = <&power RK3366_PD_VPU>;
1127                 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
1128                 reset-names = "video_h", "video_a";
1129                 name = "vpu_service";
1130                 dev_mode = <0>;
1131                 /* 0 means ion, 1 means drm */
1132                 allocator = <1>;
1133                 status = "disabled";
1134         };
1135
1136         vpu_mmu: iommu@ff9a0800 {
1137                 compatible = "rockchip,iommu";
1138                 reg = <0x0 0xff9a0800 0x0 0x100>;
1139                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1140                 interrupt-names = "vpu_mmu";
1141                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1142                 clock-names = "aclk", "hclk";
1143                 power-domains = <&power RK3366_PD_VPU>;
1144                 #iommu-cells = <0>;
1145                 status = "disabled";
1146         };
1147
1148         rkvdec: rkvdec@ff9b0000 {
1149                 compatible = "rockchip,rkvdec";
1150                 rockchip,grf = <&grf>;
1151                 iommus = <&vdec_mmu>;
1152                 iommu_enabled = <1>;
1153                 reg = <0x0 0xff9b0000 0x0 0x400>;
1154                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1155                 interrupt-names = "irq_dec";
1156                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
1157                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
1158                 power-domains = <&power RK3366_PD_RKVDEC>;
1159                 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
1160                 reset-names = "video_h", "video_a";
1161                 dev_mode = <2>;
1162                 name = "rkvdec";
1163                 /* 0 means ion, 1 means drm */
1164                 allocator = <1>;
1165                 status = "disabled";
1166         };
1167
1168         vdec_mmu: iommu@ff9b0480 {
1169                 compatible = "rockchip,iommu";
1170                 reg = <0x0 0xff9b0480 0x0 0x40>,
1171                         <0x0 0xff9b04c0 0x0 0x40>;
1172                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1173                 interrupt-names = "vdec_mmu";
1174                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
1175                 clock-names = "aclk", "hclk";
1176                 power-domains = <&power RK3366_PD_RKVDEC>;
1177                 #iommu-cells = <0>;
1178                 status = "disabled";
1179         };
1180
1181         pinctrl: pinctrl {
1182                 compatible = "rockchip,rk3366-pinctrl";
1183                 rockchip,grf = <&grf>;
1184                 rockchip,pmu = <&pmugrf>;
1185                 #address-cells = <0x2>;
1186                 #size-cells = <0x2>;
1187                 ranges;
1188
1189                 gpio0: gpio0@ff750000 {
1190                         compatible = "rockchip,gpio-bank";
1191                         reg = <0x0 0xff750000 0x0 0x100>;
1192                         clocks = <&cru PCLK_GPIO0>;
1193                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1194
1195                         gpio-controller;
1196                         #gpio-cells = <0x2>;
1197
1198                         interrupt-controller;
1199                         #interrupt-cells = <0x2>;
1200                 };
1201
1202                 gpio1: gpio1@ff780000 {
1203                         compatible = "rockchip,gpio-bank";
1204                         reg = <0x0 0xff758000 0x0 0x100>;
1205                         clocks = <&cru PCLK_GPIO1>;
1206                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1207
1208                         gpio-controller;
1209                         #gpio-cells = <0x2>;
1210
1211                         interrupt-controller;
1212                         #interrupt-cells = <0x2>;
1213                 };
1214
1215                 gpio2: gpio2@ff790000 {
1216                         compatible = "rockchip,gpio-bank";
1217                         reg = <0x0 0xff790000 0x0 0x100>;
1218                         clocks = <&cru PCLK_GPIO2>;
1219                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1220
1221                         gpio-controller;
1222                         #gpio-cells = <0x2>;
1223
1224                         interrupt-controller;
1225                         #interrupt-cells = <0x2>;
1226                 };
1227
1228                 gpio3: gpio3@ff7a0000 {
1229                         compatible = "rockchip,gpio-bank";
1230                         reg = <0x0 0xff7a0000 0x0 0x100>;
1231                         clocks = <&cru PCLK_GPIO3>;
1232                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1233
1234                         gpio-controller;
1235                         #gpio-cells = <0x2>;
1236
1237                         interrupt-controller;
1238                         #interrupt-cells = <0x2>;
1239                 };
1240
1241                 gpio4: gpio4@ff7b0000 {
1242                         compatible = "rockchip,gpio-bank";
1243                         reg = <0x0 0xff7b0000 0x0 0x100>;
1244                         clocks = <&cru PCLK_GPIO4>;
1245                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1246
1247                         gpio-controller;
1248                         #gpio-cells = <0x2>;
1249
1250                         interrupt-controller;
1251                         #interrupt-cells = <0x2>;
1252                 };
1253
1254                 gpio5: gpio5@ff7c0000 {
1255                         compatible = "rockchip,gpio-bank";
1256                         reg = <0x0 0xff7c0000 0x0 0x100>;
1257                         clocks = <&cru PCLK_GPIO5>;
1258                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1259
1260                         gpio-controller;
1261                         #gpio-cells = <0x2>;
1262
1263                         interrupt-controller;
1264                         #interrupt-cells = <0x2>;
1265                 };
1266
1267                 pcfg_pull_up: pcfg-pull-up {
1268                         bias-pull-up;
1269                 };
1270
1271                 pcfg_pull_down: pcfg-pull-down {
1272                         bias-pull-down;
1273                 };
1274
1275                 pcfg_pull_none: pcfg-pull-none {
1276                         bias-disable;
1277                 };
1278
1279                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1280                         bias-disable;
1281                         drive-strength = <12>;
1282                 };
1283
1284                 emmc {
1285                         emmc_clk: emmc-clk {
1286                                 rockchip,pins =
1287                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
1288                         };
1289
1290                         emmc_cmd: emmc-cmd {
1291                                 rockchip,pins =
1292                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
1293                         };
1294
1295                         emmc_pwr: emmc-pwr {
1296                                 rockchip,pins =
1297                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
1298                         };
1299
1300                         emmc_bus1: emmc-bus1 {
1301                                 rockchip,pins =
1302                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
1303                         };
1304
1305                         emmc_bus4: emmc-bus4 {
1306                                 rockchip,pins =
1307                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1308                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1309                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1310                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1311                         };
1312
1313                         emmc_bus8: emmc-bus8 {
1314                                 rockchip,pins =
1315                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1316                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1317                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1318                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
1319                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
1320                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
1321                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
1322                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
1323                         };
1324                 };
1325
1326                 sdmmc {
1327                         sdmmc_cd: sdmmc-cd {
1328                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1329                         };
1330
1331                         sdmmc_bus1: sdmmc-bus1 {
1332                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1333                         };
1334
1335                         sdmmc_bus4: sdmmc-bus4 {
1336                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1337                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1338                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1339                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1340                         };
1341
1342                         sdmmc_clk: sdmmc-clk {
1343                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1344                         };
1345
1346                         sdmmc_cmd: sdmmc-cmd {
1347                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1348                         };
1349                 };
1350
1351                 sdio {
1352                         sdio_bus1: sdio-bus1 {
1353                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1354                         };
1355
1356                         sdio_bus4: sdio-bus4 {
1357                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1358                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1359                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1360                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1361                         };
1362
1363                         sdio_cmd: sdio-cmd {
1364                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1365                         };
1366
1367                         sdio_clk: sdio-clk {
1368                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1369                         };
1370
1371                         sdio_cd: sdio-cd {
1372                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1373                         };
1374
1375                         sdio_wp: sdio-wp {
1376                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1377                         };
1378
1379                         sdio_int: sdio-int {
1380                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1381                         };
1382
1383                         sdio_pwr: sdio-pwr {
1384                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1385                         };
1386                 };
1387
1388                 hdmi_i2c {
1389                         hdmii2c_xfer: hdmii2c-xfer {
1390                                 rockchip,pins =
1391                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
1392                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
1393                         };
1394                 };
1395
1396                 hdmi_pin {
1397                         hdmi_cec: hdmi-cec {
1398                                 rockchip,pins =
1399                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
1400                         };
1401                 };
1402
1403                 i2c0 {
1404                         i2c0_xfer: i2c0-xfer {
1405                                 rockchip,pins =
1406                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
1407                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
1408                         };
1409                 };
1410
1411                 i2c1 {
1412                         i2c1_xfer: i2c1-xfer {
1413                                 rockchip,pins =
1414                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1415                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1416                         };
1417                 };
1418
1419                 i2c2 {
1420                         i2c2_xfer: i2c2-xfer {
1421                                 rockchip,pins =
1422                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1423                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1424                         };
1425
1426                         i2c2_gpio: i2c2-gpio {
1427                                 rockchip,pins =
1428                                         <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1429                                         <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1430                         };
1431                 };
1432
1433                 i2c3 {
1434                         i2c3_xfer: i2c3-xfer {
1435                                 rockchip,pins =
1436                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1437                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1438                         };
1439                 };
1440
1441                 i2c4 {
1442                         i2c4_xfer: i2c4-xfer {
1443                                 rockchip,pins =
1444                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1445                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1446                         };
1447
1448                         i2c4_gpio: i2c4-gpio {
1449                                 rockchip,pins =
1450                                         <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1451                                         <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1452                         };
1453                 };
1454
1455                 i2c5 {
1456                         i2c5_xfer: i2c5-xfer {
1457                                 rockchip,pins =
1458                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1459                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1460                         };
1461                         i2c5_gpio: i2c5-gpio {
1462                                 rockchip,pins =
1463                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1464                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1465                         };
1466                 };
1467
1468                 i2s {
1469                         i2s_8ch_bus: i2s-8ch-bus {
1470                                 rockchip,pins =
1471                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1472                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1473                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1474                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1475                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1476                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1477                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1478                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1479                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1480                         };
1481                 };
1482
1483                 spdif {
1484                         spdif_bus: spdif-bus {
1485                                 rockchip,pins =
1486                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1487                         };
1488                 };
1489
1490                 spi0 {
1491                         spi0_clk: spi0-clk {
1492                                 rockchip,pins =
1493                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1494                         };
1495                         spi0_cs0: spi0-cs0 {
1496                                 rockchip,pins =
1497                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1498                         };
1499                         spi0_cs1: spi0-cs1 {
1500                                 rockchip,pins =
1501                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1502                         };
1503                         spi0_tx: spi0-tx {
1504                                 rockchip,pins =
1505                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1506                         };
1507                         spi0_rx: spi0-rx {
1508                                 rockchip,pins =
1509                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1510                         };
1511                 };
1512
1513                 spi1 {
1514                         spi1_clk: spi1-clk {
1515                                 rockchip,pins =
1516                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1517                         };
1518                         spi1_cs0: spi1-cs0 {
1519                                 rockchip,pins =
1520                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1521                         };
1522                         spi1_tx: spi1-tx {
1523                                 rockchip,pins =
1524                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1525                         };
1526                         spi1_rx: spi1-rx {
1527                                 rockchip,pins =
1528                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1529                         };
1530                 };
1531
1532                 scr {
1533                         scr_clk: scr-clk {
1534                                 rockchip,pins =
1535                                         <5 8 RK_FUNC_2 &pcfg_pull_none>;
1536                         };
1537
1538                         scr_io: scr-io {
1539                                 rockchip,pins =
1540                                         <5 9 RK_FUNC_2 &pcfg_pull_up>;
1541                         };
1542
1543                         scr_rst: scr-rst {
1544                                 rockchip,pins =
1545                                         <5 10 RK_FUNC_1 &pcfg_pull_none>;
1546                         };
1547
1548                         scr_detect: scr-detect {
1549                                 rockchip,pins =
1550                                         <5 11 RK_FUNC_1 &pcfg_pull_none>;
1551                         };
1552                 };
1553
1554                 uart0 {
1555                         uart0_xfer: uart0-xfer {
1556                                 rockchip,pins =
1557                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1558                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1559                         };
1560
1561                         uart0_cts: uart0-cts {
1562                                 rockchip,pins =
1563                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1564                         };
1565
1566                         uart0_rts: uart0-rts {
1567                                 rockchip,pins =
1568                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1569                         };
1570                 };
1571
1572                 uart2_t0 {
1573                         uart2_t0_xfer: uart2_t0-xfer {
1574                                 rockchip,pins =
1575                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1576                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1577                         };
1578                         /* no rts / cts for uart2 */
1579                 };
1580
1581                 uart2_t1 {
1582                         uart2_t1_xfer: uart2_t1-xfer {
1583                                 rockchip,pins =
1584                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1585                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1586                         };
1587                         /* no rts / cts for uart2 */
1588                 };
1589
1590                 uart2_t2 {
1591                         uart2_t2_xfer: uart2_t2-xfer {
1592                                 rockchip,pins =
1593                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1594                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1595                         };
1596                         /* no rts / cts for uart2 */
1597                 };
1598
1599                 uart3 {
1600                         uart3_xfer: uart3-xfer {
1601                                 rockchip,pins =
1602                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1603                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1604                         };
1605
1606                         uart3_cts: uart3-cts {
1607                                 rockchip,pins =
1608                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1609                         };
1610
1611                         uart3_rts: uart3-rts {
1612                                 rockchip,pins =
1613                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1614                         };
1615                 };
1616
1617                 pwm0 {
1618                         pwm0_pin: pwm0-pin {
1619                                 rockchip,pins =
1620                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1621                         };
1622                 };
1623
1624                 pwm1 {
1625                         pwm1_pin: pwm1-pin {
1626                                 rockchip,pins =
1627                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1628                         };
1629                 };
1630
1631                 pwm2_t0 {
1632                         pwm2_t0_pin: pwm2_t0-pin {
1633                                 rockchip,pins =
1634                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1635                         };
1636                 };
1637
1638                 pwm2_t1 {
1639                         pwm2_t1_pin: pwm2_t1-pin {
1640                                 rockchip,pins =
1641                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1642                         };
1643                 };
1644
1645                 pwm3_t0 {
1646                         pwm3_t0_pin: pwm3_t0-pin {
1647                                 rockchip,pins =
1648                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1649                         };
1650                 };
1651
1652                 pwm3_t1 {
1653                         pwm3_t1_pin: pwm3_t1-pin {
1654                                 rockchip,pins =
1655                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1656                         };
1657                 };
1658
1659                 pwm3_t2 {
1660                         pwm3_t2_pin: pwm3_t2-pin {
1661                                 rockchip,pins =
1662                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1663                         };
1664                 };
1665
1666                 lcdc {
1667                         lcdc_lcdc: lcdc-lcdc {
1668                                 rockchip,pins =
1669                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1670                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1671                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1672                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1673                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1674                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1675                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1676                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1677                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1678                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1679                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1680                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1681                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1682                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1683                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1684                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1685                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1686                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1687                         };
1688
1689                         lcdc_gpio: lcdc-gpio {
1690                                 rockchip,pins =
1691                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1692                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1693                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1694                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1695                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1696                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1697                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1698                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1699                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1700                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1701                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1702                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1703                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1704                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1705                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1706                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1707                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1708                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1709                         };
1710                 };
1711
1712                 gmac {
1713                         rgmii_pins: rgmii-pins {
1714                                 rockchip,pins =
1715                                         /* mac_rxd3 */
1716                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1717                                         /* mac_rxd2 */
1718                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1719                                         /* mac_txd3 */
1720                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1721                                         /* mac_txd2 */
1722                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1723                                         /* mac_rxd1 */
1724                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1725                                         /* mac_rxd0 */
1726                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1727                                         /* mac_txd1 */
1728                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1729                                         /* mac_txd0 */
1730                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1731                                         /* mac_txclkout */
1732                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1733                                         /* mac_crs */
1734                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1735                                         /* mac_rxclkin */
1736                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1737                                         /* mac_mdio */
1738                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1739                                         /* mac_txen */
1740                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1741                                         /* mac_clk */
1742                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1743                                         /* mac_rxer */
1744                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1745                                         /* mac_rxdv */
1746                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1747                                         /* mac_mdc */
1748                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1749                         };
1750
1751                         rmii_pins: rmii-pins {
1752                                 rockchip,pins =
1753                                         /* mac_rxd1 */
1754                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1755                                         /* mac_rxd0 */
1756                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1757                                         /* mac_txd1 */
1758                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1759                                         /* mac_txd0 */
1760                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1761                                         /* mac_crs */
1762                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1763                                         /* mac_rxclkin */
1764                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1765                                         /* mac_mdio */
1766                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1767                                         /* mac_txen */
1768                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1769                                         /* mac_clk */
1770                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1771                                         /* mac_rxer */
1772                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1773                                         /* mac_rxdv */
1774                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1775                                         /* mac_mdc */
1776                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1777                         };
1778                 };
1779
1780                 eth_phy {
1781                         eth_phy_pwr: eth-phy-pwr {
1782                                 rockchip,pins =
1783                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1784                         };
1785                 };
1786
1787                 tsadc_pin {
1788                         tsadc_gpio: tsadc-gpio {
1789                                 rockchip,pins =
1790                                         <0 22 RK_FUNC_GPIO &pcfg_pull_none>;
1791                         };
1792
1793                         tsadc_int: tsadc-int {
1794                                 rockchip,pins =
1795                                         <0 22 RK_FUNC_2 &pcfg_pull_none>;
1796                         };
1797                 };
1798
1799                 usb2 {
1800                         host_vbus_drv: host-vbus-drv {
1801                                 rockchip,pins =
1802                                         <0 16 RK_FUNC_GPIO &pcfg_pull_none>;
1803                         };
1804                 };
1805
1806         };
1807
1808         gpu: gpu@ffa30000 {
1809                 compatible = "arm,malit764",
1810                              "arm,malit76x",
1811                              "arm,malit7xx",
1812                              "arm,mali-midgard";
1813
1814                 reg = <0x0 0xffa30000 0 0x10000>;
1815
1816                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1817                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1818                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1819                 interrupt-names = "GPU", "MMU", "JOB";
1820
1821                 clocks = <&cru ACLK_GPU>;
1822                 clock-names = "clk_mali";
1823                 #cooling-cells = <2>; /* min followed by max */
1824                 power-domains = <&power RK3366_PD_GPU>;
1825                 operating-points-v2 = <&gpu_opp_table>;
1826                 status = "disabled";
1827
1828                 power_model {
1829                         compatible = "arm,mali-simple-power-model";
1830                         voltage = <900>;
1831                         frequency = <500>;
1832                         static-power = <300>;
1833                         dynamic-power = <1780>;
1834                         ts = <32000 4700 (-80) 2>;
1835                         thermal-zone = "gpu-thermal";
1836                 };
1837         };
1838
1839         gpu_opp_table: gpu_opp_table {
1840                 compatible = "operating-points-v2";
1841                 opp-shared;
1842
1843                 opp-96000000 {
1844                         opp-hz = /bits/ 64 <96000000>;
1845                         opp-microvolt = <1100000>;
1846                 };
1847                 opp-192000000 {
1848                         opp-hz = /bits/ 64 <192000000>;
1849                         opp-microvolt = <1100000>;
1850                 };
1851                 opp-288000000 {
1852                         opp-hz = /bits/ 64 <288000000>;
1853                         opp-microvolt = <1100000>;
1854                 };
1855                 opp-375000000 {
1856                         opp-hz = /bits/ 64 <375000000>;
1857                         opp-microvolt = <1125000>;
1858                 };
1859                 opp-480000000 {
1860                         opp-hz = /bits/ 64 <480000000>;
1861                         opp-microvolt = <1200000>;
1862                 };
1863         };
1864 };