2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3366-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/mipi_dsi.h>
49 #include <dt-bindings/power/rk3366-power.h>
50 #include <dt-bindings/soc/rockchip,boot-mode.h>
51 #include <dt-bindings/thermal/thermal.h>
52 #include <dt-bindings/display/drm_mipi_dsi.h>
53 #include <dt-bindings/display/media-bus-format.h>
56 compatible = "rockchip,rk3366";
57 interrupt-parent = <&gic>;
76 #address-cells = <0x2>;
81 compatible = "arm,cortex-a53","arm,armv8";
83 enable-method = "psci";
84 clocks = <&cru ARMCLK>;
85 operating-points-v2 = <&cpu0_opp_table>;
86 cpu-idle-states = <&cpu_sleep>;
87 #cooling-cells = <2>; /* min followed by max */
88 dynamic-power-coefficient = <166>;
93 compatible = "arm,cortex-a53","arm,armv8";
95 enable-method = "psci";
96 operating-points-v2 = <&cpu0_opp_table>;
97 cpu-idle-states = <&cpu_sleep>;
102 compatible = "arm,cortex-a53","arm,armv8";
104 enable-method = "psci";
105 operating-points-v2 = <&cpu0_opp_table>;
106 cpu-idle-states = <&cpu_sleep>;
111 compatible = "arm,cortex-a53","arm,armv8";
113 enable-method = "psci";
114 operating-points-v2 = <&cpu0_opp_table>;
115 cpu-idle-states = <&cpu_sleep>;
119 entry-method = "psci";
120 cpu_sleep: cpu-sleep-0 {
121 compatible = "arm,idle-state";
123 arm,psci-suspend-param = <0x0010000>;
124 entry-latency-us = <350>;
125 exit-latency-us = <600>;
126 min-residency-us = <1150>;
131 cpu0_opp_table: opp_table0 {
132 compatible = "operating-points-v2";
135 nvmem-cells = <&cpu_leakage>;
136 nvmem-cell-names = "cpu_leakage";
139 opp-hz = /bits/ 64 <408000000>;
140 opp-microvolt = <950000>;
141 clock-latency-ns = <40000>;
145 opp-hz = /bits/ 64 <600000000>;
146 opp-microvolt = <950000>;
149 opp-hz = /bits/ 64 <816000000>;
150 opp-microvolt = <1000000>;
153 opp-hz = /bits/ 64 <1008000000>;
154 opp-microvolt = <1075000>;
157 opp-hz = /bits/ 64 <1200000000>;
158 opp-microvolt = <1175000>;
161 opp-hz = /bits/ 64 <1296000000>;
162 opp-microvolt = <1250000>;
167 compatible = "arm,psci-1.0";
172 compatible = "arm,armv8-timer";
173 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
174 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
175 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
176 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
180 compatible = "arm,cortex-a53-pmu";
181 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-affinity = <&cpu0>,
192 compatible = "fixed-clock";
194 clock-frequency = <24000000>;
195 clock-output-names = "xin24m";
198 gic: interrupt-controller@ffb71000 {
199 compatible = "arm,gic-400";
200 interrupt-controller;
201 #interrupt-cells = <3>;
202 #address-cells = <0>;
204 reg = <0x0 0xffb71000 0x0 0x1000>,
205 <0x0 0xffb72000 0x0 0x1000>,
206 <0x0 0xffb74000 0x0 0x2000>,
207 <0x0 0xffb76000 0x0 0x2000>;
208 interrupts = <GIC_PPI 9
209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
212 nandc0: nandc@ff0c0000 {
213 compatible = "rockchip,rk-nandc";
214 reg = <0x0 0xff0c0000 0x0 0x4000>;
215 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
218 clock-names = "clk_nandc", "hclk_nandc";
222 saradc: saradc@ff100000 {
223 compatible = "rockchip,saradc";
224 reg = <0x0 0xff100000 0x0 0x100>;
225 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
226 #io-channel-cells = <1>;
227 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
228 clock-names = "saradc", "apb_pclk";
233 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
234 reg = <0x0 0xff110000 0x0 0x1000>;
235 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
236 clock-names = "spiclk", "apb_pclk";
237 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
240 #address-cells = <1>;
246 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
247 reg = <0x0 0xff120000 0x0 0x1000>;
248 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
249 clock-names = "spiclk", "apb_pclk";
250 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
253 #address-cells = <1>;
258 scr: rkscr@ff1d0000 {
259 compatible = "rockchip-scr";
260 reg = <0x0 0xff1d0000 0x0 0x10000>;
261 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
262 #address-cells = <1>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
266 clocks = <&cru PCLK_SIM>;
267 clock-names = "g_pclk_sim_card";
272 soc_thermal: soc-thermal {
273 polling-delay-passive = <100>; /* milliseconds */
274 polling-delay = <1000>; /* milliseconds */
275 sustainable-power = <1600>; /* milliwatts */
277 thermal-sensors = <&tsadc 0>;
280 threshold: trip-point@0 {
281 temperature = <70000>; /* millicelsius */
282 hysteresis = <2000>; /* millicelsius */
285 target: trip-point@1 {
286 temperature = <85000>; /* millicelsius */
287 hysteresis = <2000>; /* millicelsius */
291 temperature = <95000>; /* millicelsius */
292 hysteresis = <2000>; /* millicelsius */
301 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
306 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
311 gpu_thermal: gpu-thermal {
312 polling-delay-passive = <100>; /* milliseconds */
313 polling-delay = <1000>; /* milliseconds */
315 thermal-sensors = <&tsadc 1>;
319 tsadc: tsadc@ff260000 {
320 compatible = "rockchip,rk3366-tsadc";
321 reg = <0x0 0xff260000 0x0 0x100>;
322 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
324 clock-names = "tsadc", "apb_pclk";
325 resets = <&cru SRST_TSADC>;
326 reset-names = "tsadc-apb";
327 pinctrl-names = "default";
328 pinctrl-0 = <&tsadc_gpio>;
329 #thermal-sensor-cells = <1>;
330 rockchip,hw-tshut-temp = <95000>;
334 sdmmc: dwmmc@ff400000 {
335 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
336 clock-freq-min-max = <400000 150000000>;
337 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
338 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
339 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
340 fifo-depth = <0x100>;
341 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
342 reg = <0x0 0xff400000 0x0 0x4000>;
346 sdio: dwmmc@ff410000 {
347 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
348 clock-freq-min-max = <400000 150000000>;
349 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
350 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
351 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
352 fifo-depth = <0x100>;
353 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
354 reg = <0x0 0xff410000 0x0 0x4000>;
358 emmc: dwmmc@ff420000 {
359 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
360 clock-freq-min-max = <400000 150000000>;
361 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
362 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
363 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
364 fifo-depth = <0x100>;
365 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
366 reg = <0x0 0xff420000 0x0 0x4000>;
371 compatible = "rockchip,rk3366-gmac";
372 reg = <0x0 0xff440000 0x0 0x10000>;
373 rockchip,grf = <&grf>;
374 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
375 interrupt-names = "macirq";
376 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
377 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
378 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
380 clock-names = "stmmaceth", "mac_clk_rx",
381 "mac_clk_tx", "clk_mac_ref",
382 "clk_mac_refout", "aclk_mac",
384 resets = <&cru SRST_MAC>;
385 reset-names = "stmmaceth";
390 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
391 reg = <0x0 0xff728000 0x0 0x1000>;
392 clocks = <&cru PCLK_I2C0>;
394 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&i2c0_xfer>;
397 #address-cells = <1>;
403 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
404 reg = <0x0 0xff140000 0x0 0x1000>;
405 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
406 #address-cells = <1>;
409 clocks = <&cru PCLK_I2C2>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&i2c2_xfer>;
416 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
417 reg = <0x0 0xff150000 0x0 0x1000>;
418 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
419 #address-cells = <1>;
422 clocks = <&cru PCLK_I2C3>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&i2c3_xfer>;
429 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
430 reg = <0x0 0xff160000 0x0 0x1000>;
431 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
432 #address-cells = <1>;
435 clocks = <&cru PCLK_I2C4>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&i2c4_xfer>;
442 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
443 reg = <0x0 0xff170000 0x0 0x1000>;
444 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
445 #address-cells = <1>;
448 clocks = <&cru PCLK_I2C5>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&i2c5_xfer>;
454 uart0: serial@ff180000 {
455 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
456 reg = <0x0 0xff180000 0x0 0x100>;
457 clock-frequency = <24000000>;
458 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
459 clock-names = "baudclk", "apb_pclk";
460 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
468 uart3: serial@ff1b0000 {
469 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
470 reg = <0x0 0xff1b0000 0x0 0x100>;
471 clock-frequency = <24000000>;
472 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
473 clock-names = "baudclk", "apb_pclk";
474 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
482 usb_host0_ehci: usb@ff480000 {
483 compatible = "generic-ehci";
484 reg = <0x0 0xff480000 0x0 0x20000>;
485 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
487 clock-names = "usbphy_480m", "hclk_host0";
488 phys = <&u2phy_host>;
493 usb_host0_ohci: usb@ff4a0000 {
494 compatible = "generic-ohci";
495 reg = <0x0 0xff4a0000 0x0 0x20000>;
496 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
498 clock-names = "usbphy_480m", "hclk_host0";
499 phys = <&u2phy_host>;
504 usb_otg: usb@ff4c0000 {
505 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
507 reg = <0x0 0xff4c0000 0x0 0x40000>;
508 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&cru HCLK_OTG>;
512 g-np-tx-fifo-size = <16>;
513 g-rx-fifo-size = <275>;
514 g-tx-fifo-size = <256 128 128 64 64 32>;
520 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
521 reg = <0x0 0xff660000 0x0 0x1000>;
522 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
523 #address-cells = <1>;
526 clocks = <&cru PCLK_I2C1>;
527 pinctrl-names = "default";
528 pinctrl-0 = <&i2c1_xfer>;
532 efuse: efuse@ff670000 {
533 compatible = "rockchip,rk3366-efuse";
534 reg = <0x0 0xff670000 0x0 0x20>;
535 #address-cells = <1>;
537 clocks = <&cru PCLK_EFUSE_256>;
538 clock-names = "pclk_efuse";
541 cpu_leakage: cpu-leakage {
544 gpu_leakage: gpu-leakage {
547 logic_leakage: logic-leakage {
550 wafer_info: wafer-info {
556 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
557 reg = <0x0 0xff680000 0x0 0x10>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&pwm0_pin>;
561 clocks = <&cru PCLK_RKPWM>;
567 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
568 reg = <0x0 0xff680010 0x0 0x10>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&pwm1_pin>;
572 clocks = <&cru PCLK_RKPWM>;
578 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
579 reg = <0x0 0xff680020 0x0 0x10>;
581 clocks = <&cru PCLK_RKPWM>;
587 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
588 reg = <0x0 0xff680030 0x0 0x10>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&pwm3_t2_pin>;
592 clocks = <&cru PCLK_RKPWM>;
597 uart2: serial@ff690000 {
598 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
599 reg = <0x0 0xff690000 0x0 0x100>;
600 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
602 clock-names = "baudclk", "apb_pclk";
605 pinctrl-names = "default";
606 pinctrl-0 = <&uart2_t1_xfer>;
610 pmu: power-management@ff730000 {
611 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
612 reg = <0x0 0xff730000 0x0 0x1000>;
614 power: power-controller {
615 compatible = "rockchip,rk3366-power-controller";
616 #power-domain-cells = <1>;
617 #address-cells = <1>;
621 * Note: Although SCLK_* are the working clocks
622 * of device without including on the NOC, needed for
625 * The clocks on the which NOC:
626 * ACLK_IEP/ACLK_VOP_FULL are on ACLK_VIO0_NOC.
627 * ACLK_RGA/ACLK_VOP_LITE are on ACLK_VIO1_NOC.
628 * ACLK_ISP is on ACLK_ISP_NOC.
629 * ACLK_HDCP is on ACLK_HDCP_NOC.
630 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NOC.
632 * Which clock are device clocks:
634 * *_IEP IEP:Image Enhancement Processor
635 * *_ISP ISP:Image Signal Processing
636 * *_VOP* VOP:Visual Output Processor
642 pd_vio@RK3366_PD_VIO {
643 reg = <RK3366_PD_VIO>;
644 clocks = <&cru ACLK_IEP>,
648 <&cru ACLK_VOP_FULL>,
649 <&cru ACLK_VOP_LITE>,
651 <&cru DCLK_VOP_FULL>,
652 <&cru DCLK_VOP_LITE>,
656 <&cru HCLK_VOP_FULL>,
657 <&cru HCLK_VOP_LITE>,
658 <&cru HCLK_VIO_HDCPMMU>,
660 <&cru PCLK_HDMI_CTRL>,
662 <&cru PCLK_MIPI_DSI0>,
663 <&cru SCLK_VOP_FULL_PWM>,
667 <&cru SCLK_HDMI_CEC>,
668 <&cru SCLK_HDMI_HDCP>;
672 * Note: ACLK_VCODEC/HCLK_VCODEC are VPU clocks
673 * that on the ACLK_VCODEC_NOC and
676 pd_vpu@RK3366_PD_VPU {
677 reg = <RK3366_PD_VPU>;
678 clocks = <&cru ACLK_VIDEO>,
683 * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
684 * clocks that on the ACLK_RKVDEC_NOC and
687 pd_rkvdec@RK3366_PD_RKVDEC {
688 reg = <RK3366_PD_RKVDEC>;
689 clocks = <&cru ACLK_RKVDEC>,
691 <&cru SCLK_HEVC_CABAC>,
692 <&cru SCLK_HEVC_CORE>;
696 * Note: ACLK_GPU is the GPU clock
697 * that on the ACLK_GPU_NOC.
699 pd_gpu@RK3366_PD_GPU {
700 reg = <RK3366_PD_GPU>;
701 clocks = <&cru ACLK_GPU>;
706 pmugrf: syscon@ff738000 {
707 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
708 reg = <0x0 0xff738000 0x0 0x1000>;
711 compatible = "syscon-reboot-mode";
713 mode-normal = <BOOT_NORMAL>;
714 mode-recovery = <BOOT_RECOVERY>;
715 mode-fastboot = <BOOT_FASTBOOT>;
716 mode-loader = <BOOT_BL_DOWNLOAD>;
720 compatible = "rockchip,rk3366-pmu-pvtm";
721 clocks = <&cru SCLK_PVTM_PMU>;
728 compatible = "arm,amba-bus";
729 #address-cells = <2>;
733 dmac_peri: dma-controller@ff250000 {
734 compatible = "arm,pl330", "arm,primecell";
735 reg = <0x0 0xff250000 0x0 0x4000>;
736 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&cru ACLK_DMAC_PERI>;
740 clock-names = "apb_pclk";
741 peripherals-req-type-burst;
744 dmac_bus: dma-controller@ff600000 {
745 compatible = "arm,pl330", "arm,primecell";
746 reg = <0x0 0xff600000 0x0 0x4000>;
747 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&cru ACLK_DMAC_BUS>;
751 clock-names = "apb_pclk";
752 peripherals-req-type-burst;
756 cru: clock-controller@ff760000 {
757 compatible = "rockchip,rk3366-cru";
758 reg = <0x0 0xff760000 0x0 0x1000>;
759 rockchip,grf = <&grf>;
763 <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
764 <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
765 <&cru SCLK_I2S_8CH_SRC>, <&cru SCLK_I2S_2CH_SRC>,
766 <&cru SCLK_SPDIF_8CH_SRC>,
767 <&cru PLL_CPLL>, <&cru PLL_GPLL>,
768 <&cru PLL_NPLL>, <&cru PLL_MPLL>,
769 <&cru PLL_WPLL>, <&cru PLL_BPLL>,
770 <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
771 <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
772 <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
774 assigned-clock-rates =
779 <750000000>, <576000000>,
780 <594000000>, <594000000>,
781 <960000000>, <520000000>,
782 <375000000>, <288000000>,
783 <100000000>, <100000000>,
784 <288000000>, <288000000>,
786 assigned-clock-parents =
787 <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
788 <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>,
789 <&cru PLL_GPLL>, <&cru PLL_GPLL>,
793 grf: syscon@ff770000 {
794 compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd";
795 reg = <0x0 0xff770000 0x0 0x1000>;
796 #address-cells = <1>;
799 u2phy: usb2-phy@700 {
800 compatible = "rockchip,rk3366-usb2phy";
802 clocks = <&cru SCLK_OTG_PHY0>;
803 clock-names = "phyclk";
805 clock-output-names = "sclk_otgphy0_480m";
807 u2phy_host: host-port {
809 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
810 interrupt-names = "linestate";
816 compatible = "rockchip,rk3366-pvtm";
817 clocks = <&cru SCLK_PVTM_CORE>, <&cru SCLK_PVTM_GPU>;
818 clock-names = "core", "gpu";
823 wdt: watchdog@ff800000 {
824 compatible = "snps,dw-wdt";
825 reg = <0x0 0xff800000 0x0 0x100>;
826 clocks = <&cru PCLK_WDT>;
827 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
831 rktimer: rktimer@ff810000 {
832 compatible = "rockchip,rk3288-timer";
833 reg = <0x0 0xff810000 0x0 0x1000>;
834 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
835 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER0>;
836 clock-names = "pclk", "timer";
839 spdif: spdif@ff880000 {
840 compatible = "rockchip,rk3366-spdif";
841 reg = <0x0 0xff880000 0x0 0x1000>;
842 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
843 dmas = <&dmac_bus 3>;
845 clock-names = "mclk", "hclk";
846 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
847 pinctrl-names = "default";
848 pinctrl-0 = <&spdif_bus>;
852 i2s_2ch: i2s-2ch@ff890000 {
853 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
854 reg = <0x0 0xff890000 0x0 0x1000>;
855 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
856 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
857 dma-names = "tx", "rx";
858 clock-names = "i2s_clk", "i2s_hclk";
859 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
863 i2s_8ch: i2s-8ch@ff898000 {
864 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
865 reg = <0x0 0xff898000 0x0 0x1000>;
866 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
867 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
868 dma-names = "tx", "rx";
869 clock-names = "i2s_clk", "i2s_hclk";
870 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
871 pinctrl-names = "default";
872 pinctrl-0 = <&i2s_8ch_bus>;
876 display_subsystem: display-subsystem {
877 compatible = "rockchip,display-subsystem";
878 ports = <&vopb_out>, <&vopl_out>;
883 compatible = "rockchip,rk3366-vop-lit";
884 reg = <0x0 0xff8f0000 0x0 0x900>;
885 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>,
887 <&cru HCLK_VOP_LITE>;
888 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
889 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>,
890 <&cru SRST_VOP1_AHB>;
891 reset-names = "axi", "ahb", "dclk";
892 power-domains = <&power RK3366_PD_VIO>;
893 iommus = <&vopl_mmu>;
897 #address-cells = <1>;
900 vopl_out_dsi: endpoint@0 {
902 remote-endpoint = <&dsi_in_vopl>;
905 vopl_out_lvds: endpoint@1 {
907 remote-endpoint = <&lvds_in_vopl>;
912 vopl_mmu: iommu@ff8f0f00 {
913 compatible = "rockchip,iommu";
914 reg = <0x0 0xff8f0f00 0x0 0x100>;
915 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>;
916 interrupt-names = "vopl_mmu";
917 clocks = <&cru ACLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
918 clock-names = "aclk", "hclk";
919 power-domains = <&power RK3366_PD_VIO>;
925 compatible = "rockchip,iep";
928 reg = <0x0 0xff900000 0x0 0x800>;
929 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
930 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
931 clock-names = "aclk_iep", "hclk_iep";
932 power-domains = <&power RK3366_PD_VIO>;
938 iep_mmu: iommu@ff900800 {
939 compatible = "rockchip,iommu";
940 reg = <0x0 0xff900800 0x0 0x100>;
941 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
942 interrupt-names = "iep_mmu";
943 power-domains = <&power RK3366_PD_VIO>;
949 compatible = "rockchip,rga2";
951 reg = <0x0 0xff920000 0x0 0x1000>;
952 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
953 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
954 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
955 power-domains = <&power RK3366_PD_VIO>;
960 compatible = "rockchip,rk3366-vop";
961 reg = <0x0 0xff930000 0x0 0x1ffc>;
962 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>,
964 <&cru HCLK_VOP_FULL>;
965 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
966 power-domains = <&power RK3366_PD_VIO>;
967 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>,
968 <&cru SRST_VOP0_AHB>;
969 reset-names = "axi", "ahb", "dclk";
970 iommus = <&vopb_mmu>;
974 #address-cells = <1>;
977 vopb_out_dsi: endpoint@0 {
979 remote-endpoint = <&dsi_in_vopb>;
982 vopb_out_lvds: endpoint@1 {
984 remote-endpoint = <&lvds_in_vopb>;
987 vopb_out_hdmi: endpoint@2 {
989 remote-endpoint = <&hdmi_in_vopb>;
994 vopb_mmu: iommu@ff932400 {
995 compatible = "rockchip,iommu";
996 reg = <0x0 0xff932400 0x0 0x100>;
997 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
998 interrupt-names = "vop_mmu";
999 clocks = <&cru ACLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
1000 clock-names = "aclk", "hclk";
1001 power-domains = <&power RK3366_PD_VIO>;
1003 status = "disabled";
1007 compatible = "rockchip,rk3366-mipi-dsi";
1008 reg = <0x0 0xff960000 0x0 0x4000>;
1009 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&cru PCLK_MIPI_DSI0>;
1011 clock-names = "pclk";
1012 resets = <&cru SRST_MIPIDSI0>;
1013 reset-names = "apb";
1014 phys = <&mipi_dphy>;
1015 phy-names = "mipi_dphy";
1016 power-domains = <&power RK3366_PD_VIO>;
1017 rockchip,grf = <&grf>;
1018 #address-cells = <1>;
1020 status = "disabled";
1024 #address-cells = <1>;
1027 dsi_in_vopb: endpoint@0 {
1029 remote-endpoint = <&vopb_out_dsi>;
1031 dsi_in_vopl: endpoint@1 {
1033 remote-endpoint = <&vopl_out_dsi>;
1039 mipi_dphy: mipi-dphy@ff968000 {
1040 compatible = "rockchip,rk3366-mipi-dphy";
1041 reg = <0x0 0xff968000 0x0 0x4000>;
1042 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>;
1043 clock-names = "ref", "pclk";
1044 resets = <&cru SRST_MIPIDPHYTX>;
1045 reset-names = "apb";
1047 status = "disabled";
1050 lvds: lvds@ff968000 {
1051 compatible = "rockchip,rk3366-lvds";
1052 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1053 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1054 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
1055 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1056 power-domains = <&power RK3366_PD_VIO>;
1057 pinctrl-names = "lcdc", "gpio";
1058 pinctrl-0 = <&lcdc_lcdc>;
1059 pinctrl-1 = <&lcdc_gpio>;
1060 rockchip,grf = <&grf>;
1061 status = "disabled";
1064 #address-cells = <1>;
1069 #address-cells = <1>;
1072 lvds_in_vopb: endpoint@0 {
1074 remote-endpoint = <&vopb_out_lvds>;
1076 lvds_in_vopl: endpoint@1 {
1078 remote-endpoint = <&vopl_out_lvds>;
1085 hdmi: hdmi@ff980000 {
1086 compatible = "rockchip,rk3366-dw-hdmi";
1087 reg = <0x0 0xff980000 0x0 0x20000>;
1089 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1090 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>,
1092 <&cru SCLK_HDMI_CEC>, <&cru DCLK_HDMIPHY>;
1093 clock-names = "iahb", "isfr", "cec", "dclk";
1094 pinctrl-names = "default";
1095 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1096 resets = <&cru SRST_HDMI>;
1097 reset-names = "hdmi";
1098 //power-domains = <&power RK3366_PD_VIO>;
1099 rockchip,grf = <&grf>;
1100 status = "disabled";
1104 #address-cells = <1>;
1107 hdmi_in_vopb: endpoint@0 {
1109 remote-endpoint = <&vopb_out_hdmi>;
1115 vpu: vpu_service@ff9a0000 {
1116 compatible = "rockchip,vpu_service";
1117 rockchip,grf = <&grf>;
1118 iommu_enabled = <1>;
1119 iommus = <&vpu_mmu>;
1120 reg = <0x0 0xff9a0000 0x0 0x800>;
1121 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1122 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1123 interrupt-names = "irq_dec", "irq_enc";
1124 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1125 clock-names = "aclk_vcodec", "hclk_vcodec";
1126 power-domains = <&power RK3366_PD_VPU>;
1127 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
1128 reset-names = "video_h", "video_a";
1129 name = "vpu_service";
1131 /* 0 means ion, 1 means drm */
1133 status = "disabled";
1136 vpu_mmu: iommu@ff9a0800 {
1137 compatible = "rockchip,iommu";
1138 reg = <0x0 0xff9a0800 0x0 0x100>;
1139 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1140 interrupt-names = "vpu_mmu";
1141 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1142 clock-names = "aclk", "hclk";
1143 power-domains = <&power RK3366_PD_VPU>;
1145 status = "disabled";
1148 rkvdec: rkvdec@ff9b0000 {
1149 compatible = "rockchip,rkvdec";
1150 rockchip,grf = <&grf>;
1151 iommus = <&vdec_mmu>;
1152 iommu_enabled = <1>;
1153 reg = <0x0 0xff9b0000 0x0 0x400>;
1154 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1155 interrupt-names = "irq_dec";
1156 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
1157 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
1158 power-domains = <&power RK3366_PD_RKVDEC>;
1159 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
1160 reset-names = "video_h", "video_a";
1163 /* 0 means ion, 1 means drm */
1165 status = "disabled";
1168 vdec_mmu: iommu@ff9b0480 {
1169 compatible = "rockchip,iommu";
1170 reg = <0x0 0xff9b0480 0x0 0x40>,
1171 <0x0 0xff9b04c0 0x0 0x40>;
1172 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1173 interrupt-names = "vdec_mmu";
1174 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
1175 clock-names = "aclk", "hclk";
1176 power-domains = <&power RK3366_PD_RKVDEC>;
1178 status = "disabled";
1182 compatible = "rockchip,rk3366-pinctrl";
1183 rockchip,grf = <&grf>;
1184 rockchip,pmu = <&pmugrf>;
1185 #address-cells = <0x2>;
1186 #size-cells = <0x2>;
1189 gpio0: gpio0@ff750000 {
1190 compatible = "rockchip,gpio-bank";
1191 reg = <0x0 0xff750000 0x0 0x100>;
1192 clocks = <&cru PCLK_GPIO0>;
1193 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1196 #gpio-cells = <0x2>;
1198 interrupt-controller;
1199 #interrupt-cells = <0x2>;
1202 gpio1: gpio1@ff780000 {
1203 compatible = "rockchip,gpio-bank";
1204 reg = <0x0 0xff758000 0x0 0x100>;
1205 clocks = <&cru PCLK_GPIO1>;
1206 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1209 #gpio-cells = <0x2>;
1211 interrupt-controller;
1212 #interrupt-cells = <0x2>;
1215 gpio2: gpio2@ff790000 {
1216 compatible = "rockchip,gpio-bank";
1217 reg = <0x0 0xff790000 0x0 0x100>;
1218 clocks = <&cru PCLK_GPIO2>;
1219 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1222 #gpio-cells = <0x2>;
1224 interrupt-controller;
1225 #interrupt-cells = <0x2>;
1228 gpio3: gpio3@ff7a0000 {
1229 compatible = "rockchip,gpio-bank";
1230 reg = <0x0 0xff7a0000 0x0 0x100>;
1231 clocks = <&cru PCLK_GPIO3>;
1232 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1235 #gpio-cells = <0x2>;
1237 interrupt-controller;
1238 #interrupt-cells = <0x2>;
1241 gpio4: gpio4@ff7b0000 {
1242 compatible = "rockchip,gpio-bank";
1243 reg = <0x0 0xff7b0000 0x0 0x100>;
1244 clocks = <&cru PCLK_GPIO4>;
1245 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1248 #gpio-cells = <0x2>;
1250 interrupt-controller;
1251 #interrupt-cells = <0x2>;
1254 gpio5: gpio5@ff7c0000 {
1255 compatible = "rockchip,gpio-bank";
1256 reg = <0x0 0xff7c0000 0x0 0x100>;
1257 clocks = <&cru PCLK_GPIO5>;
1258 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1261 #gpio-cells = <0x2>;
1263 interrupt-controller;
1264 #interrupt-cells = <0x2>;
1267 pcfg_pull_up: pcfg-pull-up {
1271 pcfg_pull_down: pcfg-pull-down {
1275 pcfg_pull_none: pcfg-pull-none {
1279 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1281 drive-strength = <12>;
1285 emmc_clk: emmc-clk {
1287 <3 4 RK_FUNC_2 &pcfg_pull_none>;
1290 emmc_cmd: emmc-cmd {
1292 <2 26 RK_FUNC_2 &pcfg_pull_up>;
1295 emmc_pwr: emmc-pwr {
1297 <2 27 RK_FUNC_2 &pcfg_pull_up>;
1300 emmc_bus1: emmc-bus1 {
1302 <2 18 RK_FUNC_2 &pcfg_pull_up>;
1305 emmc_bus4: emmc-bus4 {
1307 <2 18 RK_FUNC_2 &pcfg_pull_up>,
1308 <2 19 RK_FUNC_2 &pcfg_pull_up>,
1309 <2 20 RK_FUNC_2 &pcfg_pull_up>,
1310 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1313 emmc_bus8: emmc-bus8 {
1315 <2 18 RK_FUNC_2 &pcfg_pull_up>,
1316 <2 19 RK_FUNC_2 &pcfg_pull_up>,
1317 <2 20 RK_FUNC_2 &pcfg_pull_up>,
1318 <2 21 RK_FUNC_2 &pcfg_pull_up>,
1319 <2 22 RK_FUNC_2 &pcfg_pull_up>,
1320 <2 23 RK_FUNC_2 &pcfg_pull_up>,
1321 <2 24 RK_FUNC_2 &pcfg_pull_up>,
1322 <2 25 RK_FUNC_2 &pcfg_pull_up>;
1327 sdmmc_cd: sdmmc-cd {
1328 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1331 sdmmc_bus1: sdmmc-bus1 {
1332 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1335 sdmmc_bus4: sdmmc-bus4 {
1336 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1337 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1338 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1339 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1342 sdmmc_clk: sdmmc-clk {
1343 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1346 sdmmc_cmd: sdmmc-cmd {
1347 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1352 sdio_bus1: sdio-bus1 {
1353 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1356 sdio_bus4: sdio-bus4 {
1357 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1358 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1359 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1360 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1363 sdio_cmd: sdio-cmd {
1364 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1367 sdio_clk: sdio-clk {
1368 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1372 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1376 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1379 sdio_int: sdio-int {
1380 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1383 sdio_pwr: sdio-pwr {
1384 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1389 hdmii2c_xfer: hdmii2c-xfer {
1391 <5 13 RK_FUNC_2 &pcfg_pull_none>,
1392 <5 14 RK_FUNC_2 &pcfg_pull_none>;
1397 hdmi_cec: hdmi-cec {
1399 <5 12 RK_FUNC_1 &pcfg_pull_none>;
1404 i2c0_xfer: i2c0-xfer {
1406 <0 3 RK_FUNC_1 &pcfg_pull_none>,
1407 <0 4 RK_FUNC_1 &pcfg_pull_none>;
1412 i2c1_xfer: i2c1-xfer {
1414 <4 25 RK_FUNC_1 &pcfg_pull_none>,
1415 <4 26 RK_FUNC_1 &pcfg_pull_none>;
1420 i2c2_xfer: i2c2-xfer {
1422 <5 15 RK_FUNC_2 &pcfg_pull_none>,
1423 <5 16 RK_FUNC_2 &pcfg_pull_none>;
1426 i2c2_gpio: i2c2-gpio {
1428 <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1429 <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1434 i2c3_xfer: i2c3-xfer {
1436 <2 16 RK_FUNC_2 &pcfg_pull_none>,
1437 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1442 i2c4_xfer: i2c4-xfer {
1444 <5 8 RK_FUNC_1 &pcfg_pull_none>,
1445 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1448 i2c4_gpio: i2c4-gpio {
1450 <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1451 <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1456 i2c5_xfer: i2c5-xfer {
1458 <5 13 RK_FUNC_1 &pcfg_pull_none>,
1459 <5 14 RK_FUNC_1 &pcfg_pull_none>;
1461 i2c5_gpio: i2c5-gpio {
1463 <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1464 <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1469 i2s_8ch_bus: i2s-8ch-bus {
1471 <4 16 RK_FUNC_1 &pcfg_pull_none>,
1472 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1473 <4 18 RK_FUNC_1 &pcfg_pull_none>,
1474 <4 19 RK_FUNC_1 &pcfg_pull_none>,
1475 <4 20 RK_FUNC_1 &pcfg_pull_none>,
1476 <4 21 RK_FUNC_1 &pcfg_pull_none>,
1477 <4 22 RK_FUNC_1 &pcfg_pull_none>,
1478 <4 23 RK_FUNC_1 &pcfg_pull_none>,
1479 <4 24 RK_FUNC_1 &pcfg_pull_none>;
1484 spdif_bus: spdif-bus {
1486 <5 19 RK_FUNC_1 &pcfg_pull_none>;
1491 spi0_clk: spi0-clk {
1493 <2 29 RK_FUNC_2 &pcfg_pull_up>;
1495 spi0_cs0: spi0-cs0 {
1497 <2 24 RK_FUNC_3 &pcfg_pull_up>;
1499 spi0_cs1: spi0-cs1 {
1501 <2 25 RK_FUNC_3 &pcfg_pull_up>;
1505 <2 23 RK_FUNC_3 &pcfg_pull_up>;
1509 <2 22 RK_FUNC_3 &pcfg_pull_up>;
1514 spi1_clk: spi1-clk {
1516 <2 4 RK_FUNC_3 &pcfg_pull_up>;
1518 spi1_cs0: spi1-cs0 {
1520 <2 5 RK_FUNC_3 &pcfg_pull_up>;
1524 <2 6 RK_FUNC_3 &pcfg_pull_up>;
1528 <2 7 RK_FUNC_3 &pcfg_pull_up>;
1535 <5 8 RK_FUNC_2 &pcfg_pull_none>;
1540 <5 9 RK_FUNC_2 &pcfg_pull_up>;
1545 <5 10 RK_FUNC_1 &pcfg_pull_none>;
1548 scr_detect: scr-detect {
1550 <5 11 RK_FUNC_1 &pcfg_pull_none>;
1555 uart0_xfer: uart0-xfer {
1557 <3 8 RK_FUNC_1 &pcfg_pull_up>,
1558 <3 9 RK_FUNC_1 &pcfg_pull_none>;
1561 uart0_cts: uart0-cts {
1563 <3 10 RK_FUNC_1 &pcfg_pull_none>;
1566 uart0_rts: uart0-rts {
1568 <3 11 RK_FUNC_1 &pcfg_pull_none>;
1573 uart2_t0_xfer: uart2_t0-xfer {
1575 <0 22 RK_FUNC_1 &pcfg_pull_up>,
1576 <0 21 RK_FUNC_1 &pcfg_pull_none>;
1578 /* no rts / cts for uart2 */
1582 uart2_t1_xfer: uart2_t1-xfer {
1584 <5 0 RK_FUNC_2 &pcfg_pull_up>,
1585 <5 1 RK_FUNC_2 &pcfg_pull_none>;
1587 /* no rts / cts for uart2 */
1591 uart2_t2_xfer: uart2_t2-xfer {
1593 <5 14 RK_FUNC_3 &pcfg_pull_up>,
1594 <5 13 RK_FUNC_3 &pcfg_pull_none>;
1596 /* no rts / cts for uart2 */
1600 uart3_xfer: uart3-xfer {
1602 <5 15 RK_FUNC_1 &pcfg_pull_up>,
1603 <5 16 RK_FUNC_1 &pcfg_pull_none>;
1606 uart3_cts: uart3-cts {
1608 <5 17 RK_FUNC_1 &pcfg_pull_none>;
1611 uart3_rts: uart3-rts {
1613 <5 18 RK_FUNC_1 &pcfg_pull_none>;
1618 pwm0_pin: pwm0-pin {
1620 <0 8 RK_FUNC_1 &pcfg_pull_none>;
1625 pwm1_pin: pwm1-pin {
1627 <1 6 RK_FUNC_2 &pcfg_pull_none>;
1632 pwm2_t0_pin: pwm2_t0-pin {
1634 <2 15 RK_FUNC_3 &pcfg_pull_none>;
1639 pwm2_t1_pin: pwm2_t1-pin {
1641 <5 17 RK_FUNC_2 &pcfg_pull_none>;
1646 pwm3_t0_pin: pwm3_t0-pin {
1648 <1 0 RK_FUNC_2 &pcfg_pull_none>;
1653 pwm3_t1_pin: pwm3_t1-pin {
1655 <0 21 RK_FUNC_2 &pcfg_pull_none>;
1660 pwm3_t2_pin: pwm3_t2-pin {
1662 <5 18 RK_FUNC_2 &pcfg_pull_none>;
1667 lcdc_lcdc: lcdc-lcdc {
1669 <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1670 <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1671 <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1672 <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1673 <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1674 <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1675 <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1676 <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1677 <1 0 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1678 <1 1 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1679 <1 2 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1680 <1 3 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1681 <1 4 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1682 <1 5 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1683 <1 6 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1684 <1 7 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1685 <1 8 RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1686 <1 9 RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1689 lcdc_gpio: lcdc-gpio {
1691 <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1692 <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1693 <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1694 <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1695 <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1696 <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1697 <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1698 <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1699 <1 0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1700 <1 1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1701 <1 2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1702 <1 3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1703 <1 4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1704 <1 5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1705 <1 6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1706 <1 7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1707 <1 8 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1708 <1 9 RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1713 rgmii_pins: rgmii-pins {
1716 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1718 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1720 <2 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1722 <2 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1724 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1726 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1728 <2 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1730 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1732 <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1734 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1736 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1738 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1740 <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1742 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1744 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1746 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1748 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1751 rmii_pins: rmii-pins {
1754 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1756 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1758 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1760 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1762 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1764 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1766 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1768 <2 12 RK_FUNC_1 &pcfg_pull_none>,
1770 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1772 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1774 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1776 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1781 eth_phy_pwr: eth-phy-pwr {
1783 <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1788 tsadc_gpio: tsadc-gpio {
1790 <0 22 RK_FUNC_GPIO &pcfg_pull_none>;
1793 tsadc_int: tsadc-int {
1795 <0 22 RK_FUNC_2 &pcfg_pull_none>;
1800 host_vbus_drv: host-vbus-drv {
1802 <0 16 RK_FUNC_GPIO &pcfg_pull_none>;
1809 compatible = "arm,malit764",
1814 reg = <0x0 0xffa30000 0 0x10000>;
1816 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1817 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1818 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1819 interrupt-names = "GPU", "MMU", "JOB";
1821 clocks = <&cru ACLK_GPU>;
1822 clock-names = "clk_mali";
1823 #cooling-cells = <2>; /* min followed by max */
1824 power-domains = <&power RK3366_PD_GPU>;
1825 operating-points-v2 = <&gpu_opp_table>;
1826 status = "disabled";
1829 compatible = "arm,mali-simple-power-model";
1832 static-power = <300>;
1833 dynamic-power = <1780>;
1834 ts = <32000 4700 (-80) 2>;
1835 thermal-zone = "gpu-thermal";
1839 gpu_opp_table: gpu_opp_table {
1840 compatible = "operating-points-v2";
1844 opp-hz = /bits/ 64 <96000000>;
1845 opp-microvolt = <1100000>;
1848 opp-hz = /bits/ 64 <192000000>;
1849 opp-microvolt = <1100000>;
1852 opp-hz = /bits/ 64 <288000000>;
1853 opp-microvolt = <1100000>;
1856 opp-hz = /bits/ 64 <375000000>;
1857 opp-microvolt = <1125000>;
1860 opp-hz = /bits/ 64 <480000000>;
1861 opp-microvolt = <1200000>;