2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3366-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
51 compatible = "rockchip,rk3366";
52 interrupt-parent = <&gic>;
71 #address-cells = <0x2>;
76 compatible = "arm,cortex-a53","arm,armv8";
78 enable-method = "psci";
83 compatible = "arm,cortex-a53","arm,armv8";
85 enable-method = "psci";
90 compatible = "arm,cortex-a53","arm,armv8";
92 enable-method = "psci";
97 compatible = "arm,cortex-a53","arm,armv8";
99 enable-method = "psci";
104 compatible = "arm,psci-1.0";
109 compatible = "arm,armv8-timer";
112 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
114 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
116 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
118 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
119 clock-frequency = <24000000>;
123 compatible = "fixed-clock";
125 clock-frequency = <24000000>;
126 clock-output-names = "xin24m";
129 gic: interrupt-controller@ffb71000 {
130 compatible = "arm,gic-400";
131 interrupt-controller;
132 #interrupt-cells = <3>;
133 #address-cells = <0>;
135 reg = <0x0 0xffb71000 0x0 0x1000>,
136 <0x0 0xffb72000 0x0 0x1000>,
137 <0x0 0xffb74000 0x0 0x2000>,
138 <0x0 0xffb76000 0x0 0x2000>;
139 interrupts = <GIC_PPI 9
140 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
143 nandc0: nandc@ff0c0000 {
144 compatible = "rockchip,rk-nandc";
145 reg = <0x0 0xff0c0000 0x0 0x4000>;
146 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
149 clock-names = "clk_nandc", "hclk_nandc";
153 saradc: saradc@ff100000 {
154 compatible = "rockchip,saradc";
155 reg = <0x0 0xff100000 0x0 0x100>;
156 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
157 #io-channel-cells = <1>;
158 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
159 clock-names = "saradc", "apb_pclk";
164 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
165 reg = <0x0 0xff110000 0x0 0x1000>;
166 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
167 clock-names = "spiclk", "apb_pclk";
168 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
171 #address-cells = <1>;
177 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
178 reg = <0x0 0xff120000 0x0 0x1000>;
179 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
180 clock-names = "spiclk", "apb_pclk";
181 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
184 #address-cells = <1>;
189 sdmmc: rksdmmc@ff400000 {
190 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
191 clock-freq-min-max = <400000 150000000>;
192 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
193 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
194 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
195 fifo-depth = <0x100>;
196 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
197 reg = <0x0 0xff400000 0x0 0x4000>;
201 sdio: rksdmmc@ff410000 {
202 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
203 clock-freq-min-max = <400000 150000000>;
204 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
205 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
206 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
207 fifo-depth = <0x100>;
208 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
209 reg = <0x0 0xff410000 0x0 0x4000>;
213 emmc: rksdmmc@ff420000 {
214 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
215 clock-freq-min-max = <400000 150000000>;
216 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
217 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
218 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
219 fifo-depth = <0x100>;
220 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
221 reg = <0x0 0xff420000 0x0 0x4000>;
226 compatible = "rockchip,rk3366-gmac";
227 reg = <0x0 0xff440000 0x0 0x10000>;
228 rockchip,grf = <&grf>;
229 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
230 interrupt-names = "macirq";
231 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
232 <&cru SCLK_MAC_RX>, <&cru SCLK_MACREF>,
233 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
235 clock-names = "stmmaceth", "mac_clk_rx",
236 "mac_clk_tx", "clk_mac_ref",
237 "clk_mac_refout", "aclk_mac",
239 resets = <&cru SRST_MAC>;
240 reset-names = "stmmaceth";
245 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
246 reg = <0x0 0xff728000 0x0 0x1000>;
247 clocks = <&cru PCLK_I2C0>;
249 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&i2c0_xfer>;
252 #address-cells = <1>;
258 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
259 reg = <0x0 0xff140000 0x0 0x1000>;
260 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
261 #address-cells = <1>;
264 clocks = <&cru PCLK_I2C2>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&i2c2_xfer>;
271 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
272 reg = <0x0 0xff150000 0x0 0x1000>;
273 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
274 #address-cells = <1>;
277 clocks = <&cru PCLK_I2C3>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&i2c3_xfer>;
284 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
285 reg = <0x0 0xff160000 0x0 0x1000>;
286 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
287 #address-cells = <1>;
290 clocks = <&cru PCLK_I2C4>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&i2c4_xfer>;
297 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
298 reg = <0x0 0xff170000 0x0 0x1000>;
299 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
300 #address-cells = <1>;
303 clocks = <&cru PCLK_I2C5>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&i2c5_xfer>;
309 uart0: serial@ff180000 {
310 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
311 reg = <0x0 0xff180000 0x0 0x100>;
312 clock-frequency = <24000000>;
313 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
314 clock-names = "baudclk", "apb_pclk";
315 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
323 uart3: serial@ff1b0000 {
324 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
325 reg = <0x0 0xff1b0000 0x0 0x100>;
326 clock-frequency = <24000000>;
327 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
328 clock-names = "baudclk", "apb_pclk";
329 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
338 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
339 reg = <0x0 0xff660000 0x0 0x1000>;
340 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
341 #address-cells = <1>;
344 clocks = <&cru PCLK_I2C1>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&i2c1_xfer>;
351 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
352 reg = <0x0 0xff680000 0x0 0x10>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&pwm0_pin>;
356 clocks = <&cru PCLK_RKPWM>;
362 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
363 reg = <0x0 0xff680010 0x0 0x10>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&pwm1_pin>;
367 clocks = <&cru PCLK_RKPWM>;
373 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
374 reg = <0x0 0xff680020 0x0 0x10>;
376 clocks = <&cru PCLK_RKPWM>;
382 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
383 reg = <0x0 0xff680030 0x0 0x10>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&pwm3_t2_pin>;
387 clocks = <&cru PCLK_RKPWM>;
392 uart2: serial@ff690000 {
393 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
394 reg = <0x0 0xff690000 0x0 0x100>;
395 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
397 clock-names = "baudclk", "apb_pclk";
400 pinctrl-names = "default";
401 pinctrl-0 = <&uart2_t1_xfer>;
405 pmugrf: syscon@ff738000 {
406 compatible = "rockchip,rk3366-pmugrf", "syscon";
407 reg = <0x0 0xff738000 0x0 0x1000>;
411 compatible = "arm,amba-bus";
412 #address-cells = <2>;
416 dmac_peri: dma-controller@ff250000 {
417 compatible = "arm,pl330", "arm,primecell";
418 reg = <0x0 0xff250000 0x0 0x4000>;
419 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&cru ACLK_DMAC_PERI>;
423 clock-names = "apb_pclk";
426 dmac_bus: dma-controller@ff600000 {
427 compatible = "arm,pl330", "arm,primecell";
428 reg = <0x0 0xff600000 0x0 0x4000>;
429 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&cru ACLK_DMAC_BUS>;
433 clock-names = "apb_pclk";
437 cru: clock-controller@ff760000 {
438 compatible = "rockchip,rk3366-cru";
439 reg = <0x0 0xff760000 0x0 0x1000>;
440 rockchip,grf = <&grf>;
445 grf: syscon@ff770000 {
446 compatible = "rockchip,rk3366-grf", "syscon";
447 reg = <0x0 0xff770000 0x0 0x1000>;
451 compatible = "rockchip,rk-fb";
452 rockchip,disp-mode = <DUAL>;
457 compatible = "rockchip,screen";
461 vop_lite: vop@ff8f0000 {
462 compatible = "rockchip,rk3366-lcdc-lite";
463 rockchip,grf = <&grf>;
464 rockchip,pwr18 = <0>;
465 rockchip,iommu-enabled = <1>;
466 reg = <0x0 0xff8f0000 0x0 0x1000>;
467 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
469 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
470 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
471 reset-names = "axi", "ahb", "dclk";
477 compatible = "rockchip,vopl_mmu";
478 reg = <0x0 0xff8f0f00 0x0 0x100>;
479 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
480 interrupt-names = "vopl_mmu";
484 vop_big: vop@ff930000 {
485 compatible = "rockchip,rk3366-lcdc-big";
486 rockchip,grf = <&grf>;
487 rockchip,prop = <PRMRY>;
488 rockchip,pwr18 = <0>;
489 rockchip,iommu-enabled = <1>;
490 reg = <0x0 0xff930000 0x0 0x23f0>;
491 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
493 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
494 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
495 reset-names = "axi", "ahb", "dclk";
501 compatible = "rockchip,vopb_mmu";
502 reg = <0x0 0xff932400 0x0 0x100>;
503 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
504 interrupt-names = "vop_mmu";
508 dsihost0: mipi@ff960000 {
509 compatible = "rockchip,rk3368-dsi";
511 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
512 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
513 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
515 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
519 lvds: lvds@ff968000 {
520 compatible = "rockchip,rk3366-lvds";
521 rockchip,grf = <&grf>;
522 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
523 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
524 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
525 clock-names = "pclk_lvds", "pclk_lvds_ctl";
530 compatible = "rockchip,rk3366-pinctrl";
531 rockchip,grf = <&grf>;
532 rockchip,pmu = <&pmugrf>;
533 #address-cells = <0x2>;
537 gpio0: gpio0@ff750000 {
538 compatible = "rockchip,gpio-bank";
539 reg = <0x0 0xff750000 0x0 0x100>;
540 clocks = <&cru PCLK_GPIO0>;
541 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
546 interrupt-controller;
547 #interrupt-cells = <0x2>;
550 gpio1: gpio1@ff780000 {
551 compatible = "rockchip,gpio-bank";
552 reg = <0x0 0xff758000 0x0 0x100>;
553 clocks = <&cru PCLK_GPIO1>;
554 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
559 interrupt-controller;
560 #interrupt-cells = <0x2>;
563 gpio2: gpio2@ff790000 {
564 compatible = "rockchip,gpio-bank";
565 reg = <0x0 0xff790000 0x0 0x100>;
566 clocks = <&cru PCLK_GPIO2>;
567 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
572 interrupt-controller;
573 #interrupt-cells = <0x2>;
576 gpio3: gpio3@ff7a0000 {
577 compatible = "rockchip,gpio-bank";
578 reg = <0x0 0xff7a0000 0x0 0x100>;
579 clocks = <&cru PCLK_GPIO3>;
580 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
585 interrupt-controller;
586 #interrupt-cells = <0x2>;
589 gpio4: gpio4@ff7b0000 {
590 compatible = "rockchip,gpio-bank";
591 reg = <0x0 0xff7b0000 0x0 0x100>;
592 clocks = <&cru PCLK_GPIO4>;
593 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
598 interrupt-controller;
599 #interrupt-cells = <0x2>;
602 gpio5: gpio5@ff7c0000 {
603 compatible = "rockchip,gpio-bank";
604 reg = <0x0 0xff7c0000 0x0 0x100>;
605 clocks = <&cru PCLK_GPIO5>;
606 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
611 interrupt-controller;
612 #interrupt-cells = <0x2>;
615 pcfg_pull_up: pcfg-pull-up {
619 pcfg_pull_down: pcfg-pull-down {
623 pcfg_pull_none: pcfg-pull-none {
627 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
629 drive-strength = <12>;
635 <3 4 RK_FUNC_2 &pcfg_pull_none>;
640 <2 26 RK_FUNC_2 &pcfg_pull_up>;
645 <2 27 RK_FUNC_2 &pcfg_pull_up>;
648 emmc_bus1: emmc-bus1 {
650 <2 18 RK_FUNC_2 &pcfg_pull_up>;
653 emmc_bus4: emmc-bus4 {
655 <2 18 RK_FUNC_2 &pcfg_pull_up>,
656 <2 19 RK_FUNC_2 &pcfg_pull_up>,
657 <2 20 RK_FUNC_2 &pcfg_pull_up>,
658 <2 21 RK_FUNC_2 &pcfg_pull_up>;
661 emmc_bus8: emmc-bus8 {
663 <2 18 RK_FUNC_2 &pcfg_pull_up>,
664 <2 19 RK_FUNC_2 &pcfg_pull_up>,
665 <2 20 RK_FUNC_2 &pcfg_pull_up>,
666 <2 21 RK_FUNC_2 &pcfg_pull_up>,
667 <2 22 RK_FUNC_2 &pcfg_pull_up>,
668 <2 23 RK_FUNC_2 &pcfg_pull_up>,
669 <2 24 RK_FUNC_2 &pcfg_pull_up>,
670 <2 25 RK_FUNC_2 &pcfg_pull_up>;
676 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
679 sdmmc_bus1: sdmmc-bus1 {
680 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
683 sdmmc_bus4: sdmmc-bus4 {
684 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
685 <5 1 RK_FUNC_1 &pcfg_pull_up>,
686 <5 2 RK_FUNC_1 &pcfg_pull_up>,
687 <5 3 RK_FUNC_1 &pcfg_pull_up>;
690 sdmmc_clk: sdmmc-clk {
691 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
694 sdmmc_cmd: sdmmc-cmd {
695 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
700 sdio_bus1: sdio-bus1 {
701 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
704 sdio_bus4: sdio-bus4 {
705 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
706 <3 13 RK_FUNC_1 &pcfg_pull_up>,
707 <3 14 RK_FUNC_1 &pcfg_pull_up>,
708 <3 15 RK_FUNC_1 &pcfg_pull_up>;
712 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
716 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
720 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
724 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
728 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
732 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
737 i2c0_xfer: i2c0-xfer {
739 <0 3 RK_FUNC_1 &pcfg_pull_none>,
740 <0 4 RK_FUNC_1 &pcfg_pull_none>;
745 i2c1_xfer: i2c1-xfer {
747 <4 25 RK_FUNC_1 &pcfg_pull_none>,
748 <4 26 RK_FUNC_1 &pcfg_pull_none>;
753 i2c2_xfer: i2c2-xfer {
755 <5 15 RK_FUNC_2 &pcfg_pull_none>,
756 <5 16 RK_FUNC_2 &pcfg_pull_none>;
761 i2c3_xfer: i2c3-xfer {
763 <2 16 RK_FUNC_2 &pcfg_pull_none>,
764 <2 17 RK_FUNC_2 &pcfg_pull_none>;
769 i2c4_xfer: i2c4-xfer {
771 <5 8 RK_FUNC_1 &pcfg_pull_none>,
772 <5 9 RK_FUNC_1 &pcfg_pull_none>;
777 i2c5_xfer: i2c5-xfer {
779 <5 13 RK_FUNC_1 &pcfg_pull_none>,
780 <5 14 RK_FUNC_1 &pcfg_pull_none>;
785 i2s_8ch_bus: i2s-8ch-bus {
787 <4 16 RK_FUNC_1 &pcfg_pull_none>,
788 <4 17 RK_FUNC_1 &pcfg_pull_none>,
789 <4 18 RK_FUNC_1 &pcfg_pull_none>,
790 <4 19 RK_FUNC_1 &pcfg_pull_none>,
791 <4 20 RK_FUNC_1 &pcfg_pull_none>,
792 <4 21 RK_FUNC_1 &pcfg_pull_none>,
793 <4 22 RK_FUNC_1 &pcfg_pull_none>,
794 <4 23 RK_FUNC_1 &pcfg_pull_none>,
795 <4 24 RK_FUNC_1 &pcfg_pull_none>;
802 <2 29 RK_FUNC_2 &pcfg_pull_up>;
806 <2 24 RK_FUNC_3 &pcfg_pull_up>;
810 <2 25 RK_FUNC_3 &pcfg_pull_up>;
814 <2 23 RK_FUNC_3 &pcfg_pull_up>;
818 <2 22 RK_FUNC_3 &pcfg_pull_up>;
825 <2 4 RK_FUNC_3 &pcfg_pull_up>;
829 <2 5 RK_FUNC_3 &pcfg_pull_up>;
833 <2 6 RK_FUNC_3 &pcfg_pull_up>;
837 <2 7 RK_FUNC_3 &pcfg_pull_up>;
842 uart0_xfer: uart0-xfer {
844 <3 8 RK_FUNC_1 &pcfg_pull_up>,
845 <3 9 RK_FUNC_1 &pcfg_pull_none>;
848 uart0_cts: uart0-cts {
850 <3 10 RK_FUNC_1 &pcfg_pull_none>;
853 uart0_rts: uart0-rts {
855 <3 11 RK_FUNC_1 &pcfg_pull_none>;
860 uart2_t0_xfer: uart2_t0-xfer {
862 <0 22 RK_FUNC_1 &pcfg_pull_up>,
863 <0 21 RK_FUNC_1 &pcfg_pull_none>;
865 /* no rts / cts for uart2 */
869 uart2_t1_xfer: uart2_t1-xfer {
871 <5 0 RK_FUNC_2 &pcfg_pull_up>,
872 <5 1 RK_FUNC_2 &pcfg_pull_none>;
874 /* no rts / cts for uart2 */
878 uart2_t2_xfer: uart2_t2-xfer {
880 <5 14 RK_FUNC_3 &pcfg_pull_up>,
881 <5 13 RK_FUNC_3 &pcfg_pull_none>;
883 /* no rts / cts for uart2 */
887 uart3_xfer: uart3-xfer {
889 <5 15 RK_FUNC_1 &pcfg_pull_up>,
890 <5 16 RK_FUNC_1 &pcfg_pull_none>;
893 uart3_cts: uart3-cts {
895 <5 17 RK_FUNC_1 &pcfg_pull_none>;
898 uart3_rts: uart3-rts {
900 <5 18 RK_FUNC_1 &pcfg_pull_none>;
907 <0 8 RK_FUNC_1 &pcfg_pull_none>;
914 <1 6 RK_FUNC_2 &pcfg_pull_none>;
919 pwm2_t0_pin: pwm2_t0-pin {
921 <2 15 RK_FUNC_3 &pcfg_pull_none>;
926 pwm2_t1_pin: pwm2_t1-pin {
928 <5 17 RK_FUNC_2 &pcfg_pull_none>;
933 pwm3_t0_pin: pwm3_t0-pin {
935 <1 0 RK_FUNC_2 &pcfg_pull_none>;
940 pwm3_t1_pin: pwm3_t1-pin {
942 <0 21 RK_FUNC_2 &pcfg_pull_none>;
947 pwm3_t2_pin: pwm3_t2-pin {
949 <5 18 RK_FUNC_2 &pcfg_pull_none>;
954 lcdc_lcdc: lcdc-lcdc {
956 <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
957 <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
958 <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
959 <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
960 <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
961 <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
962 <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
963 <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
964 <1 0 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
965 <1 1 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
966 <1 2 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
967 <1 3 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
968 <1 4 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
969 <1 5 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
970 <1 6 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
971 <1 7 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
972 <1 8 RK_FUNC_1 &pcfg_pull_none>, /* DEN */
973 <1 9 RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
976 lcdc_gpio: lcdc-gpio {
978 <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
979 <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
980 <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
981 <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
982 <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
983 <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
984 <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
985 <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
986 <1 0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
987 <1 1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
988 <1 2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
989 <1 3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
990 <1 4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
991 <1 5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
992 <1 6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
993 <1 7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
994 <1 8 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
995 <1 9 RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1000 rgmii_pins: rgmii-pins {
1003 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1005 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1007 <2 5 RK_FUNC_1 &pcfg_pull_none>,
1009 <2 4 RK_FUNC_1 &pcfg_pull_none>,
1011 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1013 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1015 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1017 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1019 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1021 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1023 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1025 <2 12 RK_FUNC_1 &pcfg_pull_none>,
1027 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1029 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1031 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1033 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1036 rmii_pins: rmii-pins {
1039 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1041 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1043 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1045 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1047 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1049 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1051 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1053 <2 12 RK_FUNC_1 &pcfg_pull_none>,
1055 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1057 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1059 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1061 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1066 eth_phy_pwr: eth-phy-pwr {
1068 <0 24 RK_FUNC_GPIO &pcfg_pull_none>;