arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/mipi_dsi.h>
  49 #include <dt-bindings/power/rk3366-power.h>
  50 #include <dt-bindings/soc/rockchip,boot-mode.h>
  51 #include <dt-bindings/thermal/thermal.h>
  52 #include <dt-bindings/display/drm_mipi_dsi.h>
  53 #include <dt-bindings/display/media-bus-format.h>
  54
  55 / {
  56         compatible = "rockchip,rk3366";
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 serial0 = &uart0;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73         };
  74
  75         cpus {
  76                 #address-cells = <0x2>;
  77                 #size-cells = <0x0>;
  78
  79                 cpu0: cpu@0 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53","arm,armv8";
  82                         reg = <0x0 0x0>;
  83                         enable-method = "psci";
  84                         clocks = <&cru ARMCLK>;
  85                         operating-points-v2 = <&cpu0_opp_table>;
  86                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  87                         #cooling-cells = <2>; /* min followed by max */
  88                         dynamic-power-coefficient = <166>;
  89                 };
  90
  91                 cpu1: cpu@1 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a53","arm,armv8";
  94                         reg = <0x0 0x1>;
  95                         enable-method = "psci";
  96                         operating-points-v2 = <&cpu0_opp_table>;
  97                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  98                 };
  99
 100                 cpu2: cpu@2 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53","arm,armv8";
 103                         reg = <0x0 0x2>;
 104                         enable-method = "psci";
 105                         operating-points-v2 = <&cpu0_opp_table>;
 106                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 107                 };
 108
 109                 cpu3: cpu@3 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53","arm,armv8";
 112                         reg = <0x0 0x3>;
 113                         enable-method = "psci";
 114                         operating-points-v2 = <&cpu0_opp_table>;
 115                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 116                 };
 117
 118                 idle-states {
 119                         entry-method = "psci";
 120
 121                         CPU_SLEEP: cpu-sleep {
 122                                 compatible = "arm,idle-state";
 123                                 local-timer-stop;
 124                                 arm,psci-suspend-param = <0x0010000>;
 125                                 entry-latency-us = <120>;
 126                                 exit-latency-us = <250>;
 127                                 min-residency-us = <900>;
 128                         };
 129
 130                         CLUSTER_SLEEP: cluster-sleep {
 131                                 compatible = "arm,idle-state";
 132                                 local-timer-stop;
 133                                 arm,psci-suspend-param = <0x1010000>;
 134                                 entry-latency-us = <400>;
 135                                 exit-latency-us = <500>;
 136                                 min-residency-us = <2000>;
 137                         };
 138                 };
 139         };
 140
 141         cpu0_opp_table: opp_table0 {
 142                 compatible = "operating-points-v2";
 143                 opp-shared;
 144
 145                 nvmem-cells = <&cpu_leakage>;
 146                 nvmem-cell-names = "cpu_leakage";
 147
 148                 opp-408000000 {
 149                         opp-hz = /bits/ 64 <408000000>;
 150                         opp-microvolt = <950000>;
 151                         clock-latency-ns = <40000>;
 152                         opp-suspend;
 153                 };
 154                 opp-600000000 {
 155                         opp-hz = /bits/ 64 <600000000>;
 156                         opp-microvolt = <950000>;
 157                 };
 158                 opp-816000000 {
 159                         opp-hz = /bits/ 64 <816000000>;
 160                         opp-microvolt = <1000000>;
 161                 };
 162                 opp-1008000000 {
 163                         opp-hz = /bits/ 64 <1008000000>;
 164                         opp-microvolt = <1075000>;
 165                 };
 166                 opp-1200000000 {
 167                         opp-hz = /bits/ 64 <1200000000>;
 168                         opp-microvolt = <1175000>;
 169                 };
 170                 opp-1296000000 {
 171                         opp-hz = /bits/ 64 <1296000000>;
 172                         opp-microvolt = <1250000>;
 173                 };
 174         };
 175
 176         psci {
 177                 compatible = "arm,psci-1.0";
 178                 method = "smc";
 179         };
 180
 181         timer {
 182                 compatible = "arm,armv8-timer";
 183                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 184                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 185                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 186                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 187         };
 188
 189         arm-pmu {
 190                 compatible = "arm,cortex-a53-pmu";
 191                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 195                 interrupt-affinity = <&cpu0>,
 196                                      <&cpu1>,
 197                                      <&cpu2>,
 198                                      <&cpu3>;
 199         };
 200
 201         xin24m: xin24m {
 202                 compatible = "fixed-clock";
 203                 #clock-cells = <0>;
 204                 clock-frequency = <24000000>;
 205                 clock-output-names = "xin24m";
 206         };
 207
 208         gic: interrupt-controller@ffb71000 {
 209                 compatible = "arm,gic-400";
 210                 interrupt-controller;
 211                 #interrupt-cells = <3>;
 212                 #address-cells = <0>;
 213
 214                 reg = <0x0 0xffb71000 0x0 0x1000>,
 215                       <0x0 0xffb72000 0x0 0x1000>,
 216                       <0x0 0xffb74000 0x0 0x2000>,
 217                       <0x0 0xffb76000 0x0 0x2000>;
 218                 interrupts = <GIC_PPI 9
 219                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 220         };
 221
 222         nandc0: nandc@ff0c0000 {
 223                 compatible = "rockchip,rk-nandc";
 224                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 225                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 226                 nandc_id = <0>;
 227                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 228                 clock-names = "clk_nandc", "hclk_nandc";
 229                 status = "disabled";
 230         };
 231
 232         saradc: saradc@ff100000 {
 233                 compatible = "rockchip,saradc";
 234                 reg = <0x0 0xff100000 0x0 0x100>;
 235                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 236                 #io-channel-cells = <1>;
 237                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 238                 clock-names = "saradc", "apb_pclk";
 239                 status = "disabled";
 240         };
 241
 242         spi0: spi@ff110000 {
 243                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 244                 reg = <0x0 0xff110000 0x0 0x1000>;
 245                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 246                 clock-names = "spiclk", "apb_pclk";
 247                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 248                 pinctrl-names = "default";
 249                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 250                 #address-cells = <1>;
 251                 #size-cells = <0>;
 252                 status = "disabled";
 253         };
 254
 255         spi1: spi@ff120000 {
 256                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 257                 reg = <0x0 0xff120000 0x0 0x1000>;
 258                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 259                 clock-names = "spiclk", "apb_pclk";
 260                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 261                 pinctrl-names = "default";
 262                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 263                 #address-cells = <1>;
 264                 #size-cells = <0>;
 265                 status = "disabled";
 266         };
 267
 268         scr: rkscr@ff1d0000 {
 269                 compatible = "rockchip-scr";
 270                 reg = <0x0 0xff1d0000 0x0 0x10000>;
 271                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 272                 #address-cells = <1>;
 273                 #size-cells = <0>;
 274                 pinctrl-names = "default";
 275                 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
 276                 clocks = <&cru PCLK_SIM>;
 277                 clock-names = "g_pclk_sim_card";
 278                 status = "disabled";
 279         };
 280
 281         thermal-zones {
 282                 soc_thermal: soc-thermal {
 283                         polling-delay-passive = <100>; /* milliseconds */
 284                         polling-delay = <1000>; /* milliseconds */
 285                         sustainable-power = <1600>; /* milliwatts */
 286
 287                         thermal-sensors = <&tsadc 0>;
 288
 289                         trips {
 290                                 threshold: trip-point@0 {
 291                                         temperature = <70000>; /* millicelsius */
 292                                         hysteresis = <2000>; /* millicelsius */
 293                                         type = "passive";
 294                                 };
 295                                 target: trip-point@1 {
 296                                         temperature = <85000>; /* millicelsius */
 297                                         hysteresis = <2000>; /* millicelsius */
 298                                         type = "passive";
 299                                 };
 300                                 soc_crit: soc-crit {
 301                                         temperature = <95000>; /* millicelsius */
 302                                         hysteresis = <2000>; /* millicelsius */
 303                                         type = "critical";
 304                                 };
 305                         };
 306
 307                         cooling-maps {
 308                                 map0 {
 309                                         trip = <&target>;
 310                                         cooling-device =
 311                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 312                                 };
 313                                 map1 {
 314                                         trip = <&target>;
 315                                         cooling-device =
 316                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 317                                 };
 318                         };
 319                 };
 320
 321                 gpu_thermal: gpu-thermal {
 322                         polling-delay-passive = <100>; /* milliseconds */
 323                         polling-delay = <1000>; /* milliseconds */
 324
 325                         thermal-sensors = <&tsadc 1>;
 326                 };
 327         };
 328
 329         tsadc: tsadc@ff260000 {
 330                 compatible = "rockchip,rk3366-tsadc";
 331                 reg = <0x0 0xff260000 0x0 0x100>;
 332                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 333                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 334                 clock-names = "tsadc", "apb_pclk";
 335                 resets = <&cru SRST_TSADC>;
 336                 reset-names = "tsadc-apb";
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&tsadc_gpio>;
 339                 #thermal-sensor-cells = <1>;
 340                 rockchip,hw-tshut-temp = <95000>;
 341                 status = "disabled";
 342         };
 343
 344         sdmmc: dwmmc@ff400000 {
 345                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 346                 clock-freq-min-max = <400000 150000000>;
 347                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 348                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 349                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 350                 fifo-depth = <0x100>;
 351                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 352                 reg = <0x0 0xff400000 0x0 0x4000>;
 353                 status = "disabled";
 354         };
 355
 356         sdio: dwmmc@ff410000 {
 357                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 358                 clock-freq-min-max = <400000 150000000>;
 359                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 360                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 361                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 362                 fifo-depth = <0x100>;
 363                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 364                 reg = <0x0 0xff410000 0x0 0x4000>;
 365                 status = "disabled";
 366         };
 367
 368         emmc: dwmmc@ff420000 {
 369                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 370                 clock-freq-min-max = <400000 150000000>;
 371                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 372                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 373                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 374                 fifo-depth = <0x100>;
 375                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 376                 reg = <0x0 0xff420000 0x0 0x4000>;
 377                 status = "disabled";
 378         };
 379
 380         gmac: eth@ff440000 {
 381                 compatible = "rockchip,rk3366-gmac";
 382                 reg = <0x0 0xff440000 0x0 0x10000>;
 383                 rockchip,grf = <&grf>;
 384                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 385                 interrupt-names = "macirq";
 386                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 387                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 388                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 389                          <&cru PCLK_GMAC>;
 390                 clock-names = "stmmaceth", "mac_clk_rx",
 391                               "mac_clk_tx", "clk_mac_ref",
 392                               "clk_mac_refout", "aclk_mac",
 393                               "pclk_mac";
 394                 resets = <&cru SRST_MAC>;
 395                 reset-names = "stmmaceth";
 396                 status = "disabled";
 397         };
 398
 399         i2c0: i2c@ff650000 {
 400                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 401                 reg = <0x0 0xff728000 0x0 0x1000>;
 402                 clocks = <&cru PCLK_I2C0>;
 403                 clock-names = "i2c";
 404                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 405                 pinctrl-names = "default";
 406                 pinctrl-0 = <&i2c0_xfer>;
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 status = "disabled";
 410         };
 411
 412         i2c2: i2c@ff140000 {
 413                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 414                 reg = <0x0 0xff140000 0x0 0x1000>;
 415                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 clock-names = "i2c";
 419                 clocks = <&cru PCLK_I2C2>;
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&i2c2_xfer>;
 422                 status = "disabled";
 423         };
 424
 425         i2c3: i2c@ff150000 {
 426                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 427                 reg = <0x0 0xff150000 0x0 0x1000>;
 428                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 clock-names = "i2c";
 432                 clocks = <&cru PCLK_I2C3>;
 433                 pinctrl-names = "default";
 434                 pinctrl-0 = <&i2c3_xfer>;
 435                 status = "disabled";
 436         };
 437
 438         i2c4: i2c@ff160000 {
 439                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 440                 reg = <0x0 0xff160000 0x0 0x1000>;
 441                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 442                 #address-cells = <1>;
 443                 #size-cells = <0>;
 444                 clock-names = "i2c";
 445                 clocks = <&cru PCLK_I2C4>;
 446                 pinctrl-names = "default";
 447                 pinctrl-0 = <&i2c4_xfer>;
 448                 status = "disabled";
 449         };
 450
 451         i2c5: i2c@ff170000 {
 452                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 453                 reg = <0x0 0xff170000 0x0 0x1000>;
 454                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 455                 #address-cells = <1>;
 456                 #size-cells = <0>;
 457                 clock-names = "i2c";
 458                 clocks = <&cru PCLK_I2C5>;
 459                 pinctrl-names = "default";
 460                 pinctrl-0 = <&i2c5_xfer>;
 461                 status = "disabled";
 462         };
 463
 464         uart0: serial@ff180000 {
 465                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 466                 reg = <0x0 0xff180000 0x0 0x100>;
 467                 clock-frequency = <24000000>;
 468                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 469                 clock-names = "baudclk", "apb_pclk";
 470                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 471                 reg-shift = <2>;
 472                 reg-io-width = <4>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 475                 status = "disabled";
 476         };
 477
 478         uart3: serial@ff1b0000 {
 479                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 480                 reg = <0x0 0xff1b0000 0x0 0x100>;
 481                 clock-frequency = <24000000>;
 482                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 483                 clock-names = "baudclk", "apb_pclk";
 484                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 485                 reg-shift = <2>;
 486                 reg-io-width = <4>;
 487                 pinctrl-names = "default";
 488                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 489                 status = "disabled";
 490         };
 491
 492         usb_host0_ehci: usb@ff480000 {
 493                 compatible = "generic-ehci";
 494                 reg = <0x0 0xff480000 0x0 0x20000>;
 495                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 496                 clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
 497                 clock-names = "usbphy_480m", "hclk_host0";
 498                 phys = <&u2phy_host>;
 499                 phy-names = "usb";
 500                 status = "disabled";
 501         };
 502
 503         usb_host0_ohci: usb@ff4a0000 {
 504                 compatible = "generic-ohci";
 505                 reg = <0x0 0xff4a0000 0x0 0x20000>;
 506                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 507                 clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
 508                 clock-names = "usbphy_480m", "hclk_host0";
 509                 phys = <&u2phy_host>;
 510                 phy-names = "usb";
 511                 status = "disabled";
 512         };
 513
 514         usb_otg: usb@ff4c0000 {
 515                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 516                              "snps,dwc2";
 517                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 518                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 519                 clocks = <&cru HCLK_OTG>;
 520                 clock-names = "otg";
 521                 dr_mode = "otg";
 522                 g-np-tx-fifo-size = <16>;
 523                 g-rx-fifo-size = <275>;
 524                 g-tx-fifo-size = <256 128 128 64 64 32>;
 525                 g-use-dma;
 526                 status = "disabled";
 527         };
 528
 529         i2c1: i2c@ff660000 {
 530                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 531                 reg = <0x0 0xff660000 0x0 0x1000>;
 532                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535                 clock-names = "i2c";
 536                 clocks = <&cru PCLK_I2C1>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&i2c1_xfer>;
 539                 status = "disabled";
 540         };
 541
 542         efuse: efuse@ff670000 {
 543                 compatible = "rockchip,rk3366-efuse";
 544                 reg = <0x0 0xff670000 0x0 0x20>;
 545                 #address-cells = <1>;
 546                 #size-cells = <1>;
 547                 clocks = <&cru PCLK_EFUSE_256>;
 548                 clock-names = "pclk_efuse";
 549
 550                 /* Data cells */
 551                 cpu_leakage: cpu-leakage {
 552                         reg = <0x17 0x1>;
 553                 };
 554                 gpu_leakage: gpu-leakage {
 555                         reg = <0x18 0x1>;
 556                 };
 557                 logic_leakage: logic-leakage {
 558                         reg = <0x19 0x1>;
 559                 };
 560                 wafer_info: wafer-info {
 561                         reg = <0x1c 0x1>;
 562                 };
 563         };
 564
 565         pwm0: pwm@ff680000 {
 566                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 567                 reg = <0x0 0xff680000 0x0 0x10>;
 568                 #pwm-cells = <3>;
 569                 pinctrl-names = "default";
 570                 pinctrl-0 = <&pwm0_pin>;
 571                 clocks = <&cru PCLK_RKPWM>;
 572                 clock-names = "pwm";
 573                 status = "disabled";
 574         };
 575
 576         pwm1: pwm@ff680010 {
 577                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 578                 reg = <0x0 0xff680010 0x0 0x10>;
 579                 #pwm-cells = <3>;
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&pwm1_pin>;
 582                 clocks = <&cru PCLK_RKPWM>;
 583                 clock-names = "pwm";
 584                 status = "disabled";
 585         };
 586
 587         pwm2: pwm@ff680020 {
 588                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 589                 reg = <0x0 0xff680020 0x0 0x10>;
 590                 #pwm-cells = <3>;
 591                 clocks = <&cru PCLK_RKPWM>;
 592                 clock-names = "pwm";
 593                 status = "disabled";
 594         };
 595
 596         pwm3: pwm@ff680030 {
 597                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 598                 reg = <0x0 0xff680030 0x0 0x10>;
 599                 #pwm-cells = <3>;
 600                 pinctrl-names = "default";
 601                 pinctrl-0 = <&pwm3_t2_pin>;
 602                 clocks = <&cru PCLK_RKPWM>;
 603                 clock-names = "pwm";
 604                 status = "disabled";
 605         };
 606
 607         uart2: serial@ff690000 {
 608                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 609                 reg = <0x0 0xff690000 0x0 0x100>;
 610                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 611                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 612                 clock-names = "baudclk", "apb_pclk";
 613                 reg-shift = <2>;
 614                 reg-io-width = <4>;
 615                 pinctrl-names = "default";
 616                 pinctrl-0 = <&uart2_t1_xfer>;
 617                 status = "disabled";
 618         };
 619
 620         pmu: power-management@ff730000 {
 621                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 622                 reg = <0x0 0xff730000 0x0 0x1000>;
 623
 624                 power: power-controller {
 625                         compatible = "rockchip,rk3366-power-controller";
 626                         #power-domain-cells = <1>;
 627                         #address-cells = <1>;
 628                         #size-cells = <0>;
 629
 630                         /*
 631                          * Note: Although SCLK_* are the working clocks
 632                          * of device without including on the NOC, needed for
 633                          * synchronous reset.
 634                          *
 635                          * The clocks on the which NOC:
 636                          * ACLK_IEP/ACLK_VOP_FULL are on ACLK_VIO0_NOC.
 637                          * ACLK_RGA/ACLK_VOP_LITE are on ACLK_VIO1_NOC.
 638                          * ACLK_ISP is on ACLK_ISP_NOC.
 639                          * ACLK_HDCP is on ACLK_HDCP_NOC.
 640                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NOC.
 641                          *
 642                          * Which clock are device clocks:
 643                          *      clocks          devices
 644                          *      *_IEP           IEP:Image Enhancement Processor
 645                          *      *_ISP           ISP:Image Signal Processing
 646                          *      *_VOP*          VOP:Visual Output Processor
 647                          *      *_RGA           RGA
 648                          *      *_DPHY*         LVDS
 649                          *      *_HDMI          HDMI
 650                          *      *_MIPI_*        MIPI/LVDS
 651                          */
 652                         pd_vio@RK3366_PD_VIO {
 653                                 reg = <RK3366_PD_VIO>;
 654                                 clocks = <&cru ACLK_IEP>,
 655                                          <&cru ACLK_ISP>,
 656                                          <&cru ACLK_RGA>,
 657                                          <&cru ACLK_HDCP>,
 658                                          <&cru ACLK_VOP_FULL>,
 659                                          <&cru ACLK_VOP_LITE>,
 660                                          <&cru ACLK_VOP_IEP>,
 661                                          <&cru DCLK_VOP_FULL>,
 662                                          <&cru DCLK_VOP_LITE>,
 663                                          <&cru HCLK_IEP>,
 664                                          <&cru HCLK_ISP>,
 665                                          <&cru HCLK_RGA>,
 666                                          <&cru HCLK_VOP_FULL>,
 667                                          <&cru HCLK_VOP_LITE>,
 668                                          <&cru HCLK_VIO_HDCPMMU>,
 669                                          <&cru PCLK_DPHYTX>,
 670                                          <&cru PCLK_HDMI_CTRL>,
 671                                          <&cru PCLK_HDCP>,
 672                                          <&cru PCLK_MIPI_DSI0>,
 673                                          <&cru SCLK_VOP_FULL_PWM>,
 674                                          <&cru SCLK_HDCP>,
 675                                          <&cru SCLK_ISP>,
 676                                          <&cru SCLK_RGA>,
 677                                          <&cru SCLK_HDMI_CEC>,
 678                                          <&cru SCLK_HDMI_HDCP>;
 679                         };
 680
 681                         /*
 682                          * Note: ACLK_VCODEC/HCLK_VCODEC are VPU clocks
 683                          * that on the ACLK_VCODEC_NOC and
 684                          * HCLK_VCODEC_NOC.
 685                          */
 686                         pd_vpu@RK3366_PD_VPU {
 687                                 reg = <RK3366_PD_VPU>;
 688                                 clocks = <&cru ACLK_VIDEO>,
 689                                          <&cru HCLK_VIDEO>;
 690                         };
 691
 692                         /*
 693                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 694                          * clocks that on the ACLK_RKVDEC_NOC and
 695                          * HCLK_RKVDEC_NOC.
 696                          */
 697                         pd_rkvdec@RK3366_PD_RKVDEC {
 698                                 reg = <RK3366_PD_RKVDEC>;
 699                                 clocks = <&cru ACLK_RKVDEC>,
 700                                          <&cru HCLK_RKVDEC>,
 701                                          <&cru SCLK_HEVC_CABAC>,
 702                                          <&cru SCLK_HEVC_CORE>;
 703                         };
 704
 705                         /*
 706                          * Note: ACLK_GPU is the GPU clock
 707                          * that on the ACLK_GPU_NOC.
 708                          */
 709                         pd_gpu@RK3366_PD_GPU {
 710                                 reg = <RK3366_PD_GPU>;
 711                                 clocks = <&cru ACLK_GPU>;
 712                         };
 713                 };
 714         };
 715
 716         pmugrf: syscon@ff738000 {
 717                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 718                 reg = <0x0 0xff738000 0x0 0x1000>;
 719
 720                 reboot-mode {
 721                         compatible = "syscon-reboot-mode";
 722                         offset = <0x200>;
 723                         mode-normal = <BOOT_NORMAL>;
 724                         mode-recovery = <BOOT_RECOVERY>;
 725                         mode-fastboot = <BOOT_FASTBOOT>;
 726                         mode-loader = <BOOT_BL_DOWNLOAD>;
 727                 };
 728
 729                 pmu_pvtm: pmu-pvtm {
 730                         compatible = "rockchip,rk3366-pmu-pvtm";
 731                         clocks = <&cru SCLK_PVTM_PMU>;
 732                         clock-names = "pmu";
 733                         status = "disabled";
 734                 };
 735         };
 736
 737         amba {
 738                 compatible = "arm,amba-bus";
 739                 #address-cells = <2>;
 740                 #size-cells = <2>;
 741                 ranges;
 742
 743                 dmac_peri: dma-controller@ff250000 {
 744                         compatible = "arm,pl330", "arm,primecell";
 745                         reg = <0x0 0xff250000 0x0 0x4000>;
 746                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 747                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 748                         #dma-cells = <1>;
 749                         clocks = <&cru ACLK_DMAC_PERI>;
 750                         clock-names = "apb_pclk";
 751                         peripherals-req-type-burst;
 752                 };
 753
 754                 dmac_bus: dma-controller@ff600000 {
 755                         compatible = "arm,pl330", "arm,primecell";
 756                         reg = <0x0 0xff600000 0x0 0x4000>;
 757                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 758                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 759                         #dma-cells = <1>;
 760                         clocks = <&cru ACLK_DMAC_BUS>;
 761                         clock-names = "apb_pclk";
 762                         peripherals-req-type-burst;
 763                 };
 764         };
 765
 766         cru: clock-controller@ff760000 {
 767                 compatible = "rockchip,rk3366-cru";
 768                 reg = <0x0 0xff760000 0x0 0x1000>;
 769                 rockchip,grf = <&grf>;
 770                 #clock-cells = <1>;
 771                 #reset-cells = <1>;
 772                 assigned-clocks =
 773                         <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
 774                         <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
 775                         <&cru SCLK_I2S_8CH_SRC>, <&cru SCLK_I2S_2CH_SRC>,
 776                         <&cru SCLK_SPDIF_8CH_SRC>,
 777                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 778                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 779                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 780                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 781                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
 782                         <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
 783                         <&cru ACLK_PERI1>;
 784                 assigned-clock-rates =
 785                         <0>, <0>,
 786                         <0>, <0>,
 787                         <0>, <0>,
 788                         <0>,
 789                         <750000000>, <576000000>,
 790                         <594000000>, <594000000>,
 791                         <960000000>, <520000000>,
 792                         <375000000>, <288000000>,
 793                         <100000000>, <100000000>,
 794                         <288000000>, <288000000>,
 795                         <144000000>;
 796                 assigned-clock-parents =
 797                         <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
 798                         <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>,
 799                         <&cru PLL_GPLL>, <&cru PLL_GPLL>,
 800                         <&cru PLL_GPLL>;
 801         };
 802
 803         grf: syscon@ff770000 {
 804                 compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd";
 805                 reg = <0x0 0xff770000 0x0 0x1000>;
 806                 #address-cells = <1>;
 807                 #size-cells = <1>;
 808
 809                 u2phy: usb2-phy@700 {
 810                         compatible = "rockchip,rk3366-usb2phy";
 811                         reg = <0x700 0x2c>;
 812                         clocks = <&cru SCLK_OTG_PHY0>;
 813                         clock-names = "phyclk";
 814                         #clock-cells = <0>;
 815                         clock-output-names = "sclk_otgphy0_480m";
 816
 817                         u2phy_host: host-port {
 818                                 #phy-cells = <0>;
 819                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 820                                 interrupt-names = "linestate";
 821                                 status = "okay";
 822                         };
 823                 };
 824
 825                 pvtm: pvtm {
 826                         compatible = "rockchip,rk3366-pvtm";
 827                         clocks = <&cru SCLK_PVTM_CORE>, <&cru SCLK_PVTM_GPU>;
 828                         clock-names = "core", "gpu";
 829                         status = "disabled";
 830                 };
 831         };
 832
 833         wdt: watchdog@ff800000 {
 834                 compatible = "snps,dw-wdt";
 835                 reg = <0x0 0xff800000 0x0 0x100>;
 836                 clocks = <&cru PCLK_WDT>;
 837                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 838                 status = "disabled";
 839         };
 840
 841         rktimer: rktimer@ff810000 {
 842                 compatible = "rockchip,rk3288-timer";
 843                 reg = <0x0 0xff810000 0x0 0x1000>;
 844                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
 845                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER0>;
 846                 clock-names = "pclk", "timer";
 847         };
 848
 849         spdif: spdif@ff880000 {
 850                 compatible = "rockchip,rk3366-spdif";
 851                 reg = <0x0 0xff880000 0x0 0x1000>;
 852                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 853                 dmas = <&dmac_bus 3>;
 854                 dma-names = "tx";
 855                 clock-names = "mclk", "hclk";
 856                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 857                 pinctrl-names = "default";
 858                 pinctrl-0 = <&spdif_bus>;
 859                 status = "disabled";
 860         };
 861
 862         i2s_2ch: i2s-2ch@ff890000 {
 863                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 864                 reg = <0x0 0xff890000 0x0 0x1000>;
 865                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 866                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 867                 dma-names = "tx", "rx";
 868                 clock-names = "i2s_clk", "i2s_hclk";
 869                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 870                 status = "disabled";
 871         };
 872
 873         i2s_8ch: i2s-8ch@ff898000 {
 874                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 875                 reg = <0x0 0xff898000 0x0 0x1000>;
 876                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 877                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 878                 dma-names = "tx", "rx";
 879                 clock-names = "i2s_clk", "i2s_hclk";
 880                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 881                 pinctrl-names = "default";
 882                 pinctrl-0 = <&i2s_8ch_bus>;
 883                 status = "disabled";
 884         };
 885
 886         display_subsystem: display-subsystem {
 887                 compatible = "rockchip,display-subsystem";
 888                 ports = <&vopb_out>, <&vopl_out>;
 889                 status = "disabled";
 890         };
 891
 892         vopl: vop@ff8f0000 {
 893                 compatible = "rockchip,rk3366-vop-lit";
 894                 reg = <0x0 0xff8f0000 0x0 0x900>;
 895                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 896                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>,
 897                          <&cru HCLK_VOP_LITE>;
 898                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 899                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>,
 900                          <&cru SRST_VOP1_AHB>;
 901                 reset-names = "axi", "ahb", "dclk";
 902                 power-domains = <&power RK3366_PD_VIO>;
 903                 iommus = <&vopl_mmu>;
 904                 status = "disabled";
 905
 906                 vopl_out: port {
 907                         #address-cells = <1>;
 908                         #size-cells = <0>;
 909
 910                         vopl_out_dsi: endpoint@0 {
 911                                 reg = <0>;
 912                                 remote-endpoint = <&dsi_in_vopl>;
 913                         };
 914
 915                         vopl_out_lvds: endpoint@1 {
 916                                 reg = <1>;
 917                                 remote-endpoint = <&lvds_in_vopl>;
 918                         };
 919                 };
 920         };
 921
 922         vopl_mmu: iommu@ff8f0f00 {
 923                 compatible = "rockchip,iommu";
 924                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 925                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>;
 926                 interrupt-names = "vopl_mmu";
 927                 clocks = <&cru ACLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 928                 clock-names = "aclk", "hclk";
 929                 power-domains = <&power RK3366_PD_VIO>;
 930                 #iommu-cells = <0>;
 931                 status = "disabled";
 932         };
 933
 934         iep: iep@ff900000 {
 935                 compatible = "rockchip,iep";
 936                 iommu_enabled = <1>;
 937                 iommus = <&iep_mmu>;
 938                 reg = <0x0 0xff900000 0x0 0x800>;
 939                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 940                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 941                 clock-names = "aclk_iep", "hclk_iep";
 942                 power-domains = <&power RK3366_PD_VIO>;
 943                 allocator = <1>;
 944                 version = <2>;
 945                 status = "disabled";
 946         };
 947
 948         iep_mmu: iommu@ff900800 {
 949                 compatible = "rockchip,iommu";
 950                 reg = <0x0 0xff900800 0x0 0x100>;
 951                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 952                 interrupt-names = "iep_mmu";
 953                 power-domains = <&power RK3366_PD_VIO>;
 954                 #iommu-cells = <0>;
 955                 status = "disabled";
 956         };
 957
 958         rga: rga@ff920000 {
 959                 compatible = "rockchip,rga2";
 960                 dev_mode = <1>;
 961                 reg = <0x0 0xff920000 0x0 0x1000>;
 962                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 963                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 964                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 965                 power-domains = <&power RK3366_PD_VIO>;
 966                 status = "disabled";
 967         };
 968
 969         vopb: vop@ff930000 {
 970                 compatible = "rockchip,rk3366-vop";
 971                 reg = <0x0 0xff930000 0x0 0x1ffc>;
 972                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 973                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>,
 974                          <&cru HCLK_VOP_FULL>;
 975                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 976                 power-domains = <&power RK3366_PD_VIO>;
 977                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>,
 978                          <&cru SRST_VOP0_AHB>;
 979                 reset-names = "axi", "ahb", "dclk";
 980                 iommus = <&vopb_mmu>;
 981                 status = "disabled";
 982
 983                 vopb_out: port {
 984                         #address-cells = <1>;
 985                         #size-cells = <0>;
 986
 987                         vopb_out_dsi: endpoint@0 {
 988                                 reg = <0>;
 989                                 remote-endpoint = <&dsi_in_vopb>;
 990                         };
 991
 992                         vopb_out_lvds: endpoint@1 {
 993                                 reg = <1>;
 994                                 remote-endpoint = <&lvds_in_vopb>;
 995                         };
 996
 997                         vopb_out_hdmi: endpoint@2 {
 998                                 reg = <2>;
 999                                 remote-endpoint = <&hdmi_in_vopb>;
1000                         };
1001                 };
1002         };
1003
1004         vopb_mmu: iommu@ff932400 {
1005                 compatible = "rockchip,iommu";
1006                 reg = <0x0 0xff932400 0x0 0x100>;
1007                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1008                 interrupt-names = "vop_mmu";
1009                 clocks = <&cru ACLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
1010                 clock-names = "aclk", "hclk";
1011                 power-domains = <&power RK3366_PD_VIO>;
1012                 #iommu-cells = <0>;
1013                 status = "disabled";
1014         };
1015
1016         dsi: dsi@ff960000 {
1017                 compatible = "rockchip,rk3366-mipi-dsi";
1018                 reg = <0x0 0xff960000 0x0 0x4000>;
1019                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1020                 clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>;
1021                 clock-names = "pclk", "hs_clk";
1022                 resets = <&cru SRST_MIPIDSI0>;
1023                 reset-names = "apb";
1024                 phys = <&mipi_dphy>;
1025                 phy-names = "mipi_dphy";
1026                 power-domains = <&power RK3366_PD_VIO>;
1027                 rockchip,grf = <&grf>;
1028                 #address-cells = <1>;
1029                 #size-cells = <0>;
1030                 status = "disabled";
1031
1032                 ports {
1033                         port {
1034                                 #address-cells = <1>;
1035                                 #size-cells = <0>;
1036
1037                                 dsi_in_vopb: endpoint@0 {
1038                                         reg = <0>;
1039                                         remote-endpoint = <&vopb_out_dsi>;
1040                                 };
1041                                 dsi_in_vopl: endpoint@1 {
1042                                         reg = <1>;
1043                                         remote-endpoint = <&vopl_out_dsi>;
1044                                 };
1045                         };
1046                 };
1047         };
1048
1049         mipi_dphy: mipi-dphy@ff968000 {
1050                 compatible = "rockchip,rk3366-mipi-dphy";
1051                 reg = <0x0 0xff968000 0x0 0x4000>;
1052                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>;
1053                 clock-names = "ref", "pclk";
1054                 clock-output-names = "mipi_dphy_pll";
1055                 #clock-cells = <0>;
1056                 resets = <&cru SRST_MIPIDPHYTX>;
1057                 reset-names = "apb";
1058                 #phy-cells = <0>;
1059                 status = "disabled";
1060         };
1061
1062         lvds: lvds@ff968000 {
1063                 compatible = "rockchip,rk3366-lvds";
1064                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff960000 0x0 0x100>;
1065                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1066                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
1067                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1068                 power-domains = <&power RK3366_PD_VIO>;
1069                 pinctrl-names = "lcdc", "gpio";
1070                 pinctrl-0 = <&lcdc_lcdc>;
1071                 pinctrl-1 = <&lcdc_gpio>;
1072                 rockchip,grf = <&grf>;
1073                 status = "disabled";
1074
1075                 ports {
1076                         #address-cells = <1>;
1077                         #size-cells = <0>;
1078
1079                         port@0 {
1080                                 reg = <0>;
1081                                 #address-cells = <1>;
1082                                 #size-cells = <0>;
1083
1084                                 lvds_in_vopb: endpoint@0 {
1085                                         reg = <0>;
1086                                         remote-endpoint = <&vopb_out_lvds>;
1087                                 };
1088                                 lvds_in_vopl: endpoint@1 {
1089                                         reg = <1>;
1090                                         remote-endpoint = <&vopl_out_lvds>;
1091                                 };
1092                         };
1093                 };
1094
1095         };
1096
1097         hdmi: hdmi@ff980000 {
1098                 compatible = "rockchip,rk3366-dw-hdmi";
1099                 reg = <0x0 0xff980000 0x0 0x20000>;
1100                 reg-io-width = <4>;
1101                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1102                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1103                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>,
1104                          <&cru SCLK_HDMI_CEC>, <&cru DCLK_HDMIPHY>;
1105                 clock-names = "iahb", "isfr", "cec", "dclk";
1106                 pinctrl-names = "default";
1107                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1108                 resets = <&cru SRST_HDMI>;
1109                 reset-names = "hdmi";
1110                 //power-domains = <&power RK3366_PD_VIO>;
1111                 rockchip,grf = <&grf>;
1112                 status = "disabled";
1113
1114                 ports {
1115                         port {
1116                                 #address-cells = <1>;
1117                                 #size-cells = <0>;
1118
1119                                 hdmi_in_vopb: endpoint@0 {
1120                                         reg = <0>;
1121                                         remote-endpoint = <&vopb_out_hdmi>;
1122                                 };
1123                         };
1124                 };
1125         };
1126
1127         vpu: vpu_service@ff9a0000 {
1128                 compatible = "rockchip,vpu_service";
1129                 rockchip,grf = <&grf>;
1130                 iommu_enabled = <1>;
1131                 iommus = <&vpu_mmu>;
1132                 reg = <0x0 0xff9a0000 0x0 0x800>;
1133                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1134                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1135                 interrupt-names = "irq_dec", "irq_enc";
1136                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1137                 clock-names = "aclk_vcodec", "hclk_vcodec";
1138                 power-domains = <&power RK3366_PD_VPU>;
1139                 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
1140                 reset-names = "video_h", "video_a";
1141                 name = "vpu_service";
1142                 dev_mode = <0>;
1143                 /* 0 means ion, 1 means drm */
1144                 allocator = <1>;
1145                 status = "disabled";
1146         };
1147
1148         vpu_mmu: iommu@ff9a0800 {
1149                 compatible = "rockchip,iommu";
1150                 reg = <0x0 0xff9a0800 0x0 0x100>;
1151                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1152                 interrupt-names = "vpu_mmu";
1153                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1154                 clock-names = "aclk", "hclk";
1155                 power-domains = <&power RK3366_PD_VPU>;
1156                 #iommu-cells = <0>;
1157                 status = "disabled";
1158         };
1159
1160         rkvdec: rkvdec@ff9b0000 {
1161                 compatible = "rockchip,rkvdec";
1162                 rockchip,grf = <&grf>;
1163                 iommus = <&vdec_mmu>;
1164                 iommu_enabled = <1>;
1165                 reg = <0x0 0xff9b0000 0x0 0x400>;
1166                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1167                 interrupt-names = "irq_dec";
1168                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
1169                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
1170                 power-domains = <&power RK3366_PD_RKVDEC>;
1171                 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
1172                 reset-names = "video_h", "video_a";
1173                 dev_mode = <2>;
1174                 name = "rkvdec";
1175                 /* 0 means ion, 1 means drm */
1176                 allocator = <1>;
1177                 status = "disabled";
1178         };
1179
1180         vdec_mmu: iommu@ff9b0480 {
1181                 compatible = "rockchip,iommu";
1182                 reg = <0x0 0xff9b0480 0x0 0x40>,
1183                         <0x0 0xff9b04c0 0x0 0x40>;
1184                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1185                 interrupt-names = "vdec_mmu";
1186                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
1187                 clock-names = "aclk", "hclk";
1188                 power-domains = <&power RK3366_PD_RKVDEC>;
1189                 #iommu-cells = <0>;
1190                 status = "disabled";
1191         };
1192
1193         pinctrl: pinctrl {
1194                 compatible = "rockchip,rk3366-pinctrl";
1195                 rockchip,grf = <&grf>;
1196                 rockchip,pmu = <&pmugrf>;
1197                 #address-cells = <0x2>;
1198                 #size-cells = <0x2>;
1199                 ranges;
1200
1201                 gpio0: gpio0@ff750000 {
1202                         compatible = "rockchip,gpio-bank";
1203                         reg = <0x0 0xff750000 0x0 0x100>;
1204                         clocks = <&cru PCLK_GPIO0>;
1205                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1206
1207                         gpio-controller;
1208                         #gpio-cells = <0x2>;
1209
1210                         interrupt-controller;
1211                         #interrupt-cells = <0x2>;
1212                 };
1213
1214                 gpio1: gpio1@ff780000 {
1215                         compatible = "rockchip,gpio-bank";
1216                         reg = <0x0 0xff758000 0x0 0x100>;
1217                         clocks = <&cru PCLK_GPIO1>;
1218                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1219
1220                         gpio-controller;
1221                         #gpio-cells = <0x2>;
1222
1223                         interrupt-controller;
1224                         #interrupt-cells = <0x2>;
1225                 };
1226
1227                 gpio2: gpio2@ff790000 {
1228                         compatible = "rockchip,gpio-bank";
1229                         reg = <0x0 0xff790000 0x0 0x100>;
1230                         clocks = <&cru PCLK_GPIO2>;
1231                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1232
1233                         gpio-controller;
1234                         #gpio-cells = <0x2>;
1235
1236                         interrupt-controller;
1237                         #interrupt-cells = <0x2>;
1238                 };
1239
1240                 gpio3: gpio3@ff7a0000 {
1241                         compatible = "rockchip,gpio-bank";
1242                         reg = <0x0 0xff7a0000 0x0 0x100>;
1243                         clocks = <&cru PCLK_GPIO3>;
1244                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1245
1246                         gpio-controller;
1247                         #gpio-cells = <0x2>;
1248
1249                         interrupt-controller;
1250                         #interrupt-cells = <0x2>;
1251                 };
1252
1253                 gpio4: gpio4@ff7b0000 {
1254                         compatible = "rockchip,gpio-bank";
1255                         reg = <0x0 0xff7b0000 0x0 0x100>;
1256                         clocks = <&cru PCLK_GPIO4>;
1257                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1258
1259                         gpio-controller;
1260                         #gpio-cells = <0x2>;
1261
1262                         interrupt-controller;
1263                         #interrupt-cells = <0x2>;
1264                 };
1265
1266                 gpio5: gpio5@ff7c0000 {
1267                         compatible = "rockchip,gpio-bank";
1268                         reg = <0x0 0xff7c0000 0x0 0x100>;
1269                         clocks = <&cru PCLK_GPIO5>;
1270                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1271
1272                         gpio-controller;
1273                         #gpio-cells = <0x2>;
1274
1275                         interrupt-controller;
1276                         #interrupt-cells = <0x2>;
1277                 };
1278
1279                 pcfg_pull_up: pcfg-pull-up {
1280                         bias-pull-up;
1281                 };
1282
1283                 pcfg_pull_down: pcfg-pull-down {
1284                         bias-pull-down;
1285                 };
1286
1287                 pcfg_pull_none: pcfg-pull-none {
1288                         bias-disable;
1289                 };
1290
1291                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1292                         bias-disable;
1293                         drive-strength = <12>;
1294                 };
1295
1296                 emmc {
1297                         emmc_clk: emmc-clk {
1298                                 rockchip,pins =
1299                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
1300                         };
1301
1302                         emmc_cmd: emmc-cmd {
1303                                 rockchip,pins =
1304                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
1305                         };
1306
1307                         emmc_pwr: emmc-pwr {
1308                                 rockchip,pins =
1309                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
1310                         };
1311
1312                         emmc_bus1: emmc-bus1 {
1313                                 rockchip,pins =
1314                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
1315                         };
1316
1317                         emmc_bus4: emmc-bus4 {
1318                                 rockchip,pins =
1319                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1320                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1321                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1322                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1323                         };
1324
1325                         emmc_bus8: emmc-bus8 {
1326                                 rockchip,pins =
1327                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1328                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1329                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1330                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
1331                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
1332                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
1333                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
1334                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
1335                         };
1336                 };
1337
1338                 sdmmc {
1339                         sdmmc_cd: sdmmc-cd {
1340                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1341                         };
1342
1343                         sdmmc_bus1: sdmmc-bus1 {
1344                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1345                         };
1346
1347                         sdmmc_bus4: sdmmc-bus4 {
1348                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1349                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1350                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1351                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1352                         };
1353
1354                         sdmmc_clk: sdmmc-clk {
1355                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1356                         };
1357
1358                         sdmmc_cmd: sdmmc-cmd {
1359                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1360                         };
1361                 };
1362
1363                 sdio {
1364                         sdio_bus1: sdio-bus1 {
1365                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1366                         };
1367
1368                         sdio_bus4: sdio-bus4 {
1369                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1370                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1371                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1372                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1373                         };
1374
1375                         sdio_cmd: sdio-cmd {
1376                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1377                         };
1378
1379                         sdio_clk: sdio-clk {
1380                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1381                         };
1382
1383                         sdio_cd: sdio-cd {
1384                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1385                         };
1386
1387                         sdio_wp: sdio-wp {
1388                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1389                         };
1390
1391                         sdio_int: sdio-int {
1392                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1393                         };
1394
1395                         sdio_pwr: sdio-pwr {
1396                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1397                         };
1398                 };
1399
1400                 hdmi_i2c {
1401                         hdmii2c_xfer: hdmii2c-xfer {
1402                                 rockchip,pins =
1403                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
1404                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
1405                         };
1406                 };
1407
1408                 hdmi_pin {
1409                         hdmi_cec: hdmi-cec {
1410                                 rockchip,pins =
1411                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
1412                         };
1413                 };
1414
1415                 i2c0 {
1416                         i2c0_xfer: i2c0-xfer {
1417                                 rockchip,pins =
1418                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
1419                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
1420                         };
1421                 };
1422
1423                 i2c1 {
1424                         i2c1_xfer: i2c1-xfer {
1425                                 rockchip,pins =
1426                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1427                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1428                         };
1429                 };
1430
1431                 i2c2 {
1432                         i2c2_xfer: i2c2-xfer {
1433                                 rockchip,pins =
1434                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1435                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1436                         };
1437
1438                         i2c2_gpio: i2c2-gpio {
1439                                 rockchip,pins =
1440                                         <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1441                                         <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1442                         };
1443                 };
1444
1445                 i2c3 {
1446                         i2c3_xfer: i2c3-xfer {
1447                                 rockchip,pins =
1448                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1449                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1450                         };
1451                 };
1452
1453                 i2c4 {
1454                         i2c4_xfer: i2c4-xfer {
1455                                 rockchip,pins =
1456                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1457                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1458                         };
1459
1460                         i2c4_gpio: i2c4-gpio {
1461                                 rockchip,pins =
1462                                         <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1463                                         <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1464                         };
1465                 };
1466
1467                 i2c5 {
1468                         i2c5_xfer: i2c5-xfer {
1469                                 rockchip,pins =
1470                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1471                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1472                         };
1473                         i2c5_gpio: i2c5-gpio {
1474                                 rockchip,pins =
1475                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1476                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1477                         };
1478                 };
1479
1480                 i2s {
1481                         i2s_8ch_bus: i2s-8ch-bus {
1482                                 rockchip,pins =
1483                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1484                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1485                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1486                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1487                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1488                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1489                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1490                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1491                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1492                         };
1493                 };
1494
1495                 spdif {
1496                         spdif_bus: spdif-bus {
1497                                 rockchip,pins =
1498                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1499                         };
1500                 };
1501
1502                 spi0 {
1503                         spi0_clk: spi0-clk {
1504                                 rockchip,pins =
1505                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1506                         };
1507                         spi0_cs0: spi0-cs0 {
1508                                 rockchip,pins =
1509                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1510                         };
1511                         spi0_cs1: spi0-cs1 {
1512                                 rockchip,pins =
1513                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1514                         };
1515                         spi0_tx: spi0-tx {
1516                                 rockchip,pins =
1517                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1518                         };
1519                         spi0_rx: spi0-rx {
1520                                 rockchip,pins =
1521                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1522                         };
1523                 };
1524
1525                 spi1 {
1526                         spi1_clk: spi1-clk {
1527                                 rockchip,pins =
1528                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1529                         };
1530                         spi1_cs0: spi1-cs0 {
1531                                 rockchip,pins =
1532                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1533                         };
1534                         spi1_tx: spi1-tx {
1535                                 rockchip,pins =
1536                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1537                         };
1538                         spi1_rx: spi1-rx {
1539                                 rockchip,pins =
1540                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1541                         };
1542                 };
1543
1544                 scr {
1545                         scr_clk: scr-clk {
1546                                 rockchip,pins =
1547                                         <5 8 RK_FUNC_2 &pcfg_pull_none>;
1548                         };
1549
1550                         scr_io: scr-io {
1551                                 rockchip,pins =
1552                                         <5 9 RK_FUNC_2 &pcfg_pull_up>;
1553                         };
1554
1555                         scr_rst: scr-rst {
1556                                 rockchip,pins =
1557                                         <5 10 RK_FUNC_1 &pcfg_pull_none>;
1558                         };
1559
1560                         scr_detect: scr-detect {
1561                                 rockchip,pins =
1562                                         <5 11 RK_FUNC_1 &pcfg_pull_none>;
1563                         };
1564                 };
1565
1566                 uart0 {
1567                         uart0_xfer: uart0-xfer {
1568                                 rockchip,pins =
1569                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1570                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1571                         };
1572
1573                         uart0_cts: uart0-cts {
1574                                 rockchip,pins =
1575                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1576                         };
1577
1578                         uart0_rts: uart0-rts {
1579                                 rockchip,pins =
1580                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1581                         };
1582                 };
1583
1584                 uart2_t0 {
1585                         uart2_t0_xfer: uart2_t0-xfer {
1586                                 rockchip,pins =
1587                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1588                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1589                         };
1590                         /* no rts / cts for uart2 */
1591                 };
1592
1593                 uart2_t1 {
1594                         uart2_t1_xfer: uart2_t1-xfer {
1595                                 rockchip,pins =
1596                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1597                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1598                         };
1599                         /* no rts / cts for uart2 */
1600                 };
1601
1602                 uart2_t2 {
1603                         uart2_t2_xfer: uart2_t2-xfer {
1604                                 rockchip,pins =
1605                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1606                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1607                         };
1608                         /* no rts / cts for uart2 */
1609                 };
1610
1611                 uart3 {
1612                         uart3_xfer: uart3-xfer {
1613                                 rockchip,pins =
1614                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1615                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1616                         };
1617
1618                         uart3_cts: uart3-cts {
1619                                 rockchip,pins =
1620                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1621                         };
1622
1623                         uart3_rts: uart3-rts {
1624                                 rockchip,pins =
1625                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1626                         };
1627                 };
1628
1629                 pwm0 {
1630                         pwm0_pin: pwm0-pin {
1631                                 rockchip,pins =
1632                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1633                         };
1634                 };
1635
1636                 pwm1 {
1637                         pwm1_pin: pwm1-pin {
1638                                 rockchip,pins =
1639                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1640                         };
1641                 };
1642
1643                 pwm2_t0 {
1644                         pwm2_t0_pin: pwm2_t0-pin {
1645                                 rockchip,pins =
1646                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1647                         };
1648                 };
1649
1650                 pwm2_t1 {
1651                         pwm2_t1_pin: pwm2_t1-pin {
1652                                 rockchip,pins =
1653                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1654                         };
1655                 };
1656
1657                 pwm3_t0 {
1658                         pwm3_t0_pin: pwm3_t0-pin {
1659                                 rockchip,pins =
1660                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1661                         };
1662                 };
1663
1664                 pwm3_t1 {
1665                         pwm3_t1_pin: pwm3_t1-pin {
1666                                 rockchip,pins =
1667                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1668                         };
1669                 };
1670
1671                 pwm3_t2 {
1672                         pwm3_t2_pin: pwm3_t2-pin {
1673                                 rockchip,pins =
1674                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1675                         };
1676                 };
1677
1678                 lcdc {
1679                         lcdc_lcdc: lcdc-lcdc {
1680                                 rockchip,pins =
1681                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1682                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1683                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1684                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1685                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1686                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1687                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1688                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1689                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1690                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1691                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1692                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1693                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1694                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1695                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1696                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1697                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1698                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1699                         };
1700
1701                         lcdc_gpio: lcdc-gpio {
1702                                 rockchip,pins =
1703                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1704                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1705                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1706                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1707                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1708                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1709                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1710                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1711                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1712                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1713                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1714                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1715                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1716                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1717                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1718                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1719                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1720                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1721                         };
1722                 };
1723
1724                 gmac {
1725                         rgmii_pins: rgmii-pins {
1726                                 rockchip,pins =
1727                                         /* mac_rxd3 */
1728                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1729                                         /* mac_rxd2 */
1730                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1731                                         /* mac_txd3 */
1732                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1733                                         /* mac_txd2 */
1734                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1735                                         /* mac_rxd1 */
1736                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1737                                         /* mac_rxd0 */
1738                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1739                                         /* mac_txd1 */
1740                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1741                                         /* mac_txd0 */
1742                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1743                                         /* mac_txclkout */
1744                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1745                                         /* mac_crs */
1746                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1747                                         /* mac_rxclkin */
1748                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1749                                         /* mac_mdio */
1750                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1751                                         /* mac_txen */
1752                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1753                                         /* mac_clk */
1754                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1755                                         /* mac_rxer */
1756                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1757                                         /* mac_rxdv */
1758                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1759                                         /* mac_mdc */
1760                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1761                         };
1762
1763                         rmii_pins: rmii-pins {
1764                                 rockchip,pins =
1765                                         /* mac_rxd1 */
1766                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1767                                         /* mac_rxd0 */
1768                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1769                                         /* mac_txd1 */
1770                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1771                                         /* mac_txd0 */
1772                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1773                                         /* mac_crs */
1774                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1775                                         /* mac_rxclkin */
1776                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1777                                         /* mac_mdio */
1778                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1779                                         /* mac_txen */
1780                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1781                                         /* mac_clk */
1782                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1783                                         /* mac_rxer */
1784                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1785                                         /* mac_rxdv */
1786                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1787                                         /* mac_mdc */
1788                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1789                         };
1790                 };
1791
1792                 eth_phy {
1793                         eth_phy_pwr: eth-phy-pwr {
1794                                 rockchip,pins =
1795                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1796                         };
1797                 };
1798
1799                 tsadc_pin {
1800                         tsadc_gpio: tsadc-gpio {
1801                                 rockchip,pins =
1802                                         <0 22 RK_FUNC_GPIO &pcfg_pull_none>;
1803                         };
1804
1805                         tsadc_int: tsadc-int {
1806                                 rockchip,pins =
1807                                         <0 22 RK_FUNC_2 &pcfg_pull_none>;
1808                         };
1809                 };
1810
1811                 usb2 {
1812                         host_vbus_drv: host-vbus-drv {
1813                                 rockchip,pins =
1814                                         <0 16 RK_FUNC_GPIO &pcfg_pull_none>;
1815                         };
1816                 };
1817
1818         };
1819
1820         gpu: gpu@ffa30000 {
1821                 compatible = "arm,malit764",
1822                              "arm,malit76x",
1823                              "arm,malit7xx",
1824                              "arm,mali-midgard";
1825
1826                 reg = <0x0 0xffa30000 0 0x10000>;
1827
1828                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1829                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1830                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1831                 interrupt-names = "GPU", "MMU", "JOB";
1832
1833                 clocks = <&cru ACLK_GPU>;
1834                 clock-names = "clk_mali";
1835                 #cooling-cells = <2>; /* min followed by max */
1836                 power-domains = <&power RK3366_PD_GPU>;
1837                 operating-points-v2 = <&gpu_opp_table>;
1838                 status = "disabled";
1839
1840                 power_model {
1841                         compatible = "arm,mali-simple-power-model";
1842                         voltage = <900>;
1843                         frequency = <500>;
1844                         static-power = <300>;
1845                         dynamic-power = <1780>;
1846                         ts = <32000 4700 (-80) 2>;
1847                         thermal-zone = "gpu-thermal";
1848                 };
1849         };
1850
1851         gpu_opp_table: gpu_opp_table {
1852                 compatible = "operating-points-v2";
1853                 opp-shared;
1854
1855                 opp-96000000 {
1856                         opp-hz = /bits/ 64 <96000000>;
1857                         opp-microvolt = <1100000>;
1858                 };
1859                 opp-192000000 {
1860                         opp-hz = /bits/ 64 <192000000>;
1861                         opp-microvolt = <1100000>;
1862                 };
1863                 opp-288000000 {
1864                         opp-hz = /bits/ 64 <288000000>;
1865                         opp-microvolt = <1100000>;
1866                 };
1867                 opp-375000000 {
1868                         opp-hz = /bits/ 64 <375000000>;
1869                         opp-microvolt = <1125000>;
1870                 };
1871                 opp-480000000 {
1872                         opp-hz = /bits/ 64 <480000000>;
1873                         opp-microvolt = <1200000>;
1874                 };
1875         };
1876 };