2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3366-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/display/mipi_dsi.h>
50 #include <dt-bindings/power/rk3366-power.h>
51 #include <dt-bindings/soc/rockchip_boot-mode.h>
52 #include <dt-bindings/thermal/thermal.h>
55 compatible = "rockchip,rk3366";
56 interrupt-parent = <&gic>;
75 #address-cells = <0x2>;
80 compatible = "arm,cortex-a53","arm,armv8";
82 enable-method = "psci";
83 clocks = <&cru ARMCLK>;
84 operating-points-v2 = <&cpu0_opp_table>;
85 cpu-idle-states = <&cpu_sleep>;
86 #cooling-cells = <2>; /* min followed by max */
87 dynamic-power-coefficient = <166>;
92 compatible = "arm,cortex-a53","arm,armv8";
94 enable-method = "psci";
95 operating-points-v2 = <&cpu0_opp_table>;
96 cpu-idle-states = <&cpu_sleep>;
101 compatible = "arm,cortex-a53","arm,armv8";
103 enable-method = "psci";
104 operating-points-v2 = <&cpu0_opp_table>;
105 cpu-idle-states = <&cpu_sleep>;
110 compatible = "arm,cortex-a53","arm,armv8";
112 enable-method = "psci";
113 operating-points-v2 = <&cpu0_opp_table>;
114 cpu-idle-states = <&cpu_sleep>;
118 entry-method = "psci";
119 cpu_sleep: cpu-sleep-0 {
120 compatible = "arm,idle-state";
122 arm,psci-suspend-param = <0x0010000>;
123 entry-latency-us = <350>;
124 exit-latency-us = <600>;
125 min-residency-us = <1150>;
130 cpu0_opp_table: opp_table0 {
131 compatible = "operating-points-v2";
135 opp-hz = /bits/ 64 <408000000>;
136 opp-microvolt = <950000>;
137 clock-latency-ns = <40000>;
141 opp-hz = /bits/ 64 <600000000>;
142 opp-microvolt = <950000>;
145 opp-hz = /bits/ 64 <816000000>;
146 opp-microvolt = <1000000>;
149 opp-hz = /bits/ 64 <1008000000>;
150 opp-microvolt = <1075000>;
153 opp-hz = /bits/ 64 <1200000000>;
154 opp-microvolt = <1175000>;
157 opp-hz = /bits/ 64 <1296000000>;
158 opp-microvolt = <1250000>;
163 compatible = "arm,psci-1.0";
168 compatible = "arm,armv8-timer";
169 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
170 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
171 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
172 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
176 compatible = "arm,cortex-a53-pmu";
177 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
181 interrupt-affinity = <&cpu0>,
188 compatible = "fixed-clock";
190 clock-frequency = <24000000>;
191 clock-output-names = "xin24m";
194 gic: interrupt-controller@ffb71000 {
195 compatible = "arm,gic-400";
196 interrupt-controller;
197 #interrupt-cells = <3>;
198 #address-cells = <0>;
200 reg = <0x0 0xffb71000 0x0 0x1000>,
201 <0x0 0xffb72000 0x0 0x1000>,
202 <0x0 0xffb74000 0x0 0x2000>,
203 <0x0 0xffb76000 0x0 0x2000>;
204 interrupts = <GIC_PPI 9
205 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
208 nandc0: nandc@ff0c0000 {
209 compatible = "rockchip,rk-nandc";
210 reg = <0x0 0xff0c0000 0x0 0x4000>;
211 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
214 clock-names = "clk_nandc", "hclk_nandc";
218 saradc: saradc@ff100000 {
219 compatible = "rockchip,saradc";
220 reg = <0x0 0xff100000 0x0 0x100>;
221 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
222 #io-channel-cells = <1>;
223 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
224 clock-names = "saradc", "apb_pclk";
229 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
230 reg = <0x0 0xff110000 0x0 0x1000>;
231 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
232 clock-names = "spiclk", "apb_pclk";
233 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
236 #address-cells = <1>;
242 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
243 reg = <0x0 0xff120000 0x0 0x1000>;
244 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
245 clock-names = "spiclk", "apb_pclk";
246 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
249 #address-cells = <1>;
254 scr: rkscr@ff1d0000 {
255 compatible = "rockchip-scr";
256 reg = <0x0 0xff1d0000 0x0 0x10000>;
257 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
258 #address-cells = <1>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
262 clocks = <&cru PCLK_SIM>;
263 clock-names = "g_pclk_sim_card";
268 soc_thermal: soc-thermal {
269 polling-delay-passive = <100>; /* milliseconds */
270 polling-delay = <1000>; /* milliseconds */
271 sustainable-power = <1600>; /* milliwatts */
273 thermal-sensors = <&tsadc 0>;
276 threshold: trip-point@0 {
277 temperature = <70000>; /* millicelsius */
278 hysteresis = <2000>; /* millicelsius */
281 target: trip-point@1 {
282 temperature = <85000>; /* millicelsius */
283 hysteresis = <2000>; /* millicelsius */
287 temperature = <95000>; /* millicelsius */
288 hysteresis = <2000>; /* millicelsius */
297 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
302 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
307 gpu_thermal: gpu-thermal {
308 polling-delay-passive = <100>; /* milliseconds */
309 polling-delay = <1000>; /* milliseconds */
311 thermal-sensors = <&tsadc 1>;
315 tsadc: tsadc@ff260000 {
316 compatible = "rockchip,rk3366-tsadc";
317 reg = <0x0 0xff260000 0x0 0x100>;
318 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
320 clock-names = "tsadc", "apb_pclk";
321 resets = <&cru SRST_TSADC>;
322 reset-names = "tsadc-apb";
323 pinctrl-names = "default";
324 pinctrl-0 = <&tsadc_gpio>;
325 #thermal-sensor-cells = <1>;
326 rockchip,hw-tshut-temp = <95000>;
330 sdmmc: rksdmmc@ff400000 {
331 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
332 clock-freq-min-max = <400000 150000000>;
333 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
334 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
335 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
336 fifo-depth = <0x100>;
337 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
338 reg = <0x0 0xff400000 0x0 0x4000>;
342 sdio: rksdmmc@ff410000 {
343 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
344 clock-freq-min-max = <400000 150000000>;
345 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
346 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
347 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
348 fifo-depth = <0x100>;
349 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
350 reg = <0x0 0xff410000 0x0 0x4000>;
354 emmc: rksdmmc@ff420000 {
355 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
356 clock-freq-min-max = <400000 150000000>;
357 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
358 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
359 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
360 fifo-depth = <0x100>;
361 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
362 reg = <0x0 0xff420000 0x0 0x4000>;
367 compatible = "rockchip,rk3366-gmac";
368 reg = <0x0 0xff440000 0x0 0x10000>;
369 rockchip,grf = <&grf>;
370 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
371 interrupt-names = "macirq";
372 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
373 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
374 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
376 clock-names = "stmmaceth", "mac_clk_rx",
377 "mac_clk_tx", "clk_mac_ref",
378 "clk_mac_refout", "aclk_mac",
380 resets = <&cru SRST_MAC>;
381 reset-names = "stmmaceth";
386 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
387 reg = <0x0 0xff728000 0x0 0x1000>;
388 clocks = <&cru PCLK_I2C0>;
390 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&i2c0_xfer>;
393 #address-cells = <1>;
399 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
400 reg = <0x0 0xff140000 0x0 0x1000>;
401 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
402 #address-cells = <1>;
405 clocks = <&cru PCLK_I2C2>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&i2c2_xfer>;
412 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
413 reg = <0x0 0xff150000 0x0 0x1000>;
414 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
415 #address-cells = <1>;
418 clocks = <&cru PCLK_I2C3>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&i2c3_xfer>;
425 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
426 reg = <0x0 0xff160000 0x0 0x1000>;
427 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
428 #address-cells = <1>;
431 clocks = <&cru PCLK_I2C4>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&i2c4_xfer>;
438 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
439 reg = <0x0 0xff170000 0x0 0x1000>;
440 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
441 #address-cells = <1>;
444 clocks = <&cru PCLK_I2C5>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&i2c5_xfer>;
450 uart0: serial@ff180000 {
451 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
452 reg = <0x0 0xff180000 0x0 0x100>;
453 clock-frequency = <24000000>;
454 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
455 clock-names = "baudclk", "apb_pclk";
456 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
464 uart3: serial@ff1b0000 {
465 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
466 reg = <0x0 0xff1b0000 0x0 0x100>;
467 clock-frequency = <24000000>;
468 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
469 clock-names = "baudclk", "apb_pclk";
470 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
478 usb_host0_ehci: usb@ff480000 {
479 compatible = "generic-ehci";
480 reg = <0x0 0xff480000 0x0 0x20000>;
481 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
483 clock-names = "sclk_otgphy0", "hclk_host0";
484 phys = <&u2phy_host>;
489 usb_host0_ohci: usb@ff4a0000 {
490 compatible = "generic-ohci";
491 reg = <0x0 0xff4a0000 0x0 0x20000>;
492 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
494 clock-names = "sclk_otgphy0", "hclk_host0";
498 usb_otg: usb@ff4c0000 {
499 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
501 reg = <0x0 0xff4c0000 0x0 0x40000>;
502 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cru HCLK_OTG>;
506 g-np-tx-fifo-size = <16>;
507 g-rx-fifo-size = <275>;
508 g-tx-fifo-size = <256 128 128 64 64 32>;
514 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
515 reg = <0x0 0xff660000 0x0 0x1000>;
516 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
517 #address-cells = <1>;
520 clocks = <&cru PCLK_I2C1>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&i2c1_xfer>;
527 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
528 reg = <0x0 0xff680000 0x0 0x10>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&pwm0_pin>;
532 clocks = <&cru PCLK_RKPWM>;
538 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
539 reg = <0x0 0xff680010 0x0 0x10>;
541 pinctrl-names = "default";
542 pinctrl-0 = <&pwm1_pin>;
543 clocks = <&cru PCLK_RKPWM>;
549 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
550 reg = <0x0 0xff680020 0x0 0x10>;
552 clocks = <&cru PCLK_RKPWM>;
558 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
559 reg = <0x0 0xff680030 0x0 0x10>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&pwm3_t2_pin>;
563 clocks = <&cru PCLK_RKPWM>;
568 uart2: serial@ff690000 {
569 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
570 reg = <0x0 0xff690000 0x0 0x100>;
571 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
573 clock-names = "baudclk", "apb_pclk";
576 pinctrl-names = "default";
577 pinctrl-0 = <&uart2_t1_xfer>;
581 pmu: power-management@ff730000 {
582 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
583 reg = <0x0 0xff730000 0x0 0x1000>;
585 power: power-controller {
587 compatible = "rockchip,rk3366-power-controller";
588 #power-domain-cells = <1>;
589 #address-cells = <1>;
593 * Note: Although SCLK_* are the working clocks
594 * of device without including on the NOC, needed for
597 * The clocks on the which NOC:
598 * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
599 * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
600 * ACLK_ISP is on ACLK_ISP_NIU.
601 * ACLK_HDCP is on ACLK_HDCP_NIU.
602 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
604 * Which clock are device clocks:
606 * *_IEP IEP:Image Enhancement Processor
607 * *_ISP ISP:Image Signal Processing
608 * *_VOP* VOP:Visual Output Processor
615 reg = <RK3366_PD_VIO>;
616 clocks = <&cru ACLK_IEP>,
620 <&cru ACLK_VOP_FULL>,
621 <&cru ACLK_VOP_LITE>,
623 <&cru DCLK_VOP_FULL>,
624 <&cru DCLK_VOP_LITE>,
628 <&cru HCLK_VOP_FULL>,
629 <&cru HCLK_VOP_LITE>,
630 <&cru HCLK_VIO_HDCPMMU>,
631 <&cru PCLK_HDMI_CTRL>,
633 <&cru PCLK_MIPI_DSI0>,
634 <&cru SCLK_VOP_FULL_PWM>,
638 <&cru SCLK_HDMI_CEC>,
639 <&cru SCLK_HDMI_HDCP>;
643 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
644 * (video endecoder & decoder) clocks that on the
645 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
648 reg = <RK3366_PD_VPU>;
649 clocks = <&cru ACLK_VIDEO>,
654 * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
655 * (video decoder) clocks that on the
656 * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
659 reg = <RK3366_PD_RKVDEC>;
660 clocks = <&cru ACLK_RKVDEC>,
665 reg = <RK3366_PD_VIDEO>;
666 clocks = <&cru ACLK_VIDEO>,
670 <&cru SCLK_HEVC_CABAC>,
671 <&cru SCLK_HEVC_CORE>;
675 * Note: ACLK_GPU is the GPU clock,
676 * and on the ACLK_GPU_NIU (NOC).
679 reg = <RK3366_PD_GPU>;
680 clocks = <&cru ACLK_GPU>;
685 pmugrf: syscon@ff738000 {
686 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
687 reg = <0x0 0xff738000 0x0 0x1000>;
690 compatible = "syscon-reboot-mode";
692 mode-normal = <BOOT_NORMAL>;
693 mode-recovery = <BOOT_RECOVERY>;
694 mode-fastboot = <BOOT_FASTBOOT>;
695 mode-loader = <BOOT_LOADER>;
700 compatible = "arm,amba-bus";
701 #address-cells = <2>;
705 dmac_peri: dma-controller@ff250000 {
706 compatible = "arm,pl330", "arm,primecell";
707 reg = <0x0 0xff250000 0x0 0x4000>;
708 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&cru ACLK_DMAC_PERI>;
712 clock-names = "apb_pclk";
715 dmac_bus: dma-controller@ff600000 {
716 compatible = "arm,pl330", "arm,primecell";
717 reg = <0x0 0xff600000 0x0 0x4000>;
718 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&cru ACLK_DMAC_BUS>;
722 clock-names = "apb_pclk";
726 cru: clock-controller@ff760000 {
727 compatible = "rockchip,rk3366-cru";
728 reg = <0x0 0xff760000 0x0 0x1000>;
729 rockchip,grf = <&grf>;
733 <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
734 <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
735 <&cru PLL_CPLL>, <&cru PLL_GPLL>,
736 <&cru PLL_NPLL>, <&cru PLL_MPLL>,
737 <&cru PLL_WPLL>, <&cru PLL_BPLL>,
738 <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
739 <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
740 <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
742 assigned-clock-rates =
745 <750000000>, <576000000>,
746 <594000000>, <594000000>,
747 <960000000>, <520000000>,
748 <375000000>, <288000000>,
749 <100000000>, <100000000>,
750 <288000000>, <288000000>,
752 assigned-clock-parents =
753 <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
754 <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
757 grf: syscon@ff770000 {
758 compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd";
759 reg = <0x0 0xff770000 0x0 0x1000>;
760 #address-cells = <1>;
764 compatible = "rockchip,rk3366-usb2phy";
766 clock-output-names = "sclk_otgphy0_480m";
768 u2phy_host: host-port {
770 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
771 interrupt-names = "linestate";
777 wdt: watchdog@ff800000 {
778 compatible = "snps,dw-wdt";
779 reg = <0x0 0xff800000 0x0 0x100>;
780 clocks = <&cru PCLK_WDT>;
781 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
785 spdif: spdif@ff880000 {
786 compatible = "rockchip,rk3366-spdif";
787 reg = <0x0 0xff880000 0x0 0x1000>;
788 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
789 dmas = <&dmac_bus 3>;
791 clock-names = "mclk", "hclk";
792 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
793 pinctrl-names = "default";
794 pinctrl-0 = <&spdif_bus>;
798 i2s_2ch: i2s-2ch@ff890000 {
799 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
800 reg = <0x0 0xff890000 0x0 0x1000>;
801 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
802 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
803 dma-names = "tx", "rx";
804 clock-names = "i2s_clk", "i2s_hclk";
805 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
809 i2s_8ch: i2s-8ch@ff898000 {
810 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
811 reg = <0x0 0xff898000 0x0 0x1000>;
812 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
813 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
814 dma-names = "tx", "rx";
815 clock-names = "i2s_clk", "i2s_hclk";
816 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
817 pinctrl-names = "default";
818 pinctrl-0 = <&i2s_8ch_bus>;
823 compatible = "rockchip,rk-fb";
824 rockchip,disp-mode = <DUAL>;
829 compatible = "rockchip,screen";
833 vop_lite: vop@ff8f0000 {
834 compatible = "rockchip,rk3366-lcdc-lite";
835 rockchip,grf = <&grf>;
836 rockchip,pwr18 = <0>;
837 rockchip,iommu-enabled = <1>;
838 reg = <0x0 0xff8f0000 0x0 0x1000>;
839 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
841 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
842 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
843 reset-names = "axi", "ahb", "dclk";
849 compatible = "rockchip,vopl_mmu";
850 reg = <0x0 0xff8f0f00 0x0 0x100>;
851 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
852 interrupt-names = "vopl_mmu";
857 compatible = "rockchip,iep";
859 reg = <0x0 0xff900000 0x0 0x800>;
860 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
862 clock-names = "aclk_iep", "hclk_iep";
868 compatible = "rockchip,rga2";
870 reg = <0x0 0xff920000 0x0 0x1000>;
871 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
873 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
877 vop_big: vop@ff930000 {
878 compatible = "rockchip,rk3366-lcdc-big";
879 rockchip,grf = <&grf>;
880 rockchip,prop = <PRMRY>;
881 rockchip,pwr18 = <0>;
882 rockchip,iommu-enabled = <1>;
883 reg = <0x0 0xff930000 0x0 0x23f0>;
884 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
886 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
887 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
888 reset-names = "axi", "ahb", "dclk";
894 compatible = "rockchip,vopb_mmu";
895 reg = <0x0 0xff932400 0x0 0x100>;
896 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
897 interrupt-names = "vop_mmu";
903 compatible = "rockchip,iep_mmu";
904 reg = <0x0 0xff900800 0x0 0x100>;
905 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
906 interrupt-names = "iep_mmu";
912 compatible = "rockchip,vpu_mmu";
913 reg = <0x0 0xff9a0800 0x0 0x100>;
914 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
915 interrupt-names = "vpu_mmu";
921 compatible = "rockchip,vdec_mmu";
922 reg = <0x0 0xff9b0480 0x0 0x40>,
923 <0x0 0xff9b04c0 0x0 0x40>;
924 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
925 interrupt-names = "vdec_mmu";
929 dsihost0: mipi@ff960000 {
930 compatible = "rockchip,rk3366-dsi";
932 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
933 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
934 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
936 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
940 lvds: lvds@ff968000 {
941 compatible = "rockchip,rk3366-lvds";
942 rockchip,grf = <&grf>;
943 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
944 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
945 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
946 clock-names = "pclk_lvds", "pclk_lvds_ctl";
950 hdmi: hdmi@ff980000 {
951 compatible = "rockchip,rk3366-hdmi";
952 reg = <0x0 0xff980000 0x0 0x20000>;
953 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&cru PCLK_HDMI_CTRL>,
956 <&cru SCLK_HDMI_HDCP>,
957 <&cru SCLK_HDMI_CEC>,
959 clock-names = "pclk_hdmi",
963 resets = <&cru SRST_HDMI>;
964 reset-names = "hdmi";
965 pinctrl-names = "default", "gpio";
966 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
967 pinctrl-1 = <&i2c5_gpio>;
971 vpu: vpu_service@ff9a0000 {
972 compatible = "rockchip,vpu_service";
973 rockchip,grf = <&grf>;
975 reg = <0x0 0xff9a0000 0x0 0x800>;
976 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
978 interrupt-names = "irq_dec", "irq_enc";
979 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
980 clock-names = "aclk_vcodec", "hclk_vcodec";
981 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
982 reset-names = "video_h", "video_a";
983 name = "vpu_service";
988 rkvdec: rkvdec@ff9b0000 {
989 compatible = "rockchip,rkvdec";
990 rockchip,grf = <&grf>;
992 reg = <0x0 0xff9b0000 0x0 0x400>;
993 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
994 interrupt-names = "irq_dec";
995 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
996 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
997 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
998 reset-names = "video_h", "video_a";
1001 status = "disabled";
1005 compatible = "rockchip,rk3366-pinctrl";
1006 rockchip,grf = <&grf>;
1007 rockchip,pmu = <&pmugrf>;
1008 #address-cells = <0x2>;
1009 #size-cells = <0x2>;
1012 gpio0: gpio0@ff750000 {
1013 compatible = "rockchip,gpio-bank";
1014 reg = <0x0 0xff750000 0x0 0x100>;
1015 clocks = <&cru PCLK_GPIO0>;
1016 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1019 #gpio-cells = <0x2>;
1021 interrupt-controller;
1022 #interrupt-cells = <0x2>;
1025 gpio1: gpio1@ff780000 {
1026 compatible = "rockchip,gpio-bank";
1027 reg = <0x0 0xff758000 0x0 0x100>;
1028 clocks = <&cru PCLK_GPIO1>;
1029 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1032 #gpio-cells = <0x2>;
1034 interrupt-controller;
1035 #interrupt-cells = <0x2>;
1038 gpio2: gpio2@ff790000 {
1039 compatible = "rockchip,gpio-bank";
1040 reg = <0x0 0xff790000 0x0 0x100>;
1041 clocks = <&cru PCLK_GPIO2>;
1042 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1045 #gpio-cells = <0x2>;
1047 interrupt-controller;
1048 #interrupt-cells = <0x2>;
1051 gpio3: gpio3@ff7a0000 {
1052 compatible = "rockchip,gpio-bank";
1053 reg = <0x0 0xff7a0000 0x0 0x100>;
1054 clocks = <&cru PCLK_GPIO3>;
1055 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1058 #gpio-cells = <0x2>;
1060 interrupt-controller;
1061 #interrupt-cells = <0x2>;
1064 gpio4: gpio4@ff7b0000 {
1065 compatible = "rockchip,gpio-bank";
1066 reg = <0x0 0xff7b0000 0x0 0x100>;
1067 clocks = <&cru PCLK_GPIO4>;
1068 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1071 #gpio-cells = <0x2>;
1073 interrupt-controller;
1074 #interrupt-cells = <0x2>;
1077 gpio5: gpio5@ff7c0000 {
1078 compatible = "rockchip,gpio-bank";
1079 reg = <0x0 0xff7c0000 0x0 0x100>;
1080 clocks = <&cru PCLK_GPIO5>;
1081 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1084 #gpio-cells = <0x2>;
1086 interrupt-controller;
1087 #interrupt-cells = <0x2>;
1090 pcfg_pull_up: pcfg-pull-up {
1094 pcfg_pull_down: pcfg-pull-down {
1098 pcfg_pull_none: pcfg-pull-none {
1102 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1104 drive-strength = <12>;
1108 emmc_clk: emmc-clk {
1110 <3 4 RK_FUNC_2 &pcfg_pull_none>;
1113 emmc_cmd: emmc-cmd {
1115 <2 26 RK_FUNC_2 &pcfg_pull_up>;
1118 emmc_pwr: emmc-pwr {
1120 <2 27 RK_FUNC_2 &pcfg_pull_up>;
1123 emmc_bus1: emmc-bus1 {
1125 <2 18 RK_FUNC_2 &pcfg_pull_up>;
1128 emmc_bus4: emmc-bus4 {
1130 <2 18 RK_FUNC_2 &pcfg_pull_up>,
1131 <2 19 RK_FUNC_2 &pcfg_pull_up>,
1132 <2 20 RK_FUNC_2 &pcfg_pull_up>,
1133 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1136 emmc_bus8: emmc-bus8 {
1138 <2 18 RK_FUNC_2 &pcfg_pull_up>,
1139 <2 19 RK_FUNC_2 &pcfg_pull_up>,
1140 <2 20 RK_FUNC_2 &pcfg_pull_up>,
1141 <2 21 RK_FUNC_2 &pcfg_pull_up>,
1142 <2 22 RK_FUNC_2 &pcfg_pull_up>,
1143 <2 23 RK_FUNC_2 &pcfg_pull_up>,
1144 <2 24 RK_FUNC_2 &pcfg_pull_up>,
1145 <2 25 RK_FUNC_2 &pcfg_pull_up>;
1150 sdmmc_cd: sdmmc-cd {
1151 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1154 sdmmc_bus1: sdmmc-bus1 {
1155 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1158 sdmmc_bus4: sdmmc-bus4 {
1159 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1160 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1161 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1162 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1165 sdmmc_clk: sdmmc-clk {
1166 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1169 sdmmc_cmd: sdmmc-cmd {
1170 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1175 sdio_bus1: sdio-bus1 {
1176 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1179 sdio_bus4: sdio-bus4 {
1180 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1181 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1182 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1183 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1186 sdio_cmd: sdio-cmd {
1187 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1190 sdio_clk: sdio-clk {
1191 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1195 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1199 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1202 sdio_int: sdio-int {
1203 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1206 sdio_pwr: sdio-pwr {
1207 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1212 hdmii2c_xfer: hdmii2c-xfer {
1214 <5 13 RK_FUNC_2 &pcfg_pull_none>,
1215 <5 14 RK_FUNC_2 &pcfg_pull_none>;
1220 hdmi_cec: hdmi-cec {
1222 <5 12 RK_FUNC_1 &pcfg_pull_none>;
1227 i2c0_xfer: i2c0-xfer {
1229 <0 3 RK_FUNC_1 &pcfg_pull_none>,
1230 <0 4 RK_FUNC_1 &pcfg_pull_none>;
1235 i2c1_xfer: i2c1-xfer {
1237 <4 25 RK_FUNC_1 &pcfg_pull_none>,
1238 <4 26 RK_FUNC_1 &pcfg_pull_none>;
1243 i2c2_xfer: i2c2-xfer {
1245 <5 15 RK_FUNC_2 &pcfg_pull_none>,
1246 <5 16 RK_FUNC_2 &pcfg_pull_none>;
1249 i2c2_gpio: i2c2-gpio {
1251 <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1252 <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1257 i2c3_xfer: i2c3-xfer {
1259 <2 16 RK_FUNC_2 &pcfg_pull_none>,
1260 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1265 i2c4_xfer: i2c4-xfer {
1267 <5 8 RK_FUNC_1 &pcfg_pull_none>,
1268 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1271 i2c4_gpio: i2c4-gpio {
1273 <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1274 <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1279 i2c5_xfer: i2c5-xfer {
1281 <5 13 RK_FUNC_1 &pcfg_pull_none>,
1282 <5 14 RK_FUNC_1 &pcfg_pull_none>;
1284 i2c5_gpio: i2c5-gpio {
1286 <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1287 <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1292 i2s_8ch_bus: i2s-8ch-bus {
1294 <4 16 RK_FUNC_1 &pcfg_pull_none>,
1295 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1296 <4 18 RK_FUNC_1 &pcfg_pull_none>,
1297 <4 19 RK_FUNC_1 &pcfg_pull_none>,
1298 <4 20 RK_FUNC_1 &pcfg_pull_none>,
1299 <4 21 RK_FUNC_1 &pcfg_pull_none>,
1300 <4 22 RK_FUNC_1 &pcfg_pull_none>,
1301 <4 23 RK_FUNC_1 &pcfg_pull_none>,
1302 <4 24 RK_FUNC_1 &pcfg_pull_none>;
1307 spdif_bus: spdif-bus {
1309 <5 19 RK_FUNC_1 &pcfg_pull_none>;
1314 spi0_clk: spi0-clk {
1316 <2 29 RK_FUNC_2 &pcfg_pull_up>;
1318 spi0_cs0: spi0-cs0 {
1320 <2 24 RK_FUNC_3 &pcfg_pull_up>;
1322 spi0_cs1: spi0-cs1 {
1324 <2 25 RK_FUNC_3 &pcfg_pull_up>;
1328 <2 23 RK_FUNC_3 &pcfg_pull_up>;
1332 <2 22 RK_FUNC_3 &pcfg_pull_up>;
1337 spi1_clk: spi1-clk {
1339 <2 4 RK_FUNC_3 &pcfg_pull_up>;
1341 spi1_cs0: spi1-cs0 {
1343 <2 5 RK_FUNC_3 &pcfg_pull_up>;
1347 <2 6 RK_FUNC_3 &pcfg_pull_up>;
1351 <2 7 RK_FUNC_3 &pcfg_pull_up>;
1358 <5 8 RK_FUNC_2 &pcfg_pull_none>;
1363 <5 9 RK_FUNC_2 &pcfg_pull_up>;
1368 <5 10 RK_FUNC_1 &pcfg_pull_none>;
1371 scr_detect: scr-detect {
1373 <5 11 RK_FUNC_1 &pcfg_pull_none>;
1378 uart0_xfer: uart0-xfer {
1380 <3 8 RK_FUNC_1 &pcfg_pull_up>,
1381 <3 9 RK_FUNC_1 &pcfg_pull_none>;
1384 uart0_cts: uart0-cts {
1386 <3 10 RK_FUNC_1 &pcfg_pull_none>;
1389 uart0_rts: uart0-rts {
1391 <3 11 RK_FUNC_1 &pcfg_pull_none>;
1396 uart2_t0_xfer: uart2_t0-xfer {
1398 <0 22 RK_FUNC_1 &pcfg_pull_up>,
1399 <0 21 RK_FUNC_1 &pcfg_pull_none>;
1401 /* no rts / cts for uart2 */
1405 uart2_t1_xfer: uart2_t1-xfer {
1407 <5 0 RK_FUNC_2 &pcfg_pull_up>,
1408 <5 1 RK_FUNC_2 &pcfg_pull_none>;
1410 /* no rts / cts for uart2 */
1414 uart2_t2_xfer: uart2_t2-xfer {
1416 <5 14 RK_FUNC_3 &pcfg_pull_up>,
1417 <5 13 RK_FUNC_3 &pcfg_pull_none>;
1419 /* no rts / cts for uart2 */
1423 uart3_xfer: uart3-xfer {
1425 <5 15 RK_FUNC_1 &pcfg_pull_up>,
1426 <5 16 RK_FUNC_1 &pcfg_pull_none>;
1429 uart3_cts: uart3-cts {
1431 <5 17 RK_FUNC_1 &pcfg_pull_none>;
1434 uart3_rts: uart3-rts {
1436 <5 18 RK_FUNC_1 &pcfg_pull_none>;
1441 pwm0_pin: pwm0-pin {
1443 <0 8 RK_FUNC_1 &pcfg_pull_none>;
1448 pwm1_pin: pwm1-pin {
1450 <1 6 RK_FUNC_2 &pcfg_pull_none>;
1455 pwm2_t0_pin: pwm2_t0-pin {
1457 <2 15 RK_FUNC_3 &pcfg_pull_none>;
1462 pwm2_t1_pin: pwm2_t1-pin {
1464 <5 17 RK_FUNC_2 &pcfg_pull_none>;
1469 pwm3_t0_pin: pwm3_t0-pin {
1471 <1 0 RK_FUNC_2 &pcfg_pull_none>;
1476 pwm3_t1_pin: pwm3_t1-pin {
1478 <0 21 RK_FUNC_2 &pcfg_pull_none>;
1483 pwm3_t2_pin: pwm3_t2-pin {
1485 <5 18 RK_FUNC_2 &pcfg_pull_none>;
1490 lcdc_lcdc: lcdc-lcdc {
1492 <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1493 <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1494 <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1495 <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1496 <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1497 <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1498 <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1499 <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1500 <1 0 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1501 <1 1 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1502 <1 2 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1503 <1 3 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1504 <1 4 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1505 <1 5 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1506 <1 6 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1507 <1 7 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1508 <1 8 RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1509 <1 9 RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1512 lcdc_gpio: lcdc-gpio {
1514 <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1515 <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1516 <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1517 <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1518 <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1519 <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1520 <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1521 <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1522 <1 0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1523 <1 1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1524 <1 2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1525 <1 3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1526 <1 4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1527 <1 5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1528 <1 6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1529 <1 7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1530 <1 8 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1531 <1 9 RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1536 rgmii_pins: rgmii-pins {
1539 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1541 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1543 <2 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
1545 <2 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
1547 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1549 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1551 <2 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
1553 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1555 <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1557 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1559 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1561 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1563 <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1565 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1567 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1569 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1571 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1574 rmii_pins: rmii-pins {
1577 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1579 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1581 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1583 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1585 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1587 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1589 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1591 <2 12 RK_FUNC_1 &pcfg_pull_none>,
1593 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1595 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1597 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1599 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1604 eth_phy_pwr: eth-phy-pwr {
1606 <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1611 tsadc_gpio: tsadc-gpio {
1613 <0 22 RK_FUNC_GPIO &pcfg_pull_none>;
1616 tsadc_int: tsadc-int {
1618 <0 22 RK_FUNC_2 &pcfg_pull_none>;
1624 compatible = "arm,malit764",
1629 reg = <0x0 0xffa30000 0 0x10000>;
1631 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1632 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1633 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1634 interrupt-names = "GPU", "MMU", "JOB";
1636 clocks = <&cru ACLK_GPU>;
1637 clock-names = "clk_mali";
1638 #cooling-cells = <2>; /* min followed by max */
1639 operating-points-v2 = <&gpu_opp_table>;
1640 status = "disabled";
1643 compatible = "arm,mali-simple-power-model";
1646 static-power = <300>;
1647 dynamic-power = <1780>;
1648 ts = <32000 4700 (-80) 2>;
1649 thermal-zone = "gpu-thermal";
1653 gpu_opp_table: gpu_opp_table {
1654 compatible = "operating-points-v2";
1658 opp-hz = /bits/ 64 <96000000>;
1659 opp-microvolt = <1100000>;
1662 opp-hz = /bits/ 64 <192000000>;
1663 opp-microvolt = <1100000>;
1666 opp-hz = /bits/ 64 <288000000>;
1667 opp-microvolt = <1100000>;
1670 opp-hz = /bits/ 64 <375000000>;
1671 opp-microvolt = <1125000>;
1674 opp-hz = /bits/ 64 <480000000>;
1675 opp-microvolt = <1200000>;