arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49
  50 / {
  51         compatible = "rockchip,rk3366";
  52         interrupt-parent = <&gic>;
  53         #address-cells = <2>;
  54         #size-cells = <2>;
  55
  56         aliases {
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61                 i2c4 = &i2c4;
  62                 i2c5 = &i2c5;
  63                 serial0 = &uart0;
  64                 serial2 = &uart2;
  65                 serial3 = &uart3;
  66                 spi0 = &spi0;
  67                 spi1 = &spi1;
  68         };
  69
  70         cpus {
  71                 #address-cells = <0x2>;
  72                 #size-cells = <0x0>;
  73
  74                 cpu0: cpu@0 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53","arm,armv8";
  77                         reg = <0x0 0x0>;
  78                         enable-method = "psci";
  79                 };
  80
  81                 cpu1: cpu@1 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a53","arm,armv8";
  84                         reg = <0x0 0x1>;
  85                         enable-method = "psci";
  86                 };
  87
  88                 cpu2: cpu@2 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a53","arm,armv8";
  91                         reg = <0x0 0x2>;
  92                         enable-method = "psci";
  93                 };
  94
  95                 cpu3: cpu@3 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a53","arm,armv8";
  98                         reg = <0x0 0x3>;
  99                         enable-method = "psci";
 100                 };
 101         };
 102
 103         psci {
 104                 compatible = "arm,psci-1.0";
 105                 method = "smc";
 106         };
 107
 108         timer {
 109                 compatible = "arm,armv8-timer";
 110                 interrupts = <
 111                                 GIC_PPI 13
 112                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 113                                 <GIC_PPI 14
 114                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 115                                 <GIC_PPI 11
 116                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 117                                 <GIC_PPI 10
 118                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 119                 clock-frequency = <24000000>;
 120         };
 121
 122         xin24m: xin24m {
 123                 compatible = "fixed-clock";
 124                 #clock-cells = <0>;
 125                 clock-frequency = <24000000>;
 126                 clock-output-names = "xin24m";
 127         };
 128
 129         gic: interrupt-controller@ffb71000 {
 130                 compatible = "arm,gic-400";
 131                 interrupt-controller;
 132                 #interrupt-cells = <3>;
 133                 #address-cells = <0>;
 134
 135                 reg = <0x0 0xffb71000 0x0 0x1000>,
 136                       <0x0 0xffb72000 0x0 0x1000>,
 137                       <0x0 0xffb74000 0x0 0x2000>,
 138                       <0x0 0xffb76000 0x0 0x2000>;
 139                 interrupts = <GIC_PPI 9
 140                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 141         };
 142
 143         nandc0: nandc@ff0c0000 {
 144                 compatible = "rockchip,rk-nandc";
 145                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 146                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 147                 nandc_id = <0>;
 148                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 149                 clock-names = "clk_nandc", "hclk_nandc";
 150                 status = "disabled";
 151         };
 152
 153         saradc: saradc@ff100000 {
 154                 compatible = "rockchip,saradc";
 155                 reg = <0x0 0xff100000 0x0 0x100>;
 156                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 157                 #io-channel-cells = <1>;
 158                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 159                 clock-names = "saradc", "apb_pclk";
 160                 status = "disabled";
 161         };
 162
 163         spi0: spi@ff110000 {
 164                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 165                 reg = <0x0 0xff110000 0x0 0x1000>;
 166                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 167                 clock-names = "spiclk", "apb_pclk";
 168                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 169                 pinctrl-names = "default";
 170                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 171                 #address-cells = <1>;
 172                 #size-cells = <0>;
 173                 status = "disabled";
 174         };
 175
 176         spi1: spi@ff120000 {
 177                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 178                 reg = <0x0 0xff120000 0x0 0x1000>;
 179                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 180                 clock-names = "spiclk", "apb_pclk";
 181                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 182                 pinctrl-names = "default";
 183                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186                 status = "disabled";
 187         };
 188
 189         sdmmc: rksdmmc@ff400000 {
 190                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 191                 clock-freq-min-max = <400000 150000000>;
 192                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 193                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 194                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 195                 fifo-depth = <0x100>;
 196                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 197                 reg = <0x0 0xff400000 0x0 0x4000>;
 198                 status = "disabled";
 199         };
 200
 201         sdio: rksdmmc@ff410000 {
 202                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 203                 clock-freq-min-max = <400000 150000000>;
 204                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 205                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 206                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 207                 fifo-depth = <0x100>;
 208                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 209                 reg = <0x0 0xff410000 0x0 0x4000>;
 210                 status = "disabled";
 211         };
 212
 213         emmc: rksdmmc@ff420000 {
 214                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 215                 clock-freq-min-max = <400000 150000000>;
 216                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 217                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 218                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 219                 fifo-depth = <0x100>;
 220                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 221                 reg = <0x0 0xff420000 0x0 0x4000>;
 222                 status = "disabled";
 223         };
 224
 225         gmac: eth@ff440000 {
 226                 compatible = "rockchip,rk3366-gmac";
 227                 reg = <0x0 0xff440000 0x0 0x10000>;
 228                 rockchip,grf = <&grf>;
 229                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 230                 interrupt-names = "macirq";
 231                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 232                          <&cru SCLK_MAC_RX>, <&cru SCLK_MACREF>,
 233                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 234                          <&cru PCLK_GMAC>;
 235                 clock-names = "stmmaceth", "mac_clk_rx",
 236                               "mac_clk_tx", "clk_mac_ref",
 237                               "clk_mac_refout", "aclk_mac",
 238                               "pclk_mac";
 239                 resets = <&cru SRST_MAC>;
 240                 reset-names = "stmmaceth";
 241                 status = "disabled";
 242         };
 243
 244         i2c0: i2c@ff650000 {
 245                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 246                 reg = <0x0 0xff728000 0x0 0x1000>;
 247                 clocks = <&cru PCLK_I2C0>;
 248                 clock-names = "i2c";
 249                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 250                 pinctrl-names = "default";
 251                 pinctrl-0 = <&i2c0_xfer>;
 252                 #address-cells = <1>;
 253                 #size-cells = <0>;
 254                 status = "disabled";
 255         };
 256
 257         i2c2: i2c@ff140000 {
 258                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 259                 reg = <0x0 0xff140000 0x0 0x1000>;
 260                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 261                 #address-cells = <1>;
 262                 #size-cells = <0>;
 263                 clock-names = "i2c";
 264                 clocks = <&cru PCLK_I2C2>;
 265                 pinctrl-names = "default";
 266                 pinctrl-0 = <&i2c2_xfer>;
 267                 status = "disabled";
 268         };
 269
 270         i2c3: i2c@ff150000 {
 271                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 272                 reg = <0x0 0xff150000 0x0 0x1000>;
 273                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 274                 #address-cells = <1>;
 275                 #size-cells = <0>;
 276                 clock-names = "i2c";
 277                 clocks = <&cru PCLK_I2C3>;
 278                 pinctrl-names = "default";
 279                 pinctrl-0 = <&i2c3_xfer>;
 280                 status = "disabled";
 281         };
 282
 283         i2c4: i2c@ff160000 {
 284                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 285                 reg = <0x0 0xff160000 0x0 0x1000>;
 286                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 287                 #address-cells = <1>;
 288                 #size-cells = <0>;
 289                 clock-names = "i2c";
 290                 clocks = <&cru PCLK_I2C4>;
 291                 pinctrl-names = "default";
 292                 pinctrl-0 = <&i2c4_xfer>;
 293                 status = "disabled";
 294         };
 295
 296         i2c5: i2c@ff170000 {
 297                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 298                 reg = <0x0 0xff170000 0x0 0x1000>;
 299                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 300                 #address-cells = <1>;
 301                 #size-cells = <0>;
 302                 clock-names = "i2c";
 303                 clocks = <&cru PCLK_I2C5>;
 304                 pinctrl-names = "default";
 305                 pinctrl-0 = <&i2c5_xfer>;
 306                 status = "disabled";
 307         };
 308
 309         uart0: serial@ff180000 {
 310                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 311                 reg = <0x0 0xff180000 0x0 0x100>;
 312                 clock-frequency = <24000000>;
 313                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 314                 clock-names = "baudclk", "apb_pclk";
 315                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 316                 reg-shift = <2>;
 317                 reg-io-width = <4>;
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 320                 status = "disabled";
 321         };
 322
 323         uart3: serial@ff1b0000 {
 324                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 325                 reg = <0x0 0xff1b0000 0x0 0x100>;
 326                 clock-frequency = <24000000>;
 327                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 328                 clock-names = "baudclk", "apb_pclk";
 329                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 330                 reg-shift = <2>;
 331                 reg-io-width = <4>;
 332                 pinctrl-names = "default";
 333                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 334                 status = "disabled";
 335         };
 336
 337         i2c1: i2c@ff660000 {
 338                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 339                 reg = <0x0 0xff660000 0x0 0x1000>;
 340                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 341                 #address-cells = <1>;
 342                 #size-cells = <0>;
 343                 clock-names = "i2c";
 344                 clocks = <&cru PCLK_I2C1>;
 345                 pinctrl-names = "default";
 346                 pinctrl-0 = <&i2c1_xfer>;
 347                 status = "disabled";
 348         };
 349
 350         pwm0: pwm@ff680000 {
 351                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 352                 reg = <0x0 0xff680000 0x0 0x10>;
 353                 #pwm-cells = <3>;
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&pwm0_pin>;
 356                 clocks = <&cru PCLK_RKPWM>;
 357                 clock-names = "pwm";
 358                 status = "disabled";
 359         };
 360
 361         pwm1: pwm@ff680010 {
 362                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 363                 reg = <0x0 0xff680010 0x0 0x10>;
 364                 #pwm-cells = <3>;
 365                 pinctrl-names = "default";
 366                 pinctrl-0 = <&pwm1_pin>;
 367                 clocks = <&cru PCLK_RKPWM>;
 368                 clock-names = "pwm";
 369                 status = "disabled";
 370         };
 371
 372         pwm2: pwm@ff680020 {
 373                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 374                 reg = <0x0 0xff680020 0x0 0x10>;
 375                 #pwm-cells = <3>;
 376                 clocks = <&cru PCLK_RKPWM>;
 377                 clock-names = "pwm";
 378                 status = "disabled";
 379         };
 380
 381         pwm3: pwm@ff680030 {
 382                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 383                 reg = <0x0 0xff680030 0x0 0x10>;
 384                 #pwm-cells = <3>;
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&pwm3_t2_pin>;
 387                 clocks = <&cru PCLK_RKPWM>;
 388                 clock-names = "pwm";
 389                 status = "disabled";
 390         };
 391
 392         uart2: serial@ff690000 {
 393                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 394                 reg = <0x0 0xff690000 0x0 0x100>;
 395                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 396                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 397                 clock-names = "baudclk", "apb_pclk";
 398                 reg-shift = <2>;
 399                 reg-io-width = <4>;
 400                 pinctrl-names = "default";
 401                 pinctrl-0 = <&uart2_t1_xfer>;
 402                 status = "disabled";
 403         };
 404
 405         pmugrf: syscon@ff738000 {
 406                 compatible = "rockchip,rk3366-pmugrf", "syscon";
 407                 reg = <0x0 0xff738000 0x0 0x1000>;
 408         };
 409
 410         amba {
 411                 compatible = "arm,amba-bus";
 412                 #address-cells = <2>;
 413                 #size-cells = <2>;
 414                 ranges;
 415
 416                 dmac_peri: dma-controller@ff250000 {
 417                         compatible = "arm,pl330", "arm,primecell";
 418                         reg = <0x0 0xff250000 0x0 0x4000>;
 419                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 420                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 421                         #dma-cells = <1>;
 422                         clocks = <&cru ACLK_DMAC_PERI>;
 423                         clock-names = "apb_pclk";
 424                 };
 425
 426                 dmac_bus: dma-controller@ff600000 {
 427                         compatible = "arm,pl330", "arm,primecell";
 428                         reg = <0x0 0xff600000 0x0 0x4000>;
 429                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 430                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 431                         #dma-cells = <1>;
 432                         clocks = <&cru ACLK_DMAC_BUS>;
 433                         clock-names = "apb_pclk";
 434                 };
 435         };
 436
 437         cru: clock-controller@ff760000 {
 438                 compatible = "rockchip,rk3366-cru";
 439                 reg = <0x0 0xff760000 0x0 0x1000>;
 440                 rockchip,grf = <&grf>;
 441                 #clock-cells = <1>;
 442                 #reset-cells = <1>;
 443         };
 444
 445         grf: syscon@ff770000 {
 446                 compatible = "rockchip,rk3366-grf", "syscon";
 447                 reg = <0x0 0xff770000 0x0 0x1000>;
 448         };
 449
 450         i2s_2ch: i2s-2ch@ff890000 {
 451                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 452                 reg = <0x0 0xff890000 0x0 0x1000>;
 453                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 454                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 455                 dma-names = "tx", "rx";
 456                 clock-names = "i2s_hclk", "i2s_clk";
 457                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
 458                 status = "disabled";
 459         };
 460
 461         i2s_8ch: i2s-8ch@ff898000 {
 462                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 463                 reg = <0x0 0xff898000 0x0 0x1000>;
 464                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 465                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 466                 dma-names = "tx", "rx";
 467                 clock-names = "i2s_hclk", "i2s_clk";
 468                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
 469                 pinctrl-names = "default";
 470                 pinctrl-0 = <&i2s_8ch_bus>;
 471                 status = "disabled";
 472         };
 473
 474         fb: fb {
 475                 compatible = "rockchip,rk-fb";
 476                 rockchip,disp-mode = <DUAL>;
 477                 status = "disabled";
 478         };
 479
 480         rk_screen: screen {
 481                 compatible = "rockchip,screen";
 482                 status = "disabled";
 483         };
 484
 485         vop_lite: vop@ff8f0000 {
 486                 compatible = "rockchip,rk3366-lcdc-lite";
 487                 rockchip,grf = <&grf>;
 488                 rockchip,pwr18 = <0>;
 489                 rockchip,iommu-enabled = <1>;
 490                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 491                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 492                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 493                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 494                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 495                 reset-names = "axi", "ahb", "dclk";
 496                 status = "disabled";
 497         };
 498
 499         vopl_mmu: vopl-mmu {
 500                 dbgname = "vop";
 501                 compatible = "rockchip,vopl_mmu";
 502                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 503                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 504                 interrupt-names = "vopl_mmu";
 505                 status = "disabled";
 506         };
 507
 508         vop_big: vop@ff930000 {
 509                 compatible = "rockchip,rk3366-lcdc-big";
 510                 rockchip,grf = <&grf>;
 511                 rockchip,prop = <PRMRY>;
 512                 rockchip,pwr18 = <0>;
 513                 rockchip,iommu-enabled = <1>;
 514                 reg = <0x0 0xff930000 0x0 0x23f0>;
 515                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 516                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 517                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 518                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 519                 reset-names = "axi", "ahb", "dclk";
 520                 status = "disabled";
 521         };
 522
 523         vopb_mmu: vopb-mmu {
 524                 dbgname = "vop";
 525                 compatible = "rockchip,vopb_mmu";
 526                 reg = <0x0 0xff932400 0x0 0x100>;
 527                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 528                 interrupt-names = "vop_mmu";
 529                 status = "disabled";
 530         };
 531
 532         dsihost0: mipi@ff960000 {
 533                 compatible = "rockchip,rk3368-dsi";
 534                 rockchip,prop = <0>;
 535                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 536                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 537                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 538                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 539                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 540                 status = "disabled";
 541         };
 542
 543         lvds: lvds@ff968000 {
 544                 compatible = "rockchip,rk3366-lvds";
 545                 rockchip,grf = <&grf>;
 546                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 547                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 548                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 549                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 550                 status = "disabled";
 551         };
 552
 553         hdmi: hdmi@ff980000 {
 554                 compatible = "rockchip,rk3366-hdmi";
 555                 reg = <0x0 0xff980000 0x0 0x20000>;
 556                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 557                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 558                 clocks = <&cru PCLK_HDMI_CTRL>,
 559                          <&cru SCLK_HDMI_HDCP>,
 560                          <&cru SCLK_HDMI_CEC>,
 561                          <&cru DCLK_HDMIPHY>;
 562                 clock-names = "pclk_hdmi",
 563                               "hdcp_clk_hdmi",
 564                               "cec_clk_hdmi",
 565                               "dclk_hdmi_phy";
 566                 resets = <&cru SRST_HDMI>;
 567                 reset-names = "hdmi";
 568                 pinctrl-names = "default", "gpio";
 569                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 570                 pinctrl-1 = <&i2c5_gpio>;
 571                 status = "disabled";
 572         };
 573
 574         pinctrl: pinctrl {
 575                 compatible = "rockchip,rk3366-pinctrl";
 576                 rockchip,grf = <&grf>;
 577                 rockchip,pmu = <&pmugrf>;
 578                 #address-cells = <0x2>;
 579                 #size-cells = <0x2>;
 580                 ranges;
 581
 582                 gpio0: gpio0@ff750000 {
 583                         compatible = "rockchip,gpio-bank";
 584                         reg = <0x0 0xff750000 0x0 0x100>;
 585                         clocks = <&cru PCLK_GPIO0>;
 586                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 587
 588                         gpio-controller;
 589                         #gpio-cells = <0x2>;
 590
 591                         interrupt-controller;
 592                         #interrupt-cells = <0x2>;
 593                 };
 594
 595                 gpio1: gpio1@ff780000 {
 596                         compatible = "rockchip,gpio-bank";
 597                         reg = <0x0 0xff758000 0x0 0x100>;
 598                         clocks = <&cru PCLK_GPIO1>;
 599                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 600
 601                         gpio-controller;
 602                         #gpio-cells = <0x2>;
 603
 604                         interrupt-controller;
 605                         #interrupt-cells = <0x2>;
 606                 };
 607
 608                 gpio2: gpio2@ff790000 {
 609                         compatible = "rockchip,gpio-bank";
 610                         reg = <0x0 0xff790000 0x0 0x100>;
 611                         clocks = <&cru PCLK_GPIO2>;
 612                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 613
 614                         gpio-controller;
 615                         #gpio-cells = <0x2>;
 616
 617                         interrupt-controller;
 618                         #interrupt-cells = <0x2>;
 619                 };
 620
 621                 gpio3: gpio3@ff7a0000 {
 622                         compatible = "rockchip,gpio-bank";
 623                         reg = <0x0 0xff7a0000 0x0 0x100>;
 624                         clocks = <&cru PCLK_GPIO3>;
 625                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 626
 627                         gpio-controller;
 628                         #gpio-cells = <0x2>;
 629
 630                         interrupt-controller;
 631                         #interrupt-cells = <0x2>;
 632                 };
 633
 634                 gpio4: gpio4@ff7b0000 {
 635                         compatible = "rockchip,gpio-bank";
 636                         reg = <0x0 0xff7b0000 0x0 0x100>;
 637                         clocks = <&cru PCLK_GPIO4>;
 638                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 639
 640                         gpio-controller;
 641                         #gpio-cells = <0x2>;
 642
 643                         interrupt-controller;
 644                         #interrupt-cells = <0x2>;
 645                 };
 646
 647                 gpio5: gpio5@ff7c0000 {
 648                         compatible = "rockchip,gpio-bank";
 649                         reg = <0x0 0xff7c0000 0x0 0x100>;
 650                         clocks = <&cru PCLK_GPIO5>;
 651                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 652
 653                         gpio-controller;
 654                         #gpio-cells = <0x2>;
 655
 656                         interrupt-controller;
 657                         #interrupt-cells = <0x2>;
 658                 };
 659
 660                 pcfg_pull_up: pcfg-pull-up {
 661                         bias-pull-up;
 662                 };
 663
 664                 pcfg_pull_down: pcfg-pull-down {
 665                         bias-pull-down;
 666                 };
 667
 668                 pcfg_pull_none: pcfg-pull-none {
 669                         bias-disable;
 670                 };
 671
 672                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 673                         bias-disable;
 674                         drive-strength = <12>;
 675                 };
 676
 677                 emmc {
 678                         emmc_clk: emmc-clk {
 679                                 rockchip,pins =
 680                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
 681                         };
 682
 683                         emmc_cmd: emmc-cmd {
 684                                 rockchip,pins =
 685                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
 686                         };
 687
 688                         emmc_pwr: emmc-pwr {
 689                                 rockchip,pins =
 690                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
 691                         };
 692
 693                         emmc_bus1: emmc-bus1 {
 694                                 rockchip,pins =
 695                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
 696                         };
 697
 698                         emmc_bus4: emmc-bus4 {
 699                                 rockchip,pins =
 700                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 701                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 702                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 703                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
 704                         };
 705
 706                         emmc_bus8: emmc-bus8 {
 707                                 rockchip,pins =
 708                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 709                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 710                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 711                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
 712                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
 713                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
 714                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
 715                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
 716                         };
 717                 };
 718
 719                 sdmmc {
 720                         sdmmc_cd: sdmmc-cd {
 721                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
 722                         };
 723
 724                         sdmmc_bus1: sdmmc-bus1 {
 725                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
 726                         };
 727
 728                         sdmmc_bus4: sdmmc-bus4 {
 729                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
 730                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
 731                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
 732                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
 733                         };
 734
 735                         sdmmc_clk: sdmmc-clk {
 736                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
 737                         };
 738
 739                         sdmmc_cmd: sdmmc-cmd {
 740                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
 741                         };
 742                 };
 743
 744                 sdio {
 745                         sdio_bus1: sdio-bus1 {
 746                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
 747                         };
 748
 749                         sdio_bus4: sdio-bus4 {
 750                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
 751                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
 752                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
 753                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
 754                         };
 755
 756                         sdio_cmd: sdio-cmd {
 757                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
 758                         };
 759
 760                         sdio_clk: sdio-clk {
 761                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
 762                         };
 763
 764                         sdio_cd: sdio-cd {
 765                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
 766                         };
 767
 768                         sdio_wp: sdio-wp {
 769                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
 770                         };
 771
 772                         sdio_int: sdio-int {
 773                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
 774                         };
 775
 776                         sdio_pwr: sdio-pwr {
 777                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
 778                         };
 779                 };
 780
 781                 hdmi_i2c {
 782                         hdmii2c_xfer: hdmii2c-xfer {
 783                                 rockchip,pins =
 784                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
 785                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
 786                         };
 787                 };
 788
 789                 hdmi_pin {
 790                         hdmi_cec: hdmi-cec {
 791                                 rockchip,pins =
 792                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
 793                         };
 794                 };
 795
 796                 i2c0 {
 797                         i2c0_xfer: i2c0-xfer {
 798                                 rockchip,pins =
 799                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
 800                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
 801                         };
 802                 };
 803
 804                 i2c1 {
 805                         i2c1_xfer: i2c1-xfer {
 806                                 rockchip,pins =
 807                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
 808                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
 809                         };
 810                 };
 811
 812                 i2c2 {
 813                         i2c2_xfer: i2c2-xfer {
 814                                 rockchip,pins =
 815                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
 816                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
 817                         };
 818                 };
 819
 820                 i2c3 {
 821                         i2c3_xfer: i2c3-xfer {
 822                                 rockchip,pins =
 823                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
 824                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
 825                         };
 826                 };
 827
 828                 i2c4 {
 829                         i2c4_xfer: i2c4-xfer {
 830                                 rockchip,pins =
 831                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
 832                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
 833                         };
 834                 };
 835
 836                 i2c5 {
 837                         i2c5_xfer: i2c5-xfer {
 838                                 rockchip,pins =
 839                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
 840                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
 841                         };
 842                         i2c5_gpio: i2c5-gpio {
 843                                 rockchip,pins =
 844                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
 845                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
 846                         };
 847                 };
 848
 849                 i2s {
 850                         i2s_8ch_bus: i2s-8ch-bus {
 851                                 rockchip,pins =
 852                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
 853                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 854                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
 855                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
 856                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
 857                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
 858                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
 859                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
 860                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
 861                         };
 862                 };
 863
 864                 spi0 {
 865                         spi0_clk: spi0-clk {
 866                                 rockchip,pins =
 867                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
 868                         };
 869                         spi0_cs0: spi0-cs0 {
 870                                 rockchip,pins =
 871                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
 872                         };
 873                         spi0_cs1: spi0-cs1 {
 874                                 rockchip,pins =
 875                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
 876                         };
 877                         spi0_tx: spi0-tx {
 878                                 rockchip,pins =
 879                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
 880                         };
 881                         spi0_rx: spi0-rx {
 882                                 rockchip,pins =
 883                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
 884                         };
 885                 };
 886
 887                 spi1 {
 888                         spi1_clk: spi1-clk {
 889                                 rockchip,pins =
 890                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
 891                         };
 892                         spi1_cs0: spi1-cs0 {
 893                                 rockchip,pins =
 894                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
 895                         };
 896                         spi1_tx: spi1-tx {
 897                                 rockchip,pins =
 898                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
 899                         };
 900                         spi1_rx: spi1-rx {
 901                                 rockchip,pins =
 902                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
 903                         };
 904                 };
 905
 906                 uart0 {
 907                         uart0_xfer: uart0-xfer {
 908                                 rockchip,pins =
 909                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
 910                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
 911                         };
 912
 913                         uart0_cts: uart0-cts {
 914                                 rockchip,pins =
 915                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
 916                         };
 917
 918                         uart0_rts: uart0-rts {
 919                                 rockchip,pins =
 920                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
 921                         };
 922                 };
 923
 924                 uart2_t0 {
 925                         uart2_t0_xfer: uart2_t0-xfer {
 926                                 rockchip,pins =
 927                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
 928                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
 929                         };
 930                         /* no rts / cts for uart2 */
 931                 };
 932
 933                 uart2_t1 {
 934                         uart2_t1_xfer: uart2_t1-xfer {
 935                                 rockchip,pins =
 936                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
 937                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
 938                         };
 939                         /* no rts / cts for uart2 */
 940                 };
 941
 942                 uart2_t2 {
 943                         uart2_t2_xfer: uart2_t2-xfer {
 944                                 rockchip,pins =
 945                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
 946                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
 947                         };
 948                         /* no rts / cts for uart2 */
 949                 };
 950
 951                 uart3 {
 952                         uart3_xfer: uart3-xfer {
 953                                 rockchip,pins =
 954                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
 955                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
 956                         };
 957
 958                         uart3_cts: uart3-cts {
 959                                 rockchip,pins =
 960                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
 961                         };
 962
 963                         uart3_rts: uart3-rts {
 964                                 rockchip,pins =
 965                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
 966                         };
 967                 };
 968
 969                 pwm0 {
 970                         pwm0_pin: pwm0-pin {
 971                                 rockchip,pins =
 972                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
 973                         };
 974                 };
 975
 976                 pwm1 {
 977                         pwm1_pin: pwm1-pin {
 978                                 rockchip,pins =
 979                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
 980                         };
 981                 };
 982
 983                 pwm2_t0 {
 984                         pwm2_t0_pin: pwm2_t0-pin {
 985                                 rockchip,pins =
 986                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
 987                         };
 988                 };
 989
 990                 pwm2_t1 {
 991                         pwm2_t1_pin: pwm2_t1-pin {
 992                                 rockchip,pins =
 993                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
 994                         };
 995                 };
 996
 997                 pwm3_t0 {
 998                         pwm3_t0_pin: pwm3_t0-pin {
 999                                 rockchip,pins =
1000                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1001                         };
1002                 };
1003
1004                 pwm3_t1 {
1005                         pwm3_t1_pin: pwm3_t1-pin {
1006                                 rockchip,pins =
1007                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1008                         };
1009                 };
1010
1011                 pwm3_t2 {
1012                         pwm3_t2_pin: pwm3_t2-pin {
1013                                 rockchip,pins =
1014                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1015                         };
1016                 };
1017
1018                 lcdc {
1019                         lcdc_lcdc: lcdc-lcdc {
1020                                 rockchip,pins =
1021                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1022                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1023                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1024                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1025                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1026                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1027                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1028                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1029                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1030                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1031                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1032                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1033                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1034                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1035                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1036                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1037                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1038                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1039                         };
1040
1041                         lcdc_gpio: lcdc-gpio {
1042                                 rockchip,pins =
1043                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1044                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1045                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1046                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1047                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1048                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1049                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1050                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1051                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1052                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1053                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1054                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1055                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1056                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1057                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1058                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1059                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1060                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1061                         };
1062                 };
1063
1064                 gmac {
1065                         rgmii_pins: rgmii-pins {
1066                                 rockchip,pins =
1067                                         /* mac_rxd3 */
1068                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1069                                         /* mac_rxd2 */
1070                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1071                                         /* mac_txd3 */
1072                                         <2 5  RK_FUNC_1 &pcfg_pull_none>,
1073                                         /* mac_txd2 */
1074                                         <2 4  RK_FUNC_1 &pcfg_pull_none>,
1075                                         /* mac_rxd1 */
1076                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1077                                         /* mac_rxd0 */
1078                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1079                                         /* mac_txd1 */
1080                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1081                                         /* mac_txd0 */
1082                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1083                                         /* mac_crs */
1084                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1085                                         /* mac_rxclkin */
1086                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1087                                         /* mac_mdio */
1088                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1089                                         /* mac_txen */
1090                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1091                                         /* mac_clk */
1092                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1093                                         /* mac_rxer */
1094                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1095                                         /* mac_rxdv */
1096                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1097                                         /* mac_mdc */
1098                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1099                         };
1100
1101                         rmii_pins: rmii-pins {
1102                                 rockchip,pins =
1103                                         /* mac_rxd1 */
1104                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1105                                         /* mac_rxd0 */
1106                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1107                                         /* mac_txd1 */
1108                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1109                                         /* mac_txd0 */
1110                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1111                                         /* mac_crs */
1112                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1113                                         /* mac_rxclkin */
1114                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1115                                         /* mac_mdio */
1116                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1117                                         /* mac_txen */
1118                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1119                                         /* mac_clk */
1120                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1121                                         /* mac_rxer */
1122                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1123                                         /* mac_rxdv */
1124                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1125                                         /* mac_mdc */
1126                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1127                         };
1128                 };
1129
1130                 eth_phy {
1131                         eth_phy_pwr: eth-phy-pwr {
1132                                 rockchip,pins =
1133                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
1134                         };
1135                 };
1136         };
1137 };