arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51 #include <dt-bindings/display/mipi_dsi.h>
  52 #include <dt-bindings/display/drm_mipi_dsi.h>
  53 #include <dt-bindings/display/media-bus-format.h>
  54
  55 / {
  56         compatible = "rockchip,rk3368";
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 ethernet0 = &gmac;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67                 i2c4 = &i2c4;
  68                 i2c5 = &i2c5;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74                 spi0 = &spi0;
  75                 spi1 = &spi1;
  76                 spi2 = &spi2;
  77         };
  78
  79         cpus {
  80                 #address-cells = <0x2>;
  81                 #size-cells = <0x0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                                 core2 {
 107                                         cpu = <&cpu_b2>;
 108                                 };
 109                                 core3 {
 110                                         cpu = <&cpu_b3>;
 111                                 };
 112                         };
 113                 };
 114
 115                 idle-states {
 116                         entry-method = "psci";
 117
 118                         cpu_sleep: cpu-sleep-0 {
 119                                 compatible = "arm,idle-state";
 120                                 arm,psci-suspend-param = <0x1010000>;
 121                                 entry-latency-us = <0x3fffffff>;
 122                                 exit-latency-us = <0x40000000>;
 123                                 min-residency-us = <0xffffffff>;
 124                         };
 125                 };
 126
 127                 cpu_l0: cpu@0 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x0 0x0>;
 131                         cpu-idle-states = <&cpu_sleep>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135                         #cooling-cells = <2>; /* min followed by max */
 136                         dynamic-power-coefficient = <149>;
 137                 };
 138
 139                 cpu_l1: cpu@1 {
 140                         device_type = "cpu";
 141                         compatible = "arm,cortex-a53", "arm,armv8";
 142                         reg = <0x0 0x1>;
 143                         cpu-idle-states = <&cpu_sleep>;
 144                         enable-method = "psci";
 145                         clocks = <&cru ARMCLKL>;
 146                         operating-points-v2 = <&cluster0_opp>;
 147                 };
 148
 149                 cpu_l2: cpu@2 {
 150                         device_type = "cpu";
 151                         compatible = "arm,cortex-a53", "arm,armv8";
 152                         reg = <0x0 0x2>;
 153                         cpu-idle-states = <&cpu_sleep>;
 154                         enable-method = "psci";
 155                         clocks = <&cru ARMCLKL>;
 156                         operating-points-v2 = <&cluster0_opp>;
 157                 };
 158
 159                 cpu_l3: cpu@3 {
 160                         device_type = "cpu";
 161                         compatible = "arm,cortex-a53", "arm,armv8";
 162                         reg = <0x0 0x3>;
 163                         cpu-idle-states = <&cpu_sleep>;
 164                         enable-method = "psci";
 165                         clocks = <&cru ARMCLKL>;
 166                         operating-points-v2 = <&cluster0_opp>;
 167                 };
 168
 169                 cpu_b0: cpu@100 {
 170                         device_type = "cpu";
 171                         compatible = "arm,cortex-a53", "arm,armv8";
 172                         reg = <0x0 0x100>;
 173                         cpu-idle-states = <&cpu_sleep>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         operating-points-v2 = <&cluster1_opp>;
 177                         #cooling-cells = <2>; /* min followed by max */
 178                         dynamic-power-coefficient = <160>;
 179                 };
 180
 181                 cpu_b1: cpu@101 {
 182                         device_type = "cpu";
 183                         compatible = "arm,cortex-a53", "arm,armv8";
 184                         reg = <0x0 0x101>;
 185                         cpu-idle-states = <&cpu_sleep>;
 186                         enable-method = "psci";
 187                         clocks = <&cru ARMCLKB>;
 188                         operating-points-v2 = <&cluster1_opp>;
 189                 };
 190
 191                 cpu_b2: cpu@102 {
 192                         device_type = "cpu";
 193                         compatible = "arm,cortex-a53", "arm,armv8";
 194                         reg = <0x0 0x102>;
 195                         cpu-idle-states = <&cpu_sleep>;
 196                         enable-method = "psci";
 197                         clocks = <&cru ARMCLKB>;
 198                         operating-points-v2 = <&cluster1_opp>;
 199                 };
 200
 201                 cpu_b3: cpu@103 {
 202                         device_type = "cpu";
 203                         compatible = "arm,cortex-a53", "arm,armv8";
 204                         reg = <0x0 0x103>;
 205                         cpu-idle-states = <&cpu_sleep>;
 206                         enable-method = "psci";
 207                         clocks = <&cru ARMCLKB>;
 208                         operating-points-v2 = <&cluster1_opp>;
 209                 };
 210         };
 211
 212         cluster0_opp: opp_table0 {
 213                 compatible = "operating-points-v2";
 214                 opp-shared;
 215
 216                 opp@216000000 {
 217                         opp-hz = /bits/ 64 <216000000>;
 218                         opp-microvolt = <950000 950000 1350000>;
 219                         clock-latency-ns = <40000>;
 220                         opp-suspend;
 221                 };
 222                 opp@408000000 {
 223                         opp-hz = /bits/ 64 <408000000>;
 224                         opp-microvolt = <950000 950000 1350000>;
 225                         clock-latency-ns = <40000>;
 226                 };
 227                 opp@600000000 {
 228                         opp-hz = /bits/ 64 <600000000>;
 229                         opp-microvolt = <950000 950000 1350000>;
 230                         clock-latency-ns = <40000>;
 231                 };
 232                 opp@816000000 {
 233                         opp-hz = /bits/ 64 <816000000>;
 234                         opp-microvolt = <1025000 1025000 1350000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@1008000000 {
 238                         opp-hz = /bits/ 64 <1008000000>;
 239                         opp-microvolt = <1125000 1125000 1350000>;
 240                         clock-latency-ns = <40000>;
 241                 };
 242                 opp@1200000000 {
 243                         opp-hz = /bits/ 64 <1200000000>;
 244                         opp-microvolt = <1225000 1225000 1350000>;
 245                         clock-latency-ns = <40000>;
 246                 };
 247         };
 248
 249         cluster1_opp: opp_table1 {
 250                 compatible = "operating-points-v2";
 251                 opp-shared;
 252
 253                 opp@216000000 {
 254                         opp-hz = /bits/ 64 <216000000>;
 255                         opp-microvolt = <950000 950000 1350000>;
 256                         clock-latency-ns = <40000>;
 257                         opp-suspend;
 258                 };
 259                 opp@408000000 {
 260                         opp-hz = /bits/ 64 <408000000>;
 261                         opp-microvolt = <950000 950000 1350000>;
 262                         clock-latency-ns = <40000>;
 263                 };
 264                 opp@600000000 {
 265                         opp-hz = /bits/ 64 <600000000>;
 266                         opp-microvolt = <950000 950000 1350000>;
 267                         clock-latency-ns = <40000>;
 268                 };
 269                 opp@816000000 {
 270                         opp-hz = /bits/ 64 <816000000>;
 271                         opp-microvolt = <975000 975000 1350000>;
 272                         clock-latency-ns = <40000>;
 273                 };
 274                 opp@1008000000 {
 275                         opp-hz = /bits/ 64 <1008000000>;
 276                         opp-microvolt = <1050000 1050000 1350000>;
 277                         clock-latency-ns = <40000>;
 278                 };
 279                 opp@1200000000 {
 280                         opp-hz = /bits/ 64 <1200000000>;
 281                         opp-microvolt = <1150000 1150000 1350000>;
 282                         clock-latency-ns = <40000>;
 283                 };
 284                 opp@1296000000 {
 285                         opp-hz = /bits/ 64 <1296000000>;
 286                         opp-microvolt = <1225000 1225000 1350000>;
 287                         clock-latency-ns = <40000>;
 288                 };
 289                 opp@1416000000 {
 290                         opp-hz = /bits/ 64 <1416000000>;
 291                         opp-microvolt = <1300000 1300000 1350000>;
 292                         clock-latency-ns = <40000>;
 293                 };
 294                 opp@1512000000 {
 295                         opp-hz = /bits/ 64 <1512000000>;
 296                         opp-microvolt = <1350000 1350000 1350000>;
 297                         clock-latency-ns = <40000>;
 298                 };
 299         };
 300
 301         cpu_avs: cpu-avs {
 302                 cluster0-avs {
 303                         cluster-id = <0>;
 304                         min-volt = <950000>; /* uV */
 305                         min-freq = <216000>; /* KHz */
 306                         leakage-adjust-volt = <
 307                         /*  mA        mA         uV */
 308                             0         254        0
 309                         >;
 310                         nvmem-cells = <&cpu_leakage>;
 311                         nvmem-cell-names = "cpu_leakage";
 312                 };
 313                 cluster1-avs {
 314                         cluster-id = <1>;
 315                         min-volt = <950000>; /* uV */
 316                         min-freq = <216000>; /* KHz */
 317                         leakage-adjust-volt = <
 318                         /*  mA        mA         uV */
 319                             0         254        0
 320                         >;
 321                         nvmem-cells = <&cpu_leakage>;
 322                         nvmem-cell-names = "cpu_leakage";
 323                 };
 324         };
 325
 326         arm-pmu {
 327                 compatible = "arm,armv8-pmuv3";
 328                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 329                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 330                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 331                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 332                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 333                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 334                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 335                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 336                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 337                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 338                                      <&cpu_b2>, <&cpu_b3>;
 339         };
 340
 341         amba {
 342                 compatible = "arm,amba-bus";
 343                 #address-cells = <2>;
 344                 #size-cells = <2>;
 345                 ranges;
 346
 347                 dmac_peri: dma-controller@ff250000 {
 348                         compatible = "arm,pl330", "arm,primecell";
 349                         reg = <0x0 0xff250000 0x0 0x4000>;
 350                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 351                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 352                         #dma-cells = <1>;
 353                         clocks = <&cru ACLK_DMAC_PERI>;
 354                         clock-names = "apb_pclk";
 355                         arm,pl330-broken-no-flushp;
 356                         peripherals-req-type-burst;
 357                 };
 358
 359                 dmac_bus: dma-controller@ff600000 {
 360                         compatible = "arm,pl330", "arm,primecell";
 361                         reg = <0x0 0xff600000 0x0 0x4000>;
 362                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 363                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 364                         #dma-cells = <1>;
 365                         clocks = <&cru ACLK_DMAC_BUS>;
 366                         clock-names = "apb_pclk";
 367                         arm,pl330-broken-no-flushp;
 368                         peripherals-req-type-burst;
 369                 };
 370         };
 371
 372         psci {
 373                 compatible = "arm,psci-0.2";
 374                 method = "smc";
 375         };
 376
 377         timer {
 378                 compatible = "arm,armv8-timer";
 379                 interrupts = <GIC_PPI 13
 380                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 381                              <GIC_PPI 14
 382                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 383                              <GIC_PPI 11
 384                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 385                              <GIC_PPI 10
 386                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 387         };
 388
 389         xin24m: oscillator {
 390                 compatible = "fixed-clock";
 391                 clock-frequency = <24000000>;
 392                 clock-output-names = "xin24m";
 393                 #clock-cells = <0>;
 394         };
 395
 396         xin32k: xin32k {
 397                 compatible = "fixed-clock";
 398                 clock-frequency = <32768>;
 399                 clock-output-names = "xin32k";
 400                 #clock-cells = <0>;
 401         };
 402
 403         sdmmc: dwmmc@ff0c0000 {
 404                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 405                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 406                 clock-freq-min-max = <400000 150000000>;
 407                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 408                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 409                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 410                 fifo-depth = <0x100>;
 411                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 412                 status = "disabled";
 413         };
 414
 415         sdio0: dwmmc@ff0d0000 {
 416                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 417                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 418                 clock-freq-min-max = <400000 150000000>;
 419                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 420                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 421                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 422                 fifo-depth = <0x100>;
 423                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 424                 status = "disabled";
 425         };
 426
 427         emmc: dwmmc@ff0f0000 {
 428                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 429                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 430                 clock-freq-min-max = <400000 150000000>;
 431                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 432                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 433                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 434                 fifo-depth = <0x100>;
 435                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 436                 status = "disabled";
 437         };
 438
 439         saradc: saradc@ff100000 {
 440                 compatible = "rockchip,saradc";
 441                 reg = <0x0 0xff100000 0x0 0x100>;
 442                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 443                 #io-channel-cells = <1>;
 444                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 445                 clock-names = "saradc", "apb_pclk";
 446                 resets = <&cru SRST_SARADC>;
 447                 reset-names = "saradc-apb";
 448                 status = "disabled";
 449         };
 450
 451         spi0: spi@ff110000 {
 452                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 453                 reg = <0x0 0xff110000 0x0 0x1000>;
 454                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 455                 clock-names = "spiclk", "apb_pclk";
 456                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 457                 pinctrl-names = "default";
 458                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 status = "disabled";
 462         };
 463
 464         spi1: spi@ff120000 {
 465                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 466                 reg = <0x0 0xff120000 0x0 0x1000>;
 467                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 468                 clock-names = "spiclk", "apb_pclk";
 469                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 470                 pinctrl-names = "default";
 471                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 472                 #address-cells = <1>;
 473                 #size-cells = <0>;
 474                 status = "disabled";
 475         };
 476
 477         spi2: spi@ff130000 {
 478                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 479                 reg = <0x0 0xff130000 0x0 0x1000>;
 480                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 481                 clock-names = "spiclk", "apb_pclk";
 482                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 485                 #address-cells = <1>;
 486                 #size-cells = <0>;
 487                 status = "disabled";
 488         };
 489
 490         i2c0: i2c@ff650000 {
 491                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 492                 reg = <0x0 0xff650000 0x0 0x1000>;
 493                 clocks = <&cru PCLK_I2C0>;
 494                 clock-names = "i2c";
 495                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 496                 pinctrl-names = "default";
 497                 pinctrl-0 = <&i2c0_xfer>;
 498                 #address-cells = <1>;
 499                 #size-cells = <0>;
 500                 status = "disabled";
 501         };
 502
 503         i2c2: i2c@ff140000 {
 504                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 505                 reg = <0x0 0xff140000 0x0 0x1000>;
 506                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 507                 #address-cells = <1>;
 508                 #size-cells = <0>;
 509                 clock-names = "i2c";
 510                 clocks = <&cru PCLK_I2C2>;
 511                 pinctrl-names = "default";
 512                 pinctrl-0 = <&i2c2_xfer>;
 513                 status = "disabled";
 514         };
 515
 516         i2c3: i2c@ff150000 {
 517                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 518                 reg = <0x0 0xff150000 0x0 0x1000>;
 519                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 520                 #address-cells = <1>;
 521                 #size-cells = <0>;
 522                 clock-names = "i2c";
 523                 clocks = <&cru PCLK_I2C3>;
 524                 pinctrl-names = "default";
 525                 pinctrl-0 = <&i2c3_xfer>;
 526                 status = "disabled";
 527         };
 528
 529         i2c4: i2c@ff160000 {
 530                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 531                 reg = <0x0 0xff160000 0x0 0x1000>;
 532                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535                 clock-names = "i2c";
 536                 clocks = <&cru PCLK_I2C4>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&i2c4_xfer>;
 539                 status = "disabled";
 540         };
 541
 542         i2c5: i2c@ff170000 {
 543                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 544                 reg = <0x0 0xff170000 0x0 0x1000>;
 545                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 clock-names = "i2c";
 549                 clocks = <&cru PCLK_I2C5>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&i2c5_xfer>;
 552                 status = "disabled";
 553         };
 554
 555         uart0: serial@ff180000 {
 556                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 557                 reg = <0x0 0xff180000 0x0 0x100>;
 558                 clock-frequency = <24000000>;
 559                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 560                 clock-names = "baudclk", "apb_pclk";
 561                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 562                 reg-shift = <2>;
 563                 reg-io-width = <4>;
 564                 status = "disabled";
 565         };
 566
 567         uart1: serial@ff190000 {
 568                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 569                 reg = <0x0 0xff190000 0x0 0x100>;
 570                 clock-frequency = <24000000>;
 571                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 572                 clock-names = "baudclk", "apb_pclk";
 573                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 574                 reg-shift = <2>;
 575                 reg-io-width = <4>;
 576                 status = "disabled";
 577         };
 578
 579         uart3: serial@ff1b0000 {
 580                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 581                 reg = <0x0 0xff1b0000 0x0 0x100>;
 582                 clock-frequency = <24000000>;
 583                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 584                 clock-names = "baudclk", "apb_pclk";
 585                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 586                 reg-shift = <2>;
 587                 reg-io-width = <4>;
 588                 status = "disabled";
 589         };
 590
 591         uart4: serial@ff1c0000 {
 592                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 593                 reg = <0x0 0xff1c0000 0x0 0x100>;
 594                 clock-frequency = <24000000>;
 595                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 596                 clock-names = "baudclk", "apb_pclk";
 597                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 598                 reg-shift = <2>;
 599                 reg-io-width = <4>;
 600                 status = "disabled";
 601         };
 602
 603         thermal_zones: thermal-zones {
 604                 soc_thermal: soc-thermal {
 605                         polling-delay-passive = <200>; /* milliseconds */
 606                         polling-delay = <200>; /* milliseconds */
 607                         sustainable-power = <600>; /* milliwatts */
 608
 609                         thermal-sensors = <&tsadc 0>;
 610                         trips {
 611                                 threshold: trip-point@0 {
 612                                         temperature = <70000>; /* millicelsius */
 613                                         hysteresis = <2000>; /* millicelsius */
 614                                         type = "passive";
 615                                 };
 616                                 target: trip-point@1 {
 617                                         temperature = <80000>; /* millicelsius */
 618                                         hysteresis = <2000>; /* millicelsius */
 619                                         type = "passive";
 620                                 };
 621                                 soc_crit: soc-crit {
 622                                         temperature = <95000>; /* millicelsius */
 623                                         hysteresis = <2000>; /* millicelsius */
 624                                         type = "critical";
 625                                 };
 626                         };
 627
 628                         cooling-maps {
 629                                 map0 {
 630                                         trip = <&target>;
 631                                         cooling-device =
 632                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 633                                         contribution = <1024>;
 634                                 };
 635                                 map1 {
 636                                         trip = <&target>;
 637                                         cooling-device =
 638                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 639                                         contribution = <1024>;
 640                                 };
 641                                 map2 {
 642                                         trip = <&target>;
 643                                         cooling-device =
 644                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 645                                         contribution = <1024>;
 646                                 };
 647                         };
 648                 };
 649
 650                 gpu_thermal: gpu-thermal {
 651                         polling-delay-passive = <200>; /* milliseconds */
 652                         polling-delay = <200>; /* milliseconds */
 653                         thermal-sensors = <&tsadc 1>;
 654                 };
 655         };
 656
 657         tsadc: tsadc@ff280000 {
 658                 compatible = "rockchip,rk3368-tsadc-legacy";
 659                 reg = <0x0 0xff280000 0x0 0x100>;
 660                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 661                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 662                 clock-names = "tsadc", "apb_pclk";
 663                 clock-frequency = <32768>;
 664                 resets = <&cru SRST_TSADC>;
 665                 reset-names = "tsadc-apb";
 666                 nvmem-cells = <&temp_adjust>;
 667                 nvmem-cell-names = "temp_adjust";
 668                 #thermal-sensor-cells = <1>;
 669                 hw-shut-temp = <95000>;
 670                 status = "disabled";
 671         };
 672
 673         gmac: ethernet@ff290000 {
 674                 compatible = "rockchip,rk3368-gmac";
 675                 reg = <0x0 0xff290000 0x0 0x10000>;
 676                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 677                 interrupt-names = "macirq";
 678                 rockchip,grf = <&grf>;
 679                 clocks = <&cru SCLK_MAC>,
 680                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 681                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 682                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 683                 clock-names = "stmmaceth",
 684                         "mac_clk_rx", "mac_clk_tx",
 685                         "clk_mac_ref", "clk_mac_refout",
 686                         "aclk_mac", "pclk_mac";
 687                 status = "disabled";
 688         };
 689
 690         nandc0: nandc@ff400000 {
 691                 compatible = "rockchip,rk-nandc";
 692                 reg = <0x0 0xff400000 0x0 0x4000>;
 693                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 694                 nandc_id = <0>;
 695                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 696                 clock-names = "clk_nandc", "hclk_nandc";
 697                 status = "disabled";
 698         };
 699
 700         usb_host0_ehci: usb@ff500000 {
 701                 compatible = "generic-ehci";
 702                 reg = <0x0 0xff500000 0x0 0x20000>;
 703                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 704                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 705                 clock-names = "usbhost", "utmi";
 706                 phys = <&u2phy_host>;
 707                 phy-names = "usb";
 708                 status = "disabled";
 709         };
 710
 711         usb_host0_ohci: usb@ff520000 {
 712                 compatible = "generic-ohci";
 713                 reg = <0x0 0xff520000 0x0 0x20000>;
 714                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 715                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 716                 clock-names = "usbhost", "utmi";
 717                 phys = <&u2phy_host>;
 718                 phy-names = "usb";
 719                 status = "disabled";
 720         };
 721
 722         usb_otg: usb@ff580000 {
 723                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 724                                 "snps,dwc2";
 725                 reg = <0x0 0xff580000 0x0 0x40000>;
 726                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 727                 clocks = <&cru HCLK_OTG0>;
 728                 clock-names = "otg";
 729                 dr_mode = "otg";
 730                 g-np-tx-fifo-size = <16>;
 731                 g-rx-fifo-size = <275>;
 732                 g-tx-fifo-size = <256 128 128 64 64 32>;
 733                 g-use-dma;
 734                 status = "disabled";
 735         };
 736
 737         ddrpctl: syscon@ff610000 {
 738                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 739                 reg = <0x0 0xff610000 0x0 0x400>;
 740         };
 741
 742         i2c1: i2c@ff660000 {
 743                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 744                 reg = <0x0 0xff660000 0x0 0x1000>;
 745                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 746                 #address-cells = <1>;
 747                 #size-cells = <0>;
 748                 clock-names = "i2c";
 749                 clocks = <&cru PCLK_I2C1>;
 750                 pinctrl-names = "default";
 751                 pinctrl-0 = <&i2c1_xfer>;
 752                 status = "disabled";
 753         };
 754
 755         pwm0: pwm@ff680000 {
 756                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 757                 reg = <0x0 0xff680000 0x0 0x10>;
 758                 #pwm-cells = <3>;
 759                 pinctrl-names = "default";
 760                 pinctrl-0 = <&pwm0_pin>;
 761                 clocks = <&cru PCLK_PWM1>;
 762                 clock-names = "pwm";
 763                 status = "disabled";
 764         };
 765
 766         pwm1: pwm@ff680010 {
 767                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 768                 reg = <0x0 0xff680010 0x0 0x10>;
 769                 #pwm-cells = <3>;
 770                 pinctrl-names = "default";
 771                 pinctrl-0 = <&pwm1_pin>;
 772                 clocks = <&cru PCLK_PWM1>;
 773                 clock-names = "pwm";
 774                 status = "disabled";
 775         };
 776
 777         pwm2: pwm@ff680020 {
 778                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 779                 reg = <0x0 0xff680020 0x0 0x10>;
 780                 #pwm-cells = <3>;
 781                 clocks = <&cru PCLK_PWM1>;
 782                 clock-names = "pwm";
 783                 status = "disabled";
 784         };
 785
 786         pwm3: pwm@ff680030 {
 787                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 788                 reg = <0x0 0xff680030 0x0 0x10>;
 789                 #pwm-cells = <3>;
 790                 pinctrl-names = "default";
 791                 pinctrl-0 = <&pwm3_pin>;
 792                 clocks = <&cru PCLK_PWM1>;
 793                 clock-names = "pwm";
 794                 status = "disabled";
 795         };
 796
 797         uart2: serial@ff690000 {
 798                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 799                 reg = <0x0 0xff690000 0x0 0x100>;
 800                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 801                 clock-names = "baudclk", "apb_pclk";
 802                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 803                 pinctrl-names = "default";
 804                 pinctrl-0 = <&uart2_xfer>;
 805                 reg-shift = <2>;
 806                 reg-io-width = <4>;
 807                 status = "disabled";
 808         };
 809
 810         mbox: mbox@ff6b0000 {
 811                 compatible = "rockchip,rk3368-mailbox";
 812                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 813                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 814                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 815                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 816                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 817                 clocks = <&cru PCLK_MAILBOX>;
 818                 clock-names = "pclk_mailbox";
 819                 #mbox-cells = <1>;
 820                 status = "disabled";
 821         };
 822
 823         mailbox: mailbox@ff6b0000 {
 824                 compatible = "rockchip,rk3368-mbox-legacy";
 825                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 826                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 827                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 828                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 829                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 830                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 831                 clocks = <&cru PCLK_MAILBOX>;
 832                 clock-names = "pclk_mailbox";
 833                 #mbox-cells = <1>;
 834                 status = "disabled";
 835         };
 836
 837         mailbox_scpi: mailbox-scpi {
 838                 compatible = "rockchip,rk3368-scpi-legacy";
 839                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 840                 chan-nums = <3>;
 841                 status = "disabled";
 842         };
 843
 844         qos_iep: qos@ffad0000 {
 845                 compatible = "syscon";
 846                 reg = <0x0 0xffad0000 0x0 0x20>;
 847         };
 848
 849         qos_isp_r0: qos@ffad0080 {
 850                 compatible = "syscon";
 851                 reg = <0x0 0xffad0080 0x0 0x20>;
 852         };
 853
 854         qos_isp_r1: qos@ffad0100 {
 855                 compatible = "syscon";
 856                 reg = <0x0 0xffad0100 0x0 0x20>;
 857         };
 858
 859         qos_isp_w0: qos@ffad0180 {
 860                 compatible = "syscon";
 861                 reg = <0x0 0xffad0180 0x0 0x20>;
 862         };
 863
 864         qos_isp_w1: qos@ffad0200 {
 865                 compatible = "syscon";
 866                 reg = <0x0 0xffad0200 0x0 0x20>;
 867         };
 868
 869         qos_vip: qos@ffad0280 {
 870                 compatible = "syscon";
 871                 reg = <0x0 0xffad0280 0x0 0x20>;
 872         };
 873
 874         qos_vop: qos@ffad0300 {
 875                 compatible = "syscon";
 876                 reg = <0x0 0xffad0300 0x0 0x20>;
 877         };
 878
 879         qos_rga_r: qos@ffad0380 {
 880                 compatible = "syscon";
 881                 reg = <0x0 0xffad0380 0x0 0x20>;
 882         };
 883
 884         qos_rga_w: qos@ffad0400 {
 885                 compatible = "syscon";
 886                 reg = <0x0 0xffad0400 0x0 0x20>;
 887         };
 888
 889         qos_hevc_r: qos@ffae0000 {
 890                 compatible = "syscon";
 891                 reg = <0x0 0xffae0000 0x0 0x20>;
 892         };
 893
 894         qos_vpu_r: qos@ffae0100 {
 895                 compatible = "syscon";
 896                 reg = <0x0 0xffae0100 0x0 0x20>;
 897         };
 898
 899         qos_vpu_w: qos@ffae0180 {
 900                 compatible = "syscon";
 901                 reg = <0x0 0xffae0180 0x0 0x20>;
 902         };
 903
 904         qos_gpu: qos@ffaf0000 {
 905                 compatible = "syscon";
 906                 reg = <0x0 0xffaf0000 0x0 0x20>;
 907         };
 908
 909         pmu: power-management@ff730000 {
 910                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 911                 reg = <0x0 0xff730000 0x0 0x1000>;
 912
 913                 power: power-controller {
 914                         compatible = "rockchip,rk3368-power-controller";
 915                         #power-domain-cells = <1>;
 916                         #address-cells = <1>;
 917                         #size-cells = <0>;
 918
 919                         /*
 920                          * Note: Although SCLK_* are the working clocks
 921                          * of device without including on the NOC, needed for
 922                          * synchronous reset.
 923                          *
 924                          * The clocks on the which NOC:
 925                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 926                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 927                          * ACLK_RGA is on ACLK_RGA_NIU.
 928                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 929                          *
 930                          * Which clock are device clocks:
 931                          *      clocks          devices
 932                          *      *_IEP           IEP:Image Enhancement Processor
 933                          *      *_ISP           ISP:Image Signal Processing
 934                          *      *_VIP           VIP:Video Input Processor
 935                          *      *_VOP*          VOP:Visual Output Processor
 936                          *      *_RGA           RGA
 937                          *      *_EDP*          EDP
 938                          *      *_DPHY*         LVDS
 939                          *      *_HDMI          HDMI
 940                          *      *_MIPI_*        MIPI
 941                          */
 942                         pd_vio {
 943                                 reg = <RK3368_PD_VIO>;
 944                                 clocks = <&cru ACLK_IEP>,
 945                                          <&cru ACLK_ISP>,
 946                                          <&cru ACLK_VIP>,
 947                                          <&cru ACLK_RGA>,
 948                                          <&cru ACLK_VOP>,
 949                                          <&cru ACLK_VOP_IEP>,
 950                                          <&cru DCLK_VOP>,
 951                                          <&cru HCLK_IEP>,
 952                                          <&cru HCLK_ISP>,
 953                                          <&cru HCLK_RGA>,
 954                                          <&cru HCLK_VIP>,
 955                                          <&cru HCLK_VOP>,
 956                                          <&cru HCLK_VIO_HDCPMMU>,
 957                                          <&cru PCLK_EDP_CTRL>,
 958                                          <&cru PCLK_HDMI_CTRL>,
 959                                          <&cru PCLK_HDCP>,
 960                                          <&cru PCLK_ISP>,
 961                                          <&cru PCLK_VIP>,
 962                                          <&cru PCLK_DPHYRX>,
 963                                          <&cru PCLK_DPHYTX0>,
 964                                          <&cru PCLK_MIPI_CSI>,
 965                                          <&cru PCLK_MIPI_DSI0>,
 966                                          <&cru SCLK_VOP0_PWM>,
 967                                          <&cru SCLK_EDP_24M>,
 968                                          <&cru SCLK_EDP>,
 969                                          <&cru SCLK_HDCP>,
 970                                          <&cru SCLK_ISP>,
 971                                          <&cru SCLK_RGA>,
 972                                          <&cru SCLK_HDMI_CEC>,
 973                                          <&cru SCLK_HDMI_HDCP>;
 974                                 pm_qos = <&qos_iep>,
 975                                          <&qos_isp_r0>,
 976                                          <&qos_isp_r1>,
 977                                          <&qos_isp_w0>,
 978                                          <&qos_isp_w1>,
 979                                          <&qos_vip>,
 980                                          <&qos_vop>,
 981                                          <&qos_rga_r>,
 982                                          <&qos_rga_w>;
 983                         };
 984                         /*
 985                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 986                          * (video endecoder & decoder) clocks that on the
 987                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 988                          */
 989                         pd_video {
 990                                 reg = <RK3368_PD_VIDEO>;
 991                                 clocks = <&cru ACLK_VIDEO>,
 992                                          <&cru HCLK_VIDEO>,
 993                                          <&cru SCLK_HEVC_CABAC>,
 994                                          <&cru SCLK_HEVC_CORE>;
 995                                 pm_qos = <&qos_hevc_r>,
 996                                          <&qos_vpu_r>,
 997                                          <&qos_vpu_w>;
 998                         };
 999                         /*
1000                          * Note: ACLK_GPU is the GPU clock,
1001                          * and on the ACLK_GPU_NIU (NOC).
1002                          */
1003                         pd_gpu_1 {
1004                                 reg = <RK3368_PD_GPU_1>;
1005                                 clocks = <&cru ACLK_GPU_CFG>,
1006                                          <&cru ACLK_GPU_MEM>,
1007                                          <&cru SCLK_GPU_CORE>;
1008                                 pm_qos = <&qos_gpu>;
1009                         };
1010                 };
1011         };
1012
1013         pmugrf: syscon@ff738000 {
1014                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1015                 reg = <0x0 0xff738000 0x0 0x1000>;
1016
1017                 pmu_io_domains: io-domains {
1018                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1019                         status = "disabled";
1020                 };
1021
1022                 reboot-mode {
1023                         compatible = "syscon-reboot-mode";
1024                         offset = <0x200>;
1025                         mode-normal = <BOOT_NORMAL>;
1026                         mode-recovery = <BOOT_RECOVERY>;
1027                         mode-bootloader = <BOOT_FASTBOOT>;
1028                         mode-loader = <BOOT_BL_DOWNLOAD>;
1029                 };
1030         };
1031
1032         cru: clock-controller@ff760000 {
1033                 compatible = "rockchip,rk3368-cru";
1034                 reg = <0x0 0xff760000 0x0 0x1000>;
1035                 rockchip,grf = <&grf>;
1036                 #clock-cells = <1>;
1037                 #reset-cells = <1>;
1038                 assigned-clocks =
1039                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1040                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1041                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1042                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
1043                 assigned-clock-rates =
1044                         <576000000>, <400000000>,
1045                         <300000000>, <300000000>,
1046                         <150000000>, <150000000>,
1047                         <75000000>, <75000000>;
1048         };
1049
1050         grf: syscon@ff770000 {
1051                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1052                 reg = <0x0 0xff770000 0x0 0x1000>;
1053                 #address-cells = <1>;
1054                 #size-cells = <1>;
1055
1056                 edp_phy: edp-phy {
1057                         compatible = "rockchip,rk3368-dp-phy";
1058                         clocks = <&cru SCLK_EDP_24M>;
1059                         clock-names = "24m";
1060                         resets = <&cru SRST_EDP_24M>;
1061                         reset-names = "edp_24m";
1062                         #phy-cells = <0>;
1063                         status = "disabled";
1064                 };
1065
1066                 io_domains: io-domains {
1067                         compatible = "rockchip,rk3368-io-voltage-domain";
1068                         status = "disabled";
1069                 };
1070
1071                 u2phy: usb2-phy@700 {
1072                         compatible = "rockchip,rk3368-usb2phy";
1073                         reg = <0x700 0x2c>;
1074                         clocks = <&cru SCLK_OTGPHY0>;
1075                         clock-names = "phyclk";
1076                         #clock-cells = <0>;
1077                         clock-output-names = "usbotg_out";
1078                         assigned-clocks = <&cru SCLK_USBPHY480M>;
1079                         assigned-clock-parents = <&u2phy>;
1080                         status = "disabled";
1081
1082                         u2phy_host: host-port {
1083                                 #phy-cells = <0>;
1084                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1085                                 interrupt-names = "linestate";
1086                                 status = "disabled";
1087                         };
1088                 };
1089         };
1090
1091         wdt: watchdog@ff800000 {
1092                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1093                 reg = <0x0 0xff800000 0x0 0x100>;
1094                 clocks = <&cru PCLK_WDT>;
1095                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1096                 status = "disabled";
1097         };
1098
1099         timer@ff810000 {
1100                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1101                 reg = <0x0 0xff810000 0x0 0x20>;
1102                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1103         };
1104
1105         i2s_2ch: i2s-2ch@ff890000 {
1106                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1107                 reg = <0x0 0xff890000 0x0 0x1000>;
1108                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1109                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1110                 dma-names = "tx", "rx";
1111                 clock-names = "i2s_clk", "i2s_hclk";
1112                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1113                 status = "disabled";
1114         };
1115
1116         i2s_8ch: i2s-8ch@ff898000 {
1117                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1118                 reg = <0x0 0xff898000 0x0 0x1000>;
1119                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1120                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1121                 dma-names = "tx", "rx";
1122                 clock-names = "i2s_clk", "i2s_hclk";
1123                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1124                 pinctrl-names = "default";
1125                 pinctrl-0 = <&i2s_8ch_bus>;
1126                 status = "disabled";
1127         };
1128
1129         isp: isp@ff910000 {
1130                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
1131                 reg = <0x0 0xff910000 0x0 0x4000>;
1132                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1133                 power-domains = <&power RK3368_PD_VIO>;
1134                 clocks =
1135                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1136                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
1137                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
1138                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
1139                 clock-names =
1140                         "aclk_isp", "hclk_isp", "clk_isp",
1141                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1142                         "clk_cif_pll", "hclk_mipiphy1",
1143                         "pclk_dphyrx", "clk_vio0_noc";
1144
1145                 pinctrl-names =
1146                         "default", "isp_dvp8bit2", "isp_dvp10bit",
1147                         "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
1148                         "isp_mipi_fl", "isp_mipi_fl_prefl",
1149                         "isp_flash_as_gpio", "isp_flash_as_trigger_out";
1150                 pinctrl-0 = <&cif_clkout>;
1151                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1152                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1153                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1154                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1155                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1156                 pinctrl-6 = <&cif_clkout>;
1157                 pinctrl-7 = <&cif_clkout &isp_prelight>;
1158                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1159                 pinctrl-9 = <&isp_flash_trigger>;
1160                 rockchip,isp,mipiphy = <2>;
1161                 rockchip,isp,cifphy = <1>;
1162                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1163                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1164                 rockchip,grf = <&grf>;
1165                 rockchip,cru = <&cru>;
1166                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
1167                 rockchip,isp,iommu-enable = <1>;
1168                 iommus = <&isp_mmu>;
1169                 status = "disabled";
1170         };
1171
1172         isp_mmu: iommu@ff914000 {
1173                 compatible = "rockchip,iommu";
1174                 reg = <0x0 0xff914000 0x0 0x100>,
1175                       <0x0 0xff915000 0x0 0x100>;
1176                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1177                 interrupt-names = "isp_mmu";
1178                 clocks = <&cru ACLK_RGA>, <&cru HCLK_ISP>;
1179                 clock-names = "aclk", "hclk";
1180                 rk_iommu,disable_reset_quirk;
1181                 #iommu-cells = <0>;
1182                 power-domains = <&power RK3368_PD_VIO>;
1183                 status = "disabled";
1184         };
1185
1186         vop: vop@ff930000 {
1187                 compatible = "rockchip,rk3368-vop";
1188                 reg = <0x0 0xff930000 0x0 0x2fc>;
1189                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1190                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1191                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1192                 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1193                 assigned-clock-rates = <400000000>, <200000000>;
1194                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1195                 reset-names = "axi", "ahb", "dclk";
1196                 power-domains = <&power RK3368_PD_VIO>;
1197                 iommus = <&vop_mmu>;
1198                 status = "disabled";
1199
1200                 vop_out: port {
1201                         #address-cells = <1>;
1202                         #size-cells = <0>;
1203
1204                         vop_out_mipi: endpoint@0 {
1205                                 reg = <0>;
1206                                 remote-endpoint = <&mipi_in_vop>;
1207                         };
1208
1209                         vop_out_edp: endpoint@1 {
1210                                 reg = <1>;
1211                                 remote-endpoint = <&edp_in_vop>;
1212                         };
1213                 };
1214         };
1215
1216         display_subsystem: display-subsystem {
1217                 compatible = "rockchip,display-subsystem";
1218                 ports = <&vop_out>;
1219                 status = "disabled";
1220         };
1221
1222         vop_mmu: iommu@ff930300 {
1223                 compatible = "rockchip,iommu";
1224                 reg = <0x0 0xff930300 0x0 0x100>;
1225                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1226                 interrupt-names = "vop_mmu";
1227                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1228                 clock-names = "aclk", "hclk";
1229                 power-domains = <&power RK3368_PD_VIO>;
1230                 #iommu-cells = <0>;
1231                 status = "disabled";
1232         };
1233
1234         mipi_dsi_host: mipi-dsi-host@ff960000 {
1235                 compatible = "rockchip,rk3368-mipi-dsi";
1236                 reg = <0x0 0xff960000 0x0 0x4000>;
1237                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1238                 clocks = <&cru PCLK_MIPI_DSI0>;
1239                 clock-names = "pclk";
1240                 phys = <&mipi_dphy>;
1241                 phy-names = "mipi_dphy";
1242                 rockchip,grf = <&grf>;
1243                 power-domains = <&power RK3368_PD_VIO>;
1244                 #address-cells = <1>;
1245                 #size-cells = <0>;
1246                 status = "disabled";
1247
1248                 ports@1 {
1249                         #address-cells = <1>;
1250                         #size-cells = <0>;
1251                         reg = <1>;
1252
1253                         mipi_in: port {
1254                                 #address-cells = <1>;
1255                                 #size-cells = <0>;
1256
1257                                 mipi_in_vop: endpoint@0 {
1258                                         reg = <0>;
1259                                         remote-endpoint = <&vop_out_mipi>;
1260                                 };
1261                         };
1262                 };
1263         };
1264
1265         mipi_dphy: mipi-dphy@ff968000 {
1266                 compatible = "rockchip,rk3368-mipi-dphy";
1267                 reg = <0x0 0xff968000 0x0 0x4000>;
1268                 #phy-cells = <0>;
1269                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1270                 clock-names = "ref", "pclk";
1271                 status = "disabled";
1272         };
1273
1274         edp: edp@ff970000 {
1275                 compatible = "rockchip,rk3368-edp";
1276                 reg = <0x0 0xff970000 0x0 0x8000>;
1277                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1278                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1279                 clock-names = "dp", "pclk";
1280                 resets = <&cru SRST_EDP>;
1281                 reset-names = "dp";
1282                 power-domains = <&power RK3368_PD_VIO>;
1283                 rockchip,grf = <&grf>;
1284                 phys = <&edp_phy>;
1285                 phy-names = "dp";
1286                 pinctrl-names = "default";
1287                 pinctrl-0 = <&edp_hpd>;
1288                 status = "disabled";
1289
1290                 ports {
1291                         #address-cells = <1>;
1292                         #size-cells = <0>;
1293
1294                         edp_in: port@0 {
1295                                 reg = <0>;
1296
1297                                 edp_in_vop: endpoint {
1298                                         remote-endpoint = <&vop_out_edp>;
1299                                 };
1300                         };
1301                 };
1302         };
1303
1304         hevc_mmu: iommu@ff9a0440 {
1305                 compatible = "rockchip,iommu";
1306                 reg = <0x0 0xff9a0440 0x0 0x40>,
1307                       <0x0 0xff9a0480 0x0 0x40>;
1308                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1309                 interrupt-names = "hevc_mmu";
1310                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1311                 clock-names = "aclk", "hclk";
1312                 power-domains = <&power RK3368_PD_VIDEO>;
1313                 #iommu-cells = <0>;
1314                 status = "disabled";
1315         };
1316
1317         vpu_mmu: iommu@ff9a0800 {
1318                 compatible = "rockchip,iommu";
1319                 reg = <0x0 0xff9a0800 0x0 0x100>;
1320                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1321                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1322                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1323                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1324                 clock-names = "aclk", "hclk";
1325                 power-domains = <&power RK3368_PD_VIDEO>;
1326                 #iommu-cells = <0>;
1327                 status = "disabled";
1328         };
1329
1330         vpu: vpu_service {
1331                 compatible = "rockchip,vpu_sub";
1332                 iommu_enabled = <1>;
1333                 iommus = <&vpu_mmu>;
1334                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1335                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1336                 interrupt-names = "irq_enc","irq_dec";
1337                 dev_mode = <0>;
1338                 name = "vpu_service";
1339                 allocator = <1>;
1340         };
1341
1342         hevc: hevc_service {
1343                 compatible = "rockchip,hevc_sub";
1344                 iommu_enabled = <1>;
1345                 iommus = <&hevc_mmu>;
1346                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1347                 interrupt-names = "irq_dec";
1348                 dev_mode = <1>;
1349                 name = "hevc_service";
1350                 allocator = <1>;
1351         };
1352
1353         vpu_combo: vpu_combo@ff9a0000 {
1354                 compatible = "rockchip,vpu_combo";
1355                 reg = <0x0 0xff9a0000 0x0 0x440>;
1356                 rockchip,grf = <&grf>;
1357                 subcnt = <2>;
1358                 rockchip,sub = <&vpu>, <&hevc>;
1359                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
1360                          <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
1361                 clock-names = "aclk_vcodec", "hclk_vcodec",
1362                               "clk_core", "clk_cabac";
1363                 resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
1364                          <&cru SRST_VIDEO>;
1365                 reset-names = "video_a", "video_h", "video";
1366                 mode_bit = <12>;
1367                 mode_ctrl = <0x418>;
1368                 name = "vpu_combo";
1369                 power-domains = <&power RK3368_PD_VIDEO>;
1370                 status = "disabled";
1371         };
1372
1373         gic: interrupt-controller@ffb71000 {
1374                 compatible = "arm,gic-400";
1375                 interrupt-controller;
1376                 #interrupt-cells = <3>;
1377                 #address-cells = <0>;
1378
1379                 reg = <0x0 0xffb71000 0x0 0x1000>,
1380                       <0x0 0xffb72000 0x0 0x2000>,
1381                       <0x0 0xffb74000 0x0 0x2000>,
1382                       <0x0 0xffb76000 0x0 0x2000>;
1383                 interrupts = <GIC_PPI 9
1384                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1385         };
1386
1387         gpu: rogue-g6110@ffa30000 {
1388                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1389                 reg = <0x0 0xffa30000 0x0 0x10000>;
1390                 clocks =
1391                         <&cru SCLK_GPU_CORE>,
1392                         <&cru ACLK_GPU_MEM>,
1393                         <&cru ACLK_GPU_CFG>;
1394                 clock-names =
1395                         "sclk_gpu_core",
1396                         "aclk_gpu_mem",
1397                         "aclk_gpu_cfg";
1398                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1399                 interrupt-names = "rogue-g6110-irq";
1400                 power-domains = <&power RK3368_PD_GPU_1>;
1401                 operating-points-v2 = <&gpu_opp_table>;
1402                 #cooling-cells = <2>; /* min followed by max */
1403                 gpu_power_model: power_model {
1404                         compatible = "arm,mali-simple-power-model";
1405                         voltage = <900>;
1406                         frequency = <500>;
1407                         static-power = <300>;
1408                         dynamic-power = <396>;
1409                         ts = <32000 4700 (-80) 2>;
1410                         thermal-zone = "gpu-thermal";
1411                 };
1412         };
1413
1414         gpu_opp_table: gpu_opp_table {
1415                 compatible = "operating-points-v2";
1416                 opp-shared;
1417
1418                 opp@200000000 {
1419                         opp-hz = /bits/ 64 <200000000>;
1420                         opp-microvolt = <1100000>;
1421                 };
1422                 opp@288000000 {
1423                         opp-hz = /bits/ 64 <288000000>;
1424                         opp-microvolt = <1100000>;
1425                 };
1426                 opp@400000000 {
1427                         opp-hz = /bits/ 64 <400000000>;
1428                         opp-microvolt = <1100000>;
1429                 };
1430                 opp@576000000 {
1431                         opp-hz = /bits/ 64 <576000000>;
1432                         opp-microvolt = <1200000>;
1433                 };
1434         };
1435
1436         efuse: efuse@ffb00000 {
1437                 compatible = "rockchip,rk3368-efuse";
1438                 reg = <0x0 0xffb00000 0x0 0x20>;
1439                 #address-cells = <1>;
1440                 #size-cells = <1>;
1441                 clocks = <&cru PCLK_EFUSE256>;
1442                 clock-names = "pclk_efuse";
1443
1444                 /* Data cells */
1445                 cpu_leakage: cpu-leakage@17 {
1446                         reg = <0x17 0x1>;
1447                 };
1448                 temp_adjust: temp-adjust@1f {
1449                         reg = <0x1f 0x1>;
1450                 };
1451         };
1452
1453         pinctrl: pinctrl {
1454                 compatible = "rockchip,rk3368-pinctrl";
1455                 rockchip,grf = <&grf>;
1456                 rockchip,pmu = <&pmugrf>;
1457                 #address-cells = <0x2>;
1458                 #size-cells = <0x2>;
1459                 ranges;
1460
1461                 gpio0: gpio0@ff750000 {
1462                         compatible = "rockchip,gpio-bank";
1463                         reg = <0x0 0xff750000 0x0 0x100>;
1464                         clocks = <&cru PCLK_GPIO0>;
1465                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1466
1467                         gpio-controller;
1468                         #gpio-cells = <0x2>;
1469
1470                         interrupt-controller;
1471                         #interrupt-cells = <0x2>;
1472                 };
1473
1474                 gpio1: gpio1@ff780000 {
1475                         compatible = "rockchip,gpio-bank";
1476                         reg = <0x0 0xff780000 0x0 0x100>;
1477                         clocks = <&cru PCLK_GPIO1>;
1478                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1479
1480                         gpio-controller;
1481                         #gpio-cells = <0x2>;
1482
1483                         interrupt-controller;
1484                         #interrupt-cells = <0x2>;
1485                 };
1486
1487                 gpio2: gpio2@ff790000 {
1488                         compatible = "rockchip,gpio-bank";
1489                         reg = <0x0 0xff790000 0x0 0x100>;
1490                         clocks = <&cru PCLK_GPIO2>;
1491                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1492
1493                         gpio-controller;
1494                         #gpio-cells = <0x2>;
1495
1496                         interrupt-controller;
1497                         #interrupt-cells = <0x2>;
1498                 };
1499
1500                 gpio3: gpio3@ff7a0000 {
1501                         compatible = "rockchip,gpio-bank";
1502                         reg = <0x0 0xff7a0000 0x0 0x100>;
1503                         clocks = <&cru PCLK_GPIO3>;
1504                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1505
1506                         gpio-controller;
1507                         #gpio-cells = <0x2>;
1508
1509                         interrupt-controller;
1510                         #interrupt-cells = <0x2>;
1511                 };
1512
1513                 pcfg_pull_up: pcfg-pull-up {
1514                         bias-pull-up;
1515                 };
1516
1517                 pcfg_pull_down: pcfg-pull-down {
1518                         bias-pull-down;
1519                 };
1520
1521                 pcfg_pull_none: pcfg-pull-none {
1522                         bias-disable;
1523                 };
1524
1525                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1526                         bias-disable;
1527                         drive-strength = <12>;
1528                 };
1529
1530                 edp {
1531                         edp_hpd: edp-hpd {
1532                                 rockchip,pins = <2 23 RK_FUNC_2 &pcfg_pull_none>;
1533                         };
1534                 };
1535
1536                 emmc {
1537                         emmc_clk: emmc-clk {
1538                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1539                         };
1540
1541                         emmc_cmd: emmc-cmd {
1542                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1543                         };
1544
1545                         emmc_pwr: emmc-pwr {
1546                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1547                         };
1548
1549                         emmc_bus1: emmc-bus1 {
1550                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1551                         };
1552
1553                         emmc_bus4: emmc-bus4 {
1554                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1555                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1556                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1557                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1558                         };
1559
1560                         emmc_bus8: emmc-bus8 {
1561                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1562                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1563                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1564                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1565                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1566                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1567                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1568                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1569                         };
1570                 };
1571
1572                 gmac {
1573                         rgmii_pins: rgmii-pins {
1574                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1575                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1576                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1577                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1578                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1579                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1580                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1581                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1582                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1583                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1584                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1585                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1586                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1587                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1588                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1589                         };
1590
1591                         rmii_pins: rmii-pins {
1592                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1593                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1594                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1595                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1596                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1597                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1598                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1599                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1600                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1601                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1602                         };
1603                 };
1604
1605                 i2c0 {
1606                         i2c0_xfer: i2c0-xfer {
1607                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1608                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1609                         };
1610                 };
1611
1612                 i2c1 {
1613                         i2c1_xfer: i2c1-xfer {
1614                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1615                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1616                         };
1617                 };
1618
1619                 i2c2 {
1620                         i2c2_xfer: i2c2-xfer {
1621                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1622                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1623                         };
1624                 };
1625
1626                 i2c3 {
1627                         i2c3_xfer: i2c3-xfer {
1628                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1629                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1630                         };
1631                 };
1632
1633                 i2c4 {
1634                         i2c4_xfer: i2c4-xfer {
1635                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1636                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1637                         };
1638                 };
1639
1640                 i2c5 {
1641                         i2c5_xfer: i2c5-xfer {
1642                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1643                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1644                         };
1645                 };
1646
1647                 i2s {
1648                         i2s_8ch_bus: i2s-8ch-bus {
1649                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1650                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1651                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1652                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1653                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1654                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1655                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1656                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1657                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1658                         };
1659                 };
1660
1661                 pwm0 {
1662                         pwm0_pin: pwm0-pin {
1663                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1664                         };
1665
1666                         vop_pwm_pin: vop-pwm {
1667                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1668                         };
1669                 };
1670
1671                 pwm1 {
1672                         pwm1_pin: pwm1-pin {
1673                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1674                         };
1675                 };
1676
1677                 pwm3 {
1678                         pwm3_pin: pwm3-pin {
1679                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1680                         };
1681                 };
1682
1683                 sdio0 {
1684                         sdio0_bus1: sdio0-bus1 {
1685                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1686                         };
1687
1688                         sdio0_bus4: sdio0-bus4 {
1689                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1690                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1691                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1692                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1693                         };
1694
1695                         sdio0_cmd: sdio0-cmd {
1696                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1697                         };
1698
1699                         sdio0_clk: sdio0-clk {
1700                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1701                         };
1702
1703                         sdio0_cd: sdio0-cd {
1704                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1705                         };
1706
1707                         sdio0_wp: sdio0-wp {
1708                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1709                         };
1710
1711                         sdio0_pwr: sdio0-pwr {
1712                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1713                         };
1714
1715                         sdio0_bkpwr: sdio0-bkpwr {
1716                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1717                         };
1718
1719                         sdio0_int: sdio0-int {
1720                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1721                         };
1722                 };
1723
1724                 sdmmc {
1725                         sdmmc_clk: sdmmc-clk {
1726                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1727                         };
1728
1729                         sdmmc_cmd: sdmmc-cmd {
1730                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1731                         };
1732
1733                         sdmmc_cd: sdmmc-cd {
1734                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1735                         };
1736
1737                         sdmmc_bus1: sdmmc-bus1 {
1738                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1739                         };
1740
1741                         sdmmc_bus4: sdmmc-bus4 {
1742                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1743                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1744                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1745                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1746                         };
1747                 };
1748
1749                 spi0 {
1750                         spi0_clk: spi0-clk {
1751                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1752                         };
1753                         spi0_cs0: spi0-cs0 {
1754                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1755                         };
1756                         spi0_cs1: spi0-cs1 {
1757                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1758                         };
1759                         spi0_tx: spi0-tx {
1760                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1761                         };
1762                         spi0_rx: spi0-rx {
1763                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1764                         };
1765                 };
1766
1767                 spi1 {
1768                         spi1_clk: spi1-clk {
1769                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1770                         };
1771                         spi1_cs0: spi1-cs0 {
1772                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1773                         };
1774                         spi1_cs1: spi1-cs1 {
1775                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1776                         };
1777                         spi1_rx: spi1-rx {
1778                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1779                         };
1780                         spi1_tx: spi1-tx {
1781                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1782                         };
1783                 };
1784
1785                 spi2 {
1786                         spi2_clk: spi2-clk {
1787                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1788                         };
1789                         spi2_cs0: spi2-cs0 {
1790                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1791                         };
1792                         spi2_rx: spi2-rx {
1793                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1794                         };
1795                         spi2_tx: spi2-tx {
1796                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1797                         };
1798                 };
1799
1800                 uart0 {
1801                         uart0_xfer: uart0-xfer {
1802                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1803                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1804                         };
1805
1806                         uart0_cts: uart0-cts {
1807                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1808                         };
1809
1810                         uart0_rts: uart0-rts {
1811                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1812                         };
1813                 };
1814
1815                 uart1 {
1816                         uart1_xfer: uart1-xfer {
1817                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1818                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1819                         };
1820
1821                         uart1_cts: uart1-cts {
1822                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1823                         };
1824
1825                         uart1_rts: uart1-rts {
1826                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1827                         };
1828                 };
1829
1830                 uart2 {
1831                         uart2_xfer: uart2-xfer {
1832                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1833                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1834                         };
1835                         /* no rts / cts for uart2 */
1836                 };
1837
1838                 uart3 {
1839                         uart3_xfer: uart3-xfer {
1840                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1841                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1842                         };
1843
1844                         uart3_cts: uart3-cts {
1845                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1846                         };
1847
1848                         uart3_rts: uart3-rts {
1849                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1850                         };
1851                 };
1852
1853                 uart4 {
1854                         uart4_xfer: uart4-xfer {
1855                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1856                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1857                         };
1858
1859                         uart4_cts: uart4-cts {
1860                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1861                         };
1862
1863                         uart4_rts: uart4-rts {
1864                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1865                         };
1866                 };
1867
1868                 isp {
1869                         cif_clkout: cif-clkout {
1870                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1871                         };
1872
1873                         isp_dvp_d2d9: isp-dvp-d2d9 {
1874                                 rockchip,pins =
1875                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1876                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1877                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1878                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1879                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1880                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1881                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1882                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1883                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1884                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1885                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1886                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1887                         };
1888
1889                         isp_dvp_d0d1: isp-dvp-d0d1 {
1890                                 rockchip,pins =
1891                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1892                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1893                         };
1894
1895                         isp_dvp_d10d11:isp_d10d11 {
1896                                 rockchip,pins =
1897                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1898                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1899                         };
1900
1901                         isp_dvp_d0d7: isp-dvp-d0d7 {
1902                                 rockchip,pins =
1903                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1904                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1905                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1906                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1907                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1908                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1909                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1910                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1911                         };
1912
1913                         isp_dvp_d4d11: isp-dvp-d4d11 {
1914                                 rockchip,pins =
1915                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1916                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1917                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1918                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1919                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1920                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1921                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1922                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1923                         };
1924
1925                         isp_shutter: isp-shutter {
1926                                 rockchip,pins =
1927                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1928                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1929                         };
1930
1931                         isp_flash_trigger: isp-flash-trigger {
1932                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1933                         };
1934
1935                         isp_prelight: isp-prelight {
1936                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1937                         };
1938
1939                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1940                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1941                         };
1942                 };
1943         };
1944 };