arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/display/mipi_dsi.h>
  50 #include <dt-bindings/power/rk3368-power.h>
  51 #include <dt-bindings/soc/rockchip,boot-mode.h>
  52 #include <dt-bindings/thermal/thermal.h>
  53
  54 / {
  55         compatible = "rockchip,rk3368";
  56         interrupt-parent = <&gic>;
  57         #address-cells = <2>;
  58         #size-cells = <2>;
  59
  60         aliases {
  61                 ethernet0 = &gmac;
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73                 spi0 = &spi0;
  74                 spi1 = &spi1;
  75                 spi2 = &spi2;
  76                 lcdc = &lcdc;
  77         };
  78
  79         cpus {
  80                 #address-cells = <0x2>;
  81                 #size-cells = <0x0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_b0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_b1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_b2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_b3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_l0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_l1>;
 105                                 };
 106                                 core2 {
 107                                         cpu = <&cpu_l2>;
 108                                 };
 109                                 core3 {
 110                                         cpu = <&cpu_l3>;
 111                                 };
 112                         };
 113                 };
 114
 115                 idle-states {
 116                         entry-method = "psci";
 117
 118                         cpu_sleep: cpu-sleep-0 {
 119                                 compatible = "arm,idle-state";
 120                                 arm,psci-suspend-param = <0x1010000>;
 121                                 entry-latency-us = <0x3fffffff>;
 122                                 exit-latency-us = <0x40000000>;
 123                                 min-residency-us = <0xffffffff>;
 124                         };
 125                 };
 126
 127                 cpu_l0: cpu@0 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x0 0x0>;
 131                         cpu-idle-states = <&cpu_sleep>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster1_opp>;
 135
 136                         #cooling-cells = <2>; /* min followed by max */
 137                 };
 138
 139                 cpu_l1: cpu@1 {
 140                         device_type = "cpu";
 141                         compatible = "arm,cortex-a53", "arm,armv8";
 142                         reg = <0x0 0x1>;
 143                         cpu-idle-states = <&cpu_sleep>;
 144                         enable-method = "psci";
 145                         clocks = <&cru ARMCLKL>;
 146                         operating-points-v2 = <&cluster1_opp>;
 147                 };
 148
 149                 cpu_l2: cpu@2 {
 150                         device_type = "cpu";
 151                         compatible = "arm,cortex-a53", "arm,armv8";
 152                         reg = <0x0 0x2>;
 153                         cpu-idle-states = <&cpu_sleep>;
 154                         enable-method = "psci";
 155                         clocks = <&cru ARMCLKL>;
 156                         operating-points-v2 = <&cluster1_opp>;
 157                 };
 158
 159                 cpu_l3: cpu@3 {
 160                         device_type = "cpu";
 161                         compatible = "arm,cortex-a53", "arm,armv8";
 162                         reg = <0x0 0x3>;
 163                         cpu-idle-states = <&cpu_sleep>;
 164                         enable-method = "psci";
 165                         clocks = <&cru ARMCLKL>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                 };
 168
 169                 cpu_b0: cpu@100 {
 170                         device_type = "cpu";
 171                         compatible = "arm,cortex-a53", "arm,armv8";
 172                         reg = <0x0 0x100>;
 173                         cpu-idle-states = <&cpu_sleep>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         operating-points-v2 = <&cluster0_opp>;
 177
 178                         #cooling-cells = <2>; /* min followed by max */
 179                 };
 180
 181                 cpu_b1: cpu@101 {
 182                         device_type = "cpu";
 183                         compatible = "arm,cortex-a53", "arm,armv8";
 184                         reg = <0x0 0x101>;
 185                         cpu-idle-states = <&cpu_sleep>;
 186                         enable-method = "psci";
 187                         clocks = <&cru ARMCLKB>;
 188                         operating-points-v2 = <&cluster0_opp>;
 189                 };
 190
 191                 cpu_b2: cpu@102 {
 192                         device_type = "cpu";
 193                         compatible = "arm,cortex-a53", "arm,armv8";
 194                         reg = <0x0 0x102>;
 195                         cpu-idle-states = <&cpu_sleep>;
 196                         enable-method = "psci";
 197                         clocks = <&cru ARMCLKB>;
 198                         operating-points-v2 = <&cluster0_opp>;
 199                 };
 200
 201                 cpu_b3: cpu@103 {
 202                         device_type = "cpu";
 203                         compatible = "arm,cortex-a53", "arm,armv8";
 204                         reg = <0x0 0x103>;
 205                         cpu-idle-states = <&cpu_sleep>;
 206                         enable-method = "psci";
 207                         clocks = <&cru ARMCLKB>;
 208                         operating-points-v2 = <&cluster0_opp>;
 209                 };
 210         };
 211
 212         cluster0_opp: opp_table0 {
 213                 compatible = "operating-points-v2";
 214                 opp-shared;
 215
 216                 opp@408000000 {
 217                         opp-hz = /bits/ 64 <408000000>;
 218                         opp-microvolt = <1200000>;
 219                         clock-latency-ns = <40000>;
 220                         opp-suspend;
 221                 };
 222                 opp@600000000 {
 223                         opp-hz = /bits/ 64 <600000000>;
 224                         opp-microvolt = <1200000>;
 225                 };
 226                 opp@816000000 {
 227                         opp-hz = /bits/ 64 <816000000>;
 228                         opp-microvolt = <1200000>;
 229                 };
 230                 opp@1008000000 {
 231                         opp-hz = /bits/ 64 <1008000000>;
 232                         opp-microvolt = <1200000>;
 233                 };
 234                 opp@1200000000 {
 235                         opp-hz = /bits/ 64 <1200000000>;
 236                         opp-microvolt = <1200000>;
 237                 };
 238         };
 239
 240         cluster1_opp: opp_table1 {
 241                 compatible = "operating-points-v2";
 242                 opp-shared;
 243
 244                 opp@408000000 {
 245                         opp-hz = /bits/ 64 <408000000>;
 246                         opp-microvolt = <1200000>;
 247                         clock-latency-ns = <40000>;
 248                         opp-suspend;
 249                 };
 250                 opp@600000000 {
 251                         opp-hz = /bits/ 64 <600000000>;
 252                         opp-microvolt = <1200000>;
 253                 };
 254                 opp@816000000 {
 255                         opp-hz = /bits/ 64 <816000000>;
 256                         opp-microvolt = <1200000>;
 257                 };
 258                 opp@1008000000 {
 259                         opp-hz = /bits/ 64 <1008000000>;
 260                         opp-microvolt = <1200000>;
 261                 };
 262         };
 263
 264         arm-pmu {
 265                 compatible = "arm,armv8-pmuv3";
 266                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 269                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 270                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 271                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 273                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 274                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 275                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 276                                      <&cpu_b2>, <&cpu_b3>;
 277         };
 278
 279         amba {
 280                 compatible = "arm,amba-bus";
 281                 #address-cells = <2>;
 282                 #size-cells = <2>;
 283                 ranges;
 284
 285                 dmac_peri: dma-controller@ff250000 {
 286                         compatible = "arm,pl330", "arm,primecell";
 287                         reg = <0x0 0xff250000 0x0 0x4000>;
 288                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 289                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 290                         #dma-cells = <1>;
 291                         clocks = <&cru ACLK_DMAC_PERI>;
 292                         clock-names = "apb_pclk";
 293                         arm,pl330-broken-no-flushp;
 294                         peripherals-req-type-burst;
 295                 };
 296
 297                 dmac_bus: dma-controller@ff600000 {
 298                         compatible = "arm,pl330", "arm,primecell";
 299                         reg = <0x0 0xff600000 0x0 0x4000>;
 300                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 301                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 302                         #dma-cells = <1>;
 303                         clocks = <&cru ACLK_DMAC_BUS>;
 304                         clock-names = "apb_pclk";
 305                         arm,pl330-broken-no-flushp;
 306                         peripherals-req-type-burst;
 307                 };
 308         };
 309
 310         psci {
 311                 compatible = "arm,psci-0.2";
 312                 method = "smc";
 313         };
 314
 315         timer {
 316                 compatible = "arm,armv8-timer";
 317                 interrupts = <GIC_PPI 13
 318                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 319                              <GIC_PPI 14
 320                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 321                              <GIC_PPI 11
 322                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 323                              <GIC_PPI 10
 324                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 325         };
 326
 327         xin24m: oscillator {
 328                 compatible = "fixed-clock";
 329                 clock-frequency = <24000000>;
 330                 clock-output-names = "xin24m";
 331                 #clock-cells = <0>;
 332         };
 333
 334         sdmmc: rksdmmc@ff0c0000 {
 335                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 336                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 337                 clock-freq-min-max = <400000 150000000>;
 338                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 339                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 340                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 341                 fifo-depth = <0x100>;
 342                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 343                 status = "disabled";
 344         };
 345
 346         sdio0: dwmmc@ff0d0000 {
 347                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 348                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 349                 clock-freq-min-max = <400000 150000000>;
 350                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 351                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 352                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 353                 fifo-depth = <0x100>;
 354                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 355                 status = "disabled";
 356         };
 357
 358         emmc: rksdmmc@ff0f0000 {
 359                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 360                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 361                 clock-freq-min-max = <400000 150000000>;
 362                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 363                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 364                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 365                 fifo-depth = <0x100>;
 366                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 367                 status = "disabled";
 368         };
 369
 370         saradc: saradc@ff100000 {
 371                 compatible = "rockchip,saradc";
 372                 reg = <0x0 0xff100000 0x0 0x100>;
 373                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 374                 #io-channel-cells = <1>;
 375                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 376                 clock-names = "saradc", "apb_pclk";
 377                 resets = <&cru SRST_SARADC>;
 378                 reset-names = "saradc-apb";
 379                 status = "disabled";
 380         };
 381
 382         spi0: spi@ff110000 {
 383                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 384                 reg = <0x0 0xff110000 0x0 0x1000>;
 385                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 386                 clock-names = "spiclk", "apb_pclk";
 387                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 388                 pinctrl-names = "default";
 389                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 390                 #address-cells = <1>;
 391                 #size-cells = <0>;
 392                 status = "disabled";
 393         };
 394
 395         spi1: spi@ff120000 {
 396                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 397                 reg = <0x0 0xff120000 0x0 0x1000>;
 398                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 399                 clock-names = "spiclk", "apb_pclk";
 400                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 status = "disabled";
 406         };
 407
 408         spi2: spi@ff130000 {
 409                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 410                 reg = <0x0 0xff130000 0x0 0x1000>;
 411                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 412                 clock-names = "spiclk", "apb_pclk";
 413                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 status = "disabled";
 419         };
 420
 421         i2c0: i2c@ff650000 {
 422                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 423                 reg = <0x0 0xff650000 0x0 0x1000>;
 424                 clocks = <&cru PCLK_I2C0>;
 425                 clock-names = "i2c";
 426                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&i2c0_xfer>;
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 status = "disabled";
 432         };
 433
 434         i2c2: i2c@ff140000 {
 435                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 436                 reg = <0x0 0xff140000 0x0 0x1000>;
 437                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 clock-names = "i2c";
 441                 clocks = <&cru PCLK_I2C2>;
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&i2c2_xfer>;
 444                 status = "disabled";
 445         };
 446
 447         i2c3: i2c@ff150000 {
 448                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 449                 reg = <0x0 0xff150000 0x0 0x1000>;
 450                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 451                 #address-cells = <1>;
 452                 #size-cells = <0>;
 453                 clock-names = "i2c";
 454                 clocks = <&cru PCLK_I2C3>;
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&i2c3_xfer>;
 457                 status = "disabled";
 458         };
 459
 460         i2c4: i2c@ff160000 {
 461                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 462                 reg = <0x0 0xff160000 0x0 0x1000>;
 463                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 464                 #address-cells = <1>;
 465                 #size-cells = <0>;
 466                 clock-names = "i2c";
 467                 clocks = <&cru PCLK_I2C4>;
 468                 pinctrl-names = "default";
 469                 pinctrl-0 = <&i2c4_xfer>;
 470                 status = "disabled";
 471         };
 472
 473         i2c5: i2c@ff170000 {
 474                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 475                 reg = <0x0 0xff170000 0x0 0x1000>;
 476                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 477                 #address-cells = <1>;
 478                 #size-cells = <0>;
 479                 clock-names = "i2c";
 480                 clocks = <&cru PCLK_I2C5>;
 481                 pinctrl-names = "default";
 482                 pinctrl-0 = <&i2c5_xfer>;
 483                 status = "disabled";
 484         };
 485
 486         uart0: serial@ff180000 {
 487                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 488                 reg = <0x0 0xff180000 0x0 0x100>;
 489                 clock-frequency = <24000000>;
 490                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 491                 clock-names = "baudclk", "apb_pclk";
 492                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 493                 reg-shift = <2>;
 494                 reg-io-width = <4>;
 495                 status = "disabled";
 496         };
 497
 498         uart1: serial@ff190000 {
 499                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 500                 reg = <0x0 0xff190000 0x0 0x100>;
 501                 clock-frequency = <24000000>;
 502                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 503                 clock-names = "baudclk", "apb_pclk";
 504                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 505                 reg-shift = <2>;
 506                 reg-io-width = <4>;
 507                 status = "disabled";
 508         };
 509
 510         uart3: serial@ff1b0000 {
 511                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 512                 reg = <0x0 0xff1b0000 0x0 0x100>;
 513                 clock-frequency = <24000000>;
 514                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 515                 clock-names = "baudclk", "apb_pclk";
 516                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 517                 reg-shift = <2>;
 518                 reg-io-width = <4>;
 519                 status = "disabled";
 520         };
 521
 522         uart4: serial@ff1c0000 {
 523                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 524                 reg = <0x0 0xff1c0000 0x0 0x100>;
 525                 clock-frequency = <24000000>;
 526                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 527                 clock-names = "baudclk", "apb_pclk";
 528                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 529                 reg-shift = <2>;
 530                 reg-io-width = <4>;
 531                 status = "disabled";
 532         };
 533
 534         thermal-zones {
 535                 #include "rk3368-thermal.dtsi"
 536         };
 537
 538         tsadc: tsadc@ff280000 {
 539                 compatible = "rockchip,rk3368-tsadc";
 540                 reg = <0x0 0xff280000 0x0 0x100>;
 541                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 542                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 543                 clock-names = "tsadc", "apb_pclk";
 544                 resets = <&cru SRST_TSADC>;
 545                 reset-names = "tsadc-apb";
 546                 pinctrl-names = "init", "default", "sleep";
 547                 pinctrl-0 = <&otp_gpio>;
 548                 pinctrl-1 = <&otp_out>;
 549                 pinctrl-2 = <&otp_gpio>;
 550                 #thermal-sensor-cells = <1>;
 551                 rockchip,hw-tshut-temp = <95000>;
 552                 status = "disabled";
 553         };
 554
 555         gmac: ethernet@ff290000 {
 556                 compatible = "rockchip,rk3368-gmac";
 557                 reg = <0x0 0xff290000 0x0 0x10000>;
 558                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 559                 interrupt-names = "macirq";
 560                 rockchip,grf = <&grf>;
 561                 clocks = <&cru SCLK_MAC>,
 562                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 563                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 564                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 565                 clock-names = "stmmaceth",
 566                         "mac_clk_rx", "mac_clk_tx",
 567                         "clk_mac_ref", "clk_mac_refout",
 568                         "aclk_mac", "pclk_mac";
 569                 status = "disabled";
 570         };
 571
 572         nandc0: nandc@ff400000 {
 573                 compatible = "rockchip,rk-nandc";
 574                 reg = <0x0 0xff400000 0x0 0x4000>;
 575                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 576                 nandc_id = <0>;
 577                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 578                 clock-names = "clk_nandc", "hclk_nandc";
 579                 status = "disabled";
 580         };
 581
 582         usb_host0_ehci: usb@ff500000 {
 583                 compatible = "generic-ehci";
 584                 reg = <0x0 0xff500000 0x0 0x100>;
 585                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 586                 clocks = <&cru HCLK_HOST0>;
 587                 clock-names = "usbhost";
 588                 status = "disabled";
 589         };
 590
 591         usb_otg: usb@ff580000 {
 592                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 593                                 "snps,dwc2";
 594                 reg = <0x0 0xff580000 0x0 0x40000>;
 595                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 596                 clocks = <&cru HCLK_OTG0>;
 597                 clock-names = "otg";
 598                 dr_mode = "otg";
 599                 g-np-tx-fifo-size = <16>;
 600                 g-rx-fifo-size = <275>;
 601                 g-tx-fifo-size = <256 128 128 64 64 32>;
 602                 g-use-dma;
 603                 status = "disabled";
 604         };
 605
 606         ddrpctl: syscon@ff610000 {
 607                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 608                 reg = <0x0 0xff610000 0x0 0x400>;
 609         };
 610
 611         i2c1: i2c@ff660000 {
 612                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 613                 reg = <0x0 0xff660000 0x0 0x1000>;
 614                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 615                 #address-cells = <1>;
 616                 #size-cells = <0>;
 617                 clock-names = "i2c";
 618                 clocks = <&cru PCLK_I2C1>;
 619                 pinctrl-names = "default";
 620                 pinctrl-0 = <&i2c1_xfer>;
 621                 status = "disabled";
 622         };
 623
 624         pwm0: pwm@ff680000 {
 625                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 626                 reg = <0x0 0xff680000 0x0 0x10>;
 627                 #pwm-cells = <3>;
 628                 pinctrl-names = "default";
 629                 pinctrl-0 = <&pwm0_pin>;
 630                 clocks = <&cru PCLK_PWM1>;
 631                 clock-names = "pwm";
 632                 status = "disabled";
 633         };
 634
 635         pwm1: pwm@ff680010 {
 636                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 637                 reg = <0x0 0xff680010 0x0 0x10>;
 638                 #pwm-cells = <3>;
 639                 pinctrl-names = "default";
 640                 pinctrl-0 = <&pwm1_pin>;
 641                 clocks = <&cru PCLK_PWM1>;
 642                 clock-names = "pwm";
 643                 status = "disabled";
 644         };
 645
 646         pwm2: pwm@ff680020 {
 647                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 648                 reg = <0x0 0xff680020 0x0 0x10>;
 649                 #pwm-cells = <3>;
 650                 clocks = <&cru PCLK_PWM1>;
 651                 clock-names = "pwm";
 652                 status = "disabled";
 653         };
 654
 655         pwm3: pwm@ff680030 {
 656                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 657                 reg = <0x0 0xff680030 0x0 0x10>;
 658                 #pwm-cells = <3>;
 659                 pinctrl-names = "default";
 660                 pinctrl-0 = <&pwm3_pin>;
 661                 clocks = <&cru PCLK_PWM1>;
 662                 clock-names = "pwm";
 663                 status = "disabled";
 664         };
 665
 666         uart2: serial@ff690000 {
 667                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 668                 reg = <0x0 0xff690000 0x0 0x100>;
 669                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 670                 clock-names = "baudclk", "apb_pclk";
 671                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 672                 pinctrl-names = "default";
 673                 pinctrl-0 = <&uart2_xfer>;
 674                 reg-shift = <2>;
 675                 reg-io-width = <4>;
 676                 status = "disabled";
 677         };
 678
 679         pmu: power-management@ff730000 {
 680                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 681                 reg = <0x0 0xff730000 0x0 0x1000>;
 682
 683                 power: power-controller {
 684                         status = "disabled";
 685                         compatible = "rockchip,rk3368-power-controller";
 686                         #power-domain-cells = <1>;
 687                         #address-cells = <1>;
 688                         #size-cells = <0>;
 689
 690                         /*
 691                          * Note: Although SCLK_* are the working clocks
 692                          * of device without including on the NOC, needed for
 693                          * synchronous reset.
 694                          *
 695                          * The clocks on the which NOC:
 696                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 697                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 698                          * ACLK_RGA is on ACLK_RGA_NIU.
 699                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 700                          *
 701                          * Which clock are device clocks:
 702                          *      clocks          devices
 703                          *      *_IEP           IEP:Image Enhancement Processor
 704                          *      *_ISP           ISP:Image Signal Processing
 705                          *      *_VIP           VIP:Video Input Processor
 706                          *      *_VOP*          VOP:Visual Output Processor
 707                          *      *_RGA           RGA
 708                          *      *_EDP*          EDP
 709                          *      *_DPHY*         LVDS
 710                          *      *_HDMI          HDMI
 711                          *      *_MIPI_*        MIPI
 712                          */
 713                         pd_vio {
 714                                 reg = <RK3368_PD_VIO>;
 715                                 clocks = <&cru ACLK_IEP>,
 716                                          <&cru ACLK_ISP>,
 717                                          <&cru ACLK_VIP>,
 718                                          <&cru ACLK_RGA>,
 719                                          <&cru ACLK_VOP>,
 720                                          <&cru ACLK_VOP_IEP>,
 721                                          <&cru DCLK_VOP>,
 722                                          <&cru HCLK_IEP>,
 723                                          <&cru HCLK_ISP>,
 724                                          <&cru HCLK_RGA>,
 725                                          <&cru HCLK_VIP>,
 726                                          <&cru HCLK_VOP>,
 727                                          <&cru HCLK_VIO_HDCPMMU>,
 728                                          <&cru PCLK_EDP_CTRL>,
 729                                          <&cru PCLK_HDMI_CTRL>,
 730                                          <&cru PCLK_HDCP>,
 731                                          <&cru PCLK_ISP>,
 732                                          <&cru PCLK_VIP>,
 733                                          <&cru PCLK_DPHYRX>,
 734                                          <&cru PCLK_DPHYTX0>,
 735                                          <&cru PCLK_MIPI_CSI>,
 736                                          <&cru PCLK_MIPI_DSI0>,
 737                                          <&cru SCLK_VOP0_PWM>,
 738                                          <&cru SCLK_EDP_24M>,
 739                                          <&cru SCLK_EDP>,
 740                                          <&cru SCLK_HDCP>,
 741                                          <&cru SCLK_ISP>,
 742                                          <&cru SCLK_RGA>,
 743                                          <&cru SCLK_HDMI_CEC>,
 744                                          <&cru SCLK_HDMI_HDCP>;
 745                         };
 746                         /*
 747                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 748                          * (video endecoder & decoder) clocks that on the
 749                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 750                          */
 751                         pd_video {
 752                                 reg = <RK3368_PD_VIDEO>;
 753                                 clocks = <&cru ACLK_VIDEO>,
 754                                          <&cru HCLK_VIDEO>,
 755                                          <&cru SCLK_HEVC_CABAC>,
 756                                          <&cru SCLK_HEVC_CORE>;
 757                         };
 758                         /*
 759                          * Note: ACLK_GPU is the GPU clock,
 760                          * and on the ACLK_GPU_NIU (NOC).
 761                          */
 762                         pd_gpu_1 {
 763                                 reg = <RK3368_PD_GPU_1>;
 764                                 clocks = <&cru ACLK_GPU_CFG>,
 765                                          <&cru ACLK_GPU_MEM>,
 766                                          <&cru SCLK_GPU_CORE>;
 767                         };
 768                 };
 769         };
 770
 771         pmugrf: syscon@ff738000 {
 772                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
 773                 reg = <0x0 0xff738000 0x0 0x1000>;
 774
 775                 reboot-mode {
 776                         compatible = "syscon-reboot-mode";
 777                         offset = <0x200>;
 778                         mode-normal = <BOOT_NORMAL>;
 779                         mode-recovery = <BOOT_RECOVERY>;
 780                         mode-bootloader = <BOOT_FASTBOOT>;
 781                         mode-loader = <BOOT_BL_DOWNLOAD>;
 782
 783                 };
 784         };
 785
 786         cru: clock-controller@ff760000 {
 787                 compatible = "rockchip,rk3368-cru";
 788                 reg = <0x0 0xff760000 0x0 0x1000>;
 789                 rockchip,grf = <&grf>;
 790                 #clock-cells = <1>;
 791                 #reset-cells = <1>;
 792                 assigned-clocks =
 793                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 794                         <&cru PLL_NPLL>,
 795                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
 796                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
 797                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
 798                 assigned-clock-rates =
 799                         <576000000>, <400000000>,
 800                         <1188000000>,
 801                         <300000000>, <300000000>,
 802                         <150000000>, <150000000>,
 803                         <75000000>, <75000000>;
 804         };
 805
 806         grf: syscon@ff770000 {
 807                 compatible = "rockchip,rk3368-grf", "syscon";
 808                 reg = <0x0 0xff770000 0x0 0x1000>;
 809         };
 810
 811         wdt: watchdog@ff800000 {
 812                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 813                 reg = <0x0 0xff800000 0x0 0x100>;
 814                 clocks = <&cru PCLK_WDT>;
 815                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 816                 status = "disabled";
 817         };
 818
 819         timer@ff810000 {
 820                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
 821                 reg = <0x0 0xff810000 0x0 0x20>;
 822                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 823         };
 824
 825         gic: interrupt-controller@ffb71000 {
 826                 compatible = "arm,gic-400";
 827                 interrupt-controller;
 828                 #interrupt-cells = <3>;
 829                 #address-cells = <0>;
 830
 831                 reg = <0x0 0xffb71000 0x0 0x1000>,
 832                       <0x0 0xffb72000 0x0 0x2000>,
 833                       <0x0 0xffb74000 0x0 0x2000>,
 834                       <0x0 0xffb76000 0x0 0x2000>;
 835                 interrupts = <GIC_PPI 9
 836                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 837         };
 838
 839         gpu: rogue-g6110@ffa30000 {
 840                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
 841                 reg = <0x0 0xffa30000 0x0 0x10000>;
 842                 clocks =
 843                         <&cru SCLK_GPU_CORE>,
 844                         <&cru ACLK_GPU_MEM>,
 845                         <&cru ACLK_GPU_CFG>;
 846                 clock-names =
 847                         "sclk_gpu_core",
 848                         "aclk_gpu_mem",
 849                         "aclk_gpu_cfg";
 850                 operating-points = <
 851                         /* KHz uV */
 852                         200000 1100000
 853                         288000 1100000
 854                         400000 1150000
 855                         576000 1200000
 856                 >;
 857                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 858                 interrupt-names = "rogue-g6110-irq";
 859         };
 860
 861         i2s_2ch: i2s-2ch@ff890000 {
 862                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 863                 reg = <0x0 0xff890000 0x0 0x1000>;
 864                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 865                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 866                 dma-names = "tx", "rx";
 867                 clock-names = "i2s_clk", "i2s_hclk";
 868                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 869                 status = "disabled";
 870         };
 871
 872         i2s_8ch: i2s-8ch@ff898000 {
 873                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 874                 reg = <0x0 0xff898000 0x0 0x1000>;
 875                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 876                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 877                 dma-names = "tx", "rx";
 878                 clock-names = "i2s_clk", "i2s_hclk";
 879                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 880                 pinctrl-names = "default";
 881                 pinctrl-0 = <&i2s_8ch_bus>;
 882                 status = "disabled";
 883         };
 884
 885         isp: isp@ff910000 {
 886                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
 887                 reg = <0x0 0xff910000 0x0 0x10000>;
 888                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 889                 /*power-domains = <&power PD_VIO>;*/
 890                 clocks =
 891                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
 892                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
 893                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
 894                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
 895                 clock-names =
 896                         "aclk_isp", "hclk_isp", "clk_isp",
 897                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
 898                         "clk_cif_pll", "hclk_mipiphy1",
 899                         "pclk_dphyrx", "clk_vio0_noc";
 900                 pinctrl-names =
 901                         "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
 902                         "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
 903                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 904                         "isp_flash_as_trigger_out";
 905                 pinctrl-0 = <&cif_clkout>;
 906                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
 907                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
 908                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
 909                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
 910                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
 911                 pinctrl-6 = <&cif_clkout>;
 912                 pinctrl-7 = <&cif_clkout &isp_prelight>;
 913                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
 914                 pinctrl-9 = <&isp_flash_trigger>;
 915                 rockchip,isp,mipiphy = <2>;
 916                 rockchip,isp,cifphy = <1>;
 917                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
 918                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
 919                 rockchip,grf = <&grf>;
 920                 rockchip,cru = <&cru>;
 921                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 922                 rockchip,isp,iommu_enable = <1>;
 923                 status = "disabled";
 924         };
 925
 926         rga: rga@ff920000 {
 927                 compatible = "rockchip,rga2";
 928                 dev_mode = <1>;
 929                 reg = <0x0 0xff920000 0x0 0x1000>;
 930                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 931                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 932                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 933                 status = "disabled";
 934         };
 935
 936         pinctrl: pinctrl {
 937                 compatible = "rockchip,rk3368-pinctrl";
 938                 rockchip,grf = <&grf>;
 939                 rockchip,pmu = <&pmugrf>;
 940                 #address-cells = <0x2>;
 941                 #size-cells = <0x2>;
 942                 ranges;
 943
 944                 gpio0: gpio0@ff750000 {
 945                         compatible = "rockchip,gpio-bank";
 946                         reg = <0x0 0xff750000 0x0 0x100>;
 947                         clocks = <&cru PCLK_GPIO0>;
 948                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
 949
 950                         gpio-controller;
 951                         #gpio-cells = <0x2>;
 952
 953                         interrupt-controller;
 954                         #interrupt-cells = <0x2>;
 955                 };
 956
 957                 gpio1: gpio1@ff780000 {
 958                         compatible = "rockchip,gpio-bank";
 959                         reg = <0x0 0xff780000 0x0 0x100>;
 960                         clocks = <&cru PCLK_GPIO1>;
 961                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
 962
 963                         gpio-controller;
 964                         #gpio-cells = <0x2>;
 965
 966                         interrupt-controller;
 967                         #interrupt-cells = <0x2>;
 968                 };
 969
 970                 gpio2: gpio2@ff790000 {
 971                         compatible = "rockchip,gpio-bank";
 972                         reg = <0x0 0xff790000 0x0 0x100>;
 973                         clocks = <&cru PCLK_GPIO2>;
 974                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
 975
 976                         gpio-controller;
 977                         #gpio-cells = <0x2>;
 978
 979                         interrupt-controller;
 980                         #interrupt-cells = <0x2>;
 981                 };
 982
 983                 gpio3: gpio3@ff7a0000 {
 984                         compatible = "rockchip,gpio-bank";
 985                         reg = <0x0 0xff7a0000 0x0 0x100>;
 986                         clocks = <&cru PCLK_GPIO3>;
 987                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
 988
 989                         gpio-controller;
 990                         #gpio-cells = <0x2>;
 991
 992                         interrupt-controller;
 993                         #interrupt-cells = <0x2>;
 994                 };
 995
 996                 pcfg_pull_up: pcfg-pull-up {
 997                         bias-pull-up;
 998                 };
 999
1000                 pcfg_pull_down: pcfg-pull-down {
1001                         bias-pull-down;
1002                 };
1003
1004                 pcfg_pull_none: pcfg-pull-none {
1005                         bias-disable;
1006                 };
1007
1008                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1009                         bias-disable;
1010                         drive-strength = <12>;
1011                 };
1012
1013                 emmc {
1014                         emmc_clk: emmc-clk {
1015                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1016                         };
1017
1018                         emmc_cmd: emmc-cmd {
1019                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1020                         };
1021
1022                         emmc_pwr: emmc-pwr {
1023                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1024                         };
1025
1026                         emmc_bus1: emmc-bus1 {
1027                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1028                         };
1029
1030                         emmc_bus4: emmc-bus4 {
1031                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1032                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1033                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1034                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1035                         };
1036
1037                         emmc_bus8: emmc-bus8 {
1038                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1039                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1040                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1041                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1042                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1043                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1044                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1045                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1046                         };
1047                 };
1048
1049                 gmac {
1050                         rgmii_pins: rgmii-pins {
1051                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1052                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1053                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1054                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1055                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1056                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1057                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1058                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1059                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1060                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1061                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1062                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1063                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1064                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1065                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1066                         };
1067
1068                         rmii_pins: rmii-pins {
1069                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1070                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1071                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1072                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1073                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1074                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1075                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1076                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1077                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1078                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1079                         };
1080                 };
1081
1082                 hdmi_i2c {
1083                         hdmii2c_xfer: hdmii2c-xfer {
1084                                 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1085                                                 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1086                         };
1087                 };
1088
1089                 hdmi_pin {
1090                         hdmi_cec: hdmi-cec {
1091                                 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1092                         };
1093                 };
1094
1095                 i2c0 {
1096                         i2c0_xfer: i2c0-xfer {
1097                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1098                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1099                         };
1100                 };
1101
1102                 i2c1 {
1103                         i2c1_xfer: i2c1-xfer {
1104                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1105                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1106                         };
1107                 };
1108
1109                 i2c2 {
1110                         i2c2_xfer: i2c2-xfer {
1111                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1112                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1113                         };
1114                 };
1115
1116                 i2c3 {
1117                         i2c3_xfer: i2c3-xfer {
1118                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1119                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1120                         };
1121                 };
1122
1123                 i2c4 {
1124                         i2c4_xfer: i2c4-xfer {
1125                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1126                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1127                         };
1128                 };
1129
1130                 i2c5 {
1131                         i2c5_xfer: i2c5-xfer {
1132                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1133                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1134                         };
1135                         i2c5_gpio: i2c5-gpio {
1136                                 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
1137                                                 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
1138                         };
1139                 };
1140
1141                 i2s {
1142                         i2s_8ch_bus: i2s-8ch-bus {
1143                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1144                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1145                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1146                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1147                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1148                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1149                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1150                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1151                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1152                         };
1153                 };
1154
1155                 sdio0 {
1156                         sdio0_bus1: sdio0-bus1 {
1157                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1158                         };
1159
1160                         sdio0_bus4: sdio0-bus4 {
1161                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1162                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1163                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1164                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1165                         };
1166
1167                         sdio0_cmd: sdio0-cmd {
1168                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1169                         };
1170
1171                         sdio0_clk: sdio0-clk {
1172                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1173                         };
1174
1175                         sdio0_cd: sdio0-cd {
1176                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1177                         };
1178
1179                         sdio0_wp: sdio0-wp {
1180                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1181                         };
1182
1183                         sdio0_pwr: sdio0-pwr {
1184                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1185                         };
1186
1187                         sdio0_bkpwr: sdio0-bkpwr {
1188                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1189                         };
1190
1191                         sdio0_int: sdio0-int {
1192                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1193                         };
1194                 };
1195
1196                 sdmmc {
1197                         sdmmc_clk: sdmmc-clk {
1198                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1199                         };
1200
1201                         sdmmc_cmd: sdmmc-cmd {
1202                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1203                         };
1204
1205                         sdmmc_cd: sdmmc-cd {
1206                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1207                         };
1208
1209                         sdmmc_bus1: sdmmc-bus1 {
1210                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1211                         };
1212
1213                         sdmmc_bus4: sdmmc-bus4 {
1214                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1215                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1216                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1217                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1218                         };
1219                 };
1220
1221                 spi0 {
1222                         spi0_clk: spi0-clk {
1223                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1224                         };
1225                         spi0_cs0: spi0-cs0 {
1226                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1227                         };
1228                         spi0_cs1: spi0-cs1 {
1229                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1230                         };
1231                         spi0_tx: spi0-tx {
1232                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1233                         };
1234                         spi0_rx: spi0-rx {
1235                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1236                         };
1237                 };
1238
1239                 spi1 {
1240                         spi1_clk: spi1-clk {
1241                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1242                         };
1243                         spi1_cs0: spi1-cs0 {
1244                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1245                         };
1246                         spi1_cs1: spi1-cs1 {
1247                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1248                         };
1249                         spi1_rx: spi1-rx {
1250                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1251                         };
1252                         spi1_tx: spi1-tx {
1253                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1254                         };
1255                 };
1256
1257                 spi2 {
1258                         spi2_clk: spi2-clk {
1259                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1260                         };
1261                         spi2_cs0: spi2-cs0 {
1262                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1263                         };
1264                         spi2_rx: spi2-rx {
1265                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1266                         };
1267                         spi2_tx: spi2-tx {
1268                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1269                         };
1270                 };
1271
1272                 tsadc {
1273                         otp_gpio: otp-gpio {
1274                                 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1275                         };
1276
1277                         otp_out: otp-out {
1278                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1279                         };
1280                 };
1281
1282                 uart0 {
1283                         uart0_xfer: uart0-xfer {
1284                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1285                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1286                         };
1287
1288                         uart0_cts: uart0-cts {
1289                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1290                         };
1291
1292                         uart0_rts: uart0-rts {
1293                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1294                         };
1295                 };
1296
1297                 uart1 {
1298                         uart1_xfer: uart1-xfer {
1299                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1300                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1301                         };
1302
1303                         uart1_cts: uart1-cts {
1304                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1305                         };
1306
1307                         uart1_rts: uart1-rts {
1308                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1309                         };
1310                 };
1311
1312                 uart2 {
1313                         uart2_xfer: uart2-xfer {
1314                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1315                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1316                         };
1317                         /* no rts / cts for uart2 */
1318                 };
1319
1320                 uart3 {
1321                         uart3_xfer: uart3-xfer {
1322                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1323                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1324                         };
1325
1326                         uart3_cts: uart3-cts {
1327                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1328                         };
1329
1330                         uart3_rts: uart3-rts {
1331                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1332                         };
1333                 };
1334
1335                 uart4 {
1336                         uart4_xfer: uart4-xfer {
1337                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1338                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1339                         };
1340
1341                         uart4_cts: uart4-cts {
1342                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1343                         };
1344
1345                         uart4_rts: uart4-rts {
1346                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1347                         };
1348                 };
1349
1350                 pwm0 {
1351                         pwm0_pin: pwm0-pin {
1352                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1353                         };
1354
1355                         vop_pwm_pin: vop-pwm {
1356                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1357                         };
1358                 };
1359
1360                 pwm1 {
1361                         pwm1_pin: pwm1-pin {
1362                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1363                         };
1364                 };
1365
1366                 pwm3 {
1367                         pwm3_pin: pwm3-pin {
1368                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1369                         };
1370                 };
1371
1372                 lcdc {
1373                         lcdc_lcdc: lcdc-lcdc {
1374                                 rockchip,pins =
1375                                                 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1376                                                 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1377                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1378                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1379                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1380                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1381                                                 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1382                                                 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1383                                                 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1384                                                 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1385                                                 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1386                                                 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1387                                                 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1388                                                 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1389                                                 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1390                                                 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1391                                                 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1392                                                 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1393                         };
1394
1395                         lcdc_gpio: lcdc-gpio {
1396                                 rockchip,pins =
1397                                                 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1398                                                 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1399                                                 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1400                                                 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1401                                                 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1402                                                 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1403                                                 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1404                                                 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1405                                                 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1406                                                 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1407                                                 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1408                                                 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1409                                                 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1410                                                 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1411                                                 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1412                                                 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1413                                                 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1414                                                 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1415                         };
1416                 };
1417
1418                 isp {
1419                         cif_clkout: cif-clkout {
1420                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1421                         };
1422
1423                         isp_dvp_d2d9: isp-dvp-d2d9 {
1424                                 rockchip,pins =
1425                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1426                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1427                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1428                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1429                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1430                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1431                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1432                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1433                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1434                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1435                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1436                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1437                         };
1438
1439                         isp_dvp_d0d1: isp-dvp-d0d1 {
1440                                 rockchip,pins =
1441                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1442                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1443                         };
1444
1445                         isp_dvp_d10d11:isp_d10d11 {
1446                                 rockchip,pins =
1447                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1448                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1449                         };
1450
1451                         isp_dvp_d0d7: isp-dvp-d0d7 {
1452                                 rockchip,pins =
1453                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1454                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1455                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1456                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1457                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1458                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1459                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1460                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1461                         };
1462
1463                         isp_dvp_d4d11: isp-dvp-d4d11 {
1464                                 rockchip,pins =
1465                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1466                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1467                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1468                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1469                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1470                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1471                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1472                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1473                         };
1474
1475                         isp_shutter: isp-shutter {
1476                                 rockchip,pins =
1477                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1478                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1479                         };
1480
1481                         isp_flash_trigger: isp-flash-trigger {
1482                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1483                         };
1484
1485                         isp_prelight: isp-prelight {
1486                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1487                         };
1488
1489                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1490                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1491                         };
1492                 };
1493         };
1494
1495         fb: fb {
1496                 compatible = "rockchip,rk-fb";
1497                 rockchip,disp-mode = <NO_DUAL>;
1498                 status = "disabled";
1499         };
1500
1501         rk_screen: screen {
1502                 compatible = "rockchip,screen";
1503                 status = "disabled";
1504         };
1505
1506         lcdc: lcdc@ff930000 {
1507                 compatible = "rockchip,rk3368-lcdc";
1508                 rockchip,grf = <&grf>;
1509                 rockchip,pmugrf = <&pmugrf>;
1510                 rockchip,cru = <&cru>;
1511                 rockchip,prop = <PRMRY>;
1512                 rockchip,pwr18 = <0>;
1513                 rockchip,iommu-enabled = <1>;
1514                 reg = <0x0 0xff930000 0x0 0x10000>;
1515                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1516                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1517                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1518                 /*power-domains = <&power PD_VIO>;*/
1519                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1520                 reset-names = "axi", "ahb", "dclk";
1521                 status = "disabled";
1522         };
1523
1524         mipi: mipi@ff960000 {
1525                 compatible = "rockchip,rk3368-dsi";
1526                 rockchip,prop = <0>;
1527                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1528                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1529                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1530                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1531                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1532                 /*power-domains = <&power PD_VIO>;*/
1533                 status = "disabled";
1534         };
1535
1536         lvds: lvds@ff968000 {
1537                 compatible = "rockchip,rk3368-lvds";
1538                 rockchip,grf = <&grf>;
1539                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1540                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1541                 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1542                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1543                 /*power-domains = <&power PD_VIO>;*/
1544                 status = "disabled";
1545         };
1546
1547         edp: edp@ff970000 {
1548                 compatible = "rockchip,rk32-edp";
1549                 reg = <0x0 0xff970000 0x0 0x4000>;
1550                 rockchip,grf = <&grf>;
1551                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1552                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1553                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1554                 /*power-domains = <&power PD_VIO>;*/
1555                 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1556                 reset-names = "edp_24m", "edp_apb";
1557                 status = "disabled";
1558         };
1559
1560         hdmi: hdmi@ff980000 {
1561                 compatible = "rockchip,rk3368-hdmi";
1562                 reg = <0x0 0xff980000 0x0 0x20000>;
1563                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1564                 clocks = <&cru PCLK_HDMI_CTRL>,
1565                          <&cru SCLK_HDMI_HDCP>,
1566                          <&cru SCLK_HDMI_CEC>;
1567                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
1568                 /*power-domains = <&power PD_VIO>;*/
1569                 resets = <&cru SRST_HDMI>;
1570                 reset-names = "hdmi";
1571                 pinctrl-names = "default", "gpio";
1572                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1573                 pinctrl-1 = <&i2c5_gpio>;
1574                 status = "disabled";
1575         };
1576
1577         iep_mmu: iep-mmu {
1578                 dbgname = "iep";
1579                 compatible = "rockchip,iep_mmu";
1580                 reg = <0x0 0xff900800 0x0 0x100>;
1581                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1582                 interrupt-names = "iep_mmu";
1583                 status = "disabled";
1584         };
1585
1586         vip_mmu: vip-mmu {
1587                 dbgname = "vip";
1588                 compatible = "rockchip,vip_mmu";
1589                 reg = <0x0 0xff950800 0x0 0x100>;
1590                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1591                 interrupt-names = "vip_mmu";
1592                 status = "disabled";
1593         };
1594
1595         vopb_mmu: vopb-mmu {
1596                 dbgname = "vop";
1597                 compatible = "rockchip,vopb_mmu";
1598                 reg = <0x0 0xff930300 0x0 0x100>;
1599                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1600                 interrupt-names = "vop_mmu";
1601                 status = "disabled";
1602         };
1603
1604         isp_mmu: isp-mmu {
1605                 dbgname = "isp_mmu";
1606                 compatible = "rockchip,isp_mmu";
1607                 reg = <0x0 0xff914000 0x0 0x100>,
1608                       <0x0 0xff915000 0x0 0x100>;
1609                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1610                 interrupt-names = "isp_mmu";
1611                 status = "disabled";
1612         };
1613
1614         hdcp_mmu: hdcp-mmu {
1615                  dbgname = "hdcp_mmu";
1616                  compatible = "rockchip,hdcp_mmu";
1617                  reg = <0x0 0xff940000 0x0 0x100>;
1618                  interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1619                  interrupt-names = "hdcp_mmu";
1620                 status = "disabled";
1621         };
1622
1623         hevc_mmu: hevc-mmu {
1624                 dbgname = "hevc";
1625                 compatible = "rockchip,hevc_mmu";
1626                 reg = <0x0 0xff9a0440 0x0 0x40>,
1627                       <0x0 0xff9a0480 0x0 0x40>;
1628                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1629                 interrupt-names = "hevc_mmu";
1630                 status = "disabled";
1631         };
1632
1633         vpu_mmu: vpu-mmu {
1634                 dbgname = "vpu";
1635                 compatible = "rockchip,vpu_mmu";
1636                 reg = <0x0 0xff9a0800 0x0 0x100>;
1637                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1638                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1639                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1640                 status = "disabled";
1641         };
1642 };