arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/soc/rockchip-system-status.h>
  51 #include <dt-bindings/suspend/rockchip-rk3368.h>
  52 #include <dt-bindings/thermal/thermal.h>
  53 #include <dt-bindings/display/mipi_dsi.h>
  54 #include <dt-bindings/display/drm_mipi_dsi.h>
  55 #include <dt-bindings/display/media-bus-format.h>
  56
  57 #include "rk3368-dram-default-timing.dtsi"
  58
  59 / {
  60         compatible = "rockchip,rk3368";
  61         interrupt-parent = <&gic>;
  62         #address-cells = <2>;
  63         #size-cells = <2>;
  64
  65         aliases {
  66                 ethernet0 = &gmac;
  67                 i2c0 = &i2c0;
  68                 i2c1 = &i2c1;
  69                 i2c2 = &i2c2;
  70                 i2c3 = &i2c3;
  71                 i2c4 = &i2c4;
  72                 i2c5 = &i2c5;
  73                 serial0 = &uart0;
  74                 serial1 = &uart1;
  75                 serial2 = &uart2;
  76                 serial3 = &uart3;
  77                 serial4 = &uart4;
  78                 spi0 = &spi0;
  79                 spi1 = &spi1;
  80                 spi2 = &spi2;
  81         };
  82
  83         cpus {
  84                 #address-cells = <0x2>;
  85                 #size-cells = <0x0>;
  86
  87                 cpu-map {
  88                         cluster0 {
  89                                 core0 {
  90                                         cpu = <&cpu_l0>;
  91                                 };
  92                                 core1 {
  93                                         cpu = <&cpu_l1>;
  94                                 };
  95                                 core2 {
  96                                         cpu = <&cpu_l2>;
  97                                 };
  98                                 core3 {
  99                                         cpu = <&cpu_l3>;
 100                                 };
 101                         };
 102
 103                         cluster1 {
 104                                 core0 {
 105                                         cpu = <&cpu_b0>;
 106                                 };
 107                                 core1 {
 108                                         cpu = <&cpu_b1>;
 109                                 };
 110                                 core2 {
 111                                         cpu = <&cpu_b2>;
 112                                 };
 113                                 core3 {
 114                                         cpu = <&cpu_b3>;
 115                                 };
 116                         };
 117                 };
 118
 119                 cpu_l0: cpu@0 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         reg = <0x0 0x0>;
 123                         enable-method = "psci";
 124                         clocks = <&cru ARMCLKL>;
 125                         next-level-cache = <&cluster0_l2>;
 126                         operating-points-v2 = <&cluster0_opp>;
 127                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 128                         #cooling-cells = <2>; /* min followed by max */
 129                         dynamic-power-coefficient = <149>;
 130                 };
 131
 132                 cpu_l1: cpu@1 {
 133                         device_type = "cpu";
 134                         compatible = "arm,cortex-a53", "arm,armv8";
 135                         reg = <0x0 0x1>;
 136                         enable-method = "psci";
 137                         clocks = <&cru ARMCLKL>;
 138                         next-level-cache = <&cluster0_l2>;
 139                         operating-points-v2 = <&cluster0_opp>;
 140                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 141                 };
 142
 143                 cpu_l2: cpu@2 {
 144                         device_type = "cpu";
 145                         compatible = "arm,cortex-a53", "arm,armv8";
 146                         reg = <0x0 0x2>;
 147                         enable-method = "psci";
 148                         clocks = <&cru ARMCLKL>;
 149                         next-level-cache = <&cluster0_l2>;
 150                         operating-points-v2 = <&cluster0_opp>;
 151                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 152                 };
 153
 154                 cpu_l3: cpu@3 {
 155                         device_type = "cpu";
 156                         compatible = "arm,cortex-a53", "arm,armv8";
 157                         reg = <0x0 0x3>;
 158                         enable-method = "psci";
 159                         clocks = <&cru ARMCLKL>;
 160                         next-level-cache = <&cluster0_l2>;
 161                         operating-points-v2 = <&cluster0_opp>;
 162                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 163                 };
 164
 165                 cpu_b0: cpu@100 {
 166                         device_type = "cpu";
 167                         compatible = "arm,cortex-a53", "arm,armv8";
 168                         reg = <0x0 0x100>;
 169                         enable-method = "psci";
 170                         clocks = <&cru ARMCLKB>;
 171                         next-level-cache = <&cluster1_l2>;
 172                         operating-points-v2 = <&cluster1_opp>;
 173                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 174                         #cooling-cells = <2>; /* min followed by max */
 175                         dynamic-power-coefficient = <160>;
 176                 };
 177
 178                 cpu_b1: cpu@101 {
 179                         device_type = "cpu";
 180                         compatible = "arm,cortex-a53", "arm,armv8";
 181                         reg = <0x0 0x101>;
 182                         enable-method = "psci";
 183                         clocks = <&cru ARMCLKB>;
 184                         next-level-cache = <&cluster1_l2>;
 185                         operating-points-v2 = <&cluster1_opp>;
 186                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 187                 };
 188
 189                 cpu_b2: cpu@102 {
 190                         device_type = "cpu";
 191                         compatible = "arm,cortex-a53", "arm,armv8";
 192                         reg = <0x0 0x102>;
 193                         enable-method = "psci";
 194                         clocks = <&cru ARMCLKB>;
 195                         next-level-cache = <&cluster1_l2>;
 196                         operating-points-v2 = <&cluster1_opp>;
 197                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 198                 };
 199
 200                 cpu_b3: cpu@103 {
 201                         device_type = "cpu";
 202                         compatible = "arm,cortex-a53", "arm,armv8";
 203                         reg = <0x0 0x103>;
 204                         enable-method = "psci";
 205                         clocks = <&cru ARMCLKB>;
 206                         next-level-cache = <&cluster1_l2>;
 207                         operating-points-v2 = <&cluster1_opp>;
 208                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 209                 };
 210
 211                 cluster0_l2: l2-cache0 {
 212                         compatible = "cache";
 213                 };
 214
 215                 cluster1_l2: l2-cache1 {
 216                         compatible = "cache";
 217                 };
 218         };
 219
 220         cluster0_opp: opp_table0 {
 221                 compatible = "operating-points-v2";
 222                 opp-shared;
 223                 leakage-voltage-sel = <
 224                         1   24   0
 225                         25  254  1
 226                 >;
 227                 nvmem-cells = <&cpu_leakage>;
 228                 nvmem-cell-names = "cpu_leakage";
 229
 230                 opp-216000000 {
 231                         opp-hz = /bits/ 64 <216000000>;
 232                         opp-microvolt = <950000 950000 1350000>;
 233                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 234                         opp-microvolt-L1 = <950000 950000 1350000>;
 235                         clock-latency-ns = <40000>;
 236                         opp-suspend;
 237                 };
 238                 opp-408000000 {
 239                         opp-hz = /bits/ 64 <408000000>;
 240                         opp-microvolt = <950000 950000 1350000>;
 241                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 242                         opp-microvolt-L1 = <950000 950000 1350000>;
 243                         clock-latency-ns = <40000>;
 244                 };
 245                 opp-600000000 {
 246                         opp-hz = /bits/ 64 <600000000>;
 247                         opp-microvolt = <950000 950000 1350000>;
 248                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 249                         opp-microvolt-L1 = <950000 950000 1350000>;
 250                         clock-latency-ns = <40000>;
 251                 };
 252                 opp-816000000 {
 253                         opp-hz = /bits/ 64 <816000000>;
 254                         opp-microvolt = <1025000 1025000 1350000>;
 255                         opp-microvolt-L0 = <1125000 1125000 1350000>;
 256                         opp-microvolt-L1 = <1025000 1025000 1350000>;
 257                         clock-latency-ns = <40000>;
 258                 };
 259                 opp-1008000000 {
 260                         opp-hz = /bits/ 64 <1008000000>;
 261                         opp-microvolt = <1125000 1125000 1350000>;
 262                         opp-microvolt-L0 = <1225000 1225000 1350000>;
 263                         opp-microvolt-L1 = <1125000 1125000 1350000>;
 264                         clock-latency-ns = <40000>;
 265                 };
 266                 opp-1200000000 {
 267                         opp-hz = /bits/ 64 <1200000000>;
 268                         opp-microvolt = <1225000 1225000 1350000>;
 269                         opp-microvolt-L0 = <1325000 1325000 1350000>;
 270                         opp-microvolt-L1 = <1225000 1225000 1350000>;
 271                         clock-latency-ns = <40000>;
 272                 };
 273         };
 274
 275         cluster1_opp: opp_table1 {
 276                 compatible = "operating-points-v2";
 277                 opp-shared;
 278                 leakage-scaling-sel = <
 279                         1   24   36
 280                         25  254  0
 281                 >;
 282                 clocks = <&cru PLL_APLLB>;
 283                 leakage-voltage-sel = <
 284                         1   24   0
 285                         25  254  1
 286                 >;
 287                 nvmem-cells = <&cpu_leakage>;
 288                 nvmem-cell-names = "cpu_leakage";
 289
 290                 opp-216000000 {
 291                         opp-hz = /bits/ 64 <216000000>;
 292                         opp-microvolt = <950000 950000 1350000>;
 293                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 294                         opp-microvolt-L1 = <950000 950000 1350000>;
 295                         clock-latency-ns = <40000>;
 296                         opp-suspend;
 297                 };
 298                 opp-408000000 {
 299                         opp-hz = /bits/ 64 <408000000>;
 300                         opp-microvolt = <950000 950000 1350000>;
 301                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 302                         opp-microvolt-L1 = <950000 950000 1350000>;
 303                         clock-latency-ns = <40000>;
 304                 };
 305                 opp-600000000 {
 306                         opp-hz = /bits/ 64 <600000000>;
 307                         opp-microvolt = <950000 950000 1350000>;
 308                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 309                         opp-microvolt-L1 = <950000 950000 1350000>;
 310                         clock-latency-ns = <40000>;
 311                 };
 312                 opp-816000000 {
 313                         opp-hz = /bits/ 64 <816000000>;
 314                         opp-microvolt = <975000 975000 1350000>;
 315                         opp-microvolt-L0 = <1075000 1075000 1350000>;
 316                         opp-microvolt-L1 = <975000 975000 1350000>;
 317                         clock-latency-ns = <40000>;
 318                 };
 319                 opp-1008000000 {
 320                         opp-hz = /bits/ 64 <1008000000>;
 321                         opp-microvolt = <1050000 1050000 1350000>;
 322                         opp-microvolt-L0 = <1150000 1150000 1350000>;
 323                         opp-microvolt-L1 = <1050000 1050000 1350000>;
 324                         clock-latency-ns = <40000>;
 325                 };
 326                 opp-1200000000 {
 327                         opp-hz = /bits/ 64 <1200000000>;
 328                         opp-microvolt = <1150000 1150000 1350000>;
 329                         opp-microvolt-L0 = <1250000 1250000 1350000>;
 330                         opp-microvolt-L1 = <1150000 1150000 1350000>;
 331                         clock-latency-ns = <40000>;
 332                 };
 333                 opp-1296000000 {
 334                         opp-hz = /bits/ 64 <1296000000>;
 335                         opp-microvolt = <1225000 1225000 1350000>;
 336                         opp-microvolt-L0 = <1350000 1350000 1350000>;
 337                         opp-microvolt-L1 = <1225000 1225000 1350000>;
 338                         clock-latency-ns = <40000>;
 339                 };
 340                 opp-1416000000 {
 341                         opp-hz = /bits/ 64 <1416000000>;
 342                         opp-microvolt = <1300000 1300000 1350000>;
 343                         opp-microvolt-L0 = <1350000 1350000 1350000>;
 344                         opp-microvolt-L1 = <1300000 1300000 1350000>;
 345                         clock-latency-ns = <40000>;
 346                 };
 347                 opp-1512000000 {
 348                         opp-hz = /bits/ 64 <1512000000>;
 349                         opp-microvolt = <1350000 1350000 1350000>;
 350                         opp-microvolt-L0 = <1350000 1350000 1350000>;
 351                         opp-microvolt-L1 = <1350000 1350000 1350000>;
 352                         clock-latency-ns = <40000>;
 353                 };
 354         };
 355
 356         energy-costs {
 357                 RK3368_CPU_COST_0: rk3368-core-cost0 {
 358                         busy-cost-data = <
 359                                 146    44       /*  216M */
 360                                 276    72       /*  408M */
 361                                 406    99       /*  600M */
 362                                 552    147      /*  816M */
 363                                 682    200      /* 1008M */
 364                                 812    255      /* 1200M */
 365                         >;
 366                         idle-cost-data = <
 367                                   6
 368                                   6
 369                                   0
 370                         >;
 371                 };
 372
 373                 RK3368_CPU_COST_1: rk3368-core-cost1 {
 374                         busy-cost-data = <
 375                                 146    53       /*  216M */
 376                                 276    86       /*  408M */
 377                                 406    118      /*  600M */
 378                                 552    166      /*  816M */
 379                                 682    226      /* 1008M */
 380                                 812    309      /* 1200M */
 381                                 878    371      /* 1200M */
 382                                 959    446      /* 1416M */
 383                                 1024   513      /* 1512M */
 384                         >;
 385                         idle-cost-data = <
 386                                    6
 387                                    6
 388                                    0
 389                         >;
 390                 };
 391
 392                 RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 {
 393                         busy-cost-data = <
 394                                 146    9        /*  216M */
 395                                 276    14       /*  408M */
 396                                 406    20       /*  600M */
 397                                 552    29       /*  816M */
 398                                 682    40       /* 1008M */
 399                                 812    51       /* 1200M */
 400                         >;
 401                         idle-cost-data = <
 402                                 56
 403                                 56
 404                                 56
 405                         >;
 406                 };
 407
 408                 RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 {
 409                         busy-cost-data = <
 410                                 146    11       /*  216M */
 411                                 276    17       /*  408M */
 412                                 406    24       /*  600M */
 413                                 552    33       /*  816M */
 414                                 682    45       /* 1008M */
 415                                 812    62       /* 1200M */
 416                                 878    74       /* 1200M */
 417                                 959    89       /* 1416M */
 418                                 1024   103      /* 1512M */
 419                         >;
 420                         idle-cost-data = <
 421                                 56
 422                                 56
 423                                 56
 424                         >;
 425                 };
 426         };
 427
 428         arm-pmu {
 429                 compatible = "arm,armv8-pmuv3";
 430                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 431                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 432                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 433                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 434                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 435                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 436                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 437                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 438                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 439                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 440                                      <&cpu_b2>, <&cpu_b3>;
 441         };
 442
 443         amba {
 444                 compatible = "arm,amba-bus";
 445                 #address-cells = <2>;
 446                 #size-cells = <2>;
 447                 ranges;
 448
 449                 dmac_peri: dma-controller@ff250000 {
 450                         compatible = "arm,pl330", "arm,primecell";
 451                         reg = <0x0 0xff250000 0x0 0x4000>;
 452                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 453                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 454                         #dma-cells = <1>;
 455                         clocks = <&cru ACLK_DMAC_PERI>;
 456                         clock-names = "apb_pclk";
 457                         arm,pl330-broken-no-flushp;
 458                         peripherals-req-type-burst;
 459                 };
 460
 461                 dmac_bus: dma-controller@ff600000 {
 462                         compatible = "arm,pl330", "arm,primecell";
 463                         reg = <0x0 0xff600000 0x0 0x4000>;
 464                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 465                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 466                         #dma-cells = <1>;
 467                         clocks = <&cru ACLK_DMAC_BUS>;
 468                         clock-names = "apb_pclk";
 469                         arm,pl330-broken-no-flushp;
 470                         peripherals-req-type-burst;
 471                 };
 472         };
 473
 474         psci {
 475                 compatible = "arm,psci-0.2";
 476                 method = "smc";
 477         };
 478
 479         timer {
 480                 compatible = "arm,armv8-timer";
 481                 interrupts = <GIC_PPI 13
 482                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 483                              <GIC_PPI 14
 484                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 485                              <GIC_PPI 11
 486                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 487                              <GIC_PPI 10
 488                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 489         };
 490
 491         xin24m: oscillator {
 492                 compatible = "fixed-clock";
 493                 clock-frequency = <24000000>;
 494                 clock-output-names = "xin24m";
 495                 #clock-cells = <0>;
 496         };
 497
 498         sdmmc: dwmmc@ff0c0000 {
 499                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 500                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 501                 clock-freq-min-max = <400000 150000000>;
 502                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 503                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 504                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 505                 fifo-depth = <0x100>;
 506                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 507                 status = "disabled";
 508         };
 509
 510         sdio0: dwmmc@ff0d0000 {
 511                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 512                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 513                 clock-freq-min-max = <400000 150000000>;
 514                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 515                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 516                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 517                 fifo-depth = <0x100>;
 518                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 519                 status = "disabled";
 520         };
 521
 522         emmc: dwmmc@ff0f0000 {
 523                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 524                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 525                 clock-freq-min-max = <400000 150000000>;
 526                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 527                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 528                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 529                 fifo-depth = <0x100>;
 530                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 531                 status = "disabled";
 532         };
 533
 534         saradc: saradc@ff100000 {
 535                 compatible = "rockchip,saradc";
 536                 reg = <0x0 0xff100000 0x0 0x100>;
 537                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 538                 #io-channel-cells = <1>;
 539                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 540                 clock-names = "saradc", "apb_pclk";
 541                 resets = <&cru SRST_SARADC>;
 542                 reset-names = "saradc-apb";
 543                 status = "disabled";
 544         };
 545
 546         spi0: spi@ff110000 {
 547                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 548                 reg = <0x0 0xff110000 0x0 0x1000>;
 549                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 550                 clock-names = "spiclk", "apb_pclk";
 551                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 552                 pinctrl-names = "default";
 553                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 554                 #address-cells = <1>;
 555                 #size-cells = <0>;
 556                 status = "disabled";
 557         };
 558
 559         spi1: spi@ff120000 {
 560                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 561                 reg = <0x0 0xff120000 0x0 0x1000>;
 562                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 563                 clock-names = "spiclk", "apb_pclk";
 564                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 565                 pinctrl-names = "default";
 566                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 567                 #address-cells = <1>;
 568                 #size-cells = <0>;
 569                 status = "disabled";
 570         };
 571
 572         spi2: spi@ff130000 {
 573                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 574                 reg = <0x0 0xff130000 0x0 0x1000>;
 575                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 576                 clock-names = "spiclk", "apb_pclk";
 577                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 578                 pinctrl-names = "default";
 579                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 580                 #address-cells = <1>;
 581                 #size-cells = <0>;
 582                 status = "disabled";
 583         };
 584
 585         i2c0: i2c@ff650000 {
 586                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 587                 reg = <0x0 0xff650000 0x0 0x1000>;
 588                 clocks = <&cru PCLK_I2C0>;
 589                 clock-names = "i2c";
 590                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 591                 pinctrl-names = "default";
 592                 pinctrl-0 = <&i2c0_xfer>;
 593                 #address-cells = <1>;
 594                 #size-cells = <0>;
 595                 status = "disabled";
 596         };
 597
 598         i2c2: i2c@ff140000 {
 599                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 600                 reg = <0x0 0xff140000 0x0 0x1000>;
 601                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 602                 #address-cells = <1>;
 603                 #size-cells = <0>;
 604                 clock-names = "i2c";
 605                 clocks = <&cru PCLK_I2C2>;
 606                 pinctrl-names = "default";
 607                 pinctrl-0 = <&i2c2_xfer>;
 608                 status = "disabled";
 609         };
 610
 611         i2c3: i2c@ff150000 {
 612                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 613                 reg = <0x0 0xff150000 0x0 0x1000>;
 614                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 615                 #address-cells = <1>;
 616                 #size-cells = <0>;
 617                 clock-names = "i2c";
 618                 clocks = <&cru PCLK_I2C3>;
 619                 pinctrl-names = "default";
 620                 pinctrl-0 = <&i2c3_xfer>;
 621                 status = "disabled";
 622         };
 623
 624         i2c4: i2c@ff160000 {
 625                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 626                 reg = <0x0 0xff160000 0x0 0x1000>;
 627                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 628                 #address-cells = <1>;
 629                 #size-cells = <0>;
 630                 clock-names = "i2c";
 631                 clocks = <&cru PCLK_I2C4>;
 632                 pinctrl-names = "default";
 633                 pinctrl-0 = <&i2c4_xfer>;
 634                 status = "disabled";
 635         };
 636
 637         i2c5: i2c@ff170000 {
 638                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 639                 reg = <0x0 0xff170000 0x0 0x1000>;
 640                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 641                 #address-cells = <1>;
 642                 #size-cells = <0>;
 643                 clock-names = "i2c";
 644                 clocks = <&cru PCLK_I2C5>;
 645                 pinctrl-names = "default";
 646                 pinctrl-0 = <&i2c5_xfer>;
 647                 status = "disabled";
 648         };
 649
 650         uart0: serial@ff180000 {
 651                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 652                 reg = <0x0 0xff180000 0x0 0x100>;
 653                 clock-frequency = <24000000>;
 654                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 655                 clock-names = "baudclk", "apb_pclk";
 656                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 657                 reg-shift = <2>;
 658                 reg-io-width = <4>;
 659                 status = "disabled";
 660         };
 661
 662         uart1: serial@ff190000 {
 663                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 664                 reg = <0x0 0xff190000 0x0 0x100>;
 665                 clock-frequency = <24000000>;
 666                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 667                 clock-names = "baudclk", "apb_pclk";
 668                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 669                 reg-shift = <2>;
 670                 reg-io-width = <4>;
 671                 status = "disabled";
 672         };
 673
 674         uart3: serial@ff1b0000 {
 675                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 676                 reg = <0x0 0xff1b0000 0x0 0x100>;
 677                 clock-frequency = <24000000>;
 678                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 679                 clock-names = "baudclk", "apb_pclk";
 680                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 681                 reg-shift = <2>;
 682                 reg-io-width = <4>;
 683                 status = "disabled";
 684         };
 685
 686         uart4: serial@ff1c0000 {
 687                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 688                 reg = <0x0 0xff1c0000 0x0 0x100>;
 689                 clock-frequency = <24000000>;
 690                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 691                 clock-names = "baudclk", "apb_pclk";
 692                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 693                 reg-shift = <2>;
 694                 reg-io-width = <4>;
 695                 status = "disabled";
 696         };
 697
 698         thermal_zones: thermal-zones {
 699                 soc_thermal: soc-thermal {
 700                         polling-delay-passive = <200>; /* milliseconds */
 701                         polling-delay = <200>; /* milliseconds */
 702                         sustainable-power = <600>; /* milliwatts */
 703
 704                         thermal-sensors = <&tsadc 0>;
 705                         trips {
 706                                 threshold: trip-point@0 {
 707                                         temperature = <70000>; /* millicelsius */
 708                                         hysteresis = <2000>; /* millicelsius */
 709                                         type = "passive";
 710                                 };
 711                                 target: trip-point@1 {
 712                                         temperature = <80000>; /* millicelsius */
 713                                         hysteresis = <2000>; /* millicelsius */
 714                                         type = "passive";
 715                                 };
 716                                 soc_crit: soc-crit {
 717                                         temperature = <95000>; /* millicelsius */
 718                                         hysteresis = <2000>; /* millicelsius */
 719                                         type = "critical";
 720                                 };
 721                         };
 722
 723                         cooling-maps {
 724                                 map0 {
 725                                         trip = <&target>;
 726                                         cooling-device =
 727                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 728                                         contribution = <1024>;
 729                                 };
 730                                 map1 {
 731                                         trip = <&target>;
 732                                         cooling-device =
 733                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 734                                         contribution = <1024>;
 735                                 };
 736                                 map2 {
 737                                         trip = <&target>;
 738                                         cooling-device =
 739                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 740                                         contribution = <1024>;
 741                                 };
 742                         };
 743                 };
 744
 745                 gpu_thermal: gpu-thermal {
 746                         polling-delay-passive = <200>; /* milliseconds */
 747                         polling-delay = <200>; /* milliseconds */
 748                         thermal-sensors = <&tsadc 1>;
 749                 };
 750         };
 751
 752         tsadc: tsadc@ff280000 {
 753                 compatible = "rockchip,rk3368-tsadc-legacy";
 754                 reg = <0x0 0xff280000 0x0 0x100>;
 755                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 756                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 757                 clock-names = "tsadc", "apb_pclk";
 758                 clock-frequency = <32768>;
 759                 resets = <&cru SRST_TSADC>;
 760                 reset-names = "tsadc-apb";
 761                 nvmem-cells = <&temp_adjust>;
 762                 nvmem-cell-names = "temp_adjust";
 763                 #thermal-sensor-cells = <1>;
 764                 hw-shut-temp = <95000>;
 765                 latency-bound = <50000>;
 766                 status = "disabled";
 767         };
 768
 769         gmac: ethernet@ff290000 {
 770                 compatible = "rockchip,rk3368-gmac";
 771                 reg = <0x0 0xff290000 0x0 0x10000>;
 772                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 773                 interrupt-names = "macirq";
 774                 rockchip,grf = <&grf>;
 775                 clocks = <&cru SCLK_MAC>,
 776                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 777                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 778                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 779                 clock-names = "stmmaceth",
 780                         "mac_clk_rx", "mac_clk_tx",
 781                         "clk_mac_ref", "clk_mac_refout",
 782                         "aclk_mac", "pclk_mac";
 783                 status = "disabled";
 784         };
 785
 786         nandc0: nandc@ff400000 {
 787                 compatible = "rockchip,rk-nandc";
 788                 reg = <0x0 0xff400000 0x0 0x4000>;
 789                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 790                 nandc_id = <0>;
 791                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 792                 clock-names = "clk_nandc", "hclk_nandc";
 793                 status = "disabled";
 794         };
 795
 796         usb_host0_ehci: usb@ff500000 {
 797                 compatible = "generic-ehci";
 798                 reg = <0x0 0xff500000 0x0 0x20000>;
 799                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 800                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 801                 clock-names = "usbhost", "utmi";
 802                 phys = <&u2phy_host>;
 803                 phy-names = "usb";
 804                 status = "disabled";
 805         };
 806
 807         usb_host0_ohci: usb@ff520000 {
 808                 compatible = "generic-ohci";
 809                 reg = <0x0 0xff520000 0x0 0x20000>;
 810                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 811                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 812                 clock-names = "usbhost", "utmi";
 813                 phys = <&u2phy_host>;
 814                 phy-names = "usb";
 815                 status = "disabled";
 816         };
 817
 818         usb_otg: usb@ff580000 {
 819                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 820                                 "snps,dwc2";
 821                 reg = <0x0 0xff580000 0x0 0x40000>;
 822                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 823                 clocks = <&cru HCLK_OTG0>;
 824                 clock-names = "otg";
 825                 dr_mode = "otg";
 826                 g-np-tx-fifo-size = <16>;
 827                 g-rx-fifo-size = <275>;
 828                 g-tx-fifo-size = <256 128 128 64 64 32>;
 829                 g-use-dma;
 830                 status = "disabled";
 831         };
 832
 833         ddrpctl: syscon@ff610000 {
 834                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 835                 reg = <0x0 0xff610000 0x0 0x400>;
 836         };
 837
 838         i2c1: i2c@ff660000 {
 839                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 840                 reg = <0x0 0xff660000 0x0 0x1000>;
 841                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 842                 #address-cells = <1>;
 843                 #size-cells = <0>;
 844                 clock-names = "i2c";
 845                 clocks = <&cru PCLK_I2C1>;
 846                 pinctrl-names = "default";
 847                 pinctrl-0 = <&i2c1_xfer>;
 848                 status = "disabled";
 849         };
 850
 851         pwm0: pwm@ff680000 {
 852                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 853                 reg = <0x0 0xff680000 0x0 0x10>;
 854                 #pwm-cells = <3>;
 855                 pinctrl-names = "default";
 856                 pinctrl-0 = <&pwm0_pin>;
 857                 clocks = <&cru PCLK_PWM1>;
 858                 clock-names = "pwm";
 859                 status = "disabled";
 860         };
 861
 862         pwm1: pwm@ff680010 {
 863                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 864                 reg = <0x0 0xff680010 0x0 0x10>;
 865                 #pwm-cells = <3>;
 866                 pinctrl-names = "default";
 867                 pinctrl-0 = <&pwm1_pin>;
 868                 clocks = <&cru PCLK_PWM1>;
 869                 clock-names = "pwm";
 870                 status = "disabled";
 871         };
 872
 873         pwm2: pwm@ff680020 {
 874                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 875                 reg = <0x0 0xff680020 0x0 0x10>;
 876                 #pwm-cells = <3>;
 877                 clocks = <&cru PCLK_PWM1>;
 878                 clock-names = "pwm";
 879                 status = "disabled";
 880         };
 881
 882         pwm3: pwm@ff680030 {
 883                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 884                 reg = <0x0 0xff680030 0x0 0x10>;
 885                 #pwm-cells = <3>;
 886                 pinctrl-names = "default";
 887                 pinctrl-0 = <&pwm3_pin>;
 888                 clocks = <&cru PCLK_PWM1>;
 889                 clock-names = "pwm";
 890                 status = "disabled";
 891         };
 892
 893         uart2: serial@ff690000 {
 894                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 895                 reg = <0x0 0xff690000 0x0 0x100>;
 896                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 897                 clock-names = "baudclk", "apb_pclk";
 898                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 899                 pinctrl-names = "default";
 900                 pinctrl-0 = <&uart2_xfer>;
 901                 reg-shift = <2>;
 902                 reg-io-width = <4>;
 903                 status = "disabled";
 904         };
 905
 906         mbox: mbox@ff6b0000 {
 907                 compatible = "rockchip,rk3368-mailbox";
 908                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 909                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 910                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 911                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 912                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 913                 clocks = <&cru PCLK_MAILBOX>;
 914                 clock-names = "pclk_mailbox";
 915                 #mbox-cells = <1>;
 916                 status = "disabled";
 917         };
 918
 919         mailbox: mailbox@ff6b0000 {
 920                 compatible = "rockchip,rk3368-mbox-legacy";
 921                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 922                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 923                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 924                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 925                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 926                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 927                 clocks = <&cru PCLK_MAILBOX>;
 928                 clock-names = "pclk_mailbox";
 929                 #mbox-cells = <1>;
 930                 status = "disabled";
 931         };
 932
 933         mailbox_scpi: mailbox-scpi {
 934                 compatible = "rockchip,rk3368-scpi-legacy";
 935                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 936                 chan-nums = <3>;
 937                 status = "disabled";
 938         };
 939
 940         qos_iep: qos@ffad0000 {
 941                 compatible = "syscon";
 942                 reg = <0x0 0xffad0000 0x0 0x20>;
 943         };
 944
 945         qos_isp_r0: qos@ffad0080 {
 946                 compatible = "syscon";
 947                 reg = <0x0 0xffad0080 0x0 0x20>;
 948         };
 949
 950         qos_isp_r1: qos@ffad0100 {
 951                 compatible = "syscon";
 952                 reg = <0x0 0xffad0100 0x0 0x20>;
 953         };
 954
 955         qos_isp_w0: qos@ffad0180 {
 956                 compatible = "syscon";
 957                 reg = <0x0 0xffad0180 0x0 0x20>;
 958         };
 959
 960         qos_isp_w1: qos@ffad0200 {
 961                 compatible = "syscon";
 962                 reg = <0x0 0xffad0200 0x0 0x20>;
 963         };
 964
 965         qos_vip: qos@ffad0280 {
 966                 compatible = "syscon";
 967                 reg = <0x0 0xffad0280 0x0 0x20>;
 968         };
 969
 970         qos_vop: qos@ffad0300 {
 971                 compatible = "syscon";
 972                 reg = <0x0 0xffad0300 0x0 0x20>;
 973         };
 974
 975         qos_rga_r: qos@ffad0380 {
 976                 compatible = "syscon";
 977                 reg = <0x0 0xffad0380 0x0 0x20>;
 978         };
 979
 980         qos_rga_w: qos@ffad0400 {
 981                 compatible = "syscon";
 982                 reg = <0x0 0xffad0400 0x0 0x20>;
 983         };
 984
 985         qos_hevc_r: qos@ffae0000 {
 986                 compatible = "syscon";
 987                 reg = <0x0 0xffae0000 0x0 0x20>;
 988         };
 989
 990         qos_vpu_r: qos@ffae0100 {
 991                 compatible = "syscon";
 992                 reg = <0x0 0xffae0100 0x0 0x20>;
 993         };
 994
 995         qos_vpu_w: qos@ffae0180 {
 996                 compatible = "syscon";
 997                 reg = <0x0 0xffae0180 0x0 0x20>;
 998         };
 999
1000         qos_gpu: qos@ffaf0000 {
1001                 compatible = "syscon";
1002                 reg = <0x0 0xffaf0000 0x0 0x20>;
1003         };
1004
1005         pmu: power-management@ff730000 {
1006                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
1007                 reg = <0x0 0xff730000 0x0 0x1000>;
1008
1009                 power: power-controller {
1010                         compatible = "rockchip,rk3368-power-controller";
1011                         #power-domain-cells = <1>;
1012                         #address-cells = <1>;
1013                         #size-cells = <0>;
1014
1015                         /*
1016                          * Note: Although SCLK_* are the working clocks
1017                          * of device without including on the NOC, needed for
1018                          * synchronous reset.
1019                          *
1020                          * The clocks on the which NOC:
1021                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
1022                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
1023                          * ACLK_RGA is on ACLK_RGA_NIU.
1024                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
1025                          *
1026                          * Which clock are device clocks:
1027                          *      clocks          devices
1028                          *      *_IEP           IEP:Image Enhancement Processor
1029                          *      *_ISP           ISP:Image Signal Processing
1030                          *      *_VIP           VIP:Video Input Processor
1031                          *      *_VOP*          VOP:Visual Output Processor
1032                          *      *_RGA           RGA
1033                          *      *_EDP*          EDP
1034                          *      *_DPHY*         LVDS
1035                          *      *_HDMI          HDMI
1036                          *      *_MIPI_*        MIPI
1037                          */
1038                         pd_vio {
1039                                 reg = <RK3368_PD_VIO>;
1040                                 clocks = <&cru ACLK_IEP>,
1041                                          <&cru ACLK_ISP>,
1042                                          <&cru ACLK_VIP>,
1043                                          <&cru ACLK_RGA>,
1044                                          <&cru ACLK_VOP>,
1045                                          <&cru ACLK_VOP_IEP>,
1046                                          <&cru DCLK_VOP>,
1047                                          <&cru HCLK_IEP>,
1048                                          <&cru HCLK_ISP>,
1049                                          <&cru HCLK_RGA>,
1050                                          <&cru HCLK_VIP>,
1051                                          <&cru HCLK_VOP>,
1052                                          <&cru HCLK_VIO_HDCPMMU>,
1053                                          <&cru PCLK_EDP_CTRL>,
1054                                          <&cru PCLK_HDMI_CTRL>,
1055                                          <&cru PCLK_HDCP>,
1056                                          <&cru PCLK_ISP>,
1057                                          <&cru PCLK_VIP>,
1058                                          <&cru PCLK_DPHYRX>,
1059                                          <&cru PCLK_DPHYTX0>,
1060                                          <&cru PCLK_MIPI_CSI>,
1061                                          <&cru PCLK_MIPI_DSI0>,
1062                                          <&cru SCLK_VOP0_PWM>,
1063                                          <&cru SCLK_EDP_24M>,
1064                                          <&cru SCLK_EDP>,
1065                                          <&cru SCLK_HDCP>,
1066                                          <&cru SCLK_ISP>,
1067                                          <&cru SCLK_RGA>,
1068                                          <&cru SCLK_HDMI_CEC>,
1069                                          <&cru SCLK_HDMI_HDCP>;
1070                                 pm_qos = <&qos_iep>,
1071                                          <&qos_isp_r0>,
1072                                          <&qos_isp_r1>,
1073                                          <&qos_isp_w0>,
1074                                          <&qos_isp_w1>,
1075                                          <&qos_vip>,
1076                                          <&qos_vop>,
1077                                          <&qos_rga_r>,
1078                                          <&qos_rga_w>;
1079                         };
1080                         /*
1081                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
1082                          * (video endecoder & decoder) clocks that on the
1083                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
1084                          */
1085                         pd_video {
1086                                 reg = <RK3368_PD_VIDEO>;
1087                                 clocks = <&cru ACLK_VIDEO>,
1088                                          <&cru HCLK_VIDEO>,
1089                                          <&cru SCLK_HEVC_CABAC>,
1090                                          <&cru SCLK_HEVC_CORE>;
1091                                 pm_qos = <&qos_hevc_r>,
1092                                          <&qos_vpu_r>,
1093                                          <&qos_vpu_w>;
1094                         };
1095                         /*
1096                          * Note: ACLK_GPU is the GPU clock,
1097                          * and on the ACLK_GPU_NIU (NOC).
1098                          */
1099                         pd_gpu_1 {
1100                                 reg = <RK3368_PD_GPU_1>;
1101                                 clocks = <&cru ACLK_GPU_CFG>,
1102                                          <&cru ACLK_GPU_MEM>,
1103                                          <&cru SCLK_GPU_CORE>;
1104                                 pm_qos = <&qos_gpu>;
1105                         };
1106                 };
1107         };
1108
1109         pmugrf: syscon@ff738000 {
1110                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1111                 reg = <0x0 0xff738000 0x0 0x1000>;
1112
1113                 pmu_io_domains: io-domains {
1114                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1115                         status = "disabled";
1116                 };
1117
1118                 reboot-mode {
1119                         compatible = "syscon-reboot-mode";
1120                         offset = <0x200>;
1121                         mode-normal = <BOOT_NORMAL>;
1122                         mode-recovery = <BOOT_RECOVERY>;
1123                         mode-bootloader = <BOOT_FASTBOOT>;
1124                         mode-loader = <BOOT_BL_DOWNLOAD>;
1125                 };
1126         };
1127
1128         cru: clock-controller@ff760000 {
1129                 compatible = "rockchip,rk3368-cru";
1130                 reg = <0x0 0xff760000 0x0 0x1000>;
1131                 rockchip,grf = <&grf>;
1132                 #clock-cells = <1>;
1133                 #reset-cells = <1>;
1134                 assigned-clocks =
1135                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1136                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1137                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1138                         <&cru PCLK_BUS>, <&cru PCLK_PERI>,
1139                         <&cru ACLK_CCI_PRE>;
1140                 assigned-clock-rates =
1141                         <576000000>, <400000000>,
1142                         <300000000>, <300000000>,
1143                         <150000000>, <150000000>,
1144                         <75000000>, <75000000>,
1145                         <576000000>;
1146         };
1147
1148         grf: syscon@ff770000 {
1149                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1150                 reg = <0x0 0xff770000 0x0 0x1000>;
1151                 #address-cells = <1>;
1152                 #size-cells = <1>;
1153
1154                 edp_phy: edp-phy {
1155                         compatible = "rockchip,rk3368-dp-phy";
1156                         clocks = <&cru SCLK_EDP_24M>;
1157                         clock-names = "24m";
1158                         resets = <&cru SRST_EDP_24M>;
1159                         reset-names = "edp_24m";
1160                         #phy-cells = <0>;
1161                         status = "disabled";
1162                 };
1163
1164                 io_domains: io-domains {
1165                         compatible = "rockchip,rk3368-io-voltage-domain";
1166                         status = "disabled";
1167                 };
1168
1169                 u2phy: usb2-phy@700 {
1170                         compatible = "rockchip,rk3368-usb2phy";
1171                         reg = <0x700 0x2c>;
1172                         clocks = <&cru SCLK_OTGPHY0>;
1173                         clock-names = "phyclk";
1174                         #clock-cells = <0>;
1175                         clock-output-names = "usbotg_out";
1176                         assigned-clocks = <&cru SCLK_USBPHY480M>;
1177                         assigned-clock-parents = <&u2phy>;
1178                         status = "disabled";
1179
1180                         u2phy_host: host-port {
1181                                 #phy-cells = <0>;
1182                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1183                                 interrupt-names = "linestate";
1184                                 status = "disabled";
1185                         };
1186                 };
1187
1188                 dfi: dfi {
1189                         compatible = "rockchip,rk3368-dfi";
1190                         status = "disabled";
1191                 };
1192         };
1193
1194         dmc: dmc {
1195                 compatible = "rockchip,rk3368-dmc";
1196                 devfreq-events = <&dfi>;
1197                 clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_DDRPHY>,
1198                          <&cru PCLK_DDRUPCTL>;
1199                 clock-names = "dmc_clk", "pclk_phy", "pclk_upctl";
1200                 ddr_timing = <&ddr_timing>;
1201                 upthreshold = <50>;
1202                 downdifferential = <20>;
1203                 operating-points-v2 = <&dmc_opp_table>;
1204                 vop-dclk-mode = <0>;
1205                 system-status-freq = <
1206                         /*system status         freq(KHz)*/
1207                         SYS_STATUS_NORMAL       600000
1208                         SYS_STATUS_REBOOT       600000
1209                         SYS_STATUS_SUSPEND      192000
1210                         SYS_STATUS_VIDEO_1080P  300000
1211                         SYS_STATUS_VIDEO_4K     600000
1212                         SYS_STATUS_PERFORMANCE  600000
1213                         SYS_STATUS_BOOST        396000
1214                         SYS_STATUS_DUALVIEW     600000
1215                         SYS_STATUS_ISP          528000
1216                 >;
1217                 auto-min-freq = <396000>;
1218                 auto-freq-en = <0>;
1219                 status = "disabled";
1220         };
1221
1222         dmc_opp_table: opp_table2 {
1223                 compatible = "operating-points-v2";
1224
1225                 opp-192000000 {
1226                         opp-hz = /bits/ 64 <192000000>;
1227                         opp-microvolt = <1100000>;
1228                 };
1229                 opp-300000000 {
1230                         opp-hz = /bits/ 64 <300000000>;
1231                         opp-microvolt = <1100000>;
1232                 };
1233                 opp-396000000 {
1234                         opp-hz = /bits/ 64 <396000000>;
1235                         opp-microvolt = <1100000>;
1236                 };
1237                 opp-528000000 {
1238                         opp-hz = /bits/ 64 <528000000>;
1239                         opp-microvolt = <1100000>;
1240                 };
1241                 opp-600000000 {
1242                         opp-hz = /bits/ 64 <600000000>;
1243                         opp-microvolt = <1100000>;
1244                 };
1245         };
1246
1247         wdt: watchdog@ff800000 {
1248                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1249                 reg = <0x0 0xff800000 0x0 0x100>;
1250                 clocks = <&cru PCLK_WDT>;
1251                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1252                 status = "disabled";
1253         };
1254
1255         timer@ff810000 {
1256                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1257                 reg = <0x0 0xff810000 0x0 0x20>;
1258                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1259         };
1260
1261         i2s_2ch: i2s-2ch@ff890000 {
1262                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1263                 reg = <0x0 0xff890000 0x0 0x1000>;
1264                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1265                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1266                 dma-names = "tx", "rx";
1267                 clock-names = "i2s_clk", "i2s_hclk";
1268                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1269                 status = "disabled";
1270         };
1271
1272         i2s_8ch: i2s-8ch@ff898000 {
1273                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1274                 reg = <0x0 0xff898000 0x0 0x1000>;
1275                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1276                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1277                 dma-names = "tx", "rx";
1278                 clock-names = "i2s_clk", "i2s_hclk";
1279                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1280                 pinctrl-names = "default";
1281                 pinctrl-0 = <&i2s_8ch_bus>;
1282                 status = "disabled";
1283         };
1284
1285         iep: iep@ff900000 {
1286                 compatible = "rockchip,iep";
1287                 iommu_enabled = <1>;
1288                 iommus = <&iep_mmu>;
1289                 reg = <0x0 0xff900000 0x0 0x800>;
1290                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1291                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1292                 clock-names = "aclk_iep", "hclk_iep";
1293                 power-domains = <&power RK3368_PD_VIO>;
1294                 allocator = <1>;
1295                 version = <2>;
1296                 status = "disabled";
1297         };
1298
1299         iep_mmu: iommu@ff900800 {
1300                 compatible = "rockchip,iommu";
1301                 reg = <0x0 0xff900800 0x0 0x100>;
1302                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1303                 interrupt-names = "iep_mmu";
1304                 power-domains = <&power RK3368_PD_VIO>;
1305                 #iommu-cells = <0>;
1306                 status = "disabled";
1307         };
1308
1309         isp: isp@ff910000 {
1310                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
1311                 reg = <0x0 0xff910000 0x0 0x4000>;
1312                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1313                 power-domains = <&power RK3368_PD_VIO>;
1314                 clocks =
1315                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1316                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
1317                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
1318                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
1319                 clock-names =
1320                         "aclk_isp", "hclk_isp", "clk_isp",
1321                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1322                         "clk_cif_pll", "hclk_mipiphy1",
1323                         "pclk_dphyrx", "clk_vio0_noc";
1324
1325                 pinctrl-names =
1326                         "default", "isp_dvp8bit2", "isp_dvp10bit",
1327                         "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
1328                         "isp_mipi_fl", "isp_mipi_fl_prefl",
1329                         "isp_flash_as_gpio", "isp_flash_as_trigger_out";
1330                 pinctrl-0 = <&cif_clkout>;
1331                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1332                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1333                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1334                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1335                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1336                 pinctrl-6 = <&cif_clkout>;
1337                 pinctrl-7 = <&cif_clkout &isp_prelight>;
1338                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1339                 pinctrl-9 = <&isp_flash_trigger>;
1340                 rockchip,isp,mipiphy = <2>;
1341                 rockchip,isp,cifphy = <1>;
1342                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1343                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1344                 rockchip,grf = <&grf>;
1345                 rockchip,cru = <&cru>;
1346                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
1347                 rockchip,isp,iommu-enable = <1>;
1348                 iommus = <&isp_mmu>;
1349                 status = "disabled";
1350         };
1351
1352         isp_mmu: iommu@ff914000 {
1353                 compatible = "rockchip,iommu";
1354                 reg = <0x0 0xff914000 0x0 0x100>,
1355                       <0x0 0xff915000 0x0 0x100>;
1356                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1357                 interrupt-names = "isp_mmu";
1358                 clocks = <&cru ACLK_RGA>, <&cru HCLK_ISP>;
1359                 clock-names = "aclk", "hclk";
1360                 rk_iommu,disable_reset_quirk;
1361                 #iommu-cells = <0>;
1362                 power-domains = <&power RK3368_PD_VIO>;
1363                 status = "disabled";
1364         };
1365
1366         vop: vop@ff930000 {
1367                 compatible = "rockchip,rk3368-vop";
1368                 reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>;
1369                 reg-names = "regs", "gamma_lut";
1370                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1371                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1372                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1373                 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1374                 assigned-clock-rates = <400000000>, <200000000>;
1375                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1376                 reset-names = "axi", "ahb", "dclk";
1377                 power-domains = <&power RK3368_PD_VIO>;
1378                 iommus = <&vop_mmu>;
1379                 status = "disabled";
1380
1381                 vop_out: port {
1382                         #address-cells = <1>;
1383                         #size-cells = <0>;
1384
1385                         vop_out_dsi: endpoint@0 {
1386                                 reg = <0>;
1387                                 remote-endpoint = <&dsi_in_vop>;
1388                         };
1389
1390                         vop_out_edp: endpoint@1 {
1391                                 reg = <1>;
1392                                 remote-endpoint = <&edp_in_vop>;
1393                         };
1394
1395                         vop_out_hdmi: endpoint@2 {
1396                                 reg = <2>;
1397                                 remote-endpoint = <&hdmi_in_vop>;
1398                         };
1399
1400                         vop_out_lvds: endpoint@3 {
1401                                 reg = <3>;
1402                                 remote-endpoint = <&lvds_in_vop>;
1403                         };
1404                 };
1405         };
1406
1407         display_subsystem: display-subsystem {
1408                 compatible = "rockchip,display-subsystem";
1409                 ports = <&vop_out>;
1410                 status = "disabled";
1411         };
1412
1413         vop_mmu: iommu@ff930300 {
1414                 compatible = "rockchip,iommu";
1415                 reg = <0x0 0xff930300 0x0 0x100>;
1416                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1417                 interrupt-names = "vop_mmu";
1418                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1419                 clock-names = "aclk", "hclk";
1420                 power-domains = <&power RK3368_PD_VIO>;
1421                 #iommu-cells = <0>;
1422                 status = "disabled";
1423         };
1424
1425         dsi: dsi@ff960000 {
1426                 compatible = "rockchip,rk3368-mipi-dsi";
1427                 reg = <0x0 0xff960000 0x0 0x4000>;
1428                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1429                 clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>;
1430                 clock-names = "pclk", "hs_clk";
1431                 resets = <&cru SRST_MIPIDSI0>;
1432                 reset-names = "apb";
1433                 phys = <&mipi_dphy>;
1434                 phy-names = "mipi_dphy";
1435                 rockchip,grf = <&grf>;
1436                 power-domains = <&power RK3368_PD_VIO>;
1437                 #address-cells = <1>;
1438                 #size-cells = <0>;
1439                 status = "disabled";
1440
1441                 ports {
1442                         port {
1443                                 dsi_in_vop: endpoint {
1444                                         remote-endpoint = <&vop_out_dsi>;
1445                                 };
1446                         };
1447                 };
1448         };
1449
1450         mipi_dphy: mipi-dphy@ff968000 {
1451                 compatible = "rockchip,rk3368-mipi-dphy";
1452                 reg = <0x0 0xff968000 0x0 0x4000>;
1453                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1454                 clock-names = "ref", "pclk";
1455                 clock-output-names = "mipi_dphy_pll";
1456                 #clock-cells = <0>;
1457                 resets = <&cru SRST_MIPIDPHYTX>;
1458                 reset-names = "apb";
1459                 #phy-cells = <0>;
1460                 status = "disabled";
1461         };
1462
1463         lvds: lvds@ff968000 {
1464                 compatible = "rockchip,rk3368-lvds";
1465                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff960000 0x0 0x100>;
1466                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1467                 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1468                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1469                 power-domains = <&power RK3368_PD_VIO>;
1470                 rockchip,grf = <&grf>;
1471                 pinctrl-names = "lcdc", "gpio";
1472                 pinctrl-0 = <&lcdc_lcdc>;
1473                 pinctrl-1 = <&lcdc_gpio>;
1474                 status = "disabled";
1475
1476                 ports {
1477                         #address-cells = <1>;
1478                         #size-cells = <0>;
1479
1480                         lvds_in: port@0 {
1481                                 reg = <0>;
1482                                 lvds_in_vop: endpoint {
1483                                         remote-endpoint = <&vop_out_lvds>;
1484                                 };
1485                         };
1486                 };
1487         };
1488
1489         edp: edp@ff970000 {
1490                 compatible = "rockchip,rk3368-edp";
1491                 reg = <0x0 0xff970000 0x0 0x8000>;
1492                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1493                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1494                 clock-names = "dp", "pclk";
1495                 resets = <&cru SRST_EDP>;
1496                 reset-names = "dp";
1497                 power-domains = <&power RK3368_PD_VIO>;
1498                 rockchip,grf = <&grf>;
1499                 phys = <&edp_phy>;
1500                 phy-names = "dp";
1501                 pinctrl-names = "default";
1502                 pinctrl-0 = <&edp_hpd>;
1503                 status = "disabled";
1504
1505                 ports {
1506                         #address-cells = <1>;
1507                         #size-cells = <0>;
1508
1509                         edp_in: port@0 {
1510                                 reg = <0>;
1511
1512                                 edp_in_vop: endpoint {
1513                                         remote-endpoint = <&vop_out_edp>;
1514                                 };
1515                         };
1516                 };
1517         };
1518
1519         hdmi: hdmi@ff980000 {
1520                 compatible = "rockchip,rk3368-dw-hdmi";
1521                 reg = <0x0 0xff980000 0x0 0x20000>;
1522                 reg-io-width = <4>;
1523                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1524                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1525                 clock-names = "iahb", "isfr", "cec";
1526                 pinctrl-names = "default";
1527                 pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>;
1528                 resets = <&cru SRST_HDMI>;
1529                 reset-names = "hdmi";
1530                 power-domains = <&power RK3368_PD_VIO>;
1531                 rockchip,grf = <&grf>;
1532                 status = "disabled";
1533
1534                 ports {
1535                         port {
1536                                 hdmi_in_vop: endpoint {
1537                                         remote-endpoint = <&vop_out_hdmi>;
1538                                 };
1539                         };
1540                 };
1541         };
1542
1543         hevc_mmu: iommu@ff9a0440 {
1544                 compatible = "rockchip,iommu";
1545                 reg = <0x0 0xff9a0440 0x0 0x40>,
1546                       <0x0 0xff9a0480 0x0 0x40>;
1547                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1548                 interrupt-names = "hevc_mmu";
1549                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1550                 clock-names = "aclk", "hclk";
1551                 power-domains = <&power RK3368_PD_VIDEO>;
1552                 #iommu-cells = <0>;
1553                 status = "disabled";
1554         };
1555
1556         vpu_mmu: iommu@ff9a0800 {
1557                 compatible = "rockchip,iommu";
1558                 reg = <0x0 0xff9a0800 0x0 0x100>;
1559                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1560                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1561                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1562                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1563                 clock-names = "aclk", "hclk";
1564                 power-domains = <&power RK3368_PD_VIDEO>;
1565                 #iommu-cells = <0>;
1566                 status = "disabled";
1567         };
1568
1569         vpu: vpu_service {
1570                 compatible = "rockchip,vpu_sub";
1571                 iommu_enabled = <1>;
1572                 iommus = <&vpu_mmu>;
1573                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1574                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1575                 interrupt-names = "irq_enc","irq_dec";
1576                 dev_mode = <0>;
1577                 name = "vpu_service";
1578                 allocator = <1>;
1579         };
1580
1581         hevc: hevc_service {
1582                 compatible = "rockchip,hevc_sub";
1583                 iommu_enabled = <1>;
1584                 iommus = <&hevc_mmu>;
1585                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1586                 interrupt-names = "irq_dec";
1587                 dev_mode = <1>;
1588                 name = "hevc_service";
1589                 allocator = <1>;
1590         };
1591
1592         vpu_combo: vpu_combo@ff9a0000 {
1593                 compatible = "rockchip,vpu_combo";
1594                 reg = <0x0 0xff9a0000 0x0 0x440>;
1595                 rockchip,grf = <&grf>;
1596                 subcnt = <2>;
1597                 rockchip,sub = <&vpu>, <&hevc>;
1598                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
1599                          <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
1600                 clock-names = "aclk_vcodec", "hclk_vcodec",
1601                               "clk_core", "clk_cabac";
1602                 resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
1603                          <&cru SRST_VIDEO>;
1604                 reset-names = "video_a", "video_h", "video";
1605                 mode_bit = <12>;
1606                 mode_ctrl = <0x418>;
1607                 name = "vpu_combo";
1608                 power-domains = <&power RK3368_PD_VIDEO>;
1609                 status = "disabled";
1610         };
1611
1612         gic: interrupt-controller@ffb71000 {
1613                 compatible = "arm,gic-400";
1614                 interrupt-controller;
1615                 #interrupt-cells = <3>;
1616                 #address-cells = <0>;
1617
1618                 reg = <0x0 0xffb71000 0x0 0x1000>,
1619                       <0x0 0xffb72000 0x0 0x2000>,
1620                       <0x0 0xffb74000 0x0 0x2000>,
1621                       <0x0 0xffb76000 0x0 0x2000>;
1622                 interrupts = <GIC_PPI 9
1623                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1624         };
1625
1626         gpu: rogue-g6110@ffa30000 {
1627                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1628                 reg = <0x0 0xffa30000 0x0 0x10000>;
1629                 clocks =
1630                         <&cru SCLK_GPU_CORE>,
1631                         <&cru ACLK_GPU_MEM>,
1632                         <&cru ACLK_GPU_CFG>;
1633                 clock-names =
1634                         "sclk_gpu_core",
1635                         "aclk_gpu_mem",
1636                         "aclk_gpu_cfg";
1637                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1638                 interrupt-names = "rogue-g6110-irq";
1639                 power-domains = <&power RK3368_PD_GPU_1>;
1640                 operating-points-v2 = <&gpu_opp_table>;
1641                 #cooling-cells = <2>; /* min followed by max */
1642                 gpu_power_model: power_model {
1643                         compatible = "arm,mali-simple-power-model";
1644                         voltage = <900>;
1645                         frequency = <500>;
1646                         static-power = <300>;
1647                         dynamic-power = <396>;
1648                         ts = <32000 4700 (-80) 2>;
1649                         thermal-zone = "gpu-thermal";
1650                 };
1651         };
1652
1653         gpu_opp_table: gpu_opp_table {
1654                 compatible = "operating-points-v2";
1655                 opp-shared;
1656
1657                 opp-200000000 {
1658                         opp-hz = /bits/ 64 <200000000>;
1659                         opp-microvolt = <1100000>;
1660                 };
1661                 opp-288000000 {
1662                         opp-hz = /bits/ 64 <288000000>;
1663                         opp-microvolt = <1100000>;
1664                 };
1665                 opp-400000000 {
1666                         opp-hz = /bits/ 64 <400000000>;
1667                         opp-microvolt = <1100000>;
1668                 };
1669                 opp-576000000 {
1670                         opp-hz = /bits/ 64 <576000000>;
1671                         opp-microvolt = <1200000>;
1672                 };
1673         };
1674
1675         efuse: efuse@ffb00000 {
1676                 compatible = "rockchip,rk3368-efuse";
1677                 reg = <0x0 0xffb00000 0x0 0x20>;
1678                 #address-cells = <1>;
1679                 #size-cells = <1>;
1680                 clocks = <&cru PCLK_EFUSE256>;
1681                 clock-names = "pclk_efuse";
1682
1683                 /* Data cells */
1684                 cpu_leakage: cpu-leakage@17 {
1685                         reg = <0x17 0x1>;
1686                 };
1687                 temp_adjust: temp-adjust@1f {
1688                         reg = <0x1f 0x1>;
1689                 };
1690         };
1691
1692         pinctrl: pinctrl {
1693                 compatible = "rockchip,rk3368-pinctrl";
1694                 rockchip,grf = <&grf>;
1695                 rockchip,pmu = <&pmugrf>;
1696                 #address-cells = <0x2>;
1697                 #size-cells = <0x2>;
1698                 ranges;
1699
1700                 gpio0: gpio0@ff750000 {
1701                         compatible = "rockchip,gpio-bank";
1702                         reg = <0x0 0xff750000 0x0 0x100>;
1703                         clocks = <&cru PCLK_GPIO0>;
1704                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1705
1706                         gpio-controller;
1707                         #gpio-cells = <0x2>;
1708
1709                         interrupt-controller;
1710                         #interrupt-cells = <0x2>;
1711                 };
1712
1713                 gpio1: gpio1@ff780000 {
1714                         compatible = "rockchip,gpio-bank";
1715                         reg = <0x0 0xff780000 0x0 0x100>;
1716                         clocks = <&cru PCLK_GPIO1>;
1717                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1718
1719                         gpio-controller;
1720                         #gpio-cells = <0x2>;
1721
1722                         interrupt-controller;
1723                         #interrupt-cells = <0x2>;
1724                 };
1725
1726                 gpio2: gpio2@ff790000 {
1727                         compatible = "rockchip,gpio-bank";
1728                         reg = <0x0 0xff790000 0x0 0x100>;
1729                         clocks = <&cru PCLK_GPIO2>;
1730                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1731
1732                         gpio-controller;
1733                         #gpio-cells = <0x2>;
1734
1735                         interrupt-controller;
1736                         #interrupt-cells = <0x2>;
1737                 };
1738
1739                 gpio3: gpio3@ff7a0000 {
1740                         compatible = "rockchip,gpio-bank";
1741                         reg = <0x0 0xff7a0000 0x0 0x100>;
1742                         clocks = <&cru PCLK_GPIO3>;
1743                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1744
1745                         gpio-controller;
1746                         #gpio-cells = <0x2>;
1747
1748                         interrupt-controller;
1749                         #interrupt-cells = <0x2>;
1750                 };
1751
1752                 pcfg_pull_up: pcfg-pull-up {
1753                         bias-pull-up;
1754                 };
1755
1756                 pcfg_pull_down: pcfg-pull-down {
1757                         bias-pull-down;
1758                 };
1759
1760                 pcfg_pull_none: pcfg-pull-none {
1761                         bias-disable;
1762                 };
1763
1764                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1765                         bias-disable;
1766                         drive-strength = <12>;
1767                 };
1768
1769                 edp {
1770                         edp_hpd: edp-hpd {
1771                                 rockchip,pins = <2 23 RK_FUNC_2 &pcfg_pull_none>;
1772                         };
1773                 };
1774
1775                 emmc {
1776                         emmc_clk: emmc-clk {
1777                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1778                         };
1779
1780                         emmc_cmd: emmc-cmd {
1781                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1782                         };
1783
1784                         emmc_pwr: emmc-pwr {
1785                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1786                         };
1787
1788                         emmc_bus1: emmc-bus1 {
1789                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1790                         };
1791
1792                         emmc_bus4: emmc-bus4 {
1793                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1794                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1795                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1796                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1797                         };
1798
1799                         emmc_bus8: emmc-bus8 {
1800                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1801                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1802                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1803                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1804                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1805                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1806                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1807                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1808                         };
1809                 };
1810
1811                 gmac {
1812                         rgmii_pins: rgmii-pins {
1813                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1814                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1815                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1816                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1817                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1818                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1819                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1820                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1821                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1822                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1823                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1824                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1825                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1826                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1827                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1828                         };
1829
1830                         rmii_pins: rmii-pins {
1831                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1832                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1833                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1834                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1835                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1836                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1837                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1838                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1839                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1840                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1841                         };
1842                 };
1843
1844                 hdmi {
1845                         hdmi_cec: hdmi-cec {
1846                                 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1847                         };
1848
1849                         hdmi_i2c_xfer: hdmi-i2c-xfer {
1850                                 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1851                                                 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1852                         };
1853                 };
1854
1855                 i2c0 {
1856                         i2c0_xfer: i2c0-xfer {
1857                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1858                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1859                         };
1860                 };
1861
1862                 i2c1 {
1863                         i2c1_xfer: i2c1-xfer {
1864                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1865                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1866                         };
1867                 };
1868
1869                 i2c2 {
1870                         i2c2_xfer: i2c2-xfer {
1871                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1872                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1873                         };
1874                 };
1875
1876                 i2c3 {
1877                         i2c3_xfer: i2c3-xfer {
1878                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1879                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1880                         };
1881                 };
1882
1883                 i2c4 {
1884                         i2c4_xfer: i2c4-xfer {
1885                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1886                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1887                         };
1888                 };
1889
1890                 i2c5 {
1891                         i2c5_xfer: i2c5-xfer {
1892                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1893                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1894                         };
1895                 };
1896
1897                 i2s {
1898                         i2s_8ch_bus: i2s-8ch-bus {
1899                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1900                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1901                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1902                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1903                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1904                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1905                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1906                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1907                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1908                         };
1909                 };
1910
1911                 pwm0 {
1912                         pwm0_pin: pwm0-pin {
1913                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1914                         };
1915
1916                         vop_pwm_pin: vop-pwm {
1917                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1918                         };
1919                 };
1920
1921                 pwm1 {
1922                         pwm1_pin: pwm1-pin {
1923                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1924                         };
1925                 };
1926
1927                 pwm3 {
1928                         pwm3_pin: pwm3-pin {
1929                                 rockchip,pins = <3 30 RK_FUNC_3 &pcfg_pull_none>;
1930                         };
1931                 };
1932
1933                 sdio0 {
1934                         sdio0_bus1: sdio0-bus1 {
1935                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1936                         };
1937
1938                         sdio0_bus4: sdio0-bus4 {
1939                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1940                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1941                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1942                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1943                         };
1944
1945                         sdio0_cmd: sdio0-cmd {
1946                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1947                         };
1948
1949                         sdio0_clk: sdio0-clk {
1950                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1951                         };
1952
1953                         sdio0_cd: sdio0-cd {
1954                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1955                         };
1956
1957                         sdio0_wp: sdio0-wp {
1958                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1959                         };
1960
1961                         sdio0_pwr: sdio0-pwr {
1962                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1963                         };
1964
1965                         sdio0_bkpwr: sdio0-bkpwr {
1966                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1967                         };
1968
1969                         sdio0_int: sdio0-int {
1970                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1971                         };
1972                 };
1973
1974                 sdmmc {
1975                         sdmmc_clk: sdmmc-clk {
1976                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1977                         };
1978
1979                         sdmmc_cmd: sdmmc-cmd {
1980                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1981                         };
1982
1983                         sdmmc_cd: sdmmc-cd {
1984                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1985                         };
1986
1987                         sdmmc_bus1: sdmmc-bus1 {
1988                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1989                         };
1990
1991                         sdmmc_bus4: sdmmc-bus4 {
1992                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1993                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1994                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1995                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1996                         };
1997                 };
1998
1999                 spi0 {
2000                         spi0_clk: spi0-clk {
2001                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
2002                         };
2003                         spi0_cs0: spi0-cs0 {
2004                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
2005                         };
2006                         spi0_cs1: spi0-cs1 {
2007                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
2008                         };
2009                         spi0_tx: spi0-tx {
2010                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
2011                         };
2012                         spi0_rx: spi0-rx {
2013                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
2014                         };
2015                 };
2016
2017                 spi1 {
2018                         spi1_clk: spi1-clk {
2019                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
2020                         };
2021                         spi1_cs0: spi1-cs0 {
2022                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
2023                         };
2024                         spi1_cs1: spi1-cs1 {
2025                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
2026                         };
2027                         spi1_rx: spi1-rx {
2028                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
2029                         };
2030                         spi1_tx: spi1-tx {
2031                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
2032                         };
2033                 };
2034
2035                 spi2 {
2036                         spi2_clk: spi2-clk {
2037                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
2038                         };
2039                         spi2_cs0: spi2-cs0 {
2040                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
2041                         };
2042                         spi2_rx: spi2-rx {
2043                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
2044                         };
2045                         spi2_tx: spi2-tx {
2046                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
2047                         };
2048                 };
2049
2050                 uart0 {
2051                         uart0_xfer: uart0-xfer {
2052                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
2053                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2054                         };
2055
2056                         uart0_cts: uart0-cts {
2057                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
2058                         };
2059
2060                         uart0_rts: uart0-rts {
2061                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
2062                         };
2063                 };
2064
2065                 uart1 {
2066                         uart1_xfer: uart1-xfer {
2067                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
2068                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
2069                         };
2070
2071                         uart1_cts: uart1-cts {
2072                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
2073                         };
2074
2075                         uart1_rts: uart1-rts {
2076                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
2077                         };
2078                 };
2079
2080                 uart2 {
2081                         uart2_xfer: uart2-xfer {
2082                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
2083                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
2084                         };
2085                         /* no rts / cts for uart2 */
2086                 };
2087
2088                 uart3 {
2089                         uart3_xfer: uart3-xfer {
2090                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
2091                                                 <3 30 RK_FUNC_2 &pcfg_pull_none>;
2092                         };
2093
2094                         uart3_cts: uart3-cts {
2095                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
2096                         };
2097
2098                         uart3_rts: uart3-rts {
2099                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
2100                         };
2101                 };
2102
2103                 uart4 {
2104                         uart4_xfer: uart4-xfer {
2105                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
2106                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
2107                         };
2108
2109                         uart4_cts: uart4-cts {
2110                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
2111                         };
2112
2113                         uart4_rts: uart4-rts {
2114                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
2115                         };
2116                 };
2117
2118                 isp {
2119                         cif_clkout: cif-clkout {
2120                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2121                         };
2122
2123                         isp_dvp_d2d9: isp-dvp-d2d9 {
2124                                 rockchip,pins =
2125                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2126                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2127                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2128                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2129                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2130                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2131                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2132                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2133                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
2134                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
2135                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
2136                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2137                         };
2138
2139                         isp_dvp_d0d1: isp-dvp-d0d1 {
2140                                 rockchip,pins =
2141                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2142                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
2143                         };
2144
2145                         isp_dvp_d10d11:isp_d10d11 {
2146                                 rockchip,pins =
2147                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2148                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2149                         };
2150
2151                         isp_dvp_d0d7: isp-dvp-d0d7 {
2152                                 rockchip,pins =
2153                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2154                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
2155                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2156                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2157                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2158                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2159                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2160                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2161                         };
2162
2163                         isp_dvp_d4d11: isp-dvp-d4d11 {
2164                                 rockchip,pins =
2165                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2166                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2167                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2168                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2169                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2170                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2171                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2172                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2173                         };
2174
2175                         isp_shutter: isp-shutter {
2176                                 rockchip,pins =
2177                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2178                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2179                         };
2180
2181                         isp_flash_trigger: isp-flash-trigger {
2182                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2183                         };
2184
2185                         isp_prelight: isp-prelight {
2186                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2187                         };
2188
2189                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2190                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2191                         };
2192                 };
2193
2194                 lcdc {
2195                         lcdc_lcdc: lcdc-lcdc {
2196                                 rockchip,pins =
2197                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D10 */
2198                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D11 */
2199                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D12 */
2200                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D13 */
2201                                         <0 18 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D14 */
2202                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D15 */
2203                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D16 */
2204                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D17 */
2205                                         <0 22 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D18 */
2206                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D19 */
2207                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D20 */
2208                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D21 */
2209                                         <0 26 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D22 */
2210                                         <0 27 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D23 */
2211                                         <0 31 RK_FUNC_1 &pcfg_pull_none>,  /* DCLK */
2212                                         <0 30 RK_FUNC_1 &pcfg_pull_none>,  /* DEN */
2213                                         <0 28 RK_FUNC_1 &pcfg_pull_none>,  /* HSYNC */
2214                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;  /* VSYN */
2215                         };
2216
2217                         lcdc_gpio: lcdc-gpio {
2218                                 rockchip,pins =
2219                                         <0 14 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D10 */
2220                                         <0 15 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D11 */
2221                                         <0 16 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D12 */
2222                                         <0 17 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D13 */
2223                                         <0 18 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D14 */
2224                                         <0 19 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D15 */
2225                                         <0 20 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D16 */
2226                                         <0 21 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D17 */
2227                                         <0 22 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D18 */
2228                                         <0 23 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D19 */
2229                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D20 */
2230                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D21 */
2231                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D22 */
2232                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D23 */
2233                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>,  /* DCLK */
2234                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>,  /* DEN */
2235                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>,  /* HSYNC */
2236                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>;  /* VSYN */
2237                         };
2238                 };
2239         };
2240
2241         rockchip_suspend: rockchip-suspend {
2242                 compatible = "rockchip,pm-rk3368";
2243                 status = "disabled";
2244                 rockchip,sleep-debug-en = <0>;
2245                 rockchip,sleep-mode-config = <
2246                         (0
2247                         | RKPM_SLP_ARMOFF_LOGPD
2248                         | RKPM_SLP_PMU_PLLS_PWRDN
2249                         | RKPM_SLP_PMU_PMUALIVE_32K
2250                         | RKPM_SLP_SFT_PLLS_DEEP
2251                         | RKPM_SLP_PMU_DIS_OSC
2252                         | RKPM_SLP_SFT_PD_NBSCUS
2253                         )
2254                 >;
2255                 rockchip,wakeup-config = <
2256                         (0
2257                         | RKPM_GPIO_WKUP_EN
2258                         | RKPM_USB_WKUP_EN
2259                         )
2260                 >;
2261         };
2262 };