2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3368-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
51 #include <dt-bindings/display/mipi_dsi.h>
52 #include <dt-bindings/display/drm_mipi_dsi.h>
53 #include <dt-bindings/display/media-bus-format.h>
56 compatible = "rockchip,rk3368";
57 interrupt-parent = <&gic>;
80 #address-cells = <0x2>;
116 entry-method = "psci";
118 cpu_sleep: cpu-sleep-0 {
119 compatible = "arm,idle-state";
120 arm,psci-suspend-param = <0x1010000>;
121 entry-latency-us = <0x3fffffff>;
122 exit-latency-us = <0x40000000>;
123 min-residency-us = <0xffffffff>;
129 compatible = "arm,cortex-a53", "arm,armv8";
131 cpu-idle-states = <&cpu_sleep>;
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
135 #cooling-cells = <2>; /* min followed by max */
136 dynamic-power-coefficient = <149>;
141 compatible = "arm,cortex-a53", "arm,armv8";
143 cpu-idle-states = <&cpu_sleep>;
144 enable-method = "psci";
145 clocks = <&cru ARMCLKL>;
146 operating-points-v2 = <&cluster0_opp>;
151 compatible = "arm,cortex-a53", "arm,armv8";
153 cpu-idle-states = <&cpu_sleep>;
154 enable-method = "psci";
155 clocks = <&cru ARMCLKL>;
156 operating-points-v2 = <&cluster0_opp>;
161 compatible = "arm,cortex-a53", "arm,armv8";
163 cpu-idle-states = <&cpu_sleep>;
164 enable-method = "psci";
165 clocks = <&cru ARMCLKL>;
166 operating-points-v2 = <&cluster0_opp>;
171 compatible = "arm,cortex-a53", "arm,armv8";
173 cpu-idle-states = <&cpu_sleep>;
174 enable-method = "psci";
175 clocks = <&cru ARMCLKB>;
176 operating-points-v2 = <&cluster1_opp>;
177 #cooling-cells = <2>; /* min followed by max */
178 dynamic-power-coefficient = <160>;
183 compatible = "arm,cortex-a53", "arm,armv8";
185 cpu-idle-states = <&cpu_sleep>;
186 enable-method = "psci";
187 clocks = <&cru ARMCLKB>;
188 operating-points-v2 = <&cluster1_opp>;
193 compatible = "arm,cortex-a53", "arm,armv8";
195 cpu-idle-states = <&cpu_sleep>;
196 enable-method = "psci";
197 clocks = <&cru ARMCLKB>;
198 operating-points-v2 = <&cluster1_opp>;
203 compatible = "arm,cortex-a53", "arm,armv8";
205 cpu-idle-states = <&cpu_sleep>;
206 enable-method = "psci";
207 clocks = <&cru ARMCLKB>;
208 operating-points-v2 = <&cluster1_opp>;
212 cluster0_opp: opp_table0 {
213 compatible = "operating-points-v2";
217 opp-hz = /bits/ 64 <216000000>;
218 opp-microvolt = <950000 950000 1350000>;
219 clock-latency-ns = <40000>;
223 opp-hz = /bits/ 64 <408000000>;
224 opp-microvolt = <950000 950000 1350000>;
225 clock-latency-ns = <40000>;
228 opp-hz = /bits/ 64 <600000000>;
229 opp-microvolt = <950000 950000 1350000>;
230 clock-latency-ns = <40000>;
233 opp-hz = /bits/ 64 <816000000>;
234 opp-microvolt = <1025000 1025000 1350000>;
235 clock-latency-ns = <40000>;
238 opp-hz = /bits/ 64 <1008000000>;
239 opp-microvolt = <1125000 1125000 1350000>;
240 clock-latency-ns = <40000>;
243 opp-hz = /bits/ 64 <1200000000>;
244 opp-microvolt = <1225000 1225000 1350000>;
245 clock-latency-ns = <40000>;
249 cluster1_opp: opp_table1 {
250 compatible = "operating-points-v2";
254 opp-hz = /bits/ 64 <216000000>;
255 opp-microvolt = <950000 950000 1350000>;
256 clock-latency-ns = <40000>;
260 opp-hz = /bits/ 64 <408000000>;
261 opp-microvolt = <950000 950000 1350000>;
262 clock-latency-ns = <40000>;
265 opp-hz = /bits/ 64 <600000000>;
266 opp-microvolt = <950000 950000 1350000>;
267 clock-latency-ns = <40000>;
270 opp-hz = /bits/ 64 <816000000>;
271 opp-microvolt = <975000 975000 1350000>;
272 clock-latency-ns = <40000>;
275 opp-hz = /bits/ 64 <1008000000>;
276 opp-microvolt = <1050000 1050000 1350000>;
277 clock-latency-ns = <40000>;
280 opp-hz = /bits/ 64 <1200000000>;
281 opp-microvolt = <1150000 1150000 1350000>;
282 clock-latency-ns = <40000>;
285 opp-hz = /bits/ 64 <1296000000>;
286 opp-microvolt = <1225000 1225000 1350000>;
287 clock-latency-ns = <40000>;
290 opp-hz = /bits/ 64 <1416000000>;
291 opp-microvolt = <1300000 1300000 1350000>;
292 clock-latency-ns = <40000>;
295 opp-hz = /bits/ 64 <1512000000>;
296 opp-microvolt = <1350000 1350000 1350000>;
297 clock-latency-ns = <40000>;
304 min-volt = <950000>; /* uV */
305 min-freq = <216000>; /* KHz */
306 leakage-adjust-volt = <
310 nvmem-cells = <&cpu_leakage>;
311 nvmem-cell-names = "cpu_leakage";
315 min-volt = <950000>; /* uV */
316 min-freq = <216000>; /* KHz */
317 leakage-adjust-volt = <
321 nvmem-cells = <&cpu_leakage>;
322 nvmem-cell-names = "cpu_leakage";
327 compatible = "arm,armv8-pmuv3";
328 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
337 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
338 <&cpu_b2>, <&cpu_b3>;
342 compatible = "arm,amba-bus";
343 #address-cells = <2>;
347 dmac_peri: dma-controller@ff250000 {
348 compatible = "arm,pl330", "arm,primecell";
349 reg = <0x0 0xff250000 0x0 0x4000>;
350 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&cru ACLK_DMAC_PERI>;
354 clock-names = "apb_pclk";
355 arm,pl330-broken-no-flushp;
356 peripherals-req-type-burst;
359 dmac_bus: dma-controller@ff600000 {
360 compatible = "arm,pl330", "arm,primecell";
361 reg = <0x0 0xff600000 0x0 0x4000>;
362 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&cru ACLK_DMAC_BUS>;
366 clock-names = "apb_pclk";
367 arm,pl330-broken-no-flushp;
368 peripherals-req-type-burst;
373 compatible = "arm,psci-0.2";
378 compatible = "arm,armv8-timer";
379 interrupts = <GIC_PPI 13
380 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
382 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
384 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
386 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
390 compatible = "fixed-clock";
391 clock-frequency = <24000000>;
392 clock-output-names = "xin24m";
397 compatible = "fixed-clock";
398 clock-frequency = <32768>;
399 clock-output-names = "xin32k";
403 sdmmc: rksdmmc@ff0c0000 {
404 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
405 reg = <0x0 0xff0c0000 0x0 0x4000>;
406 clock-freq-min-max = <400000 150000000>;
407 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
408 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
409 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
410 fifo-depth = <0x100>;
411 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
415 sdio0: dwmmc@ff0d0000 {
416 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
417 reg = <0x0 0xff0d0000 0x0 0x4000>;
418 clock-freq-min-max = <400000 150000000>;
419 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
420 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
421 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
422 fifo-depth = <0x100>;
423 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
427 emmc: rksdmmc@ff0f0000 {
428 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
429 reg = <0x0 0xff0f0000 0x0 0x4000>;
430 clock-freq-min-max = <400000 150000000>;
431 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
432 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
433 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
434 fifo-depth = <0x100>;
435 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
439 saradc: saradc@ff100000 {
440 compatible = "rockchip,saradc";
441 reg = <0x0 0xff100000 0x0 0x100>;
442 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
443 #io-channel-cells = <1>;
444 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
445 clock-names = "saradc", "apb_pclk";
446 resets = <&cru SRST_SARADC>;
447 reset-names = "saradc-apb";
452 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
453 reg = <0x0 0xff110000 0x0 0x1000>;
454 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
455 clock-names = "spiclk", "apb_pclk";
456 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
459 #address-cells = <1>;
465 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
466 reg = <0x0 0xff120000 0x0 0x1000>;
467 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
468 clock-names = "spiclk", "apb_pclk";
469 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
472 #address-cells = <1>;
478 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
479 reg = <0x0 0xff130000 0x0 0x1000>;
480 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
481 clock-names = "spiclk", "apb_pclk";
482 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
485 #address-cells = <1>;
491 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
492 reg = <0x0 0xff650000 0x0 0x1000>;
493 clocks = <&cru PCLK_I2C0>;
495 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&i2c0_xfer>;
498 #address-cells = <1>;
504 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
505 reg = <0x0 0xff140000 0x0 0x1000>;
506 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
507 #address-cells = <1>;
510 clocks = <&cru PCLK_I2C2>;
511 pinctrl-names = "default";
512 pinctrl-0 = <&i2c2_xfer>;
517 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
518 reg = <0x0 0xff150000 0x0 0x1000>;
519 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
520 #address-cells = <1>;
523 clocks = <&cru PCLK_I2C3>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&i2c3_xfer>;
530 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
531 reg = <0x0 0xff160000 0x0 0x1000>;
532 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
533 #address-cells = <1>;
536 clocks = <&cru PCLK_I2C4>;
537 pinctrl-names = "default";
538 pinctrl-0 = <&i2c4_xfer>;
543 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
544 reg = <0x0 0xff170000 0x0 0x1000>;
545 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>;
549 clocks = <&cru PCLK_I2C5>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&i2c5_xfer>;
555 uart0: serial@ff180000 {
556 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
557 reg = <0x0 0xff180000 0x0 0x100>;
558 clock-frequency = <24000000>;
559 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
560 clock-names = "baudclk", "apb_pclk";
561 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
567 uart1: serial@ff190000 {
568 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
569 reg = <0x0 0xff190000 0x0 0x100>;
570 clock-frequency = <24000000>;
571 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
572 clock-names = "baudclk", "apb_pclk";
573 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
579 uart3: serial@ff1b0000 {
580 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
581 reg = <0x0 0xff1b0000 0x0 0x100>;
582 clock-frequency = <24000000>;
583 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
584 clock-names = "baudclk", "apb_pclk";
585 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
591 uart4: serial@ff1c0000 {
592 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
593 reg = <0x0 0xff1c0000 0x0 0x100>;
594 clock-frequency = <24000000>;
595 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
596 clock-names = "baudclk", "apb_pclk";
597 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
605 polling-delay-passive = <300>; /* milliseconds */
606 polling-delay = <300>; /* milliseconds */
607 sustainable-power = <600>; /* milliwatts */
609 thermal-sensors = <&tsadc 0>;
611 cpu_alert0: cpu_alert0 {
612 temperature = <70000>; /* millicelsius */
613 hysteresis = <2000>; /* millicelsius */
616 cpu_alert1: cpu_alert1 {
617 temperature = <80000>; /* millicelsius */
618 hysteresis = <2000>; /* millicelsius */
622 temperature = <90000>; /* millicelsius */
623 hysteresis = <2000>; /* millicelsius */
630 trip = <&cpu_alert1>;
632 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
633 contribution = <1024>;
636 trip = <&cpu_alert1>;
638 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
639 contribution = <1024>;
644 gpu_thermal: gpu-thermal {
645 polling-delay-passive = <300>; /* milliseconds */
646 polling-delay = <300>; /* milliseconds */
647 thermal-sensors = <&tsadc 1>;
651 tsadc: tsadc@ff280000 {
652 compatible = "rockchip,rk3368-tsadc-legacy";
653 reg = <0x0 0xff280000 0x0 0x100>;
654 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
656 clock-names = "tsadc", "apb_pclk";
657 clock-frequency = <32768>;
658 resets = <&cru SRST_TSADC>;
659 reset-names = "tsadc-apb";
660 nvmem-cells = <&temp_adjust>;
661 nvmem-cell-names = "temp_adjust";
662 #thermal-sensor-cells = <1>;
663 hw-shut-temp = <95000>;
667 gmac: ethernet@ff290000 {
668 compatible = "rockchip,rk3368-gmac";
669 reg = <0x0 0xff290000 0x0 0x10000>;
670 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
671 interrupt-names = "macirq";
672 rockchip,grf = <&grf>;
673 clocks = <&cru SCLK_MAC>,
674 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
675 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
676 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
677 clock-names = "stmmaceth",
678 "mac_clk_rx", "mac_clk_tx",
679 "clk_mac_ref", "clk_mac_refout",
680 "aclk_mac", "pclk_mac";
684 nandc0: nandc@ff400000 {
685 compatible = "rockchip,rk-nandc";
686 reg = <0x0 0xff400000 0x0 0x4000>;
687 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
690 clock-names = "clk_nandc", "hclk_nandc";
694 usb_host0_ehci: usb@ff500000 {
695 compatible = "generic-ehci";
696 reg = <0x0 0xff500000 0x0 0x20000>;
697 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&cru HCLK_HOST0>, <&u2phy>;
699 clock-names = "usbhost", "utmi";
700 phys = <&u2phy_host>;
705 usb_host0_ohci: usb@ff520000 {
706 compatible = "generic-ohci";
707 reg = <0x0 0xff520000 0x0 0x20000>;
708 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&cru HCLK_HOST0>, <&u2phy>;
710 clock-names = "usbhost", "utmi";
711 phys = <&u2phy_host>;
716 usb_otg: usb@ff580000 {
717 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
719 reg = <0x0 0xff580000 0x0 0x40000>;
720 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&cru HCLK_OTG0>;
724 g-np-tx-fifo-size = <16>;
725 g-rx-fifo-size = <275>;
726 g-tx-fifo-size = <256 128 128 64 64 32>;
731 ddrpctl: syscon@ff610000 {
732 compatible = "rockchip,rk3368-ddrpctl", "syscon";
733 reg = <0x0 0xff610000 0x0 0x400>;
737 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
738 reg = <0x0 0xff660000 0x0 0x1000>;
739 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
740 #address-cells = <1>;
743 clocks = <&cru PCLK_I2C1>;
744 pinctrl-names = "default";
745 pinctrl-0 = <&i2c1_xfer>;
750 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
751 reg = <0x0 0xff680000 0x0 0x10>;
753 pinctrl-names = "default";
754 pinctrl-0 = <&pwm0_pin>;
755 clocks = <&cru PCLK_PWM1>;
761 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
762 reg = <0x0 0xff680010 0x0 0x10>;
764 pinctrl-names = "default";
765 pinctrl-0 = <&pwm1_pin>;
766 clocks = <&cru PCLK_PWM1>;
772 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
773 reg = <0x0 0xff680020 0x0 0x10>;
775 clocks = <&cru PCLK_PWM1>;
781 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
782 reg = <0x0 0xff680030 0x0 0x10>;
784 pinctrl-names = "default";
785 pinctrl-0 = <&pwm3_pin>;
786 clocks = <&cru PCLK_PWM1>;
791 uart2: serial@ff690000 {
792 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
793 reg = <0x0 0xff690000 0x0 0x100>;
794 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
795 clock-names = "baudclk", "apb_pclk";
796 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
797 pinctrl-names = "default";
798 pinctrl-0 = <&uart2_xfer>;
804 mbox: mbox@ff6b0000 {
805 compatible = "rockchip,rk3368-mailbox";
806 reg = <0x0 0xff6b0000 0x0 0x1000>;
807 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&cru PCLK_MAILBOX>;
812 clock-names = "pclk_mailbox";
817 mailbox: mailbox@ff6b0000 {
818 compatible = "rockchip,rk3368-mbox-legacy";
819 reg = <0x0 0xff6b0000 0x0 0x1000>,
820 <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
821 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&cru PCLK_MAILBOX>;
826 clock-names = "pclk_mailbox";
831 mailbox_scpi: mailbox-scpi {
832 compatible = "rockchip,rk3368-scpi-legacy";
833 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
838 qos_iep: qos@ffad0000 {
839 compatible = "syscon";
840 reg = <0x0 0xffad0000 0x0 0x20>;
843 qos_isp_r0: qos@ffad0080 {
844 compatible = "syscon";
845 reg = <0x0 0xffad0080 0x0 0x20>;
848 qos_isp_r1: qos@ffad0100 {
849 compatible = "syscon";
850 reg = <0x0 0xffad0100 0x0 0x20>;
853 qos_isp_w0: qos@ffad0180 {
854 compatible = "syscon";
855 reg = <0x0 0xffad0180 0x0 0x20>;
858 qos_isp_w1: qos@ffad0200 {
859 compatible = "syscon";
860 reg = <0x0 0xffad0200 0x0 0x20>;
863 qos_vip: qos@ffad0280 {
864 compatible = "syscon";
865 reg = <0x0 0xffad0280 0x0 0x20>;
868 qos_vop: qos@ffad0300 {
869 compatible = "syscon";
870 reg = <0x0 0xffad0300 0x0 0x20>;
873 qos_rga_r: qos@ffad0380 {
874 compatible = "syscon";
875 reg = <0x0 0xffad0380 0x0 0x20>;
878 qos_rga_w: qos@ffad0400 {
879 compatible = "syscon";
880 reg = <0x0 0xffad0400 0x0 0x20>;
883 qos_hevc_r: qos@ffae0000 {
884 compatible = "syscon";
885 reg = <0x0 0xffae0000 0x0 0x20>;
888 qos_vpu_r: qos@ffae0100 {
889 compatible = "syscon";
890 reg = <0x0 0xffae0100 0x0 0x20>;
893 qos_vpu_w: qos@ffae0180 {
894 compatible = "syscon";
895 reg = <0x0 0xffae0180 0x0 0x20>;
898 qos_gpu: qos@ffaf0000 {
899 compatible = "syscon";
900 reg = <0x0 0xffaf0000 0x0 0x20>;
903 pmu: power-management@ff730000 {
904 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
905 reg = <0x0 0xff730000 0x0 0x1000>;
907 power: power-controller {
908 compatible = "rockchip,rk3368-power-controller";
909 #power-domain-cells = <1>;
910 #address-cells = <1>;
914 * Note: Although SCLK_* are the working clocks
915 * of device without including on the NOC, needed for
918 * The clocks on the which NOC:
919 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
920 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
921 * ACLK_RGA is on ACLK_RGA_NIU.
922 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
924 * Which clock are device clocks:
926 * *_IEP IEP:Image Enhancement Processor
927 * *_ISP ISP:Image Signal Processing
928 * *_VIP VIP:Video Input Processor
929 * *_VOP* VOP:Visual Output Processor
937 reg = <RK3368_PD_VIO>;
938 clocks = <&cru ACLK_IEP>,
950 <&cru HCLK_VIO_HDCPMMU>,
951 <&cru PCLK_EDP_CTRL>,
952 <&cru PCLK_HDMI_CTRL>,
958 <&cru PCLK_MIPI_CSI>,
959 <&cru PCLK_MIPI_DSI0>,
960 <&cru SCLK_VOP0_PWM>,
966 <&cru SCLK_HDMI_CEC>,
967 <&cru SCLK_HDMI_HDCP>;
979 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
980 * (video endecoder & decoder) clocks that on the
981 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
984 reg = <RK3368_PD_VIDEO>;
985 clocks = <&cru ACLK_VIDEO>,
987 <&cru SCLK_HEVC_CABAC>,
988 <&cru SCLK_HEVC_CORE>;
989 pm_qos = <&qos_hevc_r>,
994 * Note: ACLK_GPU is the GPU clock,
995 * and on the ACLK_GPU_NIU (NOC).
998 reg = <RK3368_PD_GPU_1>;
999 clocks = <&cru ACLK_GPU_CFG>,
1000 <&cru ACLK_GPU_MEM>,
1001 <&cru SCLK_GPU_CORE>;
1002 pm_qos = <&qos_gpu>;
1007 pmugrf: syscon@ff738000 {
1008 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1009 reg = <0x0 0xff738000 0x0 0x1000>;
1011 pmu_io_domains: io-domains {
1012 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1013 status = "disabled";
1017 compatible = "syscon-reboot-mode";
1019 mode-normal = <BOOT_NORMAL>;
1020 mode-recovery = <BOOT_RECOVERY>;
1021 mode-bootloader = <BOOT_FASTBOOT>;
1022 mode-loader = <BOOT_BL_DOWNLOAD>;
1026 cru: clock-controller@ff760000 {
1027 compatible = "rockchip,rk3368-cru";
1028 reg = <0x0 0xff760000 0x0 0x1000>;
1029 rockchip,grf = <&grf>;
1033 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1034 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1035 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1036 <&cru PCLK_BUS>, <&cru PCLK_PERI>;
1037 assigned-clock-rates =
1038 <576000000>, <400000000>,
1039 <300000000>, <300000000>,
1040 <150000000>, <150000000>,
1041 <75000000>, <75000000>;
1044 grf: syscon@ff770000 {
1045 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1046 reg = <0x0 0xff770000 0x0 0x1000>;
1047 #address-cells = <1>;
1050 io_domains: io-domains {
1051 compatible = "rockchip,rk3368-io-voltage-domain";
1052 status = "disabled";
1055 u2phy: usb2-phy@700 {
1056 compatible = "rockchip,rk3368-usb2phy";
1058 clocks = <&cru SCLK_OTGPHY0>;
1059 clock-names = "phyclk";
1061 clock-output-names = "usbotg_out";
1062 assigned-clocks = <&cru SCLK_USBPHY480M>;
1063 assigned-clock-parents = <&u2phy>;
1064 status = "disabled";
1066 u2phy_host: host-port {
1068 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1069 interrupt-names = "linestate";
1070 status = "disabled";
1075 wdt: watchdog@ff800000 {
1076 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1077 reg = <0x0 0xff800000 0x0 0x100>;
1078 clocks = <&cru PCLK_WDT>;
1079 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1080 status = "disabled";
1084 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1085 reg = <0x0 0xff810000 0x0 0x20>;
1086 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1089 i2s_2ch: i2s-2ch@ff890000 {
1090 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1091 reg = <0x0 0xff890000 0x0 0x1000>;
1092 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1093 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1094 dma-names = "tx", "rx";
1095 clock-names = "i2s_clk", "i2s_hclk";
1096 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1097 status = "disabled";
1100 i2s_8ch: i2s-8ch@ff898000 {
1101 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1102 reg = <0x0 0xff898000 0x0 0x1000>;
1103 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1104 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1105 dma-names = "tx", "rx";
1106 clock-names = "i2s_clk", "i2s_hclk";
1107 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1108 pinctrl-names = "default";
1109 pinctrl-0 = <&i2s_8ch_bus>;
1110 status = "disabled";
1114 compatible = "rockchip,rk3368-isp", "rockchip,isp";
1115 reg = <0x0 0xff910000 0x0 0x4000>;
1116 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1117 power-domains = <&power RK3368_PD_VIO>;
1119 <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1120 <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
1121 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
1122 <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
1124 "aclk_isp", "hclk_isp", "clk_isp",
1125 "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1126 "clk_cif_pll", "hclk_mipiphy1",
1127 "pclk_dphyrx", "clk_vio0_noc";
1130 "default", "isp_dvp8bit2", "isp_dvp10bit",
1131 "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
1132 "isp_mipi_fl", "isp_mipi_fl_prefl",
1133 "isp_flash_as_gpio", "isp_flash_as_trigger_out";
1134 pinctrl-0 = <&cif_clkout>;
1135 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1136 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1137 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1138 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1139 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1140 pinctrl-6 = <&cif_clkout>;
1141 pinctrl-7 = <&cif_clkout &isp_prelight>;
1142 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1143 pinctrl-9 = <&isp_flash_trigger>;
1144 rockchip,isp,mipiphy = <2>;
1145 rockchip,isp,cifphy = <1>;
1146 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1147 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1148 rockchip,grf = <&grf>;
1149 rockchip,cru = <&cru>;
1150 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
1151 rockchip,isp,iommu-enable = <1>;
1152 iommus = <&isp_mmu>;
1153 status = "disabled";
1156 isp_mmu: iommu@ff914000 {
1157 compatible = "rockchip,iommu";
1158 reg = <0x0 0xff914000 0x0 0x100>,
1159 <0x0 0xff915000 0x0 0x100>;
1160 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1161 interrupt-names = "isp_mmu";
1162 clocks = <&cru ACLK_RGA>, <&cru HCLK_ISP>;
1163 clock-names = "aclk", "hclk";
1164 rk_iommu,disable_reset_quirk;
1166 power-domains = <&power RK3368_PD_VIO>;
1167 status = "disabled";
1171 compatible = "rockchip,rk3368-vop";
1172 reg = <0x0 0xff930000 0x0 0x2fc>;
1173 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1174 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1175 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1176 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1177 assigned-clock-rates = <400000000>, <200000000>;
1178 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1179 reset-names = "axi", "ahb", "dclk";
1180 power-domains = <&power RK3368_PD_VIO>;
1181 iommus = <&vop_mmu>;
1182 status = "disabled";
1185 #address-cells = <1>;
1188 vop_out_mipi: endpoint@0 {
1190 remote-endpoint = <&mipi_in_vop>;
1195 display_subsystem: display-subsystem {
1196 compatible = "rockchip,display-subsystem";
1198 status = "disabled";
1201 vop_mmu: iommu@ff930300 {
1202 compatible = "rockchip,iommu";
1203 reg = <0x0 0xff930300 0x0 0x100>;
1204 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1205 interrupt-names = "vop_mmu";
1206 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1207 clock-names = "aclk", "hclk";
1208 power-domains = <&power RK3368_PD_VIO>;
1210 status = "disabled";
1213 mipi_dsi_host: mipi-dsi-host@ff960000 {
1214 compatible = "rockchip,rk3368-mipi-dsi";
1215 reg = <0x0 0xff960000 0x0 0x4000>;
1216 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1217 clocks = <&cru PCLK_MIPI_DSI0>;
1218 clock-names = "pclk";
1219 phys = <&mipi_dphy>;
1220 phy-names = "mipi_dphy";
1221 rockchip,grf = <&grf>;
1222 power-domains = <&power RK3368_PD_VIO>;
1223 #address-cells = <1>;
1225 status = "disabled";
1228 #address-cells = <1>;
1233 #address-cells = <1>;
1236 mipi_in_vop: endpoint@0 {
1238 remote-endpoint = <&vop_out_mipi>;
1244 mipi_dphy: mipi-dphy@ff968000 {
1245 compatible = "rockchip,rk3368-mipi-dphy";
1246 reg = <0x0 0xff968000 0x0 0x4000>;
1248 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1249 clock-names = "ref", "pclk";
1250 status = "disabled";
1253 hevc_mmu: iommu@ff9a0440 {
1254 compatible = "rockchip,iommu";
1255 reg = <0x0 0xff9a0440 0x0 0x40>,
1256 <0x0 0xff9a0480 0x0 0x40>;
1257 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1258 interrupt-names = "hevc_mmu";
1259 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1260 clock-names = "aclk", "hclk";
1261 power-domains = <&power RK3368_PD_VIDEO>;
1263 status = "disabled";
1266 vpu_mmu: iommu@ff9a0800 {
1267 compatible = "rockchip,iommu";
1268 reg = <0x0 0xff9a0800 0x0 0x100>;
1269 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1271 interrupt-names = "vepu_mmu", "vdpu_mmu";
1272 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1273 clock-names = "aclk", "hclk";
1274 power-domains = <&power RK3368_PD_VIDEO>;
1276 status = "disabled";
1280 compatible = "rockchip,vpu_sub";
1281 iommu_enabled = <1>;
1282 iommus = <&vpu_mmu>;
1283 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1284 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1285 interrupt-names = "irq_enc","irq_dec";
1287 name = "vpu_service";
1291 hevc: hevc_service {
1292 compatible = "rockchip,hevc_sub";
1293 iommu_enabled = <1>;
1294 iommus = <&hevc_mmu>;
1295 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1296 interrupt-names = "irq_dec";
1298 name = "hevc_service";
1302 vpu_combo: vpu_combo@ff9a0000 {
1303 compatible = "rockchip,vpu_combo";
1304 reg = <0x0 0xff9a0000 0x0 0x440>;
1305 rockchip,grf = <&grf>;
1307 rockchip,sub = <&vpu>, <&hevc>;
1308 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
1309 <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
1310 clock-names = "aclk_vcodec", "hclk_vcodec",
1311 "clk_core", "clk_cabac";
1312 resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
1314 reset-names = "video_a", "video_h", "video";
1316 mode_ctrl = <0x418>;
1318 power-domains = <&power RK3368_PD_VIDEO>;
1319 status = "disabled";
1322 gic: interrupt-controller@ffb71000 {
1323 compatible = "arm,gic-400";
1324 interrupt-controller;
1325 #interrupt-cells = <3>;
1326 #address-cells = <0>;
1328 reg = <0x0 0xffb71000 0x0 0x1000>,
1329 <0x0 0xffb72000 0x0 0x2000>,
1330 <0x0 0xffb74000 0x0 0x2000>,
1331 <0x0 0xffb76000 0x0 0x2000>;
1332 interrupts = <GIC_PPI 9
1333 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1336 gpu: rogue-g6110@ffa30000 {
1337 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1338 reg = <0x0 0xffa30000 0x0 0x10000>;
1340 <&cru SCLK_GPU_CORE>,
1341 <&cru ACLK_GPU_MEM>,
1342 <&cru ACLK_GPU_CFG>;
1347 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1348 interrupt-names = "rogue-g6110-irq";
1349 power-domains = <&power RK3368_PD_GPU_1>;
1350 operating-points-v2 = <&gpu_opp_table>;
1353 gpu_opp_table: gpu_opp_table {
1354 compatible = "operating-points-v2";
1358 opp-hz = /bits/ 64 <200000000>;
1359 opp-microvolt = <1100000>;
1362 opp-hz = /bits/ 64 <288000000>;
1363 opp-microvolt = <1100000>;
1366 opp-hz = /bits/ 64 <400000000>;
1367 opp-microvolt = <1100000>;
1370 opp-hz = /bits/ 64 <576000000>;
1371 opp-microvolt = <1200000>;
1375 efuse: efuse@ffb00000 {
1376 compatible = "rockchip,rk3368-efuse";
1377 reg = <0x0 0xffb00000 0x0 0x20>;
1378 #address-cells = <1>;
1380 clocks = <&cru PCLK_EFUSE256>;
1381 clock-names = "pclk_efuse";
1384 cpu_leakage: cpu-leakage@17 {
1387 temp_adjust: temp-adjust@1f {
1393 compatible = "rockchip,rk3368-pinctrl";
1394 rockchip,grf = <&grf>;
1395 rockchip,pmu = <&pmugrf>;
1396 #address-cells = <0x2>;
1397 #size-cells = <0x2>;
1400 gpio0: gpio0@ff750000 {
1401 compatible = "rockchip,gpio-bank";
1402 reg = <0x0 0xff750000 0x0 0x100>;
1403 clocks = <&cru PCLK_GPIO0>;
1404 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1407 #gpio-cells = <0x2>;
1409 interrupt-controller;
1410 #interrupt-cells = <0x2>;
1413 gpio1: gpio1@ff780000 {
1414 compatible = "rockchip,gpio-bank";
1415 reg = <0x0 0xff780000 0x0 0x100>;
1416 clocks = <&cru PCLK_GPIO1>;
1417 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1420 #gpio-cells = <0x2>;
1422 interrupt-controller;
1423 #interrupt-cells = <0x2>;
1426 gpio2: gpio2@ff790000 {
1427 compatible = "rockchip,gpio-bank";
1428 reg = <0x0 0xff790000 0x0 0x100>;
1429 clocks = <&cru PCLK_GPIO2>;
1430 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1433 #gpio-cells = <0x2>;
1435 interrupt-controller;
1436 #interrupt-cells = <0x2>;
1439 gpio3: gpio3@ff7a0000 {
1440 compatible = "rockchip,gpio-bank";
1441 reg = <0x0 0xff7a0000 0x0 0x100>;
1442 clocks = <&cru PCLK_GPIO3>;
1443 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1446 #gpio-cells = <0x2>;
1448 interrupt-controller;
1449 #interrupt-cells = <0x2>;
1452 pcfg_pull_up: pcfg-pull-up {
1456 pcfg_pull_down: pcfg-pull-down {
1460 pcfg_pull_none: pcfg-pull-none {
1464 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1466 drive-strength = <12>;
1470 emmc_clk: emmc-clk {
1471 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1474 emmc_cmd: emmc-cmd {
1475 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1478 emmc_pwr: emmc-pwr {
1479 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1482 emmc_bus1: emmc-bus1 {
1483 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1486 emmc_bus4: emmc-bus4 {
1487 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1488 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1489 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1490 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1493 emmc_bus8: emmc-bus8 {
1494 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1495 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1496 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1497 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1498 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1499 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1500 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1501 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1506 rgmii_pins: rgmii-pins {
1507 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1508 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1509 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1510 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1511 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1512 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1513 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1514 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1515 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1516 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1517 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1518 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1519 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1520 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1521 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1524 rmii_pins: rmii-pins {
1525 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1526 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1527 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1528 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1529 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1530 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1531 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1532 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1533 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1534 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1539 i2c0_xfer: i2c0-xfer {
1540 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1541 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1546 i2c1_xfer: i2c1-xfer {
1547 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1548 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1553 i2c2_xfer: i2c2-xfer {
1554 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1555 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1560 i2c3_xfer: i2c3-xfer {
1561 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1562 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1567 i2c4_xfer: i2c4-xfer {
1568 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1569 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1574 i2c5_xfer: i2c5-xfer {
1575 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1576 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1581 i2s_8ch_bus: i2s-8ch-bus {
1582 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1583 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1584 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1585 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1586 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1587 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1588 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1589 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1590 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1595 pwm0_pin: pwm0-pin {
1596 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1599 vop_pwm_pin: vop-pwm {
1600 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1605 pwm1_pin: pwm1-pin {
1606 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1611 pwm3_pin: pwm3-pin {
1612 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1617 sdio0_bus1: sdio0-bus1 {
1618 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1621 sdio0_bus4: sdio0-bus4 {
1622 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1623 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1624 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1625 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1628 sdio0_cmd: sdio0-cmd {
1629 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1632 sdio0_clk: sdio0-clk {
1633 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1636 sdio0_cd: sdio0-cd {
1637 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1640 sdio0_wp: sdio0-wp {
1641 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1644 sdio0_pwr: sdio0-pwr {
1645 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1648 sdio0_bkpwr: sdio0-bkpwr {
1649 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1652 sdio0_int: sdio0-int {
1653 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1658 sdmmc_clk: sdmmc-clk {
1659 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1662 sdmmc_cmd: sdmmc-cmd {
1663 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1666 sdmmc_cd: sdmmc-cd {
1667 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1670 sdmmc_bus1: sdmmc-bus1 {
1671 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1674 sdmmc_bus4: sdmmc-bus4 {
1675 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1676 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1677 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1678 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1683 spi0_clk: spi0-clk {
1684 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1686 spi0_cs0: spi0-cs0 {
1687 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1689 spi0_cs1: spi0-cs1 {
1690 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1693 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1696 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1701 spi1_clk: spi1-clk {
1702 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1704 spi1_cs0: spi1-cs0 {
1705 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1707 spi1_cs1: spi1-cs1 {
1708 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1711 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1714 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1719 spi2_clk: spi2-clk {
1720 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1722 spi2_cs0: spi2-cs0 {
1723 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1726 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1729 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1734 uart0_xfer: uart0-xfer {
1735 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1736 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1739 uart0_cts: uart0-cts {
1740 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1743 uart0_rts: uart0-rts {
1744 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1749 uart1_xfer: uart1-xfer {
1750 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1751 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1754 uart1_cts: uart1-cts {
1755 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1758 uart1_rts: uart1-rts {
1759 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1764 uart2_xfer: uart2-xfer {
1765 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1766 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1768 /* no rts / cts for uart2 */
1772 uart3_xfer: uart3-xfer {
1773 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1774 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1777 uart3_cts: uart3-cts {
1778 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1781 uart3_rts: uart3-rts {
1782 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1787 uart4_xfer: uart4-xfer {
1788 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1789 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1792 uart4_cts: uart4-cts {
1793 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1796 uart4_rts: uart4-rts {
1797 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1802 cif_clkout: cif-clkout {
1803 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1806 isp_dvp_d2d9: isp-dvp-d2d9 {
1808 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1809 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1810 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1811 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1812 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1813 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1814 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1815 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1816 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1817 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1818 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1819 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1822 isp_dvp_d0d1: isp-dvp-d0d1 {
1824 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1825 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1828 isp_dvp_d10d11:isp_d10d11 {
1830 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1831 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1834 isp_dvp_d0d7: isp-dvp-d0d7 {
1836 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1837 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1838 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1839 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1840 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1841 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1842 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1843 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1846 isp_dvp_d4d11: isp-dvp-d4d11 {
1848 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1849 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1850 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1851 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1852 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1853 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1854 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1855 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1858 isp_shutter: isp-shutter {
1860 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1861 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1864 isp_flash_trigger: isp-flash-trigger {
1865 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1868 isp_prelight: isp-prelight {
1869 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1872 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1873 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU