2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3368-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "rockchip,rk3368";
54 interrupt-parent = <&gic>;
77 #address-cells = <0x2>;
113 entry-method = "psci";
115 cpu_sleep: cpu-sleep-0 {
116 compatible = "arm,idle-state";
117 arm,psci-suspend-param = <0x1010000>;
118 entry-latency-us = <0x3fffffff>;
119 exit-latency-us = <0x40000000>;
120 min-residency-us = <0xffffffff>;
126 compatible = "arm,cortex-a53", "arm,armv8";
128 cpu-idle-states = <&cpu_sleep>;
129 enable-method = "psci";
130 clocks = <&cru ARMCLKL>;
131 operating-points-v2 = <&cluster1_opp>;
133 #cooling-cells = <2>; /* min followed by max */
138 compatible = "arm,cortex-a53", "arm,armv8";
140 cpu-idle-states = <&cpu_sleep>;
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 operating-points-v2 = <&cluster1_opp>;
148 compatible = "arm,cortex-a53", "arm,armv8";
150 cpu-idle-states = <&cpu_sleep>;
151 enable-method = "psci";
152 clocks = <&cru ARMCLKL>;
153 operating-points-v2 = <&cluster1_opp>;
158 compatible = "arm,cortex-a53", "arm,armv8";
160 cpu-idle-states = <&cpu_sleep>;
161 enable-method = "psci";
162 clocks = <&cru ARMCLKL>;
163 operating-points-v2 = <&cluster1_opp>;
168 compatible = "arm,cortex-a53", "arm,armv8";
170 cpu-idle-states = <&cpu_sleep>;
171 enable-method = "psci";
172 clocks = <&cru ARMCLKB>;
173 operating-points-v2 = <&cluster0_opp>;
175 #cooling-cells = <2>; /* min followed by max */
180 compatible = "arm,cortex-a53", "arm,armv8";
182 cpu-idle-states = <&cpu_sleep>;
183 enable-method = "psci";
184 clocks = <&cru ARMCLKB>;
185 operating-points-v2 = <&cluster0_opp>;
190 compatible = "arm,cortex-a53", "arm,armv8";
192 cpu-idle-states = <&cpu_sleep>;
193 enable-method = "psci";
194 clocks = <&cru ARMCLKB>;
195 operating-points-v2 = <&cluster0_opp>;
200 compatible = "arm,cortex-a53", "arm,armv8";
202 cpu-idle-states = <&cpu_sleep>;
203 enable-method = "psci";
204 clocks = <&cru ARMCLKB>;
205 operating-points-v2 = <&cluster0_opp>;
209 cluster0_opp: opp_table0 {
210 compatible = "operating-points-v2";
214 opp-hz = /bits/ 64 <408000000>;
215 opp-microvolt = <1200000>;
216 clock-latency-ns = <40000>;
220 opp-hz = /bits/ 64 <600000000>;
221 opp-microvolt = <1200000>;
224 opp-hz = /bits/ 64 <816000000>;
225 opp-microvolt = <1200000>;
228 opp-hz = /bits/ 64 <1008000000>;
229 opp-microvolt = <1200000>;
232 opp-hz = /bits/ 64 <1200000000>;
233 opp-microvolt = <1200000>;
237 cluster1_opp: opp_table1 {
238 compatible = "operating-points-v2";
242 opp-hz = /bits/ 64 <408000000>;
243 opp-microvolt = <1200000>;
244 clock-latency-ns = <40000>;
248 opp-hz = /bits/ 64 <600000000>;
249 opp-microvolt = <1200000>;
252 opp-hz = /bits/ 64 <816000000>;
253 opp-microvolt = <1200000>;
256 opp-hz = /bits/ 64 <1008000000>;
257 opp-microvolt = <1200000>;
264 min-volt = <950000>; /* uV */
265 min-freq = <216000>; /* KHz */
266 leakage-adjust-volt = <
270 nvmem-cells = <&cpu_leakage>;
271 nvmem-cell-names = "cpu_leakage";
275 min-volt = <950000>; /* uV */
276 min-freq = <216000>; /* KHz */
277 leakage-adjust-volt = <
281 nvmem-cells = <&cpu_leakage>;
282 nvmem-cell-names = "cpu_leakage";
287 compatible = "arm,armv8-pmuv3";
288 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
297 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
298 <&cpu_b2>, <&cpu_b3>;
302 compatible = "arm,amba-bus";
303 #address-cells = <2>;
307 dmac_peri: dma-controller@ff250000 {
308 compatible = "arm,pl330", "arm,primecell";
309 reg = <0x0 0xff250000 0x0 0x4000>;
310 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&cru ACLK_DMAC_PERI>;
314 clock-names = "apb_pclk";
315 arm,pl330-broken-no-flushp;
316 peripherals-req-type-burst;
319 dmac_bus: dma-controller@ff600000 {
320 compatible = "arm,pl330", "arm,primecell";
321 reg = <0x0 0xff600000 0x0 0x4000>;
322 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cru ACLK_DMAC_BUS>;
326 clock-names = "apb_pclk";
327 arm,pl330-broken-no-flushp;
328 peripherals-req-type-burst;
333 compatible = "arm,psci-0.2";
338 compatible = "arm,armv8-timer";
339 interrupts = <GIC_PPI 13
340 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
342 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
344 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
346 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
350 compatible = "fixed-clock";
351 clock-frequency = <24000000>;
352 clock-output-names = "xin24m";
356 sdmmc: rksdmmc@ff0c0000 {
357 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
358 reg = <0x0 0xff0c0000 0x0 0x4000>;
359 clock-freq-min-max = <400000 150000000>;
360 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
361 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
362 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
363 fifo-depth = <0x100>;
364 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
368 sdio0: dwmmc@ff0d0000 {
369 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
370 reg = <0x0 0xff0d0000 0x0 0x4000>;
371 clock-freq-min-max = <400000 150000000>;
372 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
373 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
374 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
375 fifo-depth = <0x100>;
376 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
380 emmc: rksdmmc@ff0f0000 {
381 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
382 reg = <0x0 0xff0f0000 0x0 0x4000>;
383 clock-freq-min-max = <400000 150000000>;
384 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
385 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
386 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
387 fifo-depth = <0x100>;
388 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
392 saradc: saradc@ff100000 {
393 compatible = "rockchip,saradc";
394 reg = <0x0 0xff100000 0x0 0x100>;
395 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
396 #io-channel-cells = <1>;
397 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
398 clock-names = "saradc", "apb_pclk";
399 resets = <&cru SRST_SARADC>;
400 reset-names = "saradc-apb";
405 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
406 reg = <0x0 0xff110000 0x0 0x1000>;
407 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
408 clock-names = "spiclk", "apb_pclk";
409 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
412 #address-cells = <1>;
418 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
419 reg = <0x0 0xff120000 0x0 0x1000>;
420 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
421 clock-names = "spiclk", "apb_pclk";
422 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
425 #address-cells = <1>;
431 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
432 reg = <0x0 0xff130000 0x0 0x1000>;
433 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
434 clock-names = "spiclk", "apb_pclk";
435 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
438 #address-cells = <1>;
444 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
445 reg = <0x0 0xff650000 0x0 0x1000>;
446 clocks = <&cru PCLK_I2C0>;
448 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&i2c0_xfer>;
451 #address-cells = <1>;
457 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
458 reg = <0x0 0xff140000 0x0 0x1000>;
459 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
460 #address-cells = <1>;
463 clocks = <&cru PCLK_I2C2>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&i2c2_xfer>;
470 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
471 reg = <0x0 0xff150000 0x0 0x1000>;
472 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
473 #address-cells = <1>;
476 clocks = <&cru PCLK_I2C3>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&i2c3_xfer>;
483 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
484 reg = <0x0 0xff160000 0x0 0x1000>;
485 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
486 #address-cells = <1>;
489 clocks = <&cru PCLK_I2C4>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&i2c4_xfer>;
496 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
497 reg = <0x0 0xff170000 0x0 0x1000>;
498 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
499 #address-cells = <1>;
502 clocks = <&cru PCLK_I2C5>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&i2c5_xfer>;
508 uart0: serial@ff180000 {
509 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
510 reg = <0x0 0xff180000 0x0 0x100>;
511 clock-frequency = <24000000>;
512 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
513 clock-names = "baudclk", "apb_pclk";
514 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
520 uart1: serial@ff190000 {
521 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
522 reg = <0x0 0xff190000 0x0 0x100>;
523 clock-frequency = <24000000>;
524 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
525 clock-names = "baudclk", "apb_pclk";
526 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
532 uart3: serial@ff1b0000 {
533 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
534 reg = <0x0 0xff1b0000 0x0 0x100>;
535 clock-frequency = <24000000>;
536 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
537 clock-names = "baudclk", "apb_pclk";
538 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
544 uart4: serial@ff1c0000 {
545 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
546 reg = <0x0 0xff1c0000 0x0 0x100>;
547 clock-frequency = <24000000>;
548 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
549 clock-names = "baudclk", "apb_pclk";
550 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
558 polling-delay-passive = <100>; /* milliseconds */
559 polling-delay = <5000>; /* milliseconds */
561 thermal-sensors = <&tsadc 0>;
564 cpu_alert0: cpu_alert0 {
565 temperature = <75000>; /* millicelsius */
566 hysteresis = <2000>; /* millicelsius */
569 cpu_alert1: cpu_alert1 {
570 temperature = <80000>; /* millicelsius */
571 hysteresis = <2000>; /* millicelsius */
575 temperature = <95000>; /* millicelsius */
576 hysteresis = <2000>; /* millicelsius */
583 trip = <&cpu_alert0>;
585 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
588 trip = <&cpu_alert1>;
590 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
596 polling-delay-passive = <100>; /* milliseconds */
597 polling-delay = <5000>; /* milliseconds */
599 thermal-sensors = <&tsadc 1>;
602 gpu_alert0: gpu_alert0 {
603 temperature = <80000>; /* millicelsius */
604 hysteresis = <2000>; /* millicelsius */
608 temperature = <115000>; /* millicelsius */
609 hysteresis = <2000>; /* millicelsius */
616 trip = <&gpu_alert0>;
618 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
624 tsadc: tsadc@ff280000 {
625 compatible = "rockchip,rk3368-tsadc";
626 reg = <0x0 0xff280000 0x0 0x100>;
627 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
629 clock-names = "tsadc", "apb_pclk";
630 resets = <&cru SRST_TSADC>;
631 reset-names = "tsadc-apb";
632 pinctrl-names = "init", "default", "sleep";
633 pinctrl-0 = <&otp_gpio>;
634 pinctrl-1 = <&otp_out>;
635 pinctrl-2 = <&otp_gpio>;
636 #thermal-sensor-cells = <1>;
637 rockchip,hw-tshut-temp = <95000>;
641 gmac: ethernet@ff290000 {
642 compatible = "rockchip,rk3368-gmac";
643 reg = <0x0 0xff290000 0x0 0x10000>;
644 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
645 interrupt-names = "macirq";
646 rockchip,grf = <&grf>;
647 clocks = <&cru SCLK_MAC>,
648 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
649 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
650 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
651 clock-names = "stmmaceth",
652 "mac_clk_rx", "mac_clk_tx",
653 "clk_mac_ref", "clk_mac_refout",
654 "aclk_mac", "pclk_mac";
658 nandc0: nandc@ff400000 {
659 compatible = "rockchip,rk-nandc";
660 reg = <0x0 0xff400000 0x0 0x4000>;
661 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
664 clock-names = "clk_nandc", "hclk_nandc";
668 usb_host0_ehci: usb@ff500000 {
669 compatible = "generic-ehci";
670 reg = <0x0 0xff500000 0x0 0x100>;
671 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&cru HCLK_HOST0>;
673 clock-names = "usbhost";
677 usb_otg: usb@ff580000 {
678 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
680 reg = <0x0 0xff580000 0x0 0x40000>;
681 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&cru HCLK_OTG0>;
685 g-np-tx-fifo-size = <16>;
686 g-rx-fifo-size = <275>;
687 g-tx-fifo-size = <256 128 128 64 64 32>;
692 ddrpctl: syscon@ff610000 {
693 compatible = "rockchip,rk3368-ddrpctl", "syscon";
694 reg = <0x0 0xff610000 0x0 0x400>;
698 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
699 reg = <0x0 0xff660000 0x0 0x1000>;
700 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
701 #address-cells = <1>;
704 clocks = <&cru PCLK_I2C1>;
705 pinctrl-names = "default";
706 pinctrl-0 = <&i2c1_xfer>;
711 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
712 reg = <0x0 0xff680000 0x0 0x10>;
714 pinctrl-names = "default";
715 pinctrl-0 = <&pwm0_pin>;
716 clocks = <&cru PCLK_PWM1>;
722 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
723 reg = <0x0 0xff680010 0x0 0x10>;
725 pinctrl-names = "default";
726 pinctrl-0 = <&pwm1_pin>;
727 clocks = <&cru PCLK_PWM1>;
733 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
734 reg = <0x0 0xff680020 0x0 0x10>;
736 clocks = <&cru PCLK_PWM1>;
742 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
743 reg = <0x0 0xff680030 0x0 0x10>;
745 pinctrl-names = "default";
746 pinctrl-0 = <&pwm3_pin>;
747 clocks = <&cru PCLK_PWM1>;
752 uart2: serial@ff690000 {
753 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
754 reg = <0x0 0xff690000 0x0 0x100>;
755 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
756 clock-names = "baudclk", "apb_pclk";
757 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
758 pinctrl-names = "default";
759 pinctrl-0 = <&uart2_xfer>;
765 mbox: mbox@ff6b0000 {
766 compatible = "rockchip,rk3368-mailbox";
767 reg = <0x0 0xff6b0000 0x0 0x1000>;
768 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&cru PCLK_MAILBOX>;
773 clock-names = "pclk_mailbox";
778 mailbox: mailbox@ff6b0000 {
779 compatible = "rockchip,rk3368-mbox-legacy";
780 reg = <0x0 0xff6b0000 0x0 0x1000>,
781 <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
782 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&cru PCLK_MAILBOX>;
787 clock-names = "pclk_mailbox";
792 mailbox_scpi: mailbox-scpi {
793 compatible = "rockchip,rk3368-scpi-legacy";
794 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
799 pmu: power-management@ff730000 {
800 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
801 reg = <0x0 0xff730000 0x0 0x1000>;
803 power: power-controller {
805 compatible = "rockchip,rk3368-power-controller";
806 #power-domain-cells = <1>;
807 #address-cells = <1>;
811 * Note: Although SCLK_* are the working clocks
812 * of device without including on the NOC, needed for
815 * The clocks on the which NOC:
816 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
817 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
818 * ACLK_RGA is on ACLK_RGA_NIU.
819 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
821 * Which clock are device clocks:
823 * *_IEP IEP:Image Enhancement Processor
824 * *_ISP ISP:Image Signal Processing
825 * *_VIP VIP:Video Input Processor
826 * *_VOP* VOP:Visual Output Processor
834 reg = <RK3368_PD_VIO>;
835 clocks = <&cru ACLK_IEP>,
847 <&cru HCLK_VIO_HDCPMMU>,
848 <&cru PCLK_EDP_CTRL>,
849 <&cru PCLK_HDMI_CTRL>,
855 <&cru PCLK_MIPI_CSI>,
856 <&cru PCLK_MIPI_DSI0>,
857 <&cru SCLK_VOP0_PWM>,
863 <&cru SCLK_HDMI_CEC>,
864 <&cru SCLK_HDMI_HDCP>;
867 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
868 * (video endecoder & decoder) clocks that on the
869 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
872 reg = <RK3368_PD_VIDEO>;
873 clocks = <&cru ACLK_VIDEO>,
875 <&cru SCLK_HEVC_CABAC>,
876 <&cru SCLK_HEVC_CORE>;
879 * Note: ACLK_GPU is the GPU clock,
880 * and on the ACLK_GPU_NIU (NOC).
883 reg = <RK3368_PD_GPU_1>;
884 clocks = <&cru ACLK_GPU_CFG>,
886 <&cru SCLK_GPU_CORE>;
891 pmugrf: syscon@ff738000 {
892 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
893 reg = <0x0 0xff738000 0x0 0x1000>;
895 pmu_io_domains: io-domains {
896 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
901 compatible = "syscon-reboot-mode";
903 mode-normal = <BOOT_NORMAL>;
904 mode-recovery = <BOOT_RECOVERY>;
905 mode-bootloader = <BOOT_FASTBOOT>;
906 mode-loader = <BOOT_BL_DOWNLOAD>;
910 cru: clock-controller@ff760000 {
911 compatible = "rockchip,rk3368-cru";
912 reg = <0x0 0xff760000 0x0 0x1000>;
913 rockchip,grf = <&grf>;
917 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
919 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
920 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
921 <&cru PCLK_BUS>, <&cru PCLK_PERI>;
922 assigned-clock-rates =
923 <576000000>, <400000000>,
925 <300000000>, <300000000>,
926 <150000000>, <150000000>,
927 <75000000>, <75000000>;
930 grf: syscon@ff770000 {
931 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
932 reg = <0x0 0xff770000 0x0 0x1000>;
934 io_domains: io-domains {
935 compatible = "rockchip,rk3368-io-voltage-domain";
940 wdt: watchdog@ff800000 {
941 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
942 reg = <0x0 0xff800000 0x0 0x100>;
943 clocks = <&cru PCLK_WDT>;
944 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
949 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
950 reg = <0x0 0xff810000 0x0 0x20>;
951 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
954 i2s_2ch: i2s-2ch@ff890000 {
955 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
956 reg = <0x0 0xff890000 0x0 0x1000>;
957 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
958 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
959 dma-names = "tx", "rx";
960 clock-names = "i2s_clk", "i2s_hclk";
961 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
965 i2s_8ch: i2s-8ch@ff898000 {
966 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
967 reg = <0x0 0xff898000 0x0 0x1000>;
968 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
969 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
970 dma-names = "tx", "rx";
971 clock-names = "i2s_clk", "i2s_hclk";
972 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
973 pinctrl-names = "default";
974 pinctrl-0 = <&i2s_8ch_bus>;
978 gic: interrupt-controller@ffb71000 {
979 compatible = "arm,gic-400";
980 interrupt-controller;
981 #interrupt-cells = <3>;
982 #address-cells = <0>;
984 reg = <0x0 0xffb71000 0x0 0x1000>,
985 <0x0 0xffb72000 0x0 0x2000>,
986 <0x0 0xffb74000 0x0 0x2000>,
987 <0x0 0xffb76000 0x0 0x2000>;
988 interrupts = <GIC_PPI 9
989 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
992 gpu: rogue-g6110@ffa30000 {
993 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
994 reg = <0x0 0xffa30000 0x0 0x10000>;
996 <&cru SCLK_GPU_CORE>,
1003 operating-points = <
1010 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1011 interrupt-names = "rogue-g6110-irq";
1014 efuse: efuse@ffb00000 {
1015 compatible = "rockchip,rk3368-efuse";
1016 reg = <0x0 0xffb00000 0x0 0x20>;
1017 #address-cells = <1>;
1019 clocks = <&cru PCLK_EFUSE256>;
1020 clock-names = "pclk_efuse";
1023 cpu_leakage: cpu-leakage@17 {
1026 temp_adjust: temp-adjust@1f {
1032 compatible = "rockchip,rk3368-pinctrl";
1033 rockchip,grf = <&grf>;
1034 rockchip,pmu = <&pmugrf>;
1035 #address-cells = <0x2>;
1036 #size-cells = <0x2>;
1039 gpio0: gpio0@ff750000 {
1040 compatible = "rockchip,gpio-bank";
1041 reg = <0x0 0xff750000 0x0 0x100>;
1042 clocks = <&cru PCLK_GPIO0>;
1043 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1046 #gpio-cells = <0x2>;
1048 interrupt-controller;
1049 #interrupt-cells = <0x2>;
1052 gpio1: gpio1@ff780000 {
1053 compatible = "rockchip,gpio-bank";
1054 reg = <0x0 0xff780000 0x0 0x100>;
1055 clocks = <&cru PCLK_GPIO1>;
1056 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1059 #gpio-cells = <0x2>;
1061 interrupt-controller;
1062 #interrupt-cells = <0x2>;
1065 gpio2: gpio2@ff790000 {
1066 compatible = "rockchip,gpio-bank";
1067 reg = <0x0 0xff790000 0x0 0x100>;
1068 clocks = <&cru PCLK_GPIO2>;
1069 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1072 #gpio-cells = <0x2>;
1074 interrupt-controller;
1075 #interrupt-cells = <0x2>;
1078 gpio3: gpio3@ff7a0000 {
1079 compatible = "rockchip,gpio-bank";
1080 reg = <0x0 0xff7a0000 0x0 0x100>;
1081 clocks = <&cru PCLK_GPIO3>;
1082 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1085 #gpio-cells = <0x2>;
1087 interrupt-controller;
1088 #interrupt-cells = <0x2>;
1091 pcfg_pull_up: pcfg-pull-up {
1095 pcfg_pull_down: pcfg-pull-down {
1099 pcfg_pull_none: pcfg-pull-none {
1103 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1105 drive-strength = <12>;
1109 emmc_clk: emmc-clk {
1110 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1113 emmc_cmd: emmc-cmd {
1114 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1117 emmc_pwr: emmc-pwr {
1118 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1121 emmc_bus1: emmc-bus1 {
1122 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1125 emmc_bus4: emmc-bus4 {
1126 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1127 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1128 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1129 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1132 emmc_bus8: emmc-bus8 {
1133 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1134 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1135 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1136 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1137 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1138 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1139 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1140 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1145 rgmii_pins: rgmii-pins {
1146 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1147 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1148 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1149 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1150 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1151 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1152 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1153 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1154 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1155 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1156 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1157 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1158 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1159 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1160 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1163 rmii_pins: rmii-pins {
1164 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1165 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1166 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1167 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1168 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1169 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1170 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1171 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1172 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1173 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1178 i2c0_xfer: i2c0-xfer {
1179 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1180 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1185 i2c1_xfer: i2c1-xfer {
1186 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1187 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1192 i2c2_xfer: i2c2-xfer {
1193 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1194 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1199 i2c3_xfer: i2c3-xfer {
1200 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1201 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1206 i2c4_xfer: i2c4-xfer {
1207 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1208 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1213 i2c5_xfer: i2c5-xfer {
1214 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1215 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1220 i2s_8ch_bus: i2s-8ch-bus {
1221 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1222 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1223 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1224 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1225 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1226 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1227 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1228 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1229 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1234 pwm0_pin: pwm0-pin {
1235 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1238 vop_pwm_pin: vop-pwm {
1239 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1244 pwm1_pin: pwm1-pin {
1245 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1250 pwm3_pin: pwm3-pin {
1251 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1256 sdio0_bus1: sdio0-bus1 {
1257 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1260 sdio0_bus4: sdio0-bus4 {
1261 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1262 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1263 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1264 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1267 sdio0_cmd: sdio0-cmd {
1268 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1271 sdio0_clk: sdio0-clk {
1272 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1275 sdio0_cd: sdio0-cd {
1276 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1279 sdio0_wp: sdio0-wp {
1280 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1283 sdio0_pwr: sdio0-pwr {
1284 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1287 sdio0_bkpwr: sdio0-bkpwr {
1288 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1291 sdio0_int: sdio0-int {
1292 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1297 sdmmc_clk: sdmmc-clk {
1298 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1301 sdmmc_cmd: sdmmc-cmd {
1302 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1305 sdmmc_cd: sdmmc-cd {
1306 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1309 sdmmc_bus1: sdmmc-bus1 {
1310 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1313 sdmmc_bus4: sdmmc-bus4 {
1314 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1315 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1316 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1317 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1322 spi0_clk: spi0-clk {
1323 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1325 spi0_cs0: spi0-cs0 {
1326 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1328 spi0_cs1: spi0-cs1 {
1329 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1332 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1335 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1340 spi1_clk: spi1-clk {
1341 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1343 spi1_cs0: spi1-cs0 {
1344 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1346 spi1_cs1: spi1-cs1 {
1347 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1350 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1353 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1358 spi2_clk: spi2-clk {
1359 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1361 spi2_cs0: spi2-cs0 {
1362 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1365 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1368 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1373 otp_gpio: otp-gpio {
1374 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1378 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1383 uart0_xfer: uart0-xfer {
1384 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1385 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1388 uart0_cts: uart0-cts {
1389 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1392 uart0_rts: uart0-rts {
1393 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1398 uart1_xfer: uart1-xfer {
1399 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1400 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1403 uart1_cts: uart1-cts {
1404 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1407 uart1_rts: uart1-rts {
1408 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1413 uart2_xfer: uart2-xfer {
1414 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1415 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1417 /* no rts / cts for uart2 */
1421 uart3_xfer: uart3-xfer {
1422 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1423 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1426 uart3_cts: uart3-cts {
1427 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1430 uart3_rts: uart3-rts {
1431 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1436 uart4_xfer: uart4-xfer {
1437 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1438 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1441 uart4_cts: uart4-cts {
1442 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1445 uart4_rts: uart4-rts {
1446 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;