arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/suspend/rockchip-rk3368.h>
  51 #include <dt-bindings/thermal/thermal.h>
  52 #include <dt-bindings/display/mipi_dsi.h>
  53 #include <dt-bindings/display/drm_mipi_dsi.h>
  54 #include <dt-bindings/display/media-bus-format.h>
  55
  56 / {
  57         compatible = "rockchip,rk3368";
  58         interrupt-parent = <&gic>;
  59         #address-cells = <2>;
  60         #size-cells = <2>;
  61
  62         aliases {
  63                 ethernet0 = &gmac;
  64                 i2c0 = &i2c0;
  65                 i2c1 = &i2c1;
  66                 i2c2 = &i2c2;
  67                 i2c3 = &i2c3;
  68                 i2c4 = &i2c4;
  69                 i2c5 = &i2c5;
  70                 serial0 = &uart0;
  71                 serial1 = &uart1;
  72                 serial2 = &uart2;
  73                 serial3 = &uart3;
  74                 serial4 = &uart4;
  75                 spi0 = &spi0;
  76                 spi1 = &spi1;
  77                 spi2 = &spi2;
  78         };
  79
  80         cpus {
  81                 #address-cells = <0x2>;
  82                 #size-cells = <0x0>;
  83
  84                 cpu-map {
  85                         cluster0 {
  86                                 core0 {
  87                                         cpu = <&cpu_l0>;
  88                                 };
  89                                 core1 {
  90                                         cpu = <&cpu_l1>;
  91                                 };
  92                                 core2 {
  93                                         cpu = <&cpu_l2>;
  94                                 };
  95                                 core3 {
  96                                         cpu = <&cpu_l3>;
  97                                 };
  98                         };
  99
 100                         cluster1 {
 101                                 core0 {
 102                                         cpu = <&cpu_b0>;
 103                                 };
 104                                 core1 {
 105                                         cpu = <&cpu_b1>;
 106                                 };
 107                                 core2 {
 108                                         cpu = <&cpu_b2>;
 109                                 };
 110                                 core3 {
 111                                         cpu = <&cpu_b3>;
 112                                 };
 113                         };
 114                 };
 115
 116                 cpu_l0: cpu@0 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a53", "arm,armv8";
 119                         reg = <0x0 0x0>;
 120                         enable-method = "psci";
 121                         clocks = <&cru ARMCLKL>;
 122                         next-level-cache = <&cluster0_l2>;
 123                         operating-points-v2 = <&cluster0_opp>;
 124                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 125                         #cooling-cells = <2>; /* min followed by max */
 126                         dynamic-power-coefficient = <149>;
 127                 };
 128
 129                 cpu_l1: cpu@1 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a53", "arm,armv8";
 132                         reg = <0x0 0x1>;
 133                         enable-method = "psci";
 134                         clocks = <&cru ARMCLKL>;
 135                         next-level-cache = <&cluster0_l2>;
 136                         operating-points-v2 = <&cluster0_opp>;
 137                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 138                 };
 139
 140                 cpu_l2: cpu@2 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a53", "arm,armv8";
 143                         reg = <0x0 0x2>;
 144                         enable-method = "psci";
 145                         clocks = <&cru ARMCLKL>;
 146                         next-level-cache = <&cluster0_l2>;
 147                         operating-points-v2 = <&cluster0_opp>;
 148                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 149                 };
 150
 151                 cpu_l3: cpu@3 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a53", "arm,armv8";
 154                         reg = <0x0 0x3>;
 155                         enable-method = "psci";
 156                         clocks = <&cru ARMCLKL>;
 157                         next-level-cache = <&cluster0_l2>;
 158                         operating-points-v2 = <&cluster0_opp>;
 159                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 160                 };
 161
 162                 cpu_b0: cpu@100 {
 163                         device_type = "cpu";
 164                         compatible = "arm,cortex-a53", "arm,armv8";
 165                         reg = <0x0 0x100>;
 166                         enable-method = "psci";
 167                         clocks = <&cru ARMCLKB>;
 168                         next-level-cache = <&cluster1_l2>;
 169                         operating-points-v2 = <&cluster1_opp>;
 170                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 171                         #cooling-cells = <2>; /* min followed by max */
 172                         dynamic-power-coefficient = <160>;
 173                 };
 174
 175                 cpu_b1: cpu@101 {
 176                         device_type = "cpu";
 177                         compatible = "arm,cortex-a53", "arm,armv8";
 178                         reg = <0x0 0x101>;
 179                         enable-method = "psci";
 180                         clocks = <&cru ARMCLKB>;
 181                         next-level-cache = <&cluster1_l2>;
 182                         operating-points-v2 = <&cluster1_opp>;
 183                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 184                 };
 185
 186                 cpu_b2: cpu@102 {
 187                         device_type = "cpu";
 188                         compatible = "arm,cortex-a53", "arm,armv8";
 189                         reg = <0x0 0x102>;
 190                         enable-method = "psci";
 191                         clocks = <&cru ARMCLKB>;
 192                         next-level-cache = <&cluster1_l2>;
 193                         operating-points-v2 = <&cluster1_opp>;
 194                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 195                 };
 196
 197                 cpu_b3: cpu@103 {
 198                         device_type = "cpu";
 199                         compatible = "arm,cortex-a53", "arm,armv8";
 200                         reg = <0x0 0x103>;
 201                         enable-method = "psci";
 202                         clocks = <&cru ARMCLKB>;
 203                         next-level-cache = <&cluster1_l2>;
 204                         operating-points-v2 = <&cluster1_opp>;
 205                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 206                 };
 207
 208                 cluster0_l2: l2-cache0 {
 209                         compatible = "cache";
 210                 };
 211
 212                 cluster1_l2: l2-cache1 {
 213                         compatible = "cache";
 214                 };
 215         };
 216
 217         cluster0_opp: opp_table0 {
 218                 compatible = "operating-points-v2";
 219                 opp-shared;
 220                 leakage-voltage-sel = <
 221                         1   24   0
 222                         25  254  1
 223                 >;
 224                 nvmem-cells = <&cpu_leakage>;
 225                 nvmem-cell-names = "cpu_leakage";
 226
 227                 opp-216000000 {
 228                         opp-hz = /bits/ 64 <216000000>;
 229                         opp-microvolt = <950000 950000 1350000>;
 230                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 231                         opp-microvolt-L1 = <950000 950000 1350000>;
 232                         clock-latency-ns = <40000>;
 233                         opp-suspend;
 234                 };
 235                 opp-408000000 {
 236                         opp-hz = /bits/ 64 <408000000>;
 237                         opp-microvolt = <950000 950000 1350000>;
 238                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 239                         opp-microvolt-L1 = <950000 950000 1350000>;
 240                         clock-latency-ns = <40000>;
 241                 };
 242                 opp-600000000 {
 243                         opp-hz = /bits/ 64 <600000000>;
 244                         opp-microvolt = <950000 950000 1350000>;
 245                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 246                         opp-microvolt-L1 = <950000 950000 1350000>;
 247                         clock-latency-ns = <40000>;
 248                 };
 249                 opp-816000000 {
 250                         opp-hz = /bits/ 64 <816000000>;
 251                         opp-microvolt = <1025000 1025000 1350000>;
 252                         opp-microvolt-L0 = <1125000 1125000 1350000>;
 253                         opp-microvolt-L1 = <1025000 1025000 1350000>;
 254                         clock-latency-ns = <40000>;
 255                 };
 256                 opp-1008000000 {
 257                         opp-hz = /bits/ 64 <1008000000>;
 258                         opp-microvolt = <1125000 1125000 1350000>;
 259                         opp-microvolt-L0 = <1225000 1225000 1350000>;
 260                         opp-microvolt-L1 = <1125000 1125000 1350000>;
 261                         clock-latency-ns = <40000>;
 262                 };
 263                 opp-1200000000 {
 264                         opp-hz = /bits/ 64 <1200000000>;
 265                         opp-microvolt = <1225000 1225000 1350000>;
 266                         opp-microvolt-L0 = <1325000 1325000 1350000>;
 267                         opp-microvolt-L1 = <1225000 1225000 1350000>;
 268                         clock-latency-ns = <40000>;
 269                 };
 270         };
 271
 272         cluster1_opp: opp_table1 {
 273                 compatible = "operating-points-v2";
 274                 opp-shared;
 275                 leakage-scaling-sel = <
 276                         1   24   36
 277                         25  254  0
 278                 >;
 279                 clocks = <&cru PLL_APLLB>;
 280                 leakage-voltage-sel = <
 281                         1   24   0
 282                         25  254  1
 283                 >;
 284                 nvmem-cells = <&cpu_leakage>;
 285                 nvmem-cell-names = "cpu_leakage";
 286
 287                 opp-216000000 {
 288                         opp-hz = /bits/ 64 <216000000>;
 289                         opp-microvolt = <950000 950000 1350000>;
 290                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 291                         opp-microvolt-L1 = <950000 950000 1350000>;
 292                         clock-latency-ns = <40000>;
 293                         opp-suspend;
 294                 };
 295                 opp-408000000 {
 296                         opp-hz = /bits/ 64 <408000000>;
 297                         opp-microvolt = <950000 950000 1350000>;
 298                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 299                         opp-microvolt-L1 = <950000 950000 1350000>;
 300                         clock-latency-ns = <40000>;
 301                 };
 302                 opp-600000000 {
 303                         opp-hz = /bits/ 64 <600000000>;
 304                         opp-microvolt = <950000 950000 1350000>;
 305                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 306                         opp-microvolt-L1 = <950000 950000 1350000>;
 307                         clock-latency-ns = <40000>;
 308                 };
 309                 opp-816000000 {
 310                         opp-hz = /bits/ 64 <816000000>;
 311                         opp-microvolt = <975000 975000 1350000>;
 312                         opp-microvolt-L0 = <1075000 1075000 1350000>;
 313                         opp-microvolt-L1 = <975000 975000 1350000>;
 314                         clock-latency-ns = <40000>;
 315                 };
 316                 opp-1008000000 {
 317                         opp-hz = /bits/ 64 <1008000000>;
 318                         opp-microvolt = <1050000 1050000 1350000>;
 319                         opp-microvolt-L0 = <1150000 1150000 1350000>;
 320                         opp-microvolt-L1 = <1050000 1050000 1350000>;
 321                         clock-latency-ns = <40000>;
 322                 };
 323                 opp-1200000000 {
 324                         opp-hz = /bits/ 64 <1200000000>;
 325                         opp-microvolt = <1150000 1150000 1350000>;
 326                         opp-microvolt-L0 = <1250000 1250000 1350000>;
 327                         opp-microvolt-L1 = <1150000 1150000 1350000>;
 328                         clock-latency-ns = <40000>;
 329                 };
 330                 opp-1296000000 {
 331                         opp-hz = /bits/ 64 <1296000000>;
 332                         opp-microvolt = <1225000 1225000 1350000>;
 333                         opp-microvolt-L0 = <1350000 1350000 1350000>;
 334                         opp-microvolt-L1 = <1225000 1225000 1350000>;
 335                         clock-latency-ns = <40000>;
 336                 };
 337                 opp-1416000000 {
 338                         opp-hz = /bits/ 64 <1416000000>;
 339                         opp-microvolt = <1300000 1300000 1350000>;
 340                         opp-microvolt-L0 = <1350000 1350000 1350000>;
 341                         opp-microvolt-L1 = <1300000 1300000 1350000>;
 342                         clock-latency-ns = <40000>;
 343                 };
 344                 opp-1512000000 {
 345                         opp-hz = /bits/ 64 <1512000000>;
 346                         opp-microvolt = <1350000 1350000 1350000>;
 347                         opp-microvolt-L0 = <1350000 1350000 1350000>;
 348                         opp-microvolt-L1 = <1350000 1350000 1350000>;
 349                         clock-latency-ns = <40000>;
 350                 };
 351         };
 352
 353         energy-costs {
 354                 RK3368_CPU_COST_0: rk3368-core-cost0 {
 355                         busy-cost-data = <
 356                                 146    44       /*  216M */
 357                                 276    72       /*  408M */
 358                                 406    99       /*  600M */
 359                                 552    147      /*  816M */
 360                                 682    200      /* 1008M */
 361                                 812    255      /* 1200M */
 362                         >;
 363                         idle-cost-data = <
 364                                   6
 365                                   6
 366                                   0
 367                         >;
 368                 };
 369
 370                 RK3368_CPU_COST_1: rk3368-core-cost1 {
 371                         busy-cost-data = <
 372                                 146    53       /*  216M */
 373                                 276    86       /*  408M */
 374                                 406    118      /*  600M */
 375                                 552    166      /*  816M */
 376                                 682    226      /* 1008M */
 377                                 812    309      /* 1200M */
 378                                 878    371      /* 1200M */
 379                                 959    446      /* 1416M */
 380                                 1024   513      /* 1512M */
 381                         >;
 382                         idle-cost-data = <
 383                                    6
 384                                    6
 385                                    0
 386                         >;
 387                 };
 388
 389                 RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 {
 390                         busy-cost-data = <
 391                                 146    9        /*  216M */
 392                                 276    14       /*  408M */
 393                                 406    20       /*  600M */
 394                                 552    29       /*  816M */
 395                                 682    40       /* 1008M */
 396                                 812    51       /* 1200M */
 397                         >;
 398                         idle-cost-data = <
 399                                 56
 400                                 56
 401                                 56
 402                         >;
 403                 };
 404
 405                 RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 {
 406                         busy-cost-data = <
 407                                 146    11       /*  216M */
 408                                 276    17       /*  408M */
 409                                 406    24       /*  600M */
 410                                 552    33       /*  816M */
 411                                 682    45       /* 1008M */
 412                                 812    62       /* 1200M */
 413                                 878    74       /* 1200M */
 414                                 959    89       /* 1416M */
 415                                 1024   103      /* 1512M */
 416                         >;
 417                         idle-cost-data = <
 418                                 56
 419                                 56
 420                                 56
 421                         >;
 422                 };
 423         };
 424
 425         arm-pmu {
 426                 compatible = "arm,armv8-pmuv3";
 427                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 428                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 429                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 430                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 431                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 432                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 433                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 434                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 435                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 436                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 437                                      <&cpu_b2>, <&cpu_b3>;
 438         };
 439
 440         amba {
 441                 compatible = "arm,amba-bus";
 442                 #address-cells = <2>;
 443                 #size-cells = <2>;
 444                 ranges;
 445
 446                 dmac_peri: dma-controller@ff250000 {
 447                         compatible = "arm,pl330", "arm,primecell";
 448                         reg = <0x0 0xff250000 0x0 0x4000>;
 449                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 450                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 451                         #dma-cells = <1>;
 452                         clocks = <&cru ACLK_DMAC_PERI>;
 453                         clock-names = "apb_pclk";
 454                         arm,pl330-broken-no-flushp;
 455                         peripherals-req-type-burst;
 456                 };
 457
 458                 dmac_bus: dma-controller@ff600000 {
 459                         compatible = "arm,pl330", "arm,primecell";
 460                         reg = <0x0 0xff600000 0x0 0x4000>;
 461                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 462                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 463                         #dma-cells = <1>;
 464                         clocks = <&cru ACLK_DMAC_BUS>;
 465                         clock-names = "apb_pclk";
 466                         arm,pl330-broken-no-flushp;
 467                         peripherals-req-type-burst;
 468                 };
 469         };
 470
 471         psci {
 472                 compatible = "arm,psci-0.2";
 473                 method = "smc";
 474         };
 475
 476         timer {
 477                 compatible = "arm,armv8-timer";
 478                 interrupts = <GIC_PPI 13
 479                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 480                              <GIC_PPI 14
 481                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 482                              <GIC_PPI 11
 483                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 484                              <GIC_PPI 10
 485                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 486         };
 487
 488         xin24m: oscillator {
 489                 compatible = "fixed-clock";
 490                 clock-frequency = <24000000>;
 491                 clock-output-names = "xin24m";
 492                 #clock-cells = <0>;
 493         };
 494
 495         sdmmc: dwmmc@ff0c0000 {
 496                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 497                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 498                 clock-freq-min-max = <400000 150000000>;
 499                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 500                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 501                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 502                 fifo-depth = <0x100>;
 503                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 504                 status = "disabled";
 505         };
 506
 507         sdio0: dwmmc@ff0d0000 {
 508                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 509                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 510                 clock-freq-min-max = <400000 150000000>;
 511                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 512                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 513                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 514                 fifo-depth = <0x100>;
 515                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 516                 status = "disabled";
 517         };
 518
 519         emmc: dwmmc@ff0f0000 {
 520                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 521                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 522                 clock-freq-min-max = <400000 150000000>;
 523                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 524                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 525                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 526                 fifo-depth = <0x100>;
 527                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 528                 status = "disabled";
 529         };
 530
 531         saradc: saradc@ff100000 {
 532                 compatible = "rockchip,saradc";
 533                 reg = <0x0 0xff100000 0x0 0x100>;
 534                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 535                 #io-channel-cells = <1>;
 536                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 537                 clock-names = "saradc", "apb_pclk";
 538                 resets = <&cru SRST_SARADC>;
 539                 reset-names = "saradc-apb";
 540                 status = "disabled";
 541         };
 542
 543         spi0: spi@ff110000 {
 544                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 545                 reg = <0x0 0xff110000 0x0 0x1000>;
 546                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 547                 clock-names = "spiclk", "apb_pclk";
 548                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 549                 pinctrl-names = "default";
 550                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 551                 #address-cells = <1>;
 552                 #size-cells = <0>;
 553                 status = "disabled";
 554         };
 555
 556         spi1: spi@ff120000 {
 557                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 558                 reg = <0x0 0xff120000 0x0 0x1000>;
 559                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 560                 clock-names = "spiclk", "apb_pclk";
 561                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 562                 pinctrl-names = "default";
 563                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 564                 #address-cells = <1>;
 565                 #size-cells = <0>;
 566                 status = "disabled";
 567         };
 568
 569         spi2: spi@ff130000 {
 570                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 571                 reg = <0x0 0xff130000 0x0 0x1000>;
 572                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 573                 clock-names = "spiclk", "apb_pclk";
 574                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 575                 pinctrl-names = "default";
 576                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 577                 #address-cells = <1>;
 578                 #size-cells = <0>;
 579                 status = "disabled";
 580         };
 581
 582         i2c0: i2c@ff650000 {
 583                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 584                 reg = <0x0 0xff650000 0x0 0x1000>;
 585                 clocks = <&cru PCLK_I2C0>;
 586                 clock-names = "i2c";
 587                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 588                 pinctrl-names = "default";
 589                 pinctrl-0 = <&i2c0_xfer>;
 590                 #address-cells = <1>;
 591                 #size-cells = <0>;
 592                 status = "disabled";
 593         };
 594
 595         i2c2: i2c@ff140000 {
 596                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 597                 reg = <0x0 0xff140000 0x0 0x1000>;
 598                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 599                 #address-cells = <1>;
 600                 #size-cells = <0>;
 601                 clock-names = "i2c";
 602                 clocks = <&cru PCLK_I2C2>;
 603                 pinctrl-names = "default";
 604                 pinctrl-0 = <&i2c2_xfer>;
 605                 status = "disabled";
 606         };
 607
 608         i2c3: i2c@ff150000 {
 609                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 610                 reg = <0x0 0xff150000 0x0 0x1000>;
 611                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 612                 #address-cells = <1>;
 613                 #size-cells = <0>;
 614                 clock-names = "i2c";
 615                 clocks = <&cru PCLK_I2C3>;
 616                 pinctrl-names = "default";
 617                 pinctrl-0 = <&i2c3_xfer>;
 618                 status = "disabled";
 619         };
 620
 621         i2c4: i2c@ff160000 {
 622                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 623                 reg = <0x0 0xff160000 0x0 0x1000>;
 624                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 625                 #address-cells = <1>;
 626                 #size-cells = <0>;
 627                 clock-names = "i2c";
 628                 clocks = <&cru PCLK_I2C4>;
 629                 pinctrl-names = "default";
 630                 pinctrl-0 = <&i2c4_xfer>;
 631                 status = "disabled";
 632         };
 633
 634         i2c5: i2c@ff170000 {
 635                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 636                 reg = <0x0 0xff170000 0x0 0x1000>;
 637                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 638                 #address-cells = <1>;
 639                 #size-cells = <0>;
 640                 clock-names = "i2c";
 641                 clocks = <&cru PCLK_I2C5>;
 642                 pinctrl-names = "default";
 643                 pinctrl-0 = <&i2c5_xfer>;
 644                 status = "disabled";
 645         };
 646
 647         uart0: serial@ff180000 {
 648                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 649                 reg = <0x0 0xff180000 0x0 0x100>;
 650                 clock-frequency = <24000000>;
 651                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 652                 clock-names = "baudclk", "apb_pclk";
 653                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 654                 reg-shift = <2>;
 655                 reg-io-width = <4>;
 656                 status = "disabled";
 657         };
 658
 659         uart1: serial@ff190000 {
 660                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 661                 reg = <0x0 0xff190000 0x0 0x100>;
 662                 clock-frequency = <24000000>;
 663                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 664                 clock-names = "baudclk", "apb_pclk";
 665                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 666                 reg-shift = <2>;
 667                 reg-io-width = <4>;
 668                 status = "disabled";
 669         };
 670
 671         uart3: serial@ff1b0000 {
 672                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 673                 reg = <0x0 0xff1b0000 0x0 0x100>;
 674                 clock-frequency = <24000000>;
 675                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 676                 clock-names = "baudclk", "apb_pclk";
 677                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 678                 reg-shift = <2>;
 679                 reg-io-width = <4>;
 680                 status = "disabled";
 681         };
 682
 683         uart4: serial@ff1c0000 {
 684                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 685                 reg = <0x0 0xff1c0000 0x0 0x100>;
 686                 clock-frequency = <24000000>;
 687                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 688                 clock-names = "baudclk", "apb_pclk";
 689                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 690                 reg-shift = <2>;
 691                 reg-io-width = <4>;
 692                 status = "disabled";
 693         };
 694
 695         thermal_zones: thermal-zones {
 696                 soc_thermal: soc-thermal {
 697                         polling-delay-passive = <200>; /* milliseconds */
 698                         polling-delay = <200>; /* milliseconds */
 699                         sustainable-power = <600>; /* milliwatts */
 700
 701                         thermal-sensors = <&tsadc 0>;
 702                         trips {
 703                                 threshold: trip-point@0 {
 704                                         temperature = <70000>; /* millicelsius */
 705                                         hysteresis = <2000>; /* millicelsius */
 706                                         type = "passive";
 707                                 };
 708                                 target: trip-point@1 {
 709                                         temperature = <80000>; /* millicelsius */
 710                                         hysteresis = <2000>; /* millicelsius */
 711                                         type = "passive";
 712                                 };
 713                                 soc_crit: soc-crit {
 714                                         temperature = <95000>; /* millicelsius */
 715                                         hysteresis = <2000>; /* millicelsius */
 716                                         type = "critical";
 717                                 };
 718                         };
 719
 720                         cooling-maps {
 721                                 map0 {
 722                                         trip = <&target>;
 723                                         cooling-device =
 724                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 725                                         contribution = <1024>;
 726                                 };
 727                                 map1 {
 728                                         trip = <&target>;
 729                                         cooling-device =
 730                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 731                                         contribution = <1024>;
 732                                 };
 733                                 map2 {
 734                                         trip = <&target>;
 735                                         cooling-device =
 736                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 737                                         contribution = <1024>;
 738                                 };
 739                         };
 740                 };
 741
 742                 gpu_thermal: gpu-thermal {
 743                         polling-delay-passive = <200>; /* milliseconds */
 744                         polling-delay = <200>; /* milliseconds */
 745                         thermal-sensors = <&tsadc 1>;
 746                 };
 747         };
 748
 749         tsadc: tsadc@ff280000 {
 750                 compatible = "rockchip,rk3368-tsadc-legacy";
 751                 reg = <0x0 0xff280000 0x0 0x100>;
 752                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 753                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 754                 clock-names = "tsadc", "apb_pclk";
 755                 clock-frequency = <32768>;
 756                 resets = <&cru SRST_TSADC>;
 757                 reset-names = "tsadc-apb";
 758                 nvmem-cells = <&temp_adjust>;
 759                 nvmem-cell-names = "temp_adjust";
 760                 #thermal-sensor-cells = <1>;
 761                 hw-shut-temp = <95000>;
 762                 latency-bound = <50000>;
 763                 status = "disabled";
 764         };
 765
 766         gmac: ethernet@ff290000 {
 767                 compatible = "rockchip,rk3368-gmac";
 768                 reg = <0x0 0xff290000 0x0 0x10000>;
 769                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 770                 interrupt-names = "macirq";
 771                 rockchip,grf = <&grf>;
 772                 clocks = <&cru SCLK_MAC>,
 773                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 774                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 775                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 776                 clock-names = "stmmaceth",
 777                         "mac_clk_rx", "mac_clk_tx",
 778                         "clk_mac_ref", "clk_mac_refout",
 779                         "aclk_mac", "pclk_mac";
 780                 status = "disabled";
 781         };
 782
 783         nandc0: nandc@ff400000 {
 784                 compatible = "rockchip,rk-nandc";
 785                 reg = <0x0 0xff400000 0x0 0x4000>;
 786                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 787                 nandc_id = <0>;
 788                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 789                 clock-names = "clk_nandc", "hclk_nandc";
 790                 status = "disabled";
 791         };
 792
 793         usb_host0_ehci: usb@ff500000 {
 794                 compatible = "generic-ehci";
 795                 reg = <0x0 0xff500000 0x0 0x20000>;
 796                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 797                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 798                 clock-names = "usbhost", "utmi";
 799                 phys = <&u2phy_host>;
 800                 phy-names = "usb";
 801                 status = "disabled";
 802         };
 803
 804         usb_host0_ohci: usb@ff520000 {
 805                 compatible = "generic-ohci";
 806                 reg = <0x0 0xff520000 0x0 0x20000>;
 807                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 808                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 809                 clock-names = "usbhost", "utmi";
 810                 phys = <&u2phy_host>;
 811                 phy-names = "usb";
 812                 status = "disabled";
 813         };
 814
 815         usb_otg: usb@ff580000 {
 816                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 817                                 "snps,dwc2";
 818                 reg = <0x0 0xff580000 0x0 0x40000>;
 819                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 820                 clocks = <&cru HCLK_OTG0>;
 821                 clock-names = "otg";
 822                 dr_mode = "otg";
 823                 g-np-tx-fifo-size = <16>;
 824                 g-rx-fifo-size = <275>;
 825                 g-tx-fifo-size = <256 128 128 64 64 32>;
 826                 g-use-dma;
 827                 status = "disabled";
 828         };
 829
 830         ddrpctl: syscon@ff610000 {
 831                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 832                 reg = <0x0 0xff610000 0x0 0x400>;
 833         };
 834
 835         i2c1: i2c@ff660000 {
 836                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 837                 reg = <0x0 0xff660000 0x0 0x1000>;
 838                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 839                 #address-cells = <1>;
 840                 #size-cells = <0>;
 841                 clock-names = "i2c";
 842                 clocks = <&cru PCLK_I2C1>;
 843                 pinctrl-names = "default";
 844                 pinctrl-0 = <&i2c1_xfer>;
 845                 status = "disabled";
 846         };
 847
 848         pwm0: pwm@ff680000 {
 849                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 850                 reg = <0x0 0xff680000 0x0 0x10>;
 851                 #pwm-cells = <3>;
 852                 pinctrl-names = "default";
 853                 pinctrl-0 = <&pwm0_pin>;
 854                 clocks = <&cru PCLK_PWM1>;
 855                 clock-names = "pwm";
 856                 status = "disabled";
 857         };
 858
 859         pwm1: pwm@ff680010 {
 860                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 861                 reg = <0x0 0xff680010 0x0 0x10>;
 862                 #pwm-cells = <3>;
 863                 pinctrl-names = "default";
 864                 pinctrl-0 = <&pwm1_pin>;
 865                 clocks = <&cru PCLK_PWM1>;
 866                 clock-names = "pwm";
 867                 status = "disabled";
 868         };
 869
 870         pwm2: pwm@ff680020 {
 871                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 872                 reg = <0x0 0xff680020 0x0 0x10>;
 873                 #pwm-cells = <3>;
 874                 clocks = <&cru PCLK_PWM1>;
 875                 clock-names = "pwm";
 876                 status = "disabled";
 877         };
 878
 879         pwm3: pwm@ff680030 {
 880                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 881                 reg = <0x0 0xff680030 0x0 0x10>;
 882                 #pwm-cells = <3>;
 883                 pinctrl-names = "default";
 884                 pinctrl-0 = <&pwm3_pin>;
 885                 clocks = <&cru PCLK_PWM1>;
 886                 clock-names = "pwm";
 887                 status = "disabled";
 888         };
 889
 890         uart2: serial@ff690000 {
 891                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 892                 reg = <0x0 0xff690000 0x0 0x100>;
 893                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 894                 clock-names = "baudclk", "apb_pclk";
 895                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 896                 pinctrl-names = "default";
 897                 pinctrl-0 = <&uart2_xfer>;
 898                 reg-shift = <2>;
 899                 reg-io-width = <4>;
 900                 status = "disabled";
 901         };
 902
 903         mbox: mbox@ff6b0000 {
 904                 compatible = "rockchip,rk3368-mailbox";
 905                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 906                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 907                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 908                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 909                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 910                 clocks = <&cru PCLK_MAILBOX>;
 911                 clock-names = "pclk_mailbox";
 912                 #mbox-cells = <1>;
 913                 status = "disabled";
 914         };
 915
 916         mailbox: mailbox@ff6b0000 {
 917                 compatible = "rockchip,rk3368-mbox-legacy";
 918                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 919                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 920                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 921                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 922                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 923                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 924                 clocks = <&cru PCLK_MAILBOX>;
 925                 clock-names = "pclk_mailbox";
 926                 #mbox-cells = <1>;
 927                 status = "disabled";
 928         };
 929
 930         mailbox_scpi: mailbox-scpi {
 931                 compatible = "rockchip,rk3368-scpi-legacy";
 932                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 933                 chan-nums = <3>;
 934                 status = "disabled";
 935         };
 936
 937         qos_iep: qos@ffad0000 {
 938                 compatible = "syscon";
 939                 reg = <0x0 0xffad0000 0x0 0x20>;
 940         };
 941
 942         qos_isp_r0: qos@ffad0080 {
 943                 compatible = "syscon";
 944                 reg = <0x0 0xffad0080 0x0 0x20>;
 945         };
 946
 947         qos_isp_r1: qos@ffad0100 {
 948                 compatible = "syscon";
 949                 reg = <0x0 0xffad0100 0x0 0x20>;
 950         };
 951
 952         qos_isp_w0: qos@ffad0180 {
 953                 compatible = "syscon";
 954                 reg = <0x0 0xffad0180 0x0 0x20>;
 955         };
 956
 957         qos_isp_w1: qos@ffad0200 {
 958                 compatible = "syscon";
 959                 reg = <0x0 0xffad0200 0x0 0x20>;
 960         };
 961
 962         qos_vip: qos@ffad0280 {
 963                 compatible = "syscon";
 964                 reg = <0x0 0xffad0280 0x0 0x20>;
 965         };
 966
 967         qos_vop: qos@ffad0300 {
 968                 compatible = "syscon";
 969                 reg = <0x0 0xffad0300 0x0 0x20>;
 970         };
 971
 972         qos_rga_r: qos@ffad0380 {
 973                 compatible = "syscon";
 974                 reg = <0x0 0xffad0380 0x0 0x20>;
 975         };
 976
 977         qos_rga_w: qos@ffad0400 {
 978                 compatible = "syscon";
 979                 reg = <0x0 0xffad0400 0x0 0x20>;
 980         };
 981
 982         qos_hevc_r: qos@ffae0000 {
 983                 compatible = "syscon";
 984                 reg = <0x0 0xffae0000 0x0 0x20>;
 985         };
 986
 987         qos_vpu_r: qos@ffae0100 {
 988                 compatible = "syscon";
 989                 reg = <0x0 0xffae0100 0x0 0x20>;
 990         };
 991
 992         qos_vpu_w: qos@ffae0180 {
 993                 compatible = "syscon";
 994                 reg = <0x0 0xffae0180 0x0 0x20>;
 995         };
 996
 997         qos_gpu: qos@ffaf0000 {
 998                 compatible = "syscon";
 999                 reg = <0x0 0xffaf0000 0x0 0x20>;
1000         };
1001
1002         pmu: power-management@ff730000 {
1003                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
1004                 reg = <0x0 0xff730000 0x0 0x1000>;
1005
1006                 power: power-controller {
1007                         compatible = "rockchip,rk3368-power-controller";
1008                         #power-domain-cells = <1>;
1009                         #address-cells = <1>;
1010                         #size-cells = <0>;
1011
1012                         /*
1013                          * Note: Although SCLK_* are the working clocks
1014                          * of device without including on the NOC, needed for
1015                          * synchronous reset.
1016                          *
1017                          * The clocks on the which NOC:
1018                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
1019                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
1020                          * ACLK_RGA is on ACLK_RGA_NIU.
1021                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
1022                          *
1023                          * Which clock are device clocks:
1024                          *      clocks          devices
1025                          *      *_IEP           IEP:Image Enhancement Processor
1026                          *      *_ISP           ISP:Image Signal Processing
1027                          *      *_VIP           VIP:Video Input Processor
1028                          *      *_VOP*          VOP:Visual Output Processor
1029                          *      *_RGA           RGA
1030                          *      *_EDP*          EDP
1031                          *      *_DPHY*         LVDS
1032                          *      *_HDMI          HDMI
1033                          *      *_MIPI_*        MIPI
1034                          */
1035                         pd_vio {
1036                                 reg = <RK3368_PD_VIO>;
1037                                 clocks = <&cru ACLK_IEP>,
1038                                          <&cru ACLK_ISP>,
1039                                          <&cru ACLK_VIP>,
1040                                          <&cru ACLK_RGA>,
1041                                          <&cru ACLK_VOP>,
1042                                          <&cru ACLK_VOP_IEP>,
1043                                          <&cru DCLK_VOP>,
1044                                          <&cru HCLK_IEP>,
1045                                          <&cru HCLK_ISP>,
1046                                          <&cru HCLK_RGA>,
1047                                          <&cru HCLK_VIP>,
1048                                          <&cru HCLK_VOP>,
1049                                          <&cru HCLK_VIO_HDCPMMU>,
1050                                          <&cru PCLK_EDP_CTRL>,
1051                                          <&cru PCLK_HDMI_CTRL>,
1052                                          <&cru PCLK_HDCP>,
1053                                          <&cru PCLK_ISP>,
1054                                          <&cru PCLK_VIP>,
1055                                          <&cru PCLK_DPHYRX>,
1056                                          <&cru PCLK_DPHYTX0>,
1057                                          <&cru PCLK_MIPI_CSI>,
1058                                          <&cru PCLK_MIPI_DSI0>,
1059                                          <&cru SCLK_VOP0_PWM>,
1060                                          <&cru SCLK_EDP_24M>,
1061                                          <&cru SCLK_EDP>,
1062                                          <&cru SCLK_HDCP>,
1063                                          <&cru SCLK_ISP>,
1064                                          <&cru SCLK_RGA>,
1065                                          <&cru SCLK_HDMI_CEC>,
1066                                          <&cru SCLK_HDMI_HDCP>;
1067                                 pm_qos = <&qos_iep>,
1068                                          <&qos_isp_r0>,
1069                                          <&qos_isp_r1>,
1070                                          <&qos_isp_w0>,
1071                                          <&qos_isp_w1>,
1072                                          <&qos_vip>,
1073                                          <&qos_vop>,
1074                                          <&qos_rga_r>,
1075                                          <&qos_rga_w>;
1076                         };
1077                         /*
1078                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
1079                          * (video endecoder & decoder) clocks that on the
1080                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
1081                          */
1082                         pd_video {
1083                                 reg = <RK3368_PD_VIDEO>;
1084                                 clocks = <&cru ACLK_VIDEO>,
1085                                          <&cru HCLK_VIDEO>,
1086                                          <&cru SCLK_HEVC_CABAC>,
1087                                          <&cru SCLK_HEVC_CORE>;
1088                                 pm_qos = <&qos_hevc_r>,
1089                                          <&qos_vpu_r>,
1090                                          <&qos_vpu_w>;
1091                         };
1092                         /*
1093                          * Note: ACLK_GPU is the GPU clock,
1094                          * and on the ACLK_GPU_NIU (NOC).
1095                          */
1096                         pd_gpu_1 {
1097                                 reg = <RK3368_PD_GPU_1>;
1098                                 clocks = <&cru ACLK_GPU_CFG>,
1099                                          <&cru ACLK_GPU_MEM>,
1100                                          <&cru SCLK_GPU_CORE>;
1101                                 pm_qos = <&qos_gpu>;
1102                         };
1103                 };
1104         };
1105
1106         pmugrf: syscon@ff738000 {
1107                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1108                 reg = <0x0 0xff738000 0x0 0x1000>;
1109
1110                 pmu_io_domains: io-domains {
1111                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1112                         status = "disabled";
1113                 };
1114
1115                 reboot-mode {
1116                         compatible = "syscon-reboot-mode";
1117                         offset = <0x200>;
1118                         mode-normal = <BOOT_NORMAL>;
1119                         mode-recovery = <BOOT_RECOVERY>;
1120                         mode-bootloader = <BOOT_FASTBOOT>;
1121                         mode-loader = <BOOT_BL_DOWNLOAD>;
1122                 };
1123         };
1124
1125         cru: clock-controller@ff760000 {
1126                 compatible = "rockchip,rk3368-cru";
1127                 reg = <0x0 0xff760000 0x0 0x1000>;
1128                 rockchip,grf = <&grf>;
1129                 #clock-cells = <1>;
1130                 #reset-cells = <1>;
1131                 assigned-clocks =
1132                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1133                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1134                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1135                         <&cru PCLK_BUS>, <&cru PCLK_PERI>,
1136                         <&cru ACLK_CCI_PRE>;
1137                 assigned-clock-rates =
1138                         <576000000>, <400000000>,
1139                         <300000000>, <300000000>,
1140                         <150000000>, <150000000>,
1141                         <75000000>, <75000000>,
1142                         <576000000>;
1143         };
1144
1145         grf: syscon@ff770000 {
1146                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1147                 reg = <0x0 0xff770000 0x0 0x1000>;
1148                 #address-cells = <1>;
1149                 #size-cells = <1>;
1150
1151                 edp_phy: edp-phy {
1152                         compatible = "rockchip,rk3368-dp-phy";
1153                         clocks = <&cru SCLK_EDP_24M>;
1154                         clock-names = "24m";
1155                         resets = <&cru SRST_EDP_24M>;
1156                         reset-names = "edp_24m";
1157                         #phy-cells = <0>;
1158                         status = "disabled";
1159                 };
1160
1161                 io_domains: io-domains {
1162                         compatible = "rockchip,rk3368-io-voltage-domain";
1163                         status = "disabled";
1164                 };
1165
1166                 u2phy: usb2-phy@700 {
1167                         compatible = "rockchip,rk3368-usb2phy";
1168                         reg = <0x700 0x2c>;
1169                         clocks = <&cru SCLK_OTGPHY0>;
1170                         clock-names = "phyclk";
1171                         #clock-cells = <0>;
1172                         clock-output-names = "usbotg_out";
1173                         assigned-clocks = <&cru SCLK_USBPHY480M>;
1174                         assigned-clock-parents = <&u2phy>;
1175                         status = "disabled";
1176
1177                         u2phy_host: host-port {
1178                                 #phy-cells = <0>;
1179                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1180                                 interrupt-names = "linestate";
1181                                 status = "disabled";
1182                         };
1183                 };
1184         };
1185
1186         wdt: watchdog@ff800000 {
1187                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1188                 reg = <0x0 0xff800000 0x0 0x100>;
1189                 clocks = <&cru PCLK_WDT>;
1190                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1191                 status = "disabled";
1192         };
1193
1194         timer@ff810000 {
1195                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1196                 reg = <0x0 0xff810000 0x0 0x20>;
1197                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1198         };
1199
1200         i2s_2ch: i2s-2ch@ff890000 {
1201                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1202                 reg = <0x0 0xff890000 0x0 0x1000>;
1203                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1204                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1205                 dma-names = "tx", "rx";
1206                 clock-names = "i2s_clk", "i2s_hclk";
1207                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1208                 status = "disabled";
1209         };
1210
1211         i2s_8ch: i2s-8ch@ff898000 {
1212                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1213                 reg = <0x0 0xff898000 0x0 0x1000>;
1214                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1215                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1216                 dma-names = "tx", "rx";
1217                 clock-names = "i2s_clk", "i2s_hclk";
1218                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1219                 pinctrl-names = "default";
1220                 pinctrl-0 = <&i2s_8ch_bus>;
1221                 status = "disabled";
1222         };
1223
1224         iep: iep@ff900000 {
1225                 compatible = "rockchip,iep";
1226                 iommu_enabled = <1>;
1227                 iommus = <&iep_mmu>;
1228                 reg = <0x0 0xff900000 0x0 0x800>;
1229                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1230                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1231                 clock-names = "aclk_iep", "hclk_iep";
1232                 power-domains = <&power RK3368_PD_VIO>;
1233                 allocator = <1>;
1234                 version = <2>;
1235                 status = "disabled";
1236         };
1237
1238         iep_mmu: iommu@ff900800 {
1239                 compatible = "rockchip,iommu";
1240                 reg = <0x0 0xff900800 0x0 0x100>;
1241                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1242                 interrupt-names = "iep_mmu";
1243                 power-domains = <&power RK3368_PD_VIO>;
1244                 #iommu-cells = <0>;
1245                 status = "disabled";
1246         };
1247
1248         isp: isp@ff910000 {
1249                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
1250                 reg = <0x0 0xff910000 0x0 0x4000>;
1251                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1252                 power-domains = <&power RK3368_PD_VIO>;
1253                 clocks =
1254                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1255                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
1256                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
1257                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
1258                 clock-names =
1259                         "aclk_isp", "hclk_isp", "clk_isp",
1260                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1261                         "clk_cif_pll", "hclk_mipiphy1",
1262                         "pclk_dphyrx", "clk_vio0_noc";
1263
1264                 pinctrl-names =
1265                         "default", "isp_dvp8bit2", "isp_dvp10bit",
1266                         "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
1267                         "isp_mipi_fl", "isp_mipi_fl_prefl",
1268                         "isp_flash_as_gpio", "isp_flash_as_trigger_out";
1269                 pinctrl-0 = <&cif_clkout>;
1270                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1271                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1272                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1273                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1274                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1275                 pinctrl-6 = <&cif_clkout>;
1276                 pinctrl-7 = <&cif_clkout &isp_prelight>;
1277                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1278                 pinctrl-9 = <&isp_flash_trigger>;
1279                 rockchip,isp,mipiphy = <2>;
1280                 rockchip,isp,cifphy = <1>;
1281                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1282                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1283                 rockchip,grf = <&grf>;
1284                 rockchip,cru = <&cru>;
1285                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
1286                 rockchip,isp,iommu-enable = <1>;
1287                 iommus = <&isp_mmu>;
1288                 status = "disabled";
1289         };
1290
1291         isp_mmu: iommu@ff914000 {
1292                 compatible = "rockchip,iommu";
1293                 reg = <0x0 0xff914000 0x0 0x100>,
1294                       <0x0 0xff915000 0x0 0x100>;
1295                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1296                 interrupt-names = "isp_mmu";
1297                 clocks = <&cru ACLK_RGA>, <&cru HCLK_ISP>;
1298                 clock-names = "aclk", "hclk";
1299                 rk_iommu,disable_reset_quirk;
1300                 #iommu-cells = <0>;
1301                 power-domains = <&power RK3368_PD_VIO>;
1302                 status = "disabled";
1303         };
1304
1305         vop: vop@ff930000 {
1306                 compatible = "rockchip,rk3368-vop";
1307                 reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>;
1308                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1309                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1310                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1311                 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1312                 assigned-clock-rates = <400000000>, <200000000>;
1313                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1314                 reset-names = "axi", "ahb", "dclk";
1315                 power-domains = <&power RK3368_PD_VIO>;
1316                 iommus = <&vop_mmu>;
1317                 status = "disabled";
1318
1319                 vop_out: port {
1320                         #address-cells = <1>;
1321                         #size-cells = <0>;
1322
1323                         vop_out_mipi: endpoint@0 {
1324                                 reg = <0>;
1325                                 remote-endpoint = <&mipi_in_vop>;
1326                         };
1327
1328                         vop_out_edp: endpoint@1 {
1329                                 reg = <1>;
1330                                 remote-endpoint = <&edp_in_vop>;
1331                         };
1332
1333                         vop_out_hdmi: endpoint@2 {
1334                                 reg = <2>;
1335                                 remote-endpoint = <&hdmi_in_vop>;
1336                         };
1337
1338                         vop_out_lvds: endpoint@3 {
1339                                 reg = <3>;
1340                                 remote-endpoint = <&lvds_in_vop>;
1341                         };
1342                 };
1343         };
1344
1345         display_subsystem: display-subsystem {
1346                 compatible = "rockchip,display-subsystem";
1347                 ports = <&vop_out>;
1348                 status = "disabled";
1349         };
1350
1351         vop_mmu: iommu@ff930300 {
1352                 compatible = "rockchip,iommu";
1353                 reg = <0x0 0xff930300 0x0 0x100>;
1354                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1355                 interrupt-names = "vop_mmu";
1356                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1357                 clock-names = "aclk", "hclk";
1358                 power-domains = <&power RK3368_PD_VIO>;
1359                 #iommu-cells = <0>;
1360                 status = "disabled";
1361         };
1362
1363         mipi_dsi_host: mipi-dsi-host@ff960000 {
1364                 compatible = "rockchip,rk3368-mipi-dsi";
1365                 reg = <0x0 0xff960000 0x0 0x4000>;
1366                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1367                 clocks = <&cru PCLK_MIPI_DSI0>;
1368                 clock-names = "pclk";
1369                 resets = <&cru SRST_MIPIDSI0>;
1370                 reset-names = "apb";
1371                 phys = <&mipi_dphy>;
1372                 phy-names = "mipi_dphy";
1373                 rockchip,grf = <&grf>;
1374                 power-domains = <&power RK3368_PD_VIO>;
1375                 #address-cells = <1>;
1376                 #size-cells = <0>;
1377                 status = "disabled";
1378
1379                 ports {
1380                         port {
1381                                 mipi_in_vop: endpoint {
1382                                         remote-endpoint = <&vop_out_mipi>;
1383                                 };
1384                         };
1385                 };
1386         };
1387
1388         mipi_dphy: mipi-dphy@ff968000 {
1389                 compatible = "rockchip,rk3368-mipi-dphy";
1390                 reg = <0x0 0xff968000 0x0 0x4000>;
1391                 #phy-cells = <0>;
1392                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1393                 clock-names = "ref", "pclk";
1394                 resets = <&cru SRST_MIPIDPHYTX>;
1395                 reset-names = "apb";
1396                 status = "disabled";
1397         };
1398
1399         lvds: lvds@ff968000 {
1400                 compatible = "rockchip,rk33xx-lvds";
1401                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1402                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1403                 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1404                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1405                 power-domains = <&power RK3368_PD_VIO>;
1406                 rockchip,grf = <&grf>;
1407                 pinctrl-names = "lcdc", "gpio";
1408                 pinctrl-0 = <&lcdc_lcdc>;
1409                 pinctrl-1 = <&lcdc_gpio>;
1410                 status = "disabled";
1411
1412                 ports {
1413                         #address-cells = <1>;
1414                         #size-cells = <0>;
1415
1416                         lvds_in: port@0 {
1417                                 reg = <0>;
1418                                 lvds_in_vop: endpoint {
1419                                         remote-endpoint = <&vop_out_lvds>;
1420                                 };
1421                         };
1422                 };
1423         };
1424
1425         edp: edp@ff970000 {
1426                 compatible = "rockchip,rk3368-edp";
1427                 reg = <0x0 0xff970000 0x0 0x8000>;
1428                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1429                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1430                 clock-names = "dp", "pclk";
1431                 resets = <&cru SRST_EDP>;
1432                 reset-names = "dp";
1433                 power-domains = <&power RK3368_PD_VIO>;
1434                 rockchip,grf = <&grf>;
1435                 phys = <&edp_phy>;
1436                 phy-names = "dp";
1437                 pinctrl-names = "default";
1438                 pinctrl-0 = <&edp_hpd>;
1439                 status = "disabled";
1440
1441                 ports {
1442                         #address-cells = <1>;
1443                         #size-cells = <0>;
1444
1445                         edp_in: port@0 {
1446                                 reg = <0>;
1447
1448                                 edp_in_vop: endpoint {
1449                                         remote-endpoint = <&vop_out_edp>;
1450                                 };
1451                         };
1452                 };
1453         };
1454
1455         hdmi: hdmi@ff980000 {
1456                 compatible = "rockchip,rk3368-dw-hdmi";
1457                 reg = <0x0 0xff980000 0x0 0x20000>;
1458                 reg-io-width = <4>;
1459                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1460                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1461                 clock-names = "iahb", "isfr", "cec";
1462                 pinctrl-names = "default";
1463                 pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>;
1464                 resets = <&cru SRST_HDMI>;
1465                 reset-names = "hdmi";
1466                 power-domains = <&power RK3368_PD_VIO>;
1467                 rockchip,grf = <&grf>;
1468                 status = "disabled";
1469
1470                 ports {
1471                         port {
1472                                 hdmi_in_vop: endpoint {
1473                                         remote-endpoint = <&vop_out_hdmi>;
1474                                 };
1475                         };
1476                 };
1477         };
1478
1479         hevc_mmu: iommu@ff9a0440 {
1480                 compatible = "rockchip,iommu";
1481                 reg = <0x0 0xff9a0440 0x0 0x40>,
1482                       <0x0 0xff9a0480 0x0 0x40>;
1483                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1484                 interrupt-names = "hevc_mmu";
1485                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1486                 clock-names = "aclk", "hclk";
1487                 power-domains = <&power RK3368_PD_VIDEO>;
1488                 #iommu-cells = <0>;
1489                 status = "disabled";
1490         };
1491
1492         vpu_mmu: iommu@ff9a0800 {
1493                 compatible = "rockchip,iommu";
1494                 reg = <0x0 0xff9a0800 0x0 0x100>;
1495                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1496                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1497                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1498                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1499                 clock-names = "aclk", "hclk";
1500                 power-domains = <&power RK3368_PD_VIDEO>;
1501                 #iommu-cells = <0>;
1502                 status = "disabled";
1503         };
1504
1505         vpu: vpu_service {
1506                 compatible = "rockchip,vpu_sub";
1507                 iommu_enabled = <1>;
1508                 iommus = <&vpu_mmu>;
1509                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1510                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1511                 interrupt-names = "irq_enc","irq_dec";
1512                 dev_mode = <0>;
1513                 name = "vpu_service";
1514                 allocator = <1>;
1515         };
1516
1517         hevc: hevc_service {
1518                 compatible = "rockchip,hevc_sub";
1519                 iommu_enabled = <1>;
1520                 iommus = <&hevc_mmu>;
1521                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1522                 interrupt-names = "irq_dec";
1523                 dev_mode = <1>;
1524                 name = "hevc_service";
1525                 allocator = <1>;
1526         };
1527
1528         vpu_combo: vpu_combo@ff9a0000 {
1529                 compatible = "rockchip,vpu_combo";
1530                 reg = <0x0 0xff9a0000 0x0 0x440>;
1531                 rockchip,grf = <&grf>;
1532                 subcnt = <2>;
1533                 rockchip,sub = <&vpu>, <&hevc>;
1534                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
1535                          <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
1536                 clock-names = "aclk_vcodec", "hclk_vcodec",
1537                               "clk_core", "clk_cabac";
1538                 resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
1539                          <&cru SRST_VIDEO>;
1540                 reset-names = "video_a", "video_h", "video";
1541                 mode_bit = <12>;
1542                 mode_ctrl = <0x418>;
1543                 name = "vpu_combo";
1544                 power-domains = <&power RK3368_PD_VIDEO>;
1545                 status = "disabled";
1546         };
1547
1548         gic: interrupt-controller@ffb71000 {
1549                 compatible = "arm,gic-400";
1550                 interrupt-controller;
1551                 #interrupt-cells = <3>;
1552                 #address-cells = <0>;
1553
1554                 reg = <0x0 0xffb71000 0x0 0x1000>,
1555                       <0x0 0xffb72000 0x0 0x2000>,
1556                       <0x0 0xffb74000 0x0 0x2000>,
1557                       <0x0 0xffb76000 0x0 0x2000>;
1558                 interrupts = <GIC_PPI 9
1559                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1560         };
1561
1562         gpu: rogue-g6110@ffa30000 {
1563                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1564                 reg = <0x0 0xffa30000 0x0 0x10000>;
1565                 clocks =
1566                         <&cru SCLK_GPU_CORE>,
1567                         <&cru ACLK_GPU_MEM>,
1568                         <&cru ACLK_GPU_CFG>;
1569                 clock-names =
1570                         "sclk_gpu_core",
1571                         "aclk_gpu_mem",
1572                         "aclk_gpu_cfg";
1573                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1574                 interrupt-names = "rogue-g6110-irq";
1575                 power-domains = <&power RK3368_PD_GPU_1>;
1576                 operating-points-v2 = <&gpu_opp_table>;
1577                 #cooling-cells = <2>; /* min followed by max */
1578                 gpu_power_model: power_model {
1579                         compatible = "arm,mali-simple-power-model";
1580                         voltage = <900>;
1581                         frequency = <500>;
1582                         static-power = <300>;
1583                         dynamic-power = <396>;
1584                         ts = <32000 4700 (-80) 2>;
1585                         thermal-zone = "gpu-thermal";
1586                 };
1587         };
1588
1589         gpu_opp_table: gpu_opp_table {
1590                 compatible = "operating-points-v2";
1591                 opp-shared;
1592
1593                 opp-200000000 {
1594                         opp-hz = /bits/ 64 <200000000>;
1595                         opp-microvolt = <1100000>;
1596                 };
1597                 opp-288000000 {
1598                         opp-hz = /bits/ 64 <288000000>;
1599                         opp-microvolt = <1100000>;
1600                 };
1601                 opp-400000000 {
1602                         opp-hz = /bits/ 64 <400000000>;
1603                         opp-microvolt = <1100000>;
1604                 };
1605                 opp-576000000 {
1606                         opp-hz = /bits/ 64 <576000000>;
1607                         opp-microvolt = <1200000>;
1608                 };
1609         };
1610
1611         efuse: efuse@ffb00000 {
1612                 compatible = "rockchip,rk3368-efuse";
1613                 reg = <0x0 0xffb00000 0x0 0x20>;
1614                 #address-cells = <1>;
1615                 #size-cells = <1>;
1616                 clocks = <&cru PCLK_EFUSE256>;
1617                 clock-names = "pclk_efuse";
1618
1619                 /* Data cells */
1620                 cpu_leakage: cpu-leakage@17 {
1621                         reg = <0x17 0x1>;
1622                 };
1623                 temp_adjust: temp-adjust@1f {
1624                         reg = <0x1f 0x1>;
1625                 };
1626         };
1627
1628         pinctrl: pinctrl {
1629                 compatible = "rockchip,rk3368-pinctrl";
1630                 rockchip,grf = <&grf>;
1631                 rockchip,pmu = <&pmugrf>;
1632                 #address-cells = <0x2>;
1633                 #size-cells = <0x2>;
1634                 ranges;
1635
1636                 gpio0: gpio0@ff750000 {
1637                         compatible = "rockchip,gpio-bank";
1638                         reg = <0x0 0xff750000 0x0 0x100>;
1639                         clocks = <&cru PCLK_GPIO0>;
1640                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1641
1642                         gpio-controller;
1643                         #gpio-cells = <0x2>;
1644
1645                         interrupt-controller;
1646                         #interrupt-cells = <0x2>;
1647                 };
1648
1649                 gpio1: gpio1@ff780000 {
1650                         compatible = "rockchip,gpio-bank";
1651                         reg = <0x0 0xff780000 0x0 0x100>;
1652                         clocks = <&cru PCLK_GPIO1>;
1653                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1654
1655                         gpio-controller;
1656                         #gpio-cells = <0x2>;
1657
1658                         interrupt-controller;
1659                         #interrupt-cells = <0x2>;
1660                 };
1661
1662                 gpio2: gpio2@ff790000 {
1663                         compatible = "rockchip,gpio-bank";
1664                         reg = <0x0 0xff790000 0x0 0x100>;
1665                         clocks = <&cru PCLK_GPIO2>;
1666                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1667
1668                         gpio-controller;
1669                         #gpio-cells = <0x2>;
1670
1671                         interrupt-controller;
1672                         #interrupt-cells = <0x2>;
1673                 };
1674
1675                 gpio3: gpio3@ff7a0000 {
1676                         compatible = "rockchip,gpio-bank";
1677                         reg = <0x0 0xff7a0000 0x0 0x100>;
1678                         clocks = <&cru PCLK_GPIO3>;
1679                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1680
1681                         gpio-controller;
1682                         #gpio-cells = <0x2>;
1683
1684                         interrupt-controller;
1685                         #interrupt-cells = <0x2>;
1686                 };
1687
1688                 pcfg_pull_up: pcfg-pull-up {
1689                         bias-pull-up;
1690                 };
1691
1692                 pcfg_pull_down: pcfg-pull-down {
1693                         bias-pull-down;
1694                 };
1695
1696                 pcfg_pull_none: pcfg-pull-none {
1697                         bias-disable;
1698                 };
1699
1700                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1701                         bias-disable;
1702                         drive-strength = <12>;
1703                 };
1704
1705                 edp {
1706                         edp_hpd: edp-hpd {
1707                                 rockchip,pins = <2 23 RK_FUNC_2 &pcfg_pull_none>;
1708                         };
1709                 };
1710
1711                 emmc {
1712                         emmc_clk: emmc-clk {
1713                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1714                         };
1715
1716                         emmc_cmd: emmc-cmd {
1717                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1718                         };
1719
1720                         emmc_pwr: emmc-pwr {
1721                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1722                         };
1723
1724                         emmc_bus1: emmc-bus1 {
1725                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1726                         };
1727
1728                         emmc_bus4: emmc-bus4 {
1729                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1730                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1731                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1732                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1733                         };
1734
1735                         emmc_bus8: emmc-bus8 {
1736                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1737                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1738                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1739                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1740                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1741                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1742                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1743                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1744                         };
1745                 };
1746
1747                 gmac {
1748                         rgmii_pins: rgmii-pins {
1749                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1750                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1751                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1752                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1753                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1754                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1755                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1756                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1757                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1758                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1759                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1760                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1761                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1762                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1763                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1764                         };
1765
1766                         rmii_pins: rmii-pins {
1767                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1768                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1769                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1770                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1771                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1772                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1773                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1774                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1775                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1776                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1777                         };
1778                 };
1779
1780                 hdmi {
1781                         hdmi_cec: hdmi-cec {
1782                                 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1783                         };
1784
1785                         hdmi_i2c_xfer: hdmi-i2c-xfer {
1786                                 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1787                                                 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1788                         };
1789                 };
1790
1791                 i2c0 {
1792                         i2c0_xfer: i2c0-xfer {
1793                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1794                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1795                         };
1796                 };
1797
1798                 i2c1 {
1799                         i2c1_xfer: i2c1-xfer {
1800                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1801                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1802                         };
1803                 };
1804
1805                 i2c2 {
1806                         i2c2_xfer: i2c2-xfer {
1807                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1808                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1809                         };
1810                 };
1811
1812                 i2c3 {
1813                         i2c3_xfer: i2c3-xfer {
1814                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1815                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1816                         };
1817                 };
1818
1819                 i2c4 {
1820                         i2c4_xfer: i2c4-xfer {
1821                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1822                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1823                         };
1824                 };
1825
1826                 i2c5 {
1827                         i2c5_xfer: i2c5-xfer {
1828                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1829                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1830                         };
1831                 };
1832
1833                 i2s {
1834                         i2s_8ch_bus: i2s-8ch-bus {
1835                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1836                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1837                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1838                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1839                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1840                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1841                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1842                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1843                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1844                         };
1845                 };
1846
1847                 pwm0 {
1848                         pwm0_pin: pwm0-pin {
1849                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1850                         };
1851
1852                         vop_pwm_pin: vop-pwm {
1853                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1854                         };
1855                 };
1856
1857                 pwm1 {
1858                         pwm1_pin: pwm1-pin {
1859                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1860                         };
1861                 };
1862
1863                 pwm3 {
1864                         pwm3_pin: pwm3-pin {
1865                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1866                         };
1867                 };
1868
1869                 sdio0 {
1870                         sdio0_bus1: sdio0-bus1 {
1871                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1872                         };
1873
1874                         sdio0_bus4: sdio0-bus4 {
1875                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1876                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1877                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1878                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1879                         };
1880
1881                         sdio0_cmd: sdio0-cmd {
1882                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1883                         };
1884
1885                         sdio0_clk: sdio0-clk {
1886                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1887                         };
1888
1889                         sdio0_cd: sdio0-cd {
1890                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1891                         };
1892
1893                         sdio0_wp: sdio0-wp {
1894                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1895                         };
1896
1897                         sdio0_pwr: sdio0-pwr {
1898                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1899                         };
1900
1901                         sdio0_bkpwr: sdio0-bkpwr {
1902                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1903                         };
1904
1905                         sdio0_int: sdio0-int {
1906                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1907                         };
1908                 };
1909
1910                 sdmmc {
1911                         sdmmc_clk: sdmmc-clk {
1912                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1913                         };
1914
1915                         sdmmc_cmd: sdmmc-cmd {
1916                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1917                         };
1918
1919                         sdmmc_cd: sdmmc-cd {
1920                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1921                         };
1922
1923                         sdmmc_bus1: sdmmc-bus1 {
1924                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1925                         };
1926
1927                         sdmmc_bus4: sdmmc-bus4 {
1928                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1929                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1930                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1931                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1932                         };
1933                 };
1934
1935                 spi0 {
1936                         spi0_clk: spi0-clk {
1937                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1938                         };
1939                         spi0_cs0: spi0-cs0 {
1940                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1941                         };
1942                         spi0_cs1: spi0-cs1 {
1943                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1944                         };
1945                         spi0_tx: spi0-tx {
1946                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1947                         };
1948                         spi0_rx: spi0-rx {
1949                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1950                         };
1951                 };
1952
1953                 spi1 {
1954                         spi1_clk: spi1-clk {
1955                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1956                         };
1957                         spi1_cs0: spi1-cs0 {
1958                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1959                         };
1960                         spi1_cs1: spi1-cs1 {
1961                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1962                         };
1963                         spi1_rx: spi1-rx {
1964                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1965                         };
1966                         spi1_tx: spi1-tx {
1967                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1968                         };
1969                 };
1970
1971                 spi2 {
1972                         spi2_clk: spi2-clk {
1973                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1974                         };
1975                         spi2_cs0: spi2-cs0 {
1976                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1977                         };
1978                         spi2_rx: spi2-rx {
1979                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1980                         };
1981                         spi2_tx: spi2-tx {
1982                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1983                         };
1984                 };
1985
1986                 uart0 {
1987                         uart0_xfer: uart0-xfer {
1988                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1989                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1990                         };
1991
1992                         uart0_cts: uart0-cts {
1993                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1994                         };
1995
1996                         uart0_rts: uart0-rts {
1997                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1998                         };
1999                 };
2000
2001                 uart1 {
2002                         uart1_xfer: uart1-xfer {
2003                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
2004                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
2005                         };
2006
2007                         uart1_cts: uart1-cts {
2008                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
2009                         };
2010
2011                         uart1_rts: uart1-rts {
2012                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
2013                         };
2014                 };
2015
2016                 uart2 {
2017                         uart2_xfer: uart2-xfer {
2018                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
2019                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
2020                         };
2021                         /* no rts / cts for uart2 */
2022                 };
2023
2024                 uart3 {
2025                         uart3_xfer: uart3-xfer {
2026                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
2027                                                 <3 30 RK_FUNC_2 &pcfg_pull_none>;
2028                         };
2029
2030                         uart3_cts: uart3-cts {
2031                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
2032                         };
2033
2034                         uart3_rts: uart3-rts {
2035                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
2036                         };
2037                 };
2038
2039                 uart4 {
2040                         uart4_xfer: uart4-xfer {
2041                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
2042                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
2043                         };
2044
2045                         uart4_cts: uart4-cts {
2046                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
2047                         };
2048
2049                         uart4_rts: uart4-rts {
2050                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
2051                         };
2052                 };
2053
2054                 isp {
2055                         cif_clkout: cif-clkout {
2056                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2057                         };
2058
2059                         isp_dvp_d2d9: isp-dvp-d2d9 {
2060                                 rockchip,pins =
2061                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2062                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2063                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2064                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2065                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2066                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2067                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2068                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2069                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
2070                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
2071                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
2072                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2073                         };
2074
2075                         isp_dvp_d0d1: isp-dvp-d0d1 {
2076                                 rockchip,pins =
2077                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2078                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
2079                         };
2080
2081                         isp_dvp_d10d11:isp_d10d11 {
2082                                 rockchip,pins =
2083                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2084                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2085                         };
2086
2087                         isp_dvp_d0d7: isp-dvp-d0d7 {
2088                                 rockchip,pins =
2089                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2090                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
2091                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2092                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2093                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2094                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2095                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2096                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2097                         };
2098
2099                         isp_dvp_d4d11: isp-dvp-d4d11 {
2100                                 rockchip,pins =
2101                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2102                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2103                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2104                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2105                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2106                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2107                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2108                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2109                         };
2110
2111                         isp_shutter: isp-shutter {
2112                                 rockchip,pins =
2113                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2114                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2115                         };
2116
2117                         isp_flash_trigger: isp-flash-trigger {
2118                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2119                         };
2120
2121                         isp_prelight: isp-prelight {
2122                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2123                         };
2124
2125                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2126                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2127                         };
2128                 };
2129
2130                 lcdc {
2131                         lcdc_lcdc: lcdc-lcdc {
2132                                 rockchip,pins =
2133                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D10 */
2134                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D11 */
2135                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D12 */
2136                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D13 */
2137                                         <0 18 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D14 */
2138                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D15 */
2139                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D16 */
2140                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D17 */
2141                                         <0 22 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D18 */
2142                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D19 */
2143                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D20 */
2144                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D21 */
2145                                         <0 26 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D22 */
2146                                         <0 27 RK_FUNC_1 &pcfg_pull_none>,  /* LCDC_D23 */
2147                                         <0 31 RK_FUNC_1 &pcfg_pull_none>,  /* DCLK */
2148                                         <0 30 RK_FUNC_1 &pcfg_pull_none>,  /* DEN */
2149                                         <0 28 RK_FUNC_1 &pcfg_pull_none>,  /* HSYNC */
2150                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;  /* VSYN */
2151                         };
2152
2153                         lcdc_gpio: lcdc-gpio {
2154                                 rockchip,pins =
2155                                         <0 14 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D10 */
2156                                         <0 15 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D11 */
2157                                         <0 16 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D12 */
2158                                         <0 17 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D13 */
2159                                         <0 18 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D14 */
2160                                         <0 19 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D15 */
2161                                         <0 20 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D16 */
2162                                         <0 21 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D17 */
2163                                         <0 22 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D18 */
2164                                         <0 23 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D19 */
2165                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D20 */
2166                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D21 */
2167                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D22 */
2168                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>,  /* LCDC_D23 */
2169                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>,  /* DCLK */
2170                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>,  /* DEN */
2171                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>,  /* HSYNC */
2172                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>;  /* VSYN */
2173                         };
2174                 };
2175         };
2176
2177         rockchip_suspend: rockchip-suspend {
2178                 compatible = "rockchip,pm-rk3368";
2179                 status = "disabled";
2180                 rockchip,sleep-debug-en = <0>;
2181                 rockchip,sleep-mode-config = <
2182                         (0
2183                         | RKPM_SLP_ARMOFF_LOGPD
2184                         | RKPM_SLP_PMU_PLLS_PWRDN
2185                         | RKPM_SLP_PMU_PMUALIVE_32K
2186                         | RKPM_SLP_SFT_PLLS_DEEP
2187                         | RKPM_SLP_PMU_DIS_OSC
2188                         | RKPM_SLP_SFT_PD_NBSCUS
2189                         )
2190                 >;
2191                 rockchip,wakeup-config = <
2192                         (0
2193                         | RKPM_GPIO_WKUP_EN
2194                         | RKPM_USB_WKUP_EN
2195                         )
2196                 >;
2197         };
2198 };