arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51 #include <dt-bindings/display/mipi_dsi.h>
  52 #include <dt-bindings/display/drm_mipi_dsi.h>
  53 #include <dt-bindings/display/media-bus-format.h>
  54
  55 / {
  56         compatible = "rockchip,rk3368";
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 ethernet0 = &gmac;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67                 i2c4 = &i2c4;
  68                 i2c5 = &i2c5;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74                 spi0 = &spi0;
  75                 spi1 = &spi1;
  76                 spi2 = &spi2;
  77         };
  78
  79         cpus {
  80                 #address-cells = <0x2>;
  81                 #size-cells = <0x0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                                 core2 {
 107                                         cpu = <&cpu_b2>;
 108                                 };
 109                                 core3 {
 110                                         cpu = <&cpu_b3>;
 111                                 };
 112                         };
 113                 };
 114
 115                 cpu_l0: cpu@0 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a53", "arm,armv8";
 118                         reg = <0x0 0x0>;
 119                         enable-method = "psci";
 120                         clocks = <&cru ARMCLKL>;
 121                         next-level-cache = <&cluster0_l2>;
 122                         operating-points-v2 = <&cluster0_opp>;
 123                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 124                         #cooling-cells = <2>; /* min followed by max */
 125                         dynamic-power-coefficient = <149>;
 126                 };
 127
 128                 cpu_l1: cpu@1 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x1>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         next-level-cache = <&cluster0_l2>;
 135                         operating-points-v2 = <&cluster0_opp>;
 136                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 137                 };
 138
 139                 cpu_l2: cpu@2 {
 140                         device_type = "cpu";
 141                         compatible = "arm,cortex-a53", "arm,armv8";
 142                         reg = <0x0 0x2>;
 143                         enable-method = "psci";
 144                         clocks = <&cru ARMCLKL>;
 145                         next-level-cache = <&cluster0_l2>;
 146                         operating-points-v2 = <&cluster0_opp>;
 147                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 148                 };
 149
 150                 cpu_l3: cpu@3 {
 151                         device_type = "cpu";
 152                         compatible = "arm,cortex-a53", "arm,armv8";
 153                         reg = <0x0 0x3>;
 154                         enable-method = "psci";
 155                         clocks = <&cru ARMCLKL>;
 156                         next-level-cache = <&cluster0_l2>;
 157                         operating-points-v2 = <&cluster0_opp>;
 158                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 159                 };
 160
 161                 cpu_b0: cpu@100 {
 162                         device_type = "cpu";
 163                         compatible = "arm,cortex-a53", "arm,armv8";
 164                         reg = <0x0 0x100>;
 165                         enable-method = "psci";
 166                         clocks = <&cru ARMCLKB>;
 167                         next-level-cache = <&cluster1_l2>;
 168                         operating-points-v2 = <&cluster1_opp>;
 169                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 170                         #cooling-cells = <2>; /* min followed by max */
 171                         dynamic-power-coefficient = <160>;
 172                 };
 173
 174                 cpu_b1: cpu@101 {
 175                         device_type = "cpu";
 176                         compatible = "arm,cortex-a53", "arm,armv8";
 177                         reg = <0x0 0x101>;
 178                         enable-method = "psci";
 179                         clocks = <&cru ARMCLKB>;
 180                         next-level-cache = <&cluster1_l2>;
 181                         operating-points-v2 = <&cluster1_opp>;
 182                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 183                 };
 184
 185                 cpu_b2: cpu@102 {
 186                         device_type = "cpu";
 187                         compatible = "arm,cortex-a53", "arm,armv8";
 188                         reg = <0x0 0x102>;
 189                         enable-method = "psci";
 190                         clocks = <&cru ARMCLKB>;
 191                         next-level-cache = <&cluster1_l2>;
 192                         operating-points-v2 = <&cluster1_opp>;
 193                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 194                 };
 195
 196                 cpu_b3: cpu@103 {
 197                         device_type = "cpu";
 198                         compatible = "arm,cortex-a53", "arm,armv8";
 199                         reg = <0x0 0x103>;
 200                         enable-method = "psci";
 201                         clocks = <&cru ARMCLKB>;
 202                         next-level-cache = <&cluster1_l2>;
 203                         operating-points-v2 = <&cluster1_opp>;
 204                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 205                 };
 206
 207                 cluster0_l2: l2-cache0 {
 208                         compatible = "cache";
 209                 };
 210
 211                 cluster1_l2: l2-cache1 {
 212                         compatible = "cache";
 213                 };
 214         };
 215
 216         cluster0_opp: opp_table0 {
 217                 compatible = "operating-points-v2";
 218                 opp-shared;
 219                 leakage-voltage-sel = <
 220                         1   24   0
 221                         25  254  1
 222                 >;
 223                 nvmem-cells = <&cpu_leakage>;
 224                 nvmem-cell-names = "cpu_leakage";
 225
 226                 opp@216000000 {
 227                         opp-hz = /bits/ 64 <216000000>;
 228                         opp-microvolt = <950000 950000 1350000>;
 229                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 230                         opp-microvolt-L1 = <950000 950000 1350000>;
 231                         clock-latency-ns = <40000>;
 232                         opp-suspend;
 233                 };
 234                 opp@408000000 {
 235                         opp-hz = /bits/ 64 <408000000>;
 236                         opp-microvolt = <950000 950000 1350000>;
 237                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 238                         opp-microvolt-L1 = <950000 950000 1350000>;
 239                         clock-latency-ns = <40000>;
 240                 };
 241                 opp@600000000 {
 242                         opp-hz = /bits/ 64 <600000000>;
 243                         opp-microvolt = <950000 950000 1350000>;
 244                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 245                         opp-microvolt-L1 = <950000 950000 1350000>;
 246                         clock-latency-ns = <40000>;
 247                 };
 248                 opp@816000000 {
 249                         opp-hz = /bits/ 64 <816000000>;
 250                         opp-microvolt = <1025000 1025000 1350000>;
 251                         opp-microvolt-L0 = <1125000 1125000 1350000>;
 252                         opp-microvolt-L1 = <1025000 1025000 1350000>;
 253                         clock-latency-ns = <40000>;
 254                 };
 255                 opp@1008000000 {
 256                         opp-hz = /bits/ 64 <1008000000>;
 257                         opp-microvolt = <1125000 1125000 1350000>;
 258                         opp-microvolt-L0 = <1225000 1225000 1350000>;
 259                         opp-microvolt-L1 = <1125000 1125000 1350000>;
 260                         clock-latency-ns = <40000>;
 261                 };
 262                 opp@1200000000 {
 263                         opp-hz = /bits/ 64 <1200000000>;
 264                         opp-microvolt = <1225000 1225000 1350000>;
 265                         opp-microvolt-L0 = <1325000 1325000 1350000>;
 266                         opp-microvolt-L1 = <1225000 1225000 1350000>;
 267                         clock-latency-ns = <40000>;
 268                 };
 269         };
 270
 271         cluster1_opp: opp_table1 {
 272                 compatible = "operating-points-v2";
 273                 opp-shared;
 274                 leakage-scaling-sel = <
 275                         1   24   36
 276                         25  254  0
 277                 >;
 278                 clocks = <&cru PLL_APLLB>;
 279                 leakage-voltage-sel = <
 280                         1   24   0
 281                         25  254  1
 282                 >;
 283                 nvmem-cells = <&cpu_leakage>;
 284                 nvmem-cell-names = "cpu_leakage";
 285
 286                 opp@216000000 {
 287                         opp-hz = /bits/ 64 <216000000>;
 288                         opp-microvolt = <950000 950000 1350000>;
 289                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 290                         opp-microvolt-L1 = <950000 950000 1350000>;
 291                         clock-latency-ns = <40000>;
 292                         opp-suspend;
 293                 };
 294                 opp@408000000 {
 295                         opp-hz = /bits/ 64 <408000000>;
 296                         opp-microvolt = <950000 950000 1350000>;
 297                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 298                         opp-microvolt-L1 = <950000 950000 1350000>;
 299                         clock-latency-ns = <40000>;
 300                 };
 301                 opp@600000000 {
 302                         opp-hz = /bits/ 64 <600000000>;
 303                         opp-microvolt = <950000 950000 1350000>;
 304                         opp-microvolt-L0 = <1050000 1050000 1350000>;
 305                         opp-microvolt-L1 = <950000 950000 1350000>;
 306                         clock-latency-ns = <40000>;
 307                 };
 308                 opp@816000000 {
 309                         opp-hz = /bits/ 64 <816000000>;
 310                         opp-microvolt = <975000 975000 1350000>;
 311                         opp-microvolt-L0 = <1075000 1075000 1350000>;
 312                         opp-microvolt-L1 = <975000 975000 1350000>;
 313                         clock-latency-ns = <40000>;
 314                 };
 315                 opp@1008000000 {
 316                         opp-hz = /bits/ 64 <1008000000>;
 317                         opp-microvolt = <1050000 1050000 1350000>;
 318                         opp-microvolt-L0 = <1150000 1150000 1350000>;
 319                         opp-microvolt-L1 = <1050000 1050000 1350000>;
 320                         clock-latency-ns = <40000>;
 321                 };
 322                 opp@1200000000 {
 323                         opp-hz = /bits/ 64 <1200000000>;
 324                         opp-microvolt = <1150000 1150000 1350000>;
 325                         opp-microvolt-L0 = <1250000 1250000 1350000>;
 326                         opp-microvolt-L1 = <1150000 1150000 1350000>;
 327                         clock-latency-ns = <40000>;
 328                 };
 329                 opp@1296000000 {
 330                         opp-hz = /bits/ 64 <1296000000>;
 331                         opp-microvolt = <1225000 1225000 1350000>;
 332                         opp-microvolt-L0 = <1350000 1350000 1350000>;
 333                         opp-microvolt-L1 = <1225000 1225000 1350000>;
 334                         clock-latency-ns = <40000>;
 335                 };
 336                 opp@1416000000 {
 337                         opp-hz = /bits/ 64 <1416000000>;
 338                         opp-microvolt = <1300000 1300000 1350000>;
 339                         opp-microvolt-L0 = <1350000 1350000 1350000>;
 340                         opp-microvolt-L1 = <1300000 1300000 1350000>;
 341                         clock-latency-ns = <40000>;
 342                 };
 343                 opp@1512000000 {
 344                         opp-hz = /bits/ 64 <1512000000>;
 345                         opp-microvolt = <1350000 1350000 1350000>;
 346                         opp-microvolt-L0 = <1350000 1350000 1350000>;
 347                         opp-microvolt-L1 = <1350000 1350000 1350000>;
 348                         clock-latency-ns = <40000>;
 349                 };
 350         };
 351
 352         energy-costs {
 353                 RK3368_CPU_COST_0: rk3368-core-cost0 {
 354                         busy-cost-data = <
 355                                 146    44       /*  216M */
 356                                 276    72       /*  408M */
 357                                 406    99       /*  600M */
 358                                 552    147      /*  816M */
 359                                 682    200      /* 1008M */
 360                                 812    255      /* 1200M */
 361                         >;
 362                         idle-cost-data = <
 363                                   6
 364                                   6
 365                                   0
 366                         >;
 367                 };
 368
 369                 RK3368_CPU_COST_1: rk3368-core-cost1 {
 370                         busy-cost-data = <
 371                                 146    53       /*  216M */
 372                                 276    86       /*  408M */
 373                                 406    118      /*  600M */
 374                                 552    166      /*  816M */
 375                                 682    226      /* 1008M */
 376                                 812    309      /* 1200M */
 377                                 878    371      /* 1200M */
 378                                 959    446      /* 1416M */
 379                                 1024   513      /* 1512M */
 380                         >;
 381                         idle-cost-data = <
 382                                    6
 383                                    6
 384                                    0
 385                         >;
 386                 };
 387
 388                 RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 {
 389                         busy-cost-data = <
 390                                 146    9        /*  216M */
 391                                 276    14       /*  408M */
 392                                 406    20       /*  600M */
 393                                 552    29       /*  816M */
 394                                 682    40       /* 1008M */
 395                                 812    51       /* 1200M */
 396                         >;
 397                         idle-cost-data = <
 398                                 56
 399                                 56
 400                                 56
 401                         >;
 402                 };
 403
 404                 RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 {
 405                         busy-cost-data = <
 406                                 146    11       /*  216M */
 407                                 276    17       /*  408M */
 408                                 406    24       /*  600M */
 409                                 552    33       /*  816M */
 410                                 682    45       /* 1008M */
 411                                 812    62       /* 1200M */
 412                                 878    74       /* 1200M */
 413                                 959    89       /* 1416M */
 414                                 1024   103      /* 1512M */
 415                         >;
 416                         idle-cost-data = <
 417                                 56
 418                                 56
 419                                 56
 420                         >;
 421                 };
 422         };
 423
 424         arm-pmu {
 425                 compatible = "arm,armv8-pmuv3";
 426                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 427                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 428                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 429                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 430                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 431                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 432                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 433                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 434                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 435                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 436                                      <&cpu_b2>, <&cpu_b3>;
 437         };
 438
 439         amba {
 440                 compatible = "arm,amba-bus";
 441                 #address-cells = <2>;
 442                 #size-cells = <2>;
 443                 ranges;
 444
 445                 dmac_peri: dma-controller@ff250000 {
 446                         compatible = "arm,pl330", "arm,primecell";
 447                         reg = <0x0 0xff250000 0x0 0x4000>;
 448                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 449                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 450                         #dma-cells = <1>;
 451                         clocks = <&cru ACLK_DMAC_PERI>;
 452                         clock-names = "apb_pclk";
 453                         arm,pl330-broken-no-flushp;
 454                         peripherals-req-type-burst;
 455                 };
 456
 457                 dmac_bus: dma-controller@ff600000 {
 458                         compatible = "arm,pl330", "arm,primecell";
 459                         reg = <0x0 0xff600000 0x0 0x4000>;
 460                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 461                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 462                         #dma-cells = <1>;
 463                         clocks = <&cru ACLK_DMAC_BUS>;
 464                         clock-names = "apb_pclk";
 465                         arm,pl330-broken-no-flushp;
 466                         peripherals-req-type-burst;
 467                 };
 468         };
 469
 470         psci {
 471                 compatible = "arm,psci-0.2";
 472                 method = "smc";
 473         };
 474
 475         timer {
 476                 compatible = "arm,armv8-timer";
 477                 interrupts = <GIC_PPI 13
 478                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 479                              <GIC_PPI 14
 480                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 481                              <GIC_PPI 11
 482                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 483                              <GIC_PPI 10
 484                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 485         };
 486
 487         xin24m: oscillator {
 488                 compatible = "fixed-clock";
 489                 clock-frequency = <24000000>;
 490                 clock-output-names = "xin24m";
 491                 #clock-cells = <0>;
 492         };
 493
 494         sdmmc: dwmmc@ff0c0000 {
 495                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 496                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 497                 clock-freq-min-max = <400000 150000000>;
 498                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 499                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 500                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 501                 fifo-depth = <0x100>;
 502                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 503                 status = "disabled";
 504         };
 505
 506         sdio0: dwmmc@ff0d0000 {
 507                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 508                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 509                 clock-freq-min-max = <400000 150000000>;
 510                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 511                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 512                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 513                 fifo-depth = <0x100>;
 514                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 515                 status = "disabled";
 516         };
 517
 518         emmc: dwmmc@ff0f0000 {
 519                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 520                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 521                 clock-freq-min-max = <400000 150000000>;
 522                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 523                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 524                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 525                 fifo-depth = <0x100>;
 526                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 527                 status = "disabled";
 528         };
 529
 530         saradc: saradc@ff100000 {
 531                 compatible = "rockchip,saradc";
 532                 reg = <0x0 0xff100000 0x0 0x100>;
 533                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 534                 #io-channel-cells = <1>;
 535                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 536                 clock-names = "saradc", "apb_pclk";
 537                 resets = <&cru SRST_SARADC>;
 538                 reset-names = "saradc-apb";
 539                 status = "disabled";
 540         };
 541
 542         spi0: spi@ff110000 {
 543                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 544                 reg = <0x0 0xff110000 0x0 0x1000>;
 545                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 546                 clock-names = "spiclk", "apb_pclk";
 547                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 548                 pinctrl-names = "default";
 549                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 550                 #address-cells = <1>;
 551                 #size-cells = <0>;
 552                 status = "disabled";
 553         };
 554
 555         spi1: spi@ff120000 {
 556                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 557                 reg = <0x0 0xff120000 0x0 0x1000>;
 558                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 559                 clock-names = "spiclk", "apb_pclk";
 560                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 561                 pinctrl-names = "default";
 562                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 status = "disabled";
 566         };
 567
 568         spi2: spi@ff130000 {
 569                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 570                 reg = <0x0 0xff130000 0x0 0x1000>;
 571                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 572                 clock-names = "spiclk", "apb_pclk";
 573                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 576                 #address-cells = <1>;
 577                 #size-cells = <0>;
 578                 status = "disabled";
 579         };
 580
 581         i2c0: i2c@ff650000 {
 582                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 583                 reg = <0x0 0xff650000 0x0 0x1000>;
 584                 clocks = <&cru PCLK_I2C0>;
 585                 clock-names = "i2c";
 586                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&i2c0_xfer>;
 589                 #address-cells = <1>;
 590                 #size-cells = <0>;
 591                 status = "disabled";
 592         };
 593
 594         i2c2: i2c@ff140000 {
 595                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 596                 reg = <0x0 0xff140000 0x0 0x1000>;
 597                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 598                 #address-cells = <1>;
 599                 #size-cells = <0>;
 600                 clock-names = "i2c";
 601                 clocks = <&cru PCLK_I2C2>;
 602                 pinctrl-names = "default";
 603                 pinctrl-0 = <&i2c2_xfer>;
 604                 status = "disabled";
 605         };
 606
 607         i2c3: i2c@ff150000 {
 608                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 609                 reg = <0x0 0xff150000 0x0 0x1000>;
 610                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 611                 #address-cells = <1>;
 612                 #size-cells = <0>;
 613                 clock-names = "i2c";
 614                 clocks = <&cru PCLK_I2C3>;
 615                 pinctrl-names = "default";
 616                 pinctrl-0 = <&i2c3_xfer>;
 617                 status = "disabled";
 618         };
 619
 620         i2c4: i2c@ff160000 {
 621                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 622                 reg = <0x0 0xff160000 0x0 0x1000>;
 623                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 624                 #address-cells = <1>;
 625                 #size-cells = <0>;
 626                 clock-names = "i2c";
 627                 clocks = <&cru PCLK_I2C4>;
 628                 pinctrl-names = "default";
 629                 pinctrl-0 = <&i2c4_xfer>;
 630                 status = "disabled";
 631         };
 632
 633         i2c5: i2c@ff170000 {
 634                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 635                 reg = <0x0 0xff170000 0x0 0x1000>;
 636                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 637                 #address-cells = <1>;
 638                 #size-cells = <0>;
 639                 clock-names = "i2c";
 640                 clocks = <&cru PCLK_I2C5>;
 641                 pinctrl-names = "default";
 642                 pinctrl-0 = <&i2c5_xfer>;
 643                 status = "disabled";
 644         };
 645
 646         uart0: serial@ff180000 {
 647                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 648                 reg = <0x0 0xff180000 0x0 0x100>;
 649                 clock-frequency = <24000000>;
 650                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 651                 clock-names = "baudclk", "apb_pclk";
 652                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 653                 reg-shift = <2>;
 654                 reg-io-width = <4>;
 655                 status = "disabled";
 656         };
 657
 658         uart1: serial@ff190000 {
 659                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 660                 reg = <0x0 0xff190000 0x0 0x100>;
 661                 clock-frequency = <24000000>;
 662                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 663                 clock-names = "baudclk", "apb_pclk";
 664                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 665                 reg-shift = <2>;
 666                 reg-io-width = <4>;
 667                 status = "disabled";
 668         };
 669
 670         uart3: serial@ff1b0000 {
 671                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 672                 reg = <0x0 0xff1b0000 0x0 0x100>;
 673                 clock-frequency = <24000000>;
 674                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 675                 clock-names = "baudclk", "apb_pclk";
 676                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 677                 reg-shift = <2>;
 678                 reg-io-width = <4>;
 679                 status = "disabled";
 680         };
 681
 682         uart4: serial@ff1c0000 {
 683                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 684                 reg = <0x0 0xff1c0000 0x0 0x100>;
 685                 clock-frequency = <24000000>;
 686                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 687                 clock-names = "baudclk", "apb_pclk";
 688                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 689                 reg-shift = <2>;
 690                 reg-io-width = <4>;
 691                 status = "disabled";
 692         };
 693
 694         thermal_zones: thermal-zones {
 695                 soc_thermal: soc-thermal {
 696                         polling-delay-passive = <200>; /* milliseconds */
 697                         polling-delay = <200>; /* milliseconds */
 698                         sustainable-power = <600>; /* milliwatts */
 699
 700                         thermal-sensors = <&tsadc 0>;
 701                         trips {
 702                                 threshold: trip-point@0 {
 703                                         temperature = <70000>; /* millicelsius */
 704                                         hysteresis = <2000>; /* millicelsius */
 705                                         type = "passive";
 706                                 };
 707                                 target: trip-point@1 {
 708                                         temperature = <80000>; /* millicelsius */
 709                                         hysteresis = <2000>; /* millicelsius */
 710                                         type = "passive";
 711                                 };
 712                                 soc_crit: soc-crit {
 713                                         temperature = <95000>; /* millicelsius */
 714                                         hysteresis = <2000>; /* millicelsius */
 715                                         type = "critical";
 716                                 };
 717                         };
 718
 719                         cooling-maps {
 720                                 map0 {
 721                                         trip = <&target>;
 722                                         cooling-device =
 723                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 724                                         contribution = <1024>;
 725                                 };
 726                                 map1 {
 727                                         trip = <&target>;
 728                                         cooling-device =
 729                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 730                                         contribution = <1024>;
 731                                 };
 732                                 map2 {
 733                                         trip = <&target>;
 734                                         cooling-device =
 735                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 736                                         contribution = <1024>;
 737                                 };
 738                         };
 739                 };
 740
 741                 gpu_thermal: gpu-thermal {
 742                         polling-delay-passive = <200>; /* milliseconds */
 743                         polling-delay = <200>; /* milliseconds */
 744                         thermal-sensors = <&tsadc 1>;
 745                 };
 746         };
 747
 748         tsadc: tsadc@ff280000 {
 749                 compatible = "rockchip,rk3368-tsadc-legacy";
 750                 reg = <0x0 0xff280000 0x0 0x100>;
 751                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 752                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 753                 clock-names = "tsadc", "apb_pclk";
 754                 clock-frequency = <32768>;
 755                 resets = <&cru SRST_TSADC>;
 756                 reset-names = "tsadc-apb";
 757                 nvmem-cells = <&temp_adjust>;
 758                 nvmem-cell-names = "temp_adjust";
 759                 #thermal-sensor-cells = <1>;
 760                 hw-shut-temp = <95000>;
 761                 latency-bound = <50000>;
 762                 status = "disabled";
 763         };
 764
 765         gmac: ethernet@ff290000 {
 766                 compatible = "rockchip,rk3368-gmac";
 767                 reg = <0x0 0xff290000 0x0 0x10000>;
 768                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 769                 interrupt-names = "macirq";
 770                 rockchip,grf = <&grf>;
 771                 clocks = <&cru SCLK_MAC>,
 772                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 773                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 774                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 775                 clock-names = "stmmaceth",
 776                         "mac_clk_rx", "mac_clk_tx",
 777                         "clk_mac_ref", "clk_mac_refout",
 778                         "aclk_mac", "pclk_mac";
 779                 status = "disabled";
 780         };
 781
 782         nandc0: nandc@ff400000 {
 783                 compatible = "rockchip,rk-nandc";
 784                 reg = <0x0 0xff400000 0x0 0x4000>;
 785                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 786                 nandc_id = <0>;
 787                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 788                 clock-names = "clk_nandc", "hclk_nandc";
 789                 status = "disabled";
 790         };
 791
 792         usb_host0_ehci: usb@ff500000 {
 793                 compatible = "generic-ehci";
 794                 reg = <0x0 0xff500000 0x0 0x20000>;
 795                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 796                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 797                 clock-names = "usbhost", "utmi";
 798                 phys = <&u2phy_host>;
 799                 phy-names = "usb";
 800                 status = "disabled";
 801         };
 802
 803         usb_host0_ohci: usb@ff520000 {
 804                 compatible = "generic-ohci";
 805                 reg = <0x0 0xff520000 0x0 0x20000>;
 806                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 807                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 808                 clock-names = "usbhost", "utmi";
 809                 phys = <&u2phy_host>;
 810                 phy-names = "usb";
 811                 status = "disabled";
 812         };
 813
 814         usb_otg: usb@ff580000 {
 815                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 816                                 "snps,dwc2";
 817                 reg = <0x0 0xff580000 0x0 0x40000>;
 818                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 819                 clocks = <&cru HCLK_OTG0>;
 820                 clock-names = "otg";
 821                 dr_mode = "otg";
 822                 g-np-tx-fifo-size = <16>;
 823                 g-rx-fifo-size = <275>;
 824                 g-tx-fifo-size = <256 128 128 64 64 32>;
 825                 g-use-dma;
 826                 status = "disabled";
 827         };
 828
 829         ddrpctl: syscon@ff610000 {
 830                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 831                 reg = <0x0 0xff610000 0x0 0x400>;
 832         };
 833
 834         i2c1: i2c@ff660000 {
 835                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 836                 reg = <0x0 0xff660000 0x0 0x1000>;
 837                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 838                 #address-cells = <1>;
 839                 #size-cells = <0>;
 840                 clock-names = "i2c";
 841                 clocks = <&cru PCLK_I2C1>;
 842                 pinctrl-names = "default";
 843                 pinctrl-0 = <&i2c1_xfer>;
 844                 status = "disabled";
 845         };
 846
 847         pwm0: pwm@ff680000 {
 848                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 849                 reg = <0x0 0xff680000 0x0 0x10>;
 850                 #pwm-cells = <3>;
 851                 pinctrl-names = "default";
 852                 pinctrl-0 = <&pwm0_pin>;
 853                 clocks = <&cru PCLK_PWM1>;
 854                 clock-names = "pwm";
 855                 status = "disabled";
 856         };
 857
 858         pwm1: pwm@ff680010 {
 859                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 860                 reg = <0x0 0xff680010 0x0 0x10>;
 861                 #pwm-cells = <3>;
 862                 pinctrl-names = "default";
 863                 pinctrl-0 = <&pwm1_pin>;
 864                 clocks = <&cru PCLK_PWM1>;
 865                 clock-names = "pwm";
 866                 status = "disabled";
 867         };
 868
 869         pwm2: pwm@ff680020 {
 870                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 871                 reg = <0x0 0xff680020 0x0 0x10>;
 872                 #pwm-cells = <3>;
 873                 clocks = <&cru PCLK_PWM1>;
 874                 clock-names = "pwm";
 875                 status = "disabled";
 876         };
 877
 878         pwm3: pwm@ff680030 {
 879                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 880                 reg = <0x0 0xff680030 0x0 0x10>;
 881                 #pwm-cells = <3>;
 882                 pinctrl-names = "default";
 883                 pinctrl-0 = <&pwm3_pin>;
 884                 clocks = <&cru PCLK_PWM1>;
 885                 clock-names = "pwm";
 886                 status = "disabled";
 887         };
 888
 889         uart2: serial@ff690000 {
 890                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 891                 reg = <0x0 0xff690000 0x0 0x100>;
 892                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 893                 clock-names = "baudclk", "apb_pclk";
 894                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 895                 pinctrl-names = "default";
 896                 pinctrl-0 = <&uart2_xfer>;
 897                 reg-shift = <2>;
 898                 reg-io-width = <4>;
 899                 status = "disabled";
 900         };
 901
 902         mbox: mbox@ff6b0000 {
 903                 compatible = "rockchip,rk3368-mailbox";
 904                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 905                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 906                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 907                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 908                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 909                 clocks = <&cru PCLK_MAILBOX>;
 910                 clock-names = "pclk_mailbox";
 911                 #mbox-cells = <1>;
 912                 status = "disabled";
 913         };
 914
 915         mailbox: mailbox@ff6b0000 {
 916                 compatible = "rockchip,rk3368-mbox-legacy";
 917                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 918                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 919                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 920                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 921                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 922                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 923                 clocks = <&cru PCLK_MAILBOX>;
 924                 clock-names = "pclk_mailbox";
 925                 #mbox-cells = <1>;
 926                 status = "disabled";
 927         };
 928
 929         mailbox_scpi: mailbox-scpi {
 930                 compatible = "rockchip,rk3368-scpi-legacy";
 931                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 932                 chan-nums = <3>;
 933                 status = "disabled";
 934         };
 935
 936         qos_iep: qos@ffad0000 {
 937                 compatible = "syscon";
 938                 reg = <0x0 0xffad0000 0x0 0x20>;
 939         };
 940
 941         qos_isp_r0: qos@ffad0080 {
 942                 compatible = "syscon";
 943                 reg = <0x0 0xffad0080 0x0 0x20>;
 944         };
 945
 946         qos_isp_r1: qos@ffad0100 {
 947                 compatible = "syscon";
 948                 reg = <0x0 0xffad0100 0x0 0x20>;
 949         };
 950
 951         qos_isp_w0: qos@ffad0180 {
 952                 compatible = "syscon";
 953                 reg = <0x0 0xffad0180 0x0 0x20>;
 954         };
 955
 956         qos_isp_w1: qos@ffad0200 {
 957                 compatible = "syscon";
 958                 reg = <0x0 0xffad0200 0x0 0x20>;
 959         };
 960
 961         qos_vip: qos@ffad0280 {
 962                 compatible = "syscon";
 963                 reg = <0x0 0xffad0280 0x0 0x20>;
 964         };
 965
 966         qos_vop: qos@ffad0300 {
 967                 compatible = "syscon";
 968                 reg = <0x0 0xffad0300 0x0 0x20>;
 969         };
 970
 971         qos_rga_r: qos@ffad0380 {
 972                 compatible = "syscon";
 973                 reg = <0x0 0xffad0380 0x0 0x20>;
 974         };
 975
 976         qos_rga_w: qos@ffad0400 {
 977                 compatible = "syscon";
 978                 reg = <0x0 0xffad0400 0x0 0x20>;
 979         };
 980
 981         qos_hevc_r: qos@ffae0000 {
 982                 compatible = "syscon";
 983                 reg = <0x0 0xffae0000 0x0 0x20>;
 984         };
 985
 986         qos_vpu_r: qos@ffae0100 {
 987                 compatible = "syscon";
 988                 reg = <0x0 0xffae0100 0x0 0x20>;
 989         };
 990
 991         qos_vpu_w: qos@ffae0180 {
 992                 compatible = "syscon";
 993                 reg = <0x0 0xffae0180 0x0 0x20>;
 994         };
 995
 996         qos_gpu: qos@ffaf0000 {
 997                 compatible = "syscon";
 998                 reg = <0x0 0xffaf0000 0x0 0x20>;
 999         };
1000
1001         pmu: power-management@ff730000 {
1002                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
1003                 reg = <0x0 0xff730000 0x0 0x1000>;
1004
1005                 power: power-controller {
1006                         compatible = "rockchip,rk3368-power-controller";
1007                         #power-domain-cells = <1>;
1008                         #address-cells = <1>;
1009                         #size-cells = <0>;
1010
1011                         /*
1012                          * Note: Although SCLK_* are the working clocks
1013                          * of device without including on the NOC, needed for
1014                          * synchronous reset.
1015                          *
1016                          * The clocks on the which NOC:
1017                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
1018                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
1019                          * ACLK_RGA is on ACLK_RGA_NIU.
1020                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
1021                          *
1022                          * Which clock are device clocks:
1023                          *      clocks          devices
1024                          *      *_IEP           IEP:Image Enhancement Processor
1025                          *      *_ISP           ISP:Image Signal Processing
1026                          *      *_VIP           VIP:Video Input Processor
1027                          *      *_VOP*          VOP:Visual Output Processor
1028                          *      *_RGA           RGA
1029                          *      *_EDP*          EDP
1030                          *      *_DPHY*         LVDS
1031                          *      *_HDMI          HDMI
1032                          *      *_MIPI_*        MIPI
1033                          */
1034                         pd_vio {
1035                                 reg = <RK3368_PD_VIO>;
1036                                 clocks = <&cru ACLK_IEP>,
1037                                          <&cru ACLK_ISP>,
1038                                          <&cru ACLK_VIP>,
1039                                          <&cru ACLK_RGA>,
1040                                          <&cru ACLK_VOP>,
1041                                          <&cru ACLK_VOP_IEP>,
1042                                          <&cru DCLK_VOP>,
1043                                          <&cru HCLK_IEP>,
1044                                          <&cru HCLK_ISP>,
1045                                          <&cru HCLK_RGA>,
1046                                          <&cru HCLK_VIP>,
1047                                          <&cru HCLK_VOP>,
1048                                          <&cru HCLK_VIO_HDCPMMU>,
1049                                          <&cru PCLK_EDP_CTRL>,
1050                                          <&cru PCLK_HDMI_CTRL>,
1051                                          <&cru PCLK_HDCP>,
1052                                          <&cru PCLK_ISP>,
1053                                          <&cru PCLK_VIP>,
1054                                          <&cru PCLK_DPHYRX>,
1055                                          <&cru PCLK_DPHYTX0>,
1056                                          <&cru PCLK_MIPI_CSI>,
1057                                          <&cru PCLK_MIPI_DSI0>,
1058                                          <&cru SCLK_VOP0_PWM>,
1059                                          <&cru SCLK_EDP_24M>,
1060                                          <&cru SCLK_EDP>,
1061                                          <&cru SCLK_HDCP>,
1062                                          <&cru SCLK_ISP>,
1063                                          <&cru SCLK_RGA>,
1064                                          <&cru SCLK_HDMI_CEC>,
1065                                          <&cru SCLK_HDMI_HDCP>;
1066                                 pm_qos = <&qos_iep>,
1067                                          <&qos_isp_r0>,
1068                                          <&qos_isp_r1>,
1069                                          <&qos_isp_w0>,
1070                                          <&qos_isp_w1>,
1071                                          <&qos_vip>,
1072                                          <&qos_vop>,
1073                                          <&qos_rga_r>,
1074                                          <&qos_rga_w>;
1075                         };
1076                         /*
1077                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
1078                          * (video endecoder & decoder) clocks that on the
1079                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
1080                          */
1081                         pd_video {
1082                                 reg = <RK3368_PD_VIDEO>;
1083                                 clocks = <&cru ACLK_VIDEO>,
1084                                          <&cru HCLK_VIDEO>,
1085                                          <&cru SCLK_HEVC_CABAC>,
1086                                          <&cru SCLK_HEVC_CORE>;
1087                                 pm_qos = <&qos_hevc_r>,
1088                                          <&qos_vpu_r>,
1089                                          <&qos_vpu_w>;
1090                         };
1091                         /*
1092                          * Note: ACLK_GPU is the GPU clock,
1093                          * and on the ACLK_GPU_NIU (NOC).
1094                          */
1095                         pd_gpu_1 {
1096                                 reg = <RK3368_PD_GPU_1>;
1097                                 clocks = <&cru ACLK_GPU_CFG>,
1098                                          <&cru ACLK_GPU_MEM>,
1099                                          <&cru SCLK_GPU_CORE>;
1100                                 pm_qos = <&qos_gpu>;
1101                         };
1102                 };
1103         };
1104
1105         pmugrf: syscon@ff738000 {
1106                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1107                 reg = <0x0 0xff738000 0x0 0x1000>;
1108
1109                 pmu_io_domains: io-domains {
1110                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1111                         status = "disabled";
1112                 };
1113
1114                 reboot-mode {
1115                         compatible = "syscon-reboot-mode";
1116                         offset = <0x200>;
1117                         mode-normal = <BOOT_NORMAL>;
1118                         mode-recovery = <BOOT_RECOVERY>;
1119                         mode-bootloader = <BOOT_FASTBOOT>;
1120                         mode-loader = <BOOT_BL_DOWNLOAD>;
1121                 };
1122         };
1123
1124         cru: clock-controller@ff760000 {
1125                 compatible = "rockchip,rk3368-cru";
1126                 reg = <0x0 0xff760000 0x0 0x1000>;
1127                 rockchip,grf = <&grf>;
1128                 #clock-cells = <1>;
1129                 #reset-cells = <1>;
1130                 assigned-clocks =
1131                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1132                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1133                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1134                         <&cru PCLK_BUS>, <&cru PCLK_PERI>,
1135                         <&cru ACLK_CCI_PRE>;
1136                 assigned-clock-rates =
1137                         <576000000>, <400000000>,
1138                         <300000000>, <300000000>,
1139                         <150000000>, <150000000>,
1140                         <75000000>, <75000000>,
1141                         <576000000>;
1142         };
1143
1144         grf: syscon@ff770000 {
1145                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1146                 reg = <0x0 0xff770000 0x0 0x1000>;
1147                 #address-cells = <1>;
1148                 #size-cells = <1>;
1149
1150                 edp_phy: edp-phy {
1151                         compatible = "rockchip,rk3368-dp-phy";
1152                         clocks = <&cru SCLK_EDP_24M>;
1153                         clock-names = "24m";
1154                         resets = <&cru SRST_EDP_24M>;
1155                         reset-names = "edp_24m";
1156                         #phy-cells = <0>;
1157                         status = "disabled";
1158                 };
1159
1160                 io_domains: io-domains {
1161                         compatible = "rockchip,rk3368-io-voltage-domain";
1162                         status = "disabled";
1163                 };
1164
1165                 u2phy: usb2-phy@700 {
1166                         compatible = "rockchip,rk3368-usb2phy";
1167                         reg = <0x700 0x2c>;
1168                         clocks = <&cru SCLK_OTGPHY0>;
1169                         clock-names = "phyclk";
1170                         #clock-cells = <0>;
1171                         clock-output-names = "usbotg_out";
1172                         assigned-clocks = <&cru SCLK_USBPHY480M>;
1173                         assigned-clock-parents = <&u2phy>;
1174                         status = "disabled";
1175
1176                         u2phy_host: host-port {
1177                                 #phy-cells = <0>;
1178                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1179                                 interrupt-names = "linestate";
1180                                 status = "disabled";
1181                         };
1182                 };
1183         };
1184
1185         wdt: watchdog@ff800000 {
1186                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1187                 reg = <0x0 0xff800000 0x0 0x100>;
1188                 clocks = <&cru PCLK_WDT>;
1189                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1190                 status = "disabled";
1191         };
1192
1193         timer@ff810000 {
1194                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1195                 reg = <0x0 0xff810000 0x0 0x20>;
1196                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1197         };
1198
1199         i2s_2ch: i2s-2ch@ff890000 {
1200                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1201                 reg = <0x0 0xff890000 0x0 0x1000>;
1202                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1203                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1204                 dma-names = "tx", "rx";
1205                 clock-names = "i2s_clk", "i2s_hclk";
1206                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1207                 status = "disabled";
1208         };
1209
1210         i2s_8ch: i2s-8ch@ff898000 {
1211                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1212                 reg = <0x0 0xff898000 0x0 0x1000>;
1213                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1214                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1215                 dma-names = "tx", "rx";
1216                 clock-names = "i2s_clk", "i2s_hclk";
1217                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1218                 pinctrl-names = "default";
1219                 pinctrl-0 = <&i2s_8ch_bus>;
1220                 status = "disabled";
1221         };
1222
1223         iep: iep@ff900000 {
1224                 compatible = "rockchip,iep";
1225                 iommu_enabled = <1>;
1226                 iommus = <&iep_mmu>;
1227                 reg = <0x0 0xff900000 0x0 0x800>;
1228                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1229                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1230                 clock-names = "aclk_iep", "hclk_iep";
1231                 power-domains = <&power RK3368_PD_VIO>;
1232                 allocator = <1>;
1233                 version = <2>;
1234                 status = "disabled";
1235         };
1236
1237         iep_mmu: iommu@ff900800 {
1238                 compatible = "rockchip,iommu";
1239                 reg = <0x0 0xff900800 0x0 0x100>;
1240                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1241                 interrupt-names = "iep_mmu";
1242                 power-domains = <&power RK3368_PD_VIO>;
1243                 #iommu-cells = <0>;
1244                 status = "disabled";
1245         };
1246
1247         isp: isp@ff910000 {
1248                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
1249                 reg = <0x0 0xff910000 0x0 0x4000>;
1250                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1251                 power-domains = <&power RK3368_PD_VIO>;
1252                 clocks =
1253                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1254                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
1255                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
1256                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
1257                 clock-names =
1258                         "aclk_isp", "hclk_isp", "clk_isp",
1259                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1260                         "clk_cif_pll", "hclk_mipiphy1",
1261                         "pclk_dphyrx", "clk_vio0_noc";
1262
1263                 pinctrl-names =
1264                         "default", "isp_dvp8bit2", "isp_dvp10bit",
1265                         "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
1266                         "isp_mipi_fl", "isp_mipi_fl_prefl",
1267                         "isp_flash_as_gpio", "isp_flash_as_trigger_out";
1268                 pinctrl-0 = <&cif_clkout>;
1269                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1270                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1271                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1272                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1273                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1274                 pinctrl-6 = <&cif_clkout>;
1275                 pinctrl-7 = <&cif_clkout &isp_prelight>;
1276                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1277                 pinctrl-9 = <&isp_flash_trigger>;
1278                 rockchip,isp,mipiphy = <2>;
1279                 rockchip,isp,cifphy = <1>;
1280                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1281                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1282                 rockchip,grf = <&grf>;
1283                 rockchip,cru = <&cru>;
1284                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
1285                 rockchip,isp,iommu-enable = <1>;
1286                 iommus = <&isp_mmu>;
1287                 status = "disabled";
1288         };
1289
1290         isp_mmu: iommu@ff914000 {
1291                 compatible = "rockchip,iommu";
1292                 reg = <0x0 0xff914000 0x0 0x100>,
1293                       <0x0 0xff915000 0x0 0x100>;
1294                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1295                 interrupt-names = "isp_mmu";
1296                 clocks = <&cru ACLK_RGA>, <&cru HCLK_ISP>;
1297                 clock-names = "aclk", "hclk";
1298                 rk_iommu,disable_reset_quirk;
1299                 #iommu-cells = <0>;
1300                 power-domains = <&power RK3368_PD_VIO>;
1301                 status = "disabled";
1302         };
1303
1304         vop: vop@ff930000 {
1305                 compatible = "rockchip,rk3368-vop";
1306                 reg = <0x0 0xff930000 0x0 0x2fc>;
1307                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1308                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1309                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1310                 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1311                 assigned-clock-rates = <400000000>, <200000000>;
1312                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1313                 reset-names = "axi", "ahb", "dclk";
1314                 power-domains = <&power RK3368_PD_VIO>;
1315                 iommus = <&vop_mmu>;
1316                 status = "disabled";
1317
1318                 vop_out: port {
1319                         #address-cells = <1>;
1320                         #size-cells = <0>;
1321
1322                         vop_out_mipi: endpoint@0 {
1323                                 reg = <0>;
1324                                 remote-endpoint = <&mipi_in_vop>;
1325                         };
1326
1327                         vop_out_edp: endpoint@1 {
1328                                 reg = <1>;
1329                                 remote-endpoint = <&edp_in_vop>;
1330                         };
1331
1332                         vop_out_hdmi: endpoint@2 {
1333                                 reg = <2>;
1334                                 remote-endpoint = <&hdmi_in_vop>;
1335                         };
1336                 };
1337         };
1338
1339         display_subsystem: display-subsystem {
1340                 compatible = "rockchip,display-subsystem";
1341                 ports = <&vop_out>;
1342                 status = "disabled";
1343         };
1344
1345         vop_mmu: iommu@ff930300 {
1346                 compatible = "rockchip,iommu";
1347                 reg = <0x0 0xff930300 0x0 0x100>;
1348                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1349                 interrupt-names = "vop_mmu";
1350                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1351                 clock-names = "aclk", "hclk";
1352                 power-domains = <&power RK3368_PD_VIO>;
1353                 #iommu-cells = <0>;
1354                 status = "disabled";
1355         };
1356
1357         mipi_dsi_host: mipi-dsi-host@ff960000 {
1358                 compatible = "rockchip,rk3368-mipi-dsi";
1359                 reg = <0x0 0xff960000 0x0 0x4000>;
1360                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1361                 clocks = <&cru PCLK_MIPI_DSI0>;
1362                 clock-names = "pclk";
1363                 resets = <&cru SRST_MIPIDSI0>;
1364                 reset-names = "apb";
1365                 phys = <&mipi_dphy>;
1366                 phy-names = "mipi_dphy";
1367                 rockchip,grf = <&grf>;
1368                 power-domains = <&power RK3368_PD_VIO>;
1369                 #address-cells = <1>;
1370                 #size-cells = <0>;
1371                 status = "disabled";
1372
1373                 ports {
1374                         port {
1375                                 mipi_in_vop: endpoint {
1376                                         remote-endpoint = <&vop_out_mipi>;
1377                                 };
1378                         };
1379                 };
1380         };
1381
1382         mipi_dphy: mipi-dphy@ff968000 {
1383                 compatible = "rockchip,rk3368-mipi-dphy";
1384                 reg = <0x0 0xff968000 0x0 0x4000>;
1385                 #phy-cells = <0>;
1386                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1387                 clock-names = "ref", "pclk";
1388                 resets = <&cru SRST_MIPIDPHYTX>;
1389                 reset-names = "apb";
1390                 status = "disabled";
1391         };
1392
1393         edp: edp@ff970000 {
1394                 compatible = "rockchip,rk3368-edp";
1395                 reg = <0x0 0xff970000 0x0 0x8000>;
1396                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1397                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1398                 clock-names = "dp", "pclk";
1399                 resets = <&cru SRST_EDP>;
1400                 reset-names = "dp";
1401                 power-domains = <&power RK3368_PD_VIO>;
1402                 rockchip,grf = <&grf>;
1403                 phys = <&edp_phy>;
1404                 phy-names = "dp";
1405                 pinctrl-names = "default";
1406                 pinctrl-0 = <&edp_hpd>;
1407                 status = "disabled";
1408
1409                 ports {
1410                         #address-cells = <1>;
1411                         #size-cells = <0>;
1412
1413                         edp_in: port@0 {
1414                                 reg = <0>;
1415
1416                                 edp_in_vop: endpoint {
1417                                         remote-endpoint = <&vop_out_edp>;
1418                                 };
1419                         };
1420                 };
1421         };
1422
1423         hdmi: hdmi@ff980000 {
1424                 compatible = "rockchip,rk3368-dw-hdmi";
1425                 reg = <0x0 0xff980000 0x0 0x20000>;
1426                 reg-io-width = <4>;
1427                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1428                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1429                 clock-names = "iahb", "isfr", "cec";
1430                 pinctrl-names = "default";
1431                 pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>;
1432                 resets = <&cru SRST_HDMI>;
1433                 reset-names = "hdmi";
1434                 power-domains = <&power RK3368_PD_VIO>;
1435                 rockchip,grf = <&grf>;
1436                 status = "disabled";
1437
1438                 ports {
1439                         port {
1440                                 hdmi_in_vop: endpoint {
1441                                         remote-endpoint = <&vop_out_hdmi>;
1442                                 };
1443                         };
1444                 };
1445         };
1446
1447         hevc_mmu: iommu@ff9a0440 {
1448                 compatible = "rockchip,iommu";
1449                 reg = <0x0 0xff9a0440 0x0 0x40>,
1450                       <0x0 0xff9a0480 0x0 0x40>;
1451                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1452                 interrupt-names = "hevc_mmu";
1453                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1454                 clock-names = "aclk", "hclk";
1455                 power-domains = <&power RK3368_PD_VIDEO>;
1456                 #iommu-cells = <0>;
1457                 status = "disabled";
1458         };
1459
1460         vpu_mmu: iommu@ff9a0800 {
1461                 compatible = "rockchip,iommu";
1462                 reg = <0x0 0xff9a0800 0x0 0x100>;
1463                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1464                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1465                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1466                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1467                 clock-names = "aclk", "hclk";
1468                 power-domains = <&power RK3368_PD_VIDEO>;
1469                 #iommu-cells = <0>;
1470                 status = "disabled";
1471         };
1472
1473         vpu: vpu_service {
1474                 compatible = "rockchip,vpu_sub";
1475                 iommu_enabled = <1>;
1476                 iommus = <&vpu_mmu>;
1477                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1478                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1479                 interrupt-names = "irq_enc","irq_dec";
1480                 dev_mode = <0>;
1481                 name = "vpu_service";
1482                 allocator = <1>;
1483         };
1484
1485         hevc: hevc_service {
1486                 compatible = "rockchip,hevc_sub";
1487                 iommu_enabled = <1>;
1488                 iommus = <&hevc_mmu>;
1489                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1490                 interrupt-names = "irq_dec";
1491                 dev_mode = <1>;
1492                 name = "hevc_service";
1493                 allocator = <1>;
1494         };
1495
1496         vpu_combo: vpu_combo@ff9a0000 {
1497                 compatible = "rockchip,vpu_combo";
1498                 reg = <0x0 0xff9a0000 0x0 0x440>;
1499                 rockchip,grf = <&grf>;
1500                 subcnt = <2>;
1501                 rockchip,sub = <&vpu>, <&hevc>;
1502                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
1503                          <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
1504                 clock-names = "aclk_vcodec", "hclk_vcodec",
1505                               "clk_core", "clk_cabac";
1506                 resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
1507                          <&cru SRST_VIDEO>;
1508                 reset-names = "video_a", "video_h", "video";
1509                 mode_bit = <12>;
1510                 mode_ctrl = <0x418>;
1511                 name = "vpu_combo";
1512                 power-domains = <&power RK3368_PD_VIDEO>;
1513                 status = "disabled";
1514         };
1515
1516         gic: interrupt-controller@ffb71000 {
1517                 compatible = "arm,gic-400";
1518                 interrupt-controller;
1519                 #interrupt-cells = <3>;
1520                 #address-cells = <0>;
1521
1522                 reg = <0x0 0xffb71000 0x0 0x1000>,
1523                       <0x0 0xffb72000 0x0 0x2000>,
1524                       <0x0 0xffb74000 0x0 0x2000>,
1525                       <0x0 0xffb76000 0x0 0x2000>;
1526                 interrupts = <GIC_PPI 9
1527                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1528         };
1529
1530         gpu: rogue-g6110@ffa30000 {
1531                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1532                 reg = <0x0 0xffa30000 0x0 0x10000>;
1533                 clocks =
1534                         <&cru SCLK_GPU_CORE>,
1535                         <&cru ACLK_GPU_MEM>,
1536                         <&cru ACLK_GPU_CFG>;
1537                 clock-names =
1538                         "sclk_gpu_core",
1539                         "aclk_gpu_mem",
1540                         "aclk_gpu_cfg";
1541                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1542                 interrupt-names = "rogue-g6110-irq";
1543                 power-domains = <&power RK3368_PD_GPU_1>;
1544                 operating-points-v2 = <&gpu_opp_table>;
1545                 #cooling-cells = <2>; /* min followed by max */
1546                 gpu_power_model: power_model {
1547                         compatible = "arm,mali-simple-power-model";
1548                         voltage = <900>;
1549                         frequency = <500>;
1550                         static-power = <300>;
1551                         dynamic-power = <396>;
1552                         ts = <32000 4700 (-80) 2>;
1553                         thermal-zone = "gpu-thermal";
1554                 };
1555         };
1556
1557         gpu_opp_table: gpu_opp_table {
1558                 compatible = "operating-points-v2";
1559                 opp-shared;
1560
1561                 opp@200000000 {
1562                         opp-hz = /bits/ 64 <200000000>;
1563                         opp-microvolt = <1100000>;
1564                 };
1565                 opp@288000000 {
1566                         opp-hz = /bits/ 64 <288000000>;
1567                         opp-microvolt = <1100000>;
1568                 };
1569                 opp@400000000 {
1570                         opp-hz = /bits/ 64 <400000000>;
1571                         opp-microvolt = <1100000>;
1572                 };
1573                 opp@576000000 {
1574                         opp-hz = /bits/ 64 <576000000>;
1575                         opp-microvolt = <1200000>;
1576                 };
1577         };
1578
1579         efuse: efuse@ffb00000 {
1580                 compatible = "rockchip,rk3368-efuse";
1581                 reg = <0x0 0xffb00000 0x0 0x20>;
1582                 #address-cells = <1>;
1583                 #size-cells = <1>;
1584                 clocks = <&cru PCLK_EFUSE256>;
1585                 clock-names = "pclk_efuse";
1586
1587                 /* Data cells */
1588                 cpu_leakage: cpu-leakage@17 {
1589                         reg = <0x17 0x1>;
1590                 };
1591                 temp_adjust: temp-adjust@1f {
1592                         reg = <0x1f 0x1>;
1593                 };
1594         };
1595
1596         pinctrl: pinctrl {
1597                 compatible = "rockchip,rk3368-pinctrl";
1598                 rockchip,grf = <&grf>;
1599                 rockchip,pmu = <&pmugrf>;
1600                 #address-cells = <0x2>;
1601                 #size-cells = <0x2>;
1602                 ranges;
1603
1604                 gpio0: gpio0@ff750000 {
1605                         compatible = "rockchip,gpio-bank";
1606                         reg = <0x0 0xff750000 0x0 0x100>;
1607                         clocks = <&cru PCLK_GPIO0>;
1608                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1609
1610                         gpio-controller;
1611                         #gpio-cells = <0x2>;
1612
1613                         interrupt-controller;
1614                         #interrupt-cells = <0x2>;
1615                 };
1616
1617                 gpio1: gpio1@ff780000 {
1618                         compatible = "rockchip,gpio-bank";
1619                         reg = <0x0 0xff780000 0x0 0x100>;
1620                         clocks = <&cru PCLK_GPIO1>;
1621                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1622
1623                         gpio-controller;
1624                         #gpio-cells = <0x2>;
1625
1626                         interrupt-controller;
1627                         #interrupt-cells = <0x2>;
1628                 };
1629
1630                 gpio2: gpio2@ff790000 {
1631                         compatible = "rockchip,gpio-bank";
1632                         reg = <0x0 0xff790000 0x0 0x100>;
1633                         clocks = <&cru PCLK_GPIO2>;
1634                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1635
1636                         gpio-controller;
1637                         #gpio-cells = <0x2>;
1638
1639                         interrupt-controller;
1640                         #interrupt-cells = <0x2>;
1641                 };
1642
1643                 gpio3: gpio3@ff7a0000 {
1644                         compatible = "rockchip,gpio-bank";
1645                         reg = <0x0 0xff7a0000 0x0 0x100>;
1646                         clocks = <&cru PCLK_GPIO3>;
1647                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1648
1649                         gpio-controller;
1650                         #gpio-cells = <0x2>;
1651
1652                         interrupt-controller;
1653                         #interrupt-cells = <0x2>;
1654                 };
1655
1656                 pcfg_pull_up: pcfg-pull-up {
1657                         bias-pull-up;
1658                 };
1659
1660                 pcfg_pull_down: pcfg-pull-down {
1661                         bias-pull-down;
1662                 };
1663
1664                 pcfg_pull_none: pcfg-pull-none {
1665                         bias-disable;
1666                 };
1667
1668                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1669                         bias-disable;
1670                         drive-strength = <12>;
1671                 };
1672
1673                 edp {
1674                         edp_hpd: edp-hpd {
1675                                 rockchip,pins = <2 23 RK_FUNC_2 &pcfg_pull_none>;
1676                         };
1677                 };
1678
1679                 emmc {
1680                         emmc_clk: emmc-clk {
1681                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1682                         };
1683
1684                         emmc_cmd: emmc-cmd {
1685                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1686                         };
1687
1688                         emmc_pwr: emmc-pwr {
1689                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1690                         };
1691
1692                         emmc_bus1: emmc-bus1 {
1693                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1694                         };
1695
1696                         emmc_bus4: emmc-bus4 {
1697                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1698                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1699                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1700                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1701                         };
1702
1703                         emmc_bus8: emmc-bus8 {
1704                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1705                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1706                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1707                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1708                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1709                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1710                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1711                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1712                         };
1713                 };
1714
1715                 gmac {
1716                         rgmii_pins: rgmii-pins {
1717                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1718                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1719                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1720                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1721                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1722                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1723                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1724                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1725                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1726                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1727                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1728                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1729                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1730                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1731                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1732                         };
1733
1734                         rmii_pins: rmii-pins {
1735                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1736                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1737                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1738                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1739                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1740                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1741                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1742                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1743                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1744                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1745                         };
1746                 };
1747
1748                 hdmi {
1749                         hdmi_cec: hdmi-cec {
1750                                 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1751                         };
1752
1753                         hdmi_i2c_xfer: hdmi-i2c-xfer {
1754                                 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1755                                                 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1756                         };
1757                 };
1758
1759                 i2c0 {
1760                         i2c0_xfer: i2c0-xfer {
1761                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1762                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1763                         };
1764                 };
1765
1766                 i2c1 {
1767                         i2c1_xfer: i2c1-xfer {
1768                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1769                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1770                         };
1771                 };
1772
1773                 i2c2 {
1774                         i2c2_xfer: i2c2-xfer {
1775                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1776                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1777                         };
1778                 };
1779
1780                 i2c3 {
1781                         i2c3_xfer: i2c3-xfer {
1782                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1783                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1784                         };
1785                 };
1786
1787                 i2c4 {
1788                         i2c4_xfer: i2c4-xfer {
1789                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1790                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1791                         };
1792                 };
1793
1794                 i2c5 {
1795                         i2c5_xfer: i2c5-xfer {
1796                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1797                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1798                         };
1799                 };
1800
1801                 i2s {
1802                         i2s_8ch_bus: i2s-8ch-bus {
1803                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1804                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1805                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1806                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1807                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1808                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1809                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1810                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1811                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1812                         };
1813                 };
1814
1815                 pwm0 {
1816                         pwm0_pin: pwm0-pin {
1817                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1818                         };
1819
1820                         vop_pwm_pin: vop-pwm {
1821                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1822                         };
1823                 };
1824
1825                 pwm1 {
1826                         pwm1_pin: pwm1-pin {
1827                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1828                         };
1829                 };
1830
1831                 pwm3 {
1832                         pwm3_pin: pwm3-pin {
1833                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1834                         };
1835                 };
1836
1837                 sdio0 {
1838                         sdio0_bus1: sdio0-bus1 {
1839                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1840                         };
1841
1842                         sdio0_bus4: sdio0-bus4 {
1843                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1844                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1845                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1846                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1847                         };
1848
1849                         sdio0_cmd: sdio0-cmd {
1850                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1851                         };
1852
1853                         sdio0_clk: sdio0-clk {
1854                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1855                         };
1856
1857                         sdio0_cd: sdio0-cd {
1858                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1859                         };
1860
1861                         sdio0_wp: sdio0-wp {
1862                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1863                         };
1864
1865                         sdio0_pwr: sdio0-pwr {
1866                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1867                         };
1868
1869                         sdio0_bkpwr: sdio0-bkpwr {
1870                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1871                         };
1872
1873                         sdio0_int: sdio0-int {
1874                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1875                         };
1876                 };
1877
1878                 sdmmc {
1879                         sdmmc_clk: sdmmc-clk {
1880                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1881                         };
1882
1883                         sdmmc_cmd: sdmmc-cmd {
1884                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1885                         };
1886
1887                         sdmmc_cd: sdmmc-cd {
1888                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1889                         };
1890
1891                         sdmmc_bus1: sdmmc-bus1 {
1892                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1893                         };
1894
1895                         sdmmc_bus4: sdmmc-bus4 {
1896                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1897                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1898                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1899                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1900                         };
1901                 };
1902
1903                 spi0 {
1904                         spi0_clk: spi0-clk {
1905                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1906                         };
1907                         spi0_cs0: spi0-cs0 {
1908                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1909                         };
1910                         spi0_cs1: spi0-cs1 {
1911                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1912                         };
1913                         spi0_tx: spi0-tx {
1914                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1915                         };
1916                         spi0_rx: spi0-rx {
1917                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1918                         };
1919                 };
1920
1921                 spi1 {
1922                         spi1_clk: spi1-clk {
1923                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1924                         };
1925                         spi1_cs0: spi1-cs0 {
1926                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1927                         };
1928                         spi1_cs1: spi1-cs1 {
1929                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1930                         };
1931                         spi1_rx: spi1-rx {
1932                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1933                         };
1934                         spi1_tx: spi1-tx {
1935                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1936                         };
1937                 };
1938
1939                 spi2 {
1940                         spi2_clk: spi2-clk {
1941                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1942                         };
1943                         spi2_cs0: spi2-cs0 {
1944                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1945                         };
1946                         spi2_rx: spi2-rx {
1947                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1948                         };
1949                         spi2_tx: spi2-tx {
1950                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1951                         };
1952                 };
1953
1954                 uart0 {
1955                         uart0_xfer: uart0-xfer {
1956                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1957                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1958                         };
1959
1960                         uart0_cts: uart0-cts {
1961                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1962                         };
1963
1964                         uart0_rts: uart0-rts {
1965                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1966                         };
1967                 };
1968
1969                 uart1 {
1970                         uart1_xfer: uart1-xfer {
1971                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1972                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1973                         };
1974
1975                         uart1_cts: uart1-cts {
1976                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1977                         };
1978
1979                         uart1_rts: uart1-rts {
1980                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1981                         };
1982                 };
1983
1984                 uart2 {
1985                         uart2_xfer: uart2-xfer {
1986                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1987                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1988                         };
1989                         /* no rts / cts for uart2 */
1990                 };
1991
1992                 uart3 {
1993                         uart3_xfer: uart3-xfer {
1994                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1995                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1996                         };
1997
1998                         uart3_cts: uart3-cts {
1999                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
2000                         };
2001
2002                         uart3_rts: uart3-rts {
2003                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
2004                         };
2005                 };
2006
2007                 uart4 {
2008                         uart4_xfer: uart4-xfer {
2009                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
2010                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
2011                         };
2012
2013                         uart4_cts: uart4-cts {
2014                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
2015                         };
2016
2017                         uart4_rts: uart4-rts {
2018                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
2019                         };
2020                 };
2021
2022                 isp {
2023                         cif_clkout: cif-clkout {
2024                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2025                         };
2026
2027                         isp_dvp_d2d9: isp-dvp-d2d9 {
2028                                 rockchip,pins =
2029                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2030                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2031                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2032                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2033                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2034                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2035                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2036                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2037                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
2038                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
2039                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
2040                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
2041                         };
2042
2043                         isp_dvp_d0d1: isp-dvp-d0d1 {
2044                                 rockchip,pins =
2045                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2046                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
2047                         };
2048
2049                         isp_dvp_d10d11:isp_d10d11 {
2050                                 rockchip,pins =
2051                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2052                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2053                         };
2054
2055                         isp_dvp_d0d7: isp-dvp-d0d7 {
2056                                 rockchip,pins =
2057                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2058                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
2059                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2060                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2061                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2062                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2063                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2064                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2065                         };
2066
2067                         isp_dvp_d4d11: isp-dvp-d4d11 {
2068                                 rockchip,pins =
2069                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2070                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2071                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2072                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2073                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2074                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2075                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2076                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2077                         };
2078
2079                         isp_shutter: isp-shutter {
2080                                 rockchip,pins =
2081                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2082                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2083                         };
2084
2085                         isp_flash_trigger: isp-flash-trigger {
2086                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2087                         };
2088
2089                         isp_prelight: isp-prelight {
2090                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2091                         };
2092
2093                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2094                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2095                         };
2096                 };
2097         };
2098 };