2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/display/mipi_dsi.h>
50 #include <dt-bindings/power/rk3368-power.h>
51 #include <dt-bindings/soc/rockchip_boot-mode.h>
54 compatible = "rockchip,rk3368";
55 interrupt-parent = <&gic>;
78 #address-cells = <0x2>;
114 entry-method = "psci";
116 cpu_sleep: cpu-sleep-0 {
117 compatible = "arm,idle-state";
118 arm,psci-suspend-param = <0x1010000>;
119 entry-latency-us = <0x3fffffff>;
120 exit-latency-us = <0x40000000>;
121 min-residency-us = <0xffffffff>;
127 compatible = "arm,cortex-a53", "arm,armv8";
129 cpu-idle-states = <&cpu_sleep>;
130 enable-method = "psci";
131 clocks = <&cru ARMCLKL>;
132 operating-points-v2 = <&cluster1_opp>;
137 compatible = "arm,cortex-a53", "arm,armv8";
139 cpu-idle-states = <&cpu_sleep>;
140 enable-method = "psci";
141 clocks = <&cru ARMCLKL>;
142 operating-points-v2 = <&cluster1_opp>;
147 compatible = "arm,cortex-a53", "arm,armv8";
149 cpu-idle-states = <&cpu_sleep>;
150 enable-method = "psci";
151 clocks = <&cru ARMCLKL>;
152 operating-points-v2 = <&cluster1_opp>;
157 compatible = "arm,cortex-a53", "arm,armv8";
159 cpu-idle-states = <&cpu_sleep>;
160 enable-method = "psci";
161 clocks = <&cru ARMCLKL>;
162 operating-points-v2 = <&cluster1_opp>;
167 compatible = "arm,cortex-a53", "arm,armv8";
169 cpu-idle-states = <&cpu_sleep>;
170 enable-method = "psci";
171 clocks = <&cru ARMCLKB>;
172 operating-points-v2 = <&cluster0_opp>;
177 compatible = "arm,cortex-a53", "arm,armv8";
179 cpu-idle-states = <&cpu_sleep>;
180 enable-method = "psci";
181 clocks = <&cru ARMCLKB>;
182 operating-points-v2 = <&cluster0_opp>;
187 compatible = "arm,cortex-a53", "arm,armv8";
189 cpu-idle-states = <&cpu_sleep>;
190 enable-method = "psci";
191 clocks = <&cru ARMCLKB>;
192 operating-points-v2 = <&cluster0_opp>;
197 compatible = "arm,cortex-a53", "arm,armv8";
199 cpu-idle-states = <&cpu_sleep>;
200 enable-method = "psci";
201 clocks = <&cru ARMCLKB>;
202 operating-points-v2 = <&cluster0_opp>;
206 cluster0_opp: opp_table0 {
207 compatible = "operating-points-v2";
211 opp-hz = /bits/ 64 <408000000>;
212 opp-microvolt = <1200000>;
213 clock-latency-ns = <40000>;
217 opp-hz = /bits/ 64 <600000000>;
218 opp-microvolt = <1200000>;
221 opp-hz = /bits/ 64 <816000000>;
222 opp-microvolt = <1200000>;
225 opp-hz = /bits/ 64 <1008000000>;
226 opp-microvolt = <1200000>;
229 opp-hz = /bits/ 64 <1200000000>;
230 opp-microvolt = <1200000>;
234 cluster1_opp: opp_table1 {
235 compatible = "operating-points-v2";
239 opp-hz = /bits/ 64 <408000000>;
240 opp-microvolt = <1200000>;
241 clock-latency-ns = <40000>;
245 opp-hz = /bits/ 64 <600000000>;
246 opp-microvolt = <1200000>;
249 opp-hz = /bits/ 64 <816000000>;
250 opp-microvolt = <1200000>;
253 opp-hz = /bits/ 64 <1008000000>;
254 opp-microvolt = <1200000>;
259 compatible = "arm,armv8-pmuv3";
260 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
268 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
269 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
270 <&cpu_b2>, <&cpu_b3>;
274 compatible = "arm,amba-bus";
275 #address-cells = <2>;
279 dmac_peri: dma-controller@ff250000 {
280 compatible = "arm,pl330", "arm,primecell";
281 reg = <0x0 0xff250000 0x0 0x4000>;
282 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cru ACLK_DMAC_PERI>;
286 clock-names = "apb_pclk";
287 arm,pl330-broken-no-flushp;
288 peripherals-req-type-burst;
291 dmac_bus: dma-controller@ff600000 {
292 compatible = "arm,pl330", "arm,primecell";
293 reg = <0x0 0xff600000 0x0 0x4000>;
294 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&cru ACLK_DMAC_BUS>;
298 clock-names = "apb_pclk";
299 arm,pl330-broken-no-flushp;
300 peripherals-req-type-burst;
305 compatible = "arm,psci-0.2";
310 compatible = "arm,armv8-timer";
311 interrupts = <GIC_PPI 13
312 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
314 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
316 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
318 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
322 compatible = "fixed-clock";
323 clock-frequency = <24000000>;
324 clock-output-names = "xin24m";
328 sdmmc: rksdmmc@ff0c0000 {
329 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
330 reg = <0x0 0xff0c0000 0x0 0x4000>;
331 clock-freq-min-max = <400000 150000000>;
332 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
333 clock-names = "biu", "ciu";
334 fifo-depth = <0x100>;
335 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
339 sdio0: dwmmc@ff0d0000 {
340 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
341 reg = <0x0 0xff0d0000 0x0 0x4000>;
342 clock-freq-min-max = <400000 150000000>;
343 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
344 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
345 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
346 fifo-depth = <0x100>;
347 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
351 emmc: rksdmmc@ff0f0000 {
352 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
353 reg = <0x0 0xff0f0000 0x0 0x4000>;
354 clock-freq-min-max = <400000 150000000>;
355 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
356 clock-names = "biu", "ciu";
357 fifo-depth = <0x100>;
358 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
362 saradc: saradc@ff100000 {
363 compatible = "rockchip,saradc";
364 reg = <0x0 0xff100000 0x0 0x100>;
365 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
366 #io-channel-cells = <1>;
367 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
368 clock-names = "saradc", "apb_pclk";
369 resets = <&cru SRST_SARADC>;
370 reset-names = "saradc-apb";
375 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
376 reg = <0x0 0xff110000 0x0 0x1000>;
377 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
378 clock-names = "spiclk", "apb_pclk";
379 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
382 #address-cells = <1>;
388 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
389 reg = <0x0 0xff120000 0x0 0x1000>;
390 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
391 clock-names = "spiclk", "apb_pclk";
392 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
395 #address-cells = <1>;
401 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
402 reg = <0x0 0xff130000 0x0 0x1000>;
403 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
404 clock-names = "spiclk", "apb_pclk";
405 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
408 #address-cells = <1>;
414 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
415 reg = <0x0 0xff650000 0x0 0x1000>;
416 clocks = <&cru PCLK_I2C0>;
418 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&i2c0_xfer>;
421 #address-cells = <1>;
427 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
428 reg = <0x0 0xff140000 0x0 0x1000>;
429 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
433 clocks = <&cru PCLK_I2C2>;
434 pinctrl-names = "default";
435 pinctrl-0 = <&i2c2_xfer>;
440 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
441 reg = <0x0 0xff150000 0x0 0x1000>;
442 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
446 clocks = <&cru PCLK_I2C3>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&i2c3_xfer>;
453 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
454 reg = <0x0 0xff160000 0x0 0x1000>;
455 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
456 #address-cells = <1>;
459 clocks = <&cru PCLK_I2C4>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&i2c4_xfer>;
466 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
467 reg = <0x0 0xff170000 0x0 0x1000>;
468 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
469 #address-cells = <1>;
472 clocks = <&cru PCLK_I2C5>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&i2c5_xfer>;
478 uart0: serial@ff180000 {
479 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
480 reg = <0x0 0xff180000 0x0 0x100>;
481 clock-frequency = <24000000>;
482 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
483 clock-names = "baudclk", "apb_pclk";
484 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
490 uart1: serial@ff190000 {
491 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
492 reg = <0x0 0xff190000 0x0 0x100>;
493 clock-frequency = <24000000>;
494 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
495 clock-names = "baudclk", "apb_pclk";
496 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
502 uart3: serial@ff1b0000 {
503 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
504 reg = <0x0 0xff1b0000 0x0 0x100>;
505 clock-frequency = <24000000>;
506 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
507 clock-names = "baudclk", "apb_pclk";
508 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
514 uart4: serial@ff1c0000 {
515 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
516 reg = <0x0 0xff1c0000 0x0 0x100>;
517 clock-frequency = <24000000>;
518 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
519 clock-names = "baudclk", "apb_pclk";
520 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
526 gmac: ethernet@ff290000 {
527 compatible = "rockchip,rk3368-gmac";
528 reg = <0x0 0xff290000 0x0 0x10000>;
529 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
530 interrupt-names = "macirq";
531 rockchip,grf = <&grf>;
532 clocks = <&cru SCLK_MAC>,
533 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
534 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
535 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
536 clock-names = "stmmaceth",
537 "mac_clk_rx", "mac_clk_tx",
538 "clk_mac_ref", "clk_mac_refout",
539 "aclk_mac", "pclk_mac";
543 nandc0: nandc@ff400000 {
544 compatible = "rockchip,rk-nandc";
545 reg = <0x0 0xff400000 0x0 0x4000>;
546 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
549 clock-names = "clk_nandc", "hclk_nandc";
553 usb_host0_ehci: usb@ff500000 {
554 compatible = "generic-ehci";
555 reg = <0x0 0xff500000 0x0 0x100>;
556 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&cru HCLK_HOST0>;
558 clock-names = "usbhost";
562 usb_otg: usb@ff580000 {
563 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
565 reg = <0x0 0xff580000 0x0 0x40000>;
566 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&cru HCLK_OTG0>;
570 g-np-tx-fifo-size = <16>;
571 g-rx-fifo-size = <275>;
572 g-tx-fifo-size = <256 128 128 64 64 32>;
577 ddrpctl: syscon@ff610000 {
578 compatible = "rockchip,rk3368-ddrpctl", "syscon";
579 reg = <0x0 0xff610000 0x0 0x400>;
583 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
584 reg = <0x0 0xff660000 0x0 0x1000>;
585 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
586 #address-cells = <1>;
589 clocks = <&cru PCLK_I2C1>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&i2c1_xfer>;
596 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
597 reg = <0x0 0xff680000 0x0 0x10>;
599 pinctrl-names = "default";
600 pinctrl-0 = <&pwm0_pin>;
601 clocks = <&cru PCLK_PWM1>;
607 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
608 reg = <0x0 0xff680010 0x0 0x10>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&pwm1_pin>;
612 clocks = <&cru PCLK_PWM1>;
618 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
619 reg = <0x0 0xff680020 0x0 0x10>;
621 clocks = <&cru PCLK_PWM1>;
627 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
628 reg = <0x0 0xff680030 0x0 0x10>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&pwm3_pin>;
632 clocks = <&cru PCLK_PWM1>;
637 uart2: serial@ff690000 {
638 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
639 reg = <0x0 0xff690000 0x0 0x100>;
640 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
641 clock-names = "baudclk", "apb_pclk";
642 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&uart2_xfer>;
650 pmu: power-management@ff730000 {
651 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
652 reg = <0x0 0xff730000 0x0 0x1000>;
654 power: power-controller {
656 compatible = "rockchip,rk3368-power-controller";
657 #power-domain-cells = <1>;
658 #address-cells = <1>;
662 * Note: Although SCLK_* are the working clocks
663 * of device without including on the NOC, needed for
666 * The clocks on the which NOC:
667 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
668 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
669 * ACLK_RGA is on ACLK_RGA_NIU.
670 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
672 * Which clock are device clocks:
674 * *_IEP IEP:Image Enhancement Processor
675 * *_ISP ISP:Image Signal Processing
676 * *_VIP VIP:Video Input Processor
677 * *_VOP* VOP:Visual Output Processor
685 reg = <RK3368_PD_VIO>;
686 clocks = <&cru ACLK_IEP>,
698 <&cru HCLK_VIO_HDCPMMU>,
699 <&cru PCLK_EDP_CTRL>,
700 <&cru PCLK_HDMI_CTRL>,
706 <&cru PCLK_MIPI_CSI>,
707 <&cru PCLK_MIPI_DSI0>,
708 <&cru SCLK_VOP0_PWM>,
714 <&cru SCLK_HDMI_CEC>,
715 <&cru SCLK_HDMI_HDCP>;
718 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
719 * (video endecoder & decoder) clocks that on the
720 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
723 reg = <RK3368_PD_VIDEO>;
724 clocks = <&cru ACLK_VIDEO>,
726 <&cru SCLK_HEVC_CABAC>,
727 <&cru SCLK_HEVC_CORE>;
730 * Note: ACLK_GPU is the GPU clock,
731 * and on the ACLK_GPU_NIU (NOC).
734 reg = <RK3368_PD_GPU_1>;
735 clocks = <&cru ACLK_GPU_CFG>,
737 <&cru SCLK_GPU_CORE>;
742 pmugrf: syscon@ff738000 {
743 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
744 reg = <0x0 0xff738000 0x0 0x1000>;
747 compatible = "syscon-reboot-mode";
749 mode-normal = <BOOT_NORMAL>;
750 mode-recovery = <BOOT_RECOVERY>;
751 mode-bootloader = <BOOT_FASTBOOT>;
752 mode-loader = <BOOT_LOADER>;
757 cru: clock-controller@ff760000 {
758 compatible = "rockchip,rk3368-cru";
759 reg = <0x0 0xff760000 0x0 0x1000>;
760 rockchip,grf = <&grf>;
764 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
766 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
767 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
768 <&cru PCLK_BUS>, <&cru PCLK_PERI>;
769 assigned-clock-rates =
770 <576000000>, <400000000>,
772 <300000000>, <300000000>,
773 <150000000>, <150000000>,
774 <75000000>, <75000000>;
777 grf: syscon@ff770000 {
778 compatible = "rockchip,rk3368-grf", "syscon";
779 reg = <0x0 0xff770000 0x0 0x1000>;
782 wdt: watchdog@ff800000 {
783 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
784 reg = <0x0 0xff800000 0x0 0x100>;
785 clocks = <&cru PCLK_WDT>;
786 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
790 gic: interrupt-controller@ffb71000 {
791 compatible = "arm,gic-400";
792 interrupt-controller;
793 #interrupt-cells = <3>;
794 #address-cells = <0>;
796 reg = <0x0 0xffb71000 0x0 0x1000>,
797 <0x0 0xffb72000 0x0 0x2000>,
798 <0x0 0xffb74000 0x0 0x2000>,
799 <0x0 0xffb76000 0x0 0x2000>;
800 interrupts = <GIC_PPI 9
801 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
804 gpu: rogue-g6110@ffa30000 {
805 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
806 reg = <0x0 0xffa30000 0x0 0x10000>;
808 <&cru SCLK_GPU_CORE>,
822 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
823 interrupt-names = "rogue-g6110-irq";
826 i2s_2ch: i2s-2ch@ff890000 {
827 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
828 reg = <0x0 0xff890000 0x0 0x1000>;
829 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
830 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
831 dma-names = "tx", "rx";
832 clock-names = "i2s_clk", "i2s_hclk";
833 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
837 i2s_8ch: i2s-8ch@ff898000 {
838 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
839 reg = <0x0 0xff898000 0x0 0x1000>;
840 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
841 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
842 dma-names = "tx", "rx";
843 clock-names = "i2s_clk", "i2s_hclk";
844 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
845 pinctrl-names = "default";
846 pinctrl-0 = <&i2s_8ch_bus>;
851 compatible = "rockchip,rk3368-isp", "rockchip,isp";
852 reg = <0x0 0xff910000 0x0 0x10000>;
853 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
854 /*power-domains = <&power PD_VIO>;*/
856 <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
857 <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
858 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
859 <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
861 "aclk_isp", "hclk_isp", "clk_isp",
862 "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
863 "clk_cif_pll", "hclk_mipiphy1",
864 "pclk_dphyrx", "clk_vio0_noc";
866 "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
867 "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
868 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
869 "isp_flash_as_trigger_out";
870 pinctrl-0 = <&cif_clkout>;
871 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
872 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
873 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
874 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
875 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
876 pinctrl-6 = <&cif_clkout>;
877 pinctrl-7 = <&cif_clkout &isp_prelight>;
878 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
879 pinctrl-9 = <&isp_flash_trigger>;
880 rockchip,isp,mipiphy = <2>;
881 rockchip,isp,cifphy = <1>;
882 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
883 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
884 rockchip,grf = <&grf>;
885 rockchip,cru = <&cru>;
886 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
887 rockchip,isp,iommu_enable = <1>;
892 compatible = "rockchip,rga2";
894 reg = <0x0 0xff920000 0x0 0x1000>;
895 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
897 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
902 compatible = "rockchip,rk3368-pinctrl";
903 rockchip,grf = <&grf>;
904 rockchip,pmu = <&pmugrf>;
905 #address-cells = <0x2>;
909 gpio0: gpio0@ff750000 {
910 compatible = "rockchip,gpio-bank";
911 reg = <0x0 0xff750000 0x0 0x100>;
912 clocks = <&cru PCLK_GPIO0>;
913 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
918 interrupt-controller;
919 #interrupt-cells = <0x2>;
922 gpio1: gpio1@ff780000 {
923 compatible = "rockchip,gpio-bank";
924 reg = <0x0 0xff780000 0x0 0x100>;
925 clocks = <&cru PCLK_GPIO1>;
926 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
931 interrupt-controller;
932 #interrupt-cells = <0x2>;
935 gpio2: gpio2@ff790000 {
936 compatible = "rockchip,gpio-bank";
937 reg = <0x0 0xff790000 0x0 0x100>;
938 clocks = <&cru PCLK_GPIO2>;
939 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
944 interrupt-controller;
945 #interrupt-cells = <0x2>;
948 gpio3: gpio3@ff7a0000 {
949 compatible = "rockchip,gpio-bank";
950 reg = <0x0 0xff7a0000 0x0 0x100>;
951 clocks = <&cru PCLK_GPIO3>;
952 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
957 interrupt-controller;
958 #interrupt-cells = <0x2>;
961 pcfg_pull_up: pcfg-pull-up {
965 pcfg_pull_down: pcfg-pull-down {
969 pcfg_pull_none: pcfg-pull-none {
973 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
975 drive-strength = <12>;
980 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
984 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
988 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
991 emmc_bus1: emmc-bus1 {
992 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
995 emmc_bus4: emmc-bus4 {
996 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
997 <1 19 RK_FUNC_2 &pcfg_pull_up>,
998 <1 20 RK_FUNC_2 &pcfg_pull_up>,
999 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1002 emmc_bus8: emmc-bus8 {
1003 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1004 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1005 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1006 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1007 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1008 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1009 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1010 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1015 rgmii_pins: rgmii-pins {
1016 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1017 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1018 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1019 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1020 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1021 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1022 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1023 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1024 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1025 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1026 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1027 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1028 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1029 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1030 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1033 rmii_pins: rmii-pins {
1034 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1035 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1036 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1037 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1038 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1039 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1040 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1041 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1042 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1043 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1048 hdmii2c_xfer: hdmii2c-xfer {
1049 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1050 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1055 hdmi_cec: hdmi-cec {
1056 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1061 i2c0_xfer: i2c0-xfer {
1062 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1063 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1068 i2c1_xfer: i2c1-xfer {
1069 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1070 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1075 i2c2_xfer: i2c2-xfer {
1076 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1077 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1082 i2c3_xfer: i2c3-xfer {
1083 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1084 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1089 i2c4_xfer: i2c4-xfer {
1090 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1091 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1096 i2c5_xfer: i2c5-xfer {
1097 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1098 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1100 i2c5_gpio: i2c5-gpio {
1101 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
1102 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
1107 i2s_8ch_bus: i2s-8ch-bus {
1108 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1109 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1110 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1111 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1112 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1113 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1114 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1115 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1116 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1121 sdio0_bus1: sdio0-bus1 {
1122 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1125 sdio0_bus4: sdio0-bus4 {
1126 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1127 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1128 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1129 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1132 sdio0_cmd: sdio0-cmd {
1133 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1136 sdio0_clk: sdio0-clk {
1137 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1140 sdio0_cd: sdio0-cd {
1141 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1144 sdio0_wp: sdio0-wp {
1145 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1148 sdio0_pwr: sdio0-pwr {
1149 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1152 sdio0_bkpwr: sdio0-bkpwr {
1153 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1156 sdio0_int: sdio0-int {
1157 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1162 sdmmc_clk: sdmmc-clk {
1163 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1166 sdmmc_cmd: sdmmc-cmd {
1167 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1170 sdmmc_cd: sdmcc-cd {
1171 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1174 sdmmc_bus1: sdmmc-bus1 {
1175 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1178 sdmmc_bus4: sdmmc-bus4 {
1179 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1180 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1181 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1182 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1187 spi0_clk: spi0-clk {
1188 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1190 spi0_cs0: spi0-cs0 {
1191 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1193 spi0_cs1: spi0-cs1 {
1194 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1197 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1200 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1205 spi1_clk: spi1-clk {
1206 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1208 spi1_cs0: spi1-cs0 {
1209 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1211 spi1_cs1: spi1-cs1 {
1212 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1215 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1218 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1223 spi2_clk: spi2-clk {
1224 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1226 spi2_cs0: spi2-cs0 {
1227 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1230 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1233 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1238 uart0_xfer: uart0-xfer {
1239 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1240 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1243 uart0_cts: uart0-cts {
1244 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1247 uart0_rts: uart0-rts {
1248 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1253 uart1_xfer: uart1-xfer {
1254 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1255 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1258 uart1_cts: uart1-cts {
1259 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1262 uart1_rts: uart1-rts {
1263 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1268 uart2_xfer: uart2-xfer {
1269 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1270 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1272 /* no rts / cts for uart2 */
1276 uart3_xfer: uart3-xfer {
1277 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1278 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1281 uart3_cts: uart3-cts {
1282 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1285 uart3_rts: uart3-rts {
1286 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1291 uart4_xfer: uart4-xfer {
1292 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1293 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1296 uart4_cts: uart4-cts {
1297 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1300 uart4_rts: uart4-rts {
1301 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1306 pwm0_pin: pwm0-pin {
1307 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1310 vop_pwm_pin: vop-pwm {
1311 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1316 pwm1_pin: pwm1-pin {
1317 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1322 pwm3_pin: pwm3-pin {
1323 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1328 lcdc_lcdc: lcdc-lcdc {
1330 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1331 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1332 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1333 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1334 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1335 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1336 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1337 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1338 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1339 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1340 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1341 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1342 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1343 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1344 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1345 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1346 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1347 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1350 lcdc_gpio: lcdc-gpio {
1352 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1353 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1354 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1355 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1356 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1357 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1358 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1359 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1360 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1361 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1362 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1363 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1364 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1365 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1366 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1367 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1368 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1369 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1374 cif_clkout: cif-clkout {
1375 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1378 isp_dvp_d2d9: isp-dvp-d2d9 {
1380 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1381 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1382 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1383 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1384 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1385 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1386 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1387 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1388 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1389 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1390 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1391 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1394 isp_dvp_d0d1: isp-dvp-d0d1 {
1396 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1397 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1400 isp_dvp_d10d11:isp_d10d11 {
1402 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1403 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1406 isp_dvp_d0d7: isp-dvp-d0d7 {
1408 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1409 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1410 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1411 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1412 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1413 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1414 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1415 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1418 isp_dvp_d4d11: isp-dvp-d4d11 {
1420 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1421 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1422 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1423 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1424 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1425 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1426 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1427 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1430 isp_shutter: isp-shutter {
1432 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1433 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1436 isp_flash_trigger: isp-flash-trigger {
1437 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1440 isp_prelight: isp-prelight {
1441 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1444 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1445 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1451 compatible = "rockchip,rk-fb";
1452 rockchip,disp-mode = <NO_DUAL>;
1453 status = "disabled";
1457 compatible = "rockchip,screen";
1458 status = "disabled";
1461 lcdc: lcdc@ff930000 {
1462 compatible = "rockchip,rk3368-lcdc";
1463 rockchip,grf = <&grf>;
1464 rockchip,pmugrf = <&pmugrf>;
1465 rockchip,cru = <&cru>;
1466 rockchip,prop = <PRMRY>;
1467 rockchip,pwr18 = <0>;
1468 rockchip,iommu-enabled = <1>;
1469 reg = <0x0 0xff930000 0x0 0x10000>;
1470 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1471 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1472 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1473 /*power-domains = <&power PD_VIO>;*/
1474 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1475 reset-names = "axi", "ahb", "dclk";
1476 status = "disabled";
1479 mipi: mipi@ff960000 {
1480 compatible = "rockchip,rk3368-dsi";
1481 rockchip,prop = <0>;
1482 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1483 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1484 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1485 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1486 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1487 /*power-domains = <&power PD_VIO>;*/
1488 status = "disabled";
1491 lvds: lvds@ff968000 {
1492 compatible = "rockchip,rk3368-lvds";
1493 rockchip,grf = <&grf>;
1494 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1495 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1496 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1497 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1498 /*power-domains = <&power PD_VIO>;*/
1499 status = "disabled";
1503 compatible = "rockchip,rk32-edp";
1504 reg = <0x0 0xff970000 0x0 0x4000>;
1505 rockchip,grf = <&grf>;
1506 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1507 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1508 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1509 /*power-domains = <&power PD_VIO>;*/
1510 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1511 reset-names = "edp_24m", "edp_apb";
1512 status = "disabled";
1515 hdmi: hdmi@ff980000 {
1516 compatible = "rockchip,rk3368-hdmi";
1517 reg = <0x0 0xff980000 0x0 0x20000>;
1518 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1519 clocks = <&cru PCLK_HDMI_CTRL>,
1520 <&cru SCLK_HDMI_HDCP>,
1521 <&cru SCLK_HDMI_CEC>;
1522 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
1523 /*power-domains = <&power PD_VIO>;*/
1524 resets = <&cru SRST_HDMI>;
1525 reset-names = "hdmi";
1526 pinctrl-names = "default", "gpio";
1527 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1528 pinctrl-1 = <&i2c5_gpio>;
1529 status = "disabled";
1534 compatible = "rockchip,iep_mmu";
1535 reg = <0x0 0xff900800 0x0 0x100>;
1536 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1537 interrupt-names = "iep_mmu";
1538 status = "disabled";
1543 compatible = "rockchip,vip_mmu";
1544 reg = <0x0 0xff950800 0x0 0x100>;
1545 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1546 interrupt-names = "vip_mmu";
1547 status = "disabled";
1550 vopb_mmu: vopb-mmu {
1552 compatible = "rockchip,vopb_mmu";
1553 reg = <0x0 0xff930300 0x0 0x100>;
1554 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1555 interrupt-names = "vop_mmu";
1556 status = "disabled";
1560 dbgname = "isp_mmu";
1561 compatible = "rockchip,isp_mmu";
1562 reg = <0x0 0xff914000 0x0 0x100>,
1563 <0x0 0xff915000 0x0 0x100>;
1564 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1565 interrupt-names = "isp_mmu";
1566 status = "disabled";
1569 hdcp_mmu: hdcp-mmu {
1570 dbgname = "hdcp_mmu";
1571 compatible = "rockchip,hdcp_mmu";
1572 reg = <0x0 0xff940000 0x0 0x100>;
1573 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1574 interrupt-names = "hdcp_mmu";
1575 status = "disabled";
1578 hevc_mmu: hevc-mmu {
1580 compatible = "rockchip,hevc_mmu";
1581 reg = <0x0 0xff9a0440 0x0 0x40>,
1582 <0x0 0xff9a0480 0x0 0x40>;
1583 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1584 interrupt-names = "hevc_mmu";
1585 status = "disabled";
1590 compatible = "rockchip,vpu_mmu";
1591 reg = <0x0 0xff9a0800 0x0 0x100>;
1592 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1593 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1594 interrupt-names = "vepu_mmu", "vdpu_mmu";
1595 status = "disabled";