arch/arm64/boot/dts/rockchip/rk3399-android-next.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/display/drm_mipi_dsi.h>
  44 #include <dt-bindings/display/media-bus-format.h>
  45
  46 / {
  47         compatible = "rockchip,android", "rockchip,rk3399";
  48
  49         chosen {
  50                 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
  51         };
  52
  53         ramoops_mem: ramoops_mem {
  54                 reg = <0x0 0x110000 0x0 0xf0000>;
  55                 reg-names = "ramoops_mem";
  56         };
  57
  58         ramoops {
  59                 compatible = "ramoops";
  60                 record-size = <0x0 0x20000>;
  61                 console-size = <0x0 0x80000>;
  62                 ftrace-size = <0x0 0x00000>;
  63                 pmsg-size = <0x0 0x50000>;
  64                 memory-region = <&ramoops_mem>;
  65         };
  66
  67         fiq_debugger: fiq-debugger {
  68                 compatible = "rockchip,fiq-debugger";
  69                 rockchip,serial-id = <2>;
  70                 rockchip,signal-irq = <182>;
  71                 rockchip,wake-irq = <0>;
  72                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
  73                 rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
  74                 pinctrl-names = "default";
  75                 pinctrl-0 = <&uart2c_xfer>;
  76         };
  77
  78         reserved-memory {
  79                 #address-cells = <2>;
  80                 #size-cells = <2>;
  81                 ranges;
  82
  83                 drm_logo: drm-logo@00000000 {
  84                         compatible = "rockchip,drm-logo";
  85                         reg = <0x0 0x0 0x0 0x0>;
  86                 };
  87         };
  88
  89         rk_key: rockchip-key {
  90                 compatible = "rockchip,key";
  91                 status = "okay";
  92
  93                 io-channels = <&saradc 1>;
  94
  95                 vol-up-key {
  96                         linux,code = <115>;
  97                         label = "volume up";
  98                         rockchip,adc_value = <1>;
  99                 };
 100
 101                 vol-down-key {
 102                         linux,code = <114>;
 103                         label = "volume down";
 104                         rockchip,adc_value = <170>;
 105                 };
 106
 107                 power-key {
 108                         gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
 109                         linux,code = <116>;
 110                         label = "power";
 111                         gpio-key,wakeup;
 112                 };
 113
 114                 menu-key {
 115                         linux,code = <59>;
 116                         label = "menu";
 117                         rockchip,adc_value = <746>;
 118                 };
 119
 120                 home-key {
 121                         linux,code = <102>;
 122                         label = "home";
 123                         rockchip,adc_value = <355>;
 124                 };
 125
 126                 back-key {
 127                         linux,code = <158>;
 128                         label = "back";
 129                         rockchip,adc_value = <560>;
 130                 };
 131
 132                 camera-key {
 133                         linux,code = <212>;
 134                         label = "camera";
 135                         rockchip,adc_value = <450>;
 136                 };
 137         };
 138
 139         vpu: vpu_service@ff650000 {
 140                 compatible = "rockchip,vpu_service";
 141                 rockchip,grf = <&grf>;
 142                 iommus = <&vpu_mmu>;
 143                 iommu_enabled = <1>;
 144                 reg = <0x0 0xff650000 0x0 0x800>;
 145                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
 146                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
 147                 interrupt-names = "irq_dec", "irq_enc";
 148                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 149                 clock-names = "aclk_vcodec", "hclk_vcodec";
 150                 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
 151                 reset-names = "video_h", "video_a";
 152                 power-domains = <&power RK3399_PD_VCODEC>;
 153                 name = "vpu_service";
 154                 dev_mode = <0>;
 155                 /* 0 means ion, 1 means drm */
 156                 allocator = <1>;
 157                 status = "disabled";
 158         };
 159
 160         vpu_mmu: iommu@ff650800 {
 161                 dbgname = "vpu";
 162                 compatible = "rockchip,iommu";
 163                 reg = <0x0 0xff650800 0x0 0x40>;
 164                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
 165                 interrupt-names = "vpu_mmu";
 166                 #iommu-cells = <0>;
 167         };
 168
 169         rkvdec: rkvdec@ff660000 {
 170                 compatible = "rockchip,rkvdec";
 171                 rockchip,grf = <&grf>;
 172                 iommus = <&vdec_mmu>;
 173                 iommu_enabled = <1>;
 174                 reg = <0x0 0xff660000 0x0 0x400>;
 175                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
 176                 interrupt-names = "irq_dec";
 177                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
 178                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
 179                 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
 180                 reset-names = "video_h", "video_a";
 181                 power-domains = <&power RK3399_PD_VDU>;
 182                 dev_mode = <2>;
 183                 name = "rkvdec";
 184                 /* 0 means ion, 1 means drm */
 185                 allocator = <1>;
 186                 status = "disabled";
 187         };
 188
 189         vdec_mmu: iommu@ff660480 {
 190                 dbgname = "vdec";
 191                 compatible = "rockchip,iommu";
 192                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
 193                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
 194                 interrupt-names = "vdec_mmu";
 195                 #iommu-cells = <0>;
 196         };
 197
 198         rga: rga@ff680000 {
 199                 compatible = "rockchip,rga2";
 200                 dev_mode = <1>;
 201                 reg = <0x0 0xff680000 0x0 0x1000>;
 202                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
 203                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
 204                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 205                 power-domains = <&power RK3399_PD_RGA>;
 206                 status = "okay";
 207         };
 208
 209         isp0: isp@ff910000 {
 210                 compatible = "rockchip,rk3399-isp", "rockchip,isp";
 211                 reg = <0x0 0xff910000 0x0 0x4000>;
 212                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
 213                 clocks =
 214                         <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
 215                         <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
 216                         <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
 217                         <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
 218                         <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
 219                 clock-names =
 220                         "clk_cif_out", "clk_cif_pll",
 221                         "pclk_dphytxrx", "pclk_dphy_ref",
 222                         "aclk_isp0_noc", "aclk_isp0_wrapper",
 223                         "hclk_isp0_noc", "hclk_isp0_wrapper",
 224                         "clk_isp0", "pclk_dphyrx";
 225                 pinctrl-names =
 226                         "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
 227                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 228                         "isp_flash_as_trigger_out";
 229                 pinctrl-0 = <&cif_clkout>;
 230                 pinctrl-1 = <&isp_dvp_d0d7>;
 231                 pinctrl-2 = <&cif_clkout>;
 232                 pinctrl-3 = <&isp_prelight>;
 233                 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
 234                 pinctrl-5 = <&isp_flash_trigger>;
 235                 rockchip,isp,mipiphy = <2>;
 236                 rockchip,isp,cifphy = <1>;
 237                 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
 238                 rockchip,grf = <&grf>;
 239                 rockchip,cru = <&cru>;
 240                 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 241                 rockchip,isp,iommu-enable = <1>;
 242                 power-domains = <&power RK3399_PD_ISP0>;
 243                 iommus = <&isp0_mmu>;
 244                 status = "disabled";
 245         };
 246
 247         isp1: isp@ff920000 {
 248                 compatible = "rockchip,rk3399-isp", "rockchip,isp";
 249                 reg = <0x0 0xff920000 0x0 0x4000>;
 250                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
 251                 clocks =
 252                         <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
 253                         <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
 254                         <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
 255                         <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
 256                         <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
 257                         <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
 258                         <&cru SCLK_MIPIDPHY_CFG>;
 259                 clock-names =
 260                         "aclk_isp1_noc", "aclk_isp1_wrapper",
 261                         "hclk_isp1_noc", "hclk_isp1_wrapper",
 262                         "clk_isp1", "clk_cif_out",
 263                         "clk_cif_pll", "pclk_dphytxrx",
 264                         "pclk_dphy_ref", "pclk_isp1",
 265                         "pclk_dphyrx", "pclk_mipi_dsi",
 266                         "mipi_dphy_cfg";
 267                 pinctrl-names =
 268                         "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
 269                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 270                         "isp_flash_as_trigger_out";
 271                 pinctrl-0 = <&cif_clkout>;
 272                 pinctrl-1 = <&isp_dvp_d0d7>;
 273                 pinctrl-2 = <&cif_clkout>;
 274                 pinctrl-3 = <&isp_prelight>;
 275                 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
 276                 pinctrl-5 = <&isp_flash_trigger>;
 277                 rockchip,isp,mipiphy = <2>;
 278                 rockchip,isp,cifphy = <1>;
 279                 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
 280                 rockchip,grf = <&grf>;
 281                 rockchip,cru = <&cru>;
 282                 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 283                 rockchip,isp,iommu-enable = <1>;
 284                 power-domains = <&power RK3399_PD_ISP1>;
 285                 iommus = <&isp1_mmu>;
 286                 status = "disabled";
 287         };
 288
 289         uboot-charge {
 290                 compatible = "rockchip,uboot-charge";
 291                 rockchip,uboot-charge-on = <1>;
 292                 rockchip,android-charge-on = <0>;
 293         };
 294 };
 295
 296 &vopb {
 297         status = "okay";
 298 };
 299
 300 &vopb_mmu {
 301         status = "okay";
 302 };
 303
 304 &vopl {
 305         status = "okay";
 306 };
 307
 308 &vopl_mmu {
 309         status = "okay";
 310 };
 311
 312 &i2c3 {
 313         status = "okay";
 314         i2c-scl-rising-time-ns = <450>;
 315         i2c-scl-falling-time-ns = <15>;
 316 };
 317
 318 &hdmi {
 319         ddc-i2c-bus = <&i2c3>;
 320         status = "okay";
 321 };
 322
 323 &display_subsystem {
 324         status = "okay";
 325
 326         ports = <&vopb_out>, <&vopl_out>;
 327         memory-region = <&drm_logo>;
 328         route {
 329                 route_hdmi: route-hdmi {
 330                         status = "disabled";
 331                         logo,uboot = "logo.bmp";
 332                         logo,kernel = "logo_kernel.bmp";
 333                         logo,mode = "fullscreen";
 334                         charge_logo,mode = "center";
 335                         connect = <&vopl_out_hdmi>;
 336                 };
 337
 338                 route_mipi: route-mipi {
 339                         status = "disabled";
 340                         logo,uboot = "logo.bmp";
 341                         logo,kernel = "logo_kernel.bmp";
 342                         logo,mode = "fullscreen";
 343                         charge_logo,mode = "center";
 344                         connect = <&vopb_out_mipi>;
 345                 };
 346
 347                 route_edp: route-edp {
 348                         status = "disabled";
 349                         logo,uboot = "logo.bmp";
 350                         logo,kernel = "logo_kernel.bmp";
 351                         logo,mode = "fullscreen";
 352                         charge_logo,mode = "center";
 353                         connect = <&vopb_out_edp>;
 354                 };
 355         };
 356 };
 357
 358 &i2s2 {
 359         #sound-dai-cells = <0>;
 360 };
 361
 362 &usbdrd_dwc3_0 {
 363         dr_mode = "otg";
 364 };
 365
 366 &pinctrl {
 367         isp {
 368                 cif_clkout: cif-clkout {
 369                         rockchip,pins =
 370                                 /*cif_clkout*/
 371                                 <2 11 RK_FUNC_3 &pcfg_pull_none>;
 372                         };
 373
 374                         isp_dvp_d0d7: isp-dvp-d0d7 {
 375                                 rockchip,pins =
 376                                         /*cif_data0*/
 377                                         <2 0 RK_FUNC_3 &pcfg_pull_none>,
 378                                         /*cif_data1*/
 379                                         <2 1 RK_FUNC_3 &pcfg_pull_none>,
 380                                         /*cif_data2*/
 381                                         <2 2 RK_FUNC_3 &pcfg_pull_none>,
 382                                         /*cif_data3*/
 383                                         <2 3 RK_FUNC_3 &pcfg_pull_none>,
 384                                         /*cif_data4*/
 385                                         <2 4 RK_FUNC_3 &pcfg_pull_none>,
 386                                         /*cif_data5*/
 387                                         <2 5 RK_FUNC_3 &pcfg_pull_none>,
 388                                         /*cif_data6*/
 389                                         <2 6 RK_FUNC_3 &pcfg_pull_none>,
 390                                         /*cif_data7*/
 391                                         <2 7 RK_FUNC_3 &pcfg_pull_none>,
 392                                         /*cif_sync*/
 393                                         <2 8 RK_FUNC_3 &pcfg_pull_none>,
 394                                         /*cif_href*/
 395                                         <2 9 RK_FUNC_3 &pcfg_pull_none>,
 396                                         /*cif_clkin*/
 397                                         <2 10 RK_FUNC_3 &pcfg_pull_none>;
 398                         };
 399
 400                         isp_shutter: isp-shutter {
 401                                 rockchip,pins =
 402                                         /*SHUTTEREN*/
 403                                         <1 1 RK_FUNC_1 &pcfg_pull_none>,
 404                                         /*SHUTTERTRIG*/
 405                                         <1 0 RK_FUNC_1 &pcfg_pull_none>;
 406                         };
 407
 408                         isp_flash_trigger: isp-flash-trigger {
 409                                 /*ISP_FLASHTRIGOU*/
 410                                 rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
 411                         };
 412
 413                         isp_prelight: isp-prelight {
 414                                 /*ISP_PRELIGHTTRIG*/
 415                                 rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
 416                         };
 417
 418                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
 419                                 /*ISP_FLASHTRIGOU*/
 420                                 rockchip,pins =
 421                                         <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
 422                         };
 423                 };
 424 };
 425