2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/display/drm_mipi_dsi.h>
44 #include <dt-bindings/display/media-bus-format.h>
45 #include "rk3399-vop-clk-set.dtsi"
48 compatible = "rockchip,android", "rockchip,rk3399";
51 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
55 compatible = "rockchip,cpuinfo";
56 nvmem-cells = <&efuse_id>;
57 nvmem-cell-names = "id";
60 ramoops_mem: ramoops_mem {
61 reg = <0x0 0x110000 0x0 0xf0000>;
62 reg-names = "ramoops_mem";
66 compatible = "ramoops";
67 record-size = <0x0 0x20000>;
68 console-size = <0x0 0x80000>;
69 ftrace-size = <0x0 0x00000>;
70 pmsg-size = <0x0 0x50000>;
71 memory-region = <&ramoops_mem>;
74 fiq_debugger: fiq-debugger {
75 compatible = "rockchip,fiq-debugger";
76 rockchip,serial-id = <2>;
77 rockchip,wake-irq = <0>;
78 rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */
79 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
80 pinctrl-names = "default";
81 pinctrl-0 = <&uart2c_xfer>;
82 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
90 drm_logo: drm-logo@00000000 {
91 compatible = "rockchip,drm-logo";
92 reg = <0x0 0x0 0x0 0x0>;
95 stb_devinfo: stb-devinfo@00000000 {
96 compatible = "rockchip,stb-devinfo";
97 reg = <0x0 0x0 0x0 0x0>;
101 rk_key: rockchip-key {
102 compatible = "rockchip,key";
105 io-channels = <&saradc 1>;
110 rockchip,adc_value = <1>;
115 label = "volume down";
116 rockchip,adc_value = <170>;
120 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
129 rockchip,adc_value = <746>;
135 rockchip,adc_value = <355>;
141 rockchip,adc_value = <560>;
147 rockchip,adc_value = <450>;
152 compatible = "rockchip,rga2";
154 reg = <0x0 0xff680000 0x0 0x1000>;
155 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
156 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
157 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
158 power-domains = <&power RK3399_PD_RGA>;
164 compatible = "rockchip,rk3399-isp", "rockchip,isp";
165 reg = <0x0 0xff910000 0x0 0x4000>;
166 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
168 <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
169 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
170 <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
171 <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
172 <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
174 "clk_cif_out", "clk_cif_pll",
175 "pclk_dphytxrx", "pclk_dphy_ref",
176 "aclk_isp0_noc", "aclk_isp0_wrapper",
177 "hclk_isp0_noc", "hclk_isp0_wrapper",
178 "clk_isp0", "pclk_dphyrx";
180 "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
181 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
182 "isp_flash_as_trigger_out";
183 pinctrl-0 = <&cif_clkout>;
184 pinctrl-1 = <&isp_dvp_d0d7>;
185 pinctrl-2 = <&cif_clkout>;
186 pinctrl-3 = <&isp_prelight>;
187 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
188 pinctrl-5 = <&isp_flash_trigger>;
189 rockchip,isp,mipiphy = <2>;
190 rockchip,isp,cifphy = <1>;
191 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
192 rockchip,grf = <&grf>;
193 rockchip,cru = <&cru>;
194 rockchip,gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
195 rockchip,isp,iommu-enable = <1>;
196 power-domains = <&power RK3399_PD_ISP0>;
197 iommus = <&isp0_mmu>;
202 compatible = "rockchip,rk3399-isp", "rockchip,isp";
203 reg = <0x0 0xff920000 0x0 0x4000>;
204 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
206 <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
207 <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
208 <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
209 <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
210 <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
211 <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
212 <&cru SCLK_MIPIDPHY_CFG>;
214 "aclk_isp1_noc", "aclk_isp1_wrapper",
215 "hclk_isp1_noc", "hclk_isp1_wrapper",
216 "clk_isp1", "clk_cif_out",
217 "clk_cif_pll", "pclk_dphytxrx",
218 "pclk_dphy_ref", "pclk_isp1",
219 "pclk_dphyrx", "pclk_mipi_dsi",
222 "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
223 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
224 "isp_flash_as_trigger_out";
225 pinctrl-0 = <&cif_clkout>;
226 pinctrl-1 = <&isp_dvp_d0d7>;
227 pinctrl-2 = <&cif_clkout>;
228 pinctrl-3 = <&isp_prelight>;
229 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
230 pinctrl-5 = <&isp_flash_trigger>;
231 rockchip,isp,mipiphy = <2>;
232 rockchip,isp,cifphy = <1>;
233 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
234 rockchip,grf = <&grf>;
235 rockchip,cru = <&cru>;
236 rockchip,gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
237 rockchip,isp,iommu-enable = <1>;
238 power-domains = <&power RK3399_PD_ISP1>;
239 iommus = <&isp1_mmu>;
244 compatible = "rockchip,uboot-charge";
245 rockchip,uboot-charge-on = <1>;
246 rockchip,android-charge-on = <0>;
249 hdmi_dp_sound: hdmi-dp-sound {
251 compatible = "rockchip,rk3399-hdmi-dp";
252 rockchip,cpu = <&i2s2>;
253 rockchip,codec = <&hdmi>, <&cdn_dp>;
274 #address-cells = <1>;
276 #sound-dai-cells = <0>;
277 ddc-i2c-scl-high-time-ns = <9625>;
278 ddc-i2c-scl-low-time-ns = <10000>;
285 ports = <&vopb_out>, <&vopl_out>;
286 memory-region = <&drm_logo>;
288 route_hdmi: route-hdmi {
290 logo,uboot = "logo.bmp";
291 logo,kernel = "logo_kernel.bmp";
292 logo,mode = "fullscreen";
293 charge_logo,mode = "center";
294 connect = <&vopb_out_hdmi>;
297 route_dsi: route-dsi {
299 logo,uboot = "logo.bmp";
300 logo,kernel = "logo_kernel.bmp";
301 logo,mode = "fullscreen";
302 charge_logo,mode = "center";
303 connect = <&vopb_out_dsi>;
306 route_edp: route-edp {
308 logo,uboot = "logo.bmp";
309 logo,kernel = "logo_kernel.bmp";
310 logo,mode = "fullscreen";
311 charge_logo,mode = "center";
312 connect = <&vopb_out_edp>;
318 #sound-dai-cells = <0>;
319 rockchip,bclk-fs = <128>;
344 cif_clkout: cif-clkout {
347 <2 11 RK_FUNC_3 &pcfg_pull_none>;
350 isp_dvp_d0d7: isp-dvp-d0d7 {
353 <2 0 RK_FUNC_3 &pcfg_pull_none>,
355 <2 1 RK_FUNC_3 &pcfg_pull_none>,
357 <2 2 RK_FUNC_3 &pcfg_pull_none>,
359 <2 3 RK_FUNC_3 &pcfg_pull_none>,
361 <2 4 RK_FUNC_3 &pcfg_pull_none>,
363 <2 5 RK_FUNC_3 &pcfg_pull_none>,
365 <2 6 RK_FUNC_3 &pcfg_pull_none>,
367 <2 7 RK_FUNC_3 &pcfg_pull_none>,
369 <2 8 RK_FUNC_3 &pcfg_pull_none>,
371 <2 9 RK_FUNC_3 &pcfg_pull_none>,
373 <2 10 RK_FUNC_3 &pcfg_pull_none>;
376 isp_shutter: isp-shutter {
379 <1 1 RK_FUNC_1 &pcfg_pull_none>,
381 <1 0 RK_FUNC_1 &pcfg_pull_none>;
384 isp_flash_trigger: isp-flash-trigger {
386 rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
389 isp_prelight: isp-prelight {
391 rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
394 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
397 <1 3 RK_FUNC_GPIO &pcfg_pull_none>;