2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/display/rk_fb.h>
45 vpu: vpu_service@ff650000 {
46 compatible = "rockchip,vpu_service";
47 rockchip,grf = <&grf>;
49 reg = <0x0 0xff650000 0x0 0x800>;
50 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
52 interrupt-names = "irq_dec", "irq_enc";
53 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
54 clock-names = "aclk_vcodec", "hclk_vcodec";
55 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
56 reset-names = "video_h", "video_a";
64 compatible = "rockchip,vpu_mmu";
65 reg = <0x0 0xff650800 0x0 0x40>;
66 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
67 interrupt-names = "vpu_mmu";
71 rkvdec: rkvdec@ff660000 {
72 compatible = "rockchip,rkvdec";
73 rockchip,grf = <&grf>;
75 reg = <0x0 0xff660000 0x0 0x400>;
76 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
77 interrupt-names = "irq_dec";
78 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
79 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
80 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
81 reset-names = "video_h", "video_a";
89 compatible = "rockchip,vdec_mmu";
90 reg = <0x0 0xff660480 0x0 0x40>,
91 <0x0 0xff6604c0 0x0 0x40>;
92 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
93 interrupt-names = "vdec_mmu";
98 compatible = "rockchip,rk-fb";
99 rockchip,disp-mode = <DUAL>;
104 compatible = "rockchip,screen";
108 vopl_rk_fb: vop-rk-fb@ff8f0000 {
109 compatible = "rockchip,rk3399-lcdc";
110 rockchip,prop = <EXTEND>;
111 reg = <0x0 0xff8f0000 0x0 0x3efc>;
112 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
114 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
115 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
116 reset-names = "axi", "ahb", "dclk";
117 rockchip,grf = <&grf>;
118 rockchip,pwr18 = <0>;
119 rockchip,iommu-enabled = <0>;
123 vopl_mmu_rk_fb: vopl-mmu {
125 compatible = "rockchip,vopl_mmu";
126 reg = <0x0 0xff8f3f00 0x0 0x100>;
127 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
128 interrupt-names = "vopl_mmu";
132 vopb_rk_fb: vop-rk-fb@ff900000 {
134 compatible = "rockchip,rk3399-lcdc";
135 rockchip,prop = <PRMRY>;
136 reg = <0x0 0xff900000 0x0 0x3efc>;
137 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
139 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
140 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
141 reset-names = "axi", "ahb", "dclk";
142 rockchip,grf = <&grf>;
143 rockchip,pwr18 = <0>;
144 rockchip,iommu-enabled = <0>;
145 power_ctr: power_ctr {
146 /*rockchip,debug = <0>;
148 rockchip,power_type = <GPIO>;
149 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;//GPIO_C6 = 22
150 rockchip,delay = <10>;
155 rockchip,power_type = <GPIO>;
156 gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;//GPIO_C5 = 21
157 rockchip,delay = <10>;
161 rockchip,power_type = <GPIO>;
162 gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
163 rockchip,delay = <5>;
168 vopb_mmu_rk_fb: vopb-mmu {
170 compatible = "rockchip,vopb_mmu";
171 reg = <0x0 0xff903f00 0x0 0x100>;
172 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
173 interrupt-names = "vopb_mmu";
177 hdmi_rk_fb: hdmi-rk-fb@ff940000 {
178 compatible = "rockchip,rk3399-hdmi";
179 reg = <0x0 0xff940000 0x0 0x20000>;
183 mipi0_rk_fb: mipi-rk-fb@ff960000 {
184 compatible = "rockchip,rk3399-dsi";
186 rockchip,grf = <&grf>;
187 reg = <0x0 0xff960000 0x0 0x8000>;
188 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
190 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
194 mipi1_rk_fb: mipi-rk-fb@ff968000 {
195 compatible = "rockchip,rk3399-dsi";
197 reg = <0x0 0xff968000 0x0 0x8000>;
198 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
200 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";