2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "dt-bindings/pwm/pwm.h"
46 #include "rk3399.dtsi"
47 #include "rk3399-opp.dtsi"
48 #include <dt-bindings/display/drm_mipi_dsi.h>
49 #include <dt-bindings/input/input.h>
50 #include "rk3399-vop-clk-set.dtsi"
53 model = "Rockchip RK3399 Firefly Board (Android)";
54 compatible = "rockchip,rk3399-firefly-android", "rockchip,rk3399";
57 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
61 compatible = "rockchip,cpuinfo";
62 nvmem-cells = <&efuse_id>;
63 nvmem-cell-names = "id";
66 ramoops_mem: ramoops_mem {
67 reg = <0x0 0x110000 0x0 0xf0000>;
68 reg-names = "ramoops_mem";
72 compatible = "ramoops";
73 record-size = <0x0 0x20000>;
74 console-size = <0x0 0x80000>;
75 ftrace-size = <0x0 0x00000>;
76 pmsg-size = <0x0 0x50000>;
77 memory-region = <&ramoops_mem>;
80 backlight: backlight {
81 compatible = "pwm-backlight";
82 pwms = <&pwm0 0 25000 0>;
86 16 17 18 19 20 21 22 23
87 24 25 26 27 28 29 30 31
88 32 33 34 35 36 37 38 39
89 40 41 42 43 44 45 46 47
90 48 49 50 51 52 53 54 55
91 56 57 58 59 60 61 62 63
92 64 65 66 67 68 69 70 71
93 72 73 74 75 76 77 78 79
94 80 81 82 83 84 85 86 87
95 88 89 90 91 92 93 94 95
96 96 97 98 99 100 101 102 103
97 104 105 106 107 108 109 110 111
98 112 113 114 115 116 117 118 119
99 120 121 122 123 124 125 126 127
100 128 129 130 131 132 133 134 135
101 136 137 138 139 140 141 142 143
102 144 145 146 147 148 149 150 151
103 152 153 154 155 156 157 158 159
104 160 161 162 163 164 165 166 167
105 168 169 170 171 172 173 174 175
106 176 177 178 179 180 181 182 183
107 184 185 186 187 188 189 190 191
108 192 193 194 195 196 197 198 199
109 200 201 202 203 204 205 206 207
110 208 209 210 211 212 213 214 215
111 216 217 218 219 220 221 222 223
112 224 225 226 227 228 229 230 231
113 232 233 234 235 236 237 238 239
114 240 241 242 243 244 245 246 247
115 248 249 250 251 252 253 254 255>;
116 default-brightness-level = <200>;
119 clkin_gmac: external-gmac-clock {
120 compatible = "fixed-clock";
121 clock-frequency = <125000000>;
122 clock-output-names = "clkin_gmac";
126 dw_hdmi_audio: dw-hdmi-audio {
128 compatible = "rockchip,dw-hdmi-audio";
129 #sound-dai-cells = <0>;
132 edp_panel: edp-panel {
133 compatible = "sharp,lcd-f402", "panel-simple";
136 backlight = <&backlight>;
137 power-supply = <&vcc_lcd>;
138 enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&lcd_panel_reset>;
143 panel_in_edp: endpoint {
144 remote-endpoint = <&edp_out_panel>;
149 fiq_debugger: fiq-debugger {
150 compatible = "rockchip,fiq-debugger";
151 rockchip,serial-id = <2>;
152 rockchip,wake-irq = <0>;
153 /* If enable uart uses irq instead of fiq */
154 rockchip,irq-mode-enable = <0>;
155 /* Only 115200 and 1500000 */
156 rockchip,baudrate = <1500000>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&uart2c_xfer>;
159 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
163 #address-cells = <2>;
167 drm_logo: drm-logo@00000000 {
168 compatible = "rockchip,drm-logo";
169 reg = <0x0 0x0 0x0 0x0>;
172 stb_devinfo: stb-devinfo@00000000 {
173 compatible = "rockchip,stb-devinfo";
174 reg = <0x0 0x0 0x0 0x0>;
179 compatible = "rockchip,key";
182 io-channels = <&saradc 1>;
184 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
192 compatible = "simple-audio-card";
193 simple-audio-card,format = "i2s";
194 simple-audio-card,name = "rockchip,rt5640-codec";
195 simple-audio-card,mclk-fs = <256>;
196 simple-audio-card,widgets =
197 "Microphone", "Mic Jack",
198 "Headphone", "Headphone Jack";
199 simple-audio-card,routing =
200 "Mic Jack", "MICBIAS1",
202 "Headphone Jack", "HPOL",
203 "Headphone Jack", "HPOR";
204 simple-audio-card,cpu {
207 simple-audio-card,codec {
208 sound-dai = <&rt5640>;
212 hdmi_sound: hdmi-sound {
214 compatible = "simple-audio-card";
215 simple-audio-card,format = "i2s";
216 simple-audio-card,mclk-fs = <256>;
217 simple-audio-card,name = "rockchip,hdmi";
219 simple-audio-card,cpu {
222 simple-audio-card,codec {
223 sound-dai = <&dw_hdmi_audio>;
227 hdmi_codec: hdmi-codec {
228 compatible = "simple-audio-card";
229 simple-audio-card,format = "i2s";
230 simple-audio-card,mclk-fs = <256>;
231 simple-audio-card,name = "HDMI-CODEC";
233 simple-audio-card,cpu {
237 simple-audio-card,codec {
243 compatible = "rockchip,rga2";
245 reg = <0x0 0xff680000 0x0 0x1000>;
246 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
247 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
248 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
249 power-domains = <&power RK3399_PD_RGA>;
255 compatible = "simple-audio-card";
258 simple-audio-card,name = "ROCKCHIP,SPDIF";
259 simple-audio-card,cpu {
260 sound-dai = <&spdif>;
262 simple-audio-card,codec {
263 sound-dai = <&spdif_out>;
267 spdif_out: spdif-out {
268 compatible = "linux,spdif-dit";
271 #sound-dai-cells = <0>;
274 sdio_pwrseq: sdio-pwrseq {
275 compatible = "mmc-pwrseq-simple";
277 clock-names = "ext_clock";
278 pinctrl-names = "default";
279 pinctrl-0 = <&wifi_enable_h>;
282 * On the module itself this is one of these (depending
283 * on the actual card populated):
284 * - SDIO_RESET_L_WL_REG_ON
285 * - PDN (power down when low)
287 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
290 vcc3v3_pcie: vcc3v3-pcie-regulator {
291 compatible = "regulator-fixed";
295 gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pcie_drv>;
298 regulator-name = "vcc3v3_pcie";
301 vcc3v3_sys: vcc3v3-sys {
302 compatible = "regulator-fixed";
303 regulator-name = "vcc3v3_sys";
306 regulator-min-microvolt = <3300000>;
307 regulator-max-microvolt = <3300000>;
310 vcc5v0_host: vcc5v0-host-regulator {
311 compatible = "regulator-fixed";
313 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&host_vbus_drv>;
316 regulator-name = "vcc5v0_host";
320 vcc5v0_sys: vcc5v0-sys {
321 compatible = "regulator-fixed";
322 regulator-name = "vcc5v0_sys";
325 regulator-min-microvolt = <5000000>;
326 regulator-max-microvolt = <5000000>;
329 vcc_phy: vcc-phy-regulator {
330 compatible = "regulator-fixed";
331 regulator-name = "vcc_phy";
337 compatible = "pwm-regulator";
338 pwms = <&pwm2 0 25000 1>;
339 regulator-name = "vdd_log";
340 regulator-min-microvolt = <800000>;
341 regulator-max-microvolt = <1400000>;
345 /* for rockchip boot on */
346 rockchip,pwm_id= <2>;
347 rockchip,pwm_voltage = <1000000>;
350 vccadc_ref: vccadc-ref {
351 compatible = "regulator-fixed";
352 regulator-name = "vcc1v8_sys";
355 regulator-min-microvolt = <1800000>;
356 regulator-max-microvolt = <1800000>;
359 vcc_lcd: vcc-lcd-regulator {
360 compatible = "regulator-fixed";
364 gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&lcd_en>;
367 regulator-name = "vcc_lcd";
371 compatible = "wlan-platdata";
372 rockchip,grf = <&grf>;
373 wifi_chip_type = "ap6354";
375 WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
380 compatible = "bluetooth-platdata";
381 //wifi-bt-power-toggle;
382 uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */
383 pinctrl-names = "default", "rts_gpio";
384 pinctrl-0 = <&uart0_rts>;
385 pinctrl-1 = <&uart0_gpios>;
386 //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */
387 BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */
388 BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */
389 BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */
395 cpu-supply = <&vdd_cpu_l>;
399 cpu-supply = <&vdd_cpu_l>;
403 cpu-supply = <&vdd_cpu_l>;
407 cpu-supply = <&vdd_cpu_l>;
411 cpu-supply = <&vdd_cpu_b>;
415 cpu-supply = <&vdd_cpu_b>;
421 ports = <&vopb_out>, <&vopl_out>;
422 memory-region = <&drm_logo>;
425 route_hdmi: route-hdmi {
427 logo,uboot = "logo.bmp";
428 logo,kernel = "logo_kernel.bmp";
429 logo,mode = "fullscreen";
430 charge_logo,mode = "center";
431 connect = <&vopl_out_hdmi>;
434 route_edp: route-edp {
436 logo,uboot = "logo.bmp";
437 logo,kernel = "logo_kernel.bmp";
438 logo,mode = "fullscreen";
439 charge_logo,mode = "center";
440 connect = <&vopb_out_edp>;
451 #address-cells = <1>;
454 edp_out_panel: endpoint@0 {
456 remote-endpoint = <&panel_in_edp>;
467 phy-supply = <&vcc_phy>;
469 clock_in_out = "input";
470 snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
471 snps,reset-active-low;
472 snps,reset-delays-us = <0 10000 50000>;
473 assigned-clocks = <&cru SCLK_RMII_SRC>;
474 assigned-clock-parents = <&clkin_gmac>;
475 pinctrl-names = "default";
476 pinctrl-0 = <&rgmii_pins>;
484 mali-supply = <&vdd_gpu>;
488 #address-cells = <1>;
490 #sound-dai-cells = <0>;
496 i2c-scl-rising-time-ns = <168>;
497 i2c-scl-falling-time-ns = <4>;
498 clock-frequency = <400000>;
500 vdd_cpu_b: syr827@40 {
501 compatible = "silergy,syr827";
503 vin-supply = <&vcc5v0_sys>;
504 regulator-compatible = "fan53555-reg";
505 regulator-name = "vdd_cpu_b";
506 regulator-min-microvolt = <712500>;
507 regulator-max-microvolt = <1500000>;
508 regulator-ramp-delay = <1000>;
509 vsel-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
510 fcs,suspend-voltage-selector = <1>;
513 regulator-initial-state = <3>;
514 regulator-state-mem {
515 regulator-off-in-suspend;
520 compatible = "silergy,syr828";
522 vin-supply = <&vcc5v0_sys>;
523 regulator-compatible = "fan53555-reg";
524 regulator-name = "vdd_gpu";
525 regulator-min-microvolt = <712500>;
526 regulator-max-microvolt = <1500000>;
527 regulator-ramp-delay = <1000>;
528 fcs,suspend-voltage-selector = <1>;
531 regulator-initial-state = <3>;
532 regulator-state-mem {
533 regulator-off-in-suspend;
538 compatible = "rockchip,rk808";
540 interrupt-parent = <&gpio1>;
541 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
542 pinctrl-names = "default";
543 pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
544 rockchip,system-power-controller;
547 clock-output-names = "xin32k", "rk808-clkout2";
549 vcc1-supply = <&vcc3v3_sys>;
550 vcc2-supply = <&vcc3v3_sys>;
551 vcc3-supply = <&vcc3v3_sys>;
552 vcc4-supply = <&vcc3v3_sys>;
553 vcc6-supply = <&vcc3v3_sys>;
554 vcc7-supply = <&vcc3v3_sys>;
555 vcc8-supply = <&vcc3v3_sys>;
556 vcc9-supply = <&vcc3v3_sys>;
557 vcc10-supply = <&vcc3v3_sys>;
558 vcc11-supply = <&vcc3v3_sys>;
559 vcc12-supply = <&vcc3v3_sys>;
560 vddio-supply = <&vcc1v8_pmu>;
563 vdd_center: DCDC_REG1 {
566 regulator-min-microvolt = <750000>;
567 regulator-max-microvolt = <1350000>;
568 regulator-ramp-delay = <6001>;
569 regulator-name = "vdd_center";
570 regulator-state-mem {
571 regulator-off-in-suspend;
575 vdd_cpu_l: DCDC_REG2 {
578 regulator-min-microvolt = <750000>;
579 regulator-max-microvolt = <1350000>;
580 regulator-ramp-delay = <6001>;
581 regulator-name = "vdd_cpu_l";
582 regulator-state-mem {
583 regulator-off-in-suspend;
590 regulator-name = "vcc_ddr";
591 regulator-state-mem {
592 regulator-on-in-suspend;
599 regulator-min-microvolt = <1800000>;
600 regulator-max-microvolt = <1800000>;
601 regulator-name = "vcc_1v8";
602 regulator-state-mem {
603 regulator-on-in-suspend;
604 regulator-suspend-microvolt = <1800000>;
608 vcc1v8_dvp: LDO_REG1 {
611 regulator-min-microvolt = <1800000>;
612 regulator-max-microvolt = <1800000>;
613 regulator-name = "vcc1v8_dvp";
614 regulator-state-mem {
615 regulator-off-in-suspend;
619 vcc3v0_tp: LDO_REG2 {
622 regulator-min-microvolt = <3000000>;
623 regulator-max-microvolt = <3000000>;
624 regulator-name = "vcc3v0_tp";
625 regulator-state-mem {
626 regulator-off-in-suspend;
630 vcc1v8_pmu: LDO_REG3 {
633 regulator-min-microvolt = <1800000>;
634 regulator-max-microvolt = <1800000>;
635 regulator-name = "vcc1v8_pmu";
636 regulator-state-mem {
637 regulator-on-in-suspend;
638 regulator-suspend-microvolt = <1800000>;
645 regulator-min-microvolt = <1800000>;
646 regulator-max-microvolt = <3300000>;
647 regulator-name = "vcc_sd";
648 regulator-state-mem {
649 regulator-on-in-suspend;
650 regulator-suspend-microvolt = <3300000>;
654 vcca3v0_codec: LDO_REG5 {
657 regulator-min-microvolt = <3000000>;
658 regulator-max-microvolt = <3000000>;
659 regulator-name = "vcca3v0_codec";
660 regulator-state-mem {
661 regulator-off-in-suspend;
668 regulator-min-microvolt = <1500000>;
669 regulator-max-microvolt = <1500000>;
670 regulator-name = "vcc_1v5";
671 regulator-state-mem {
672 regulator-on-in-suspend;
673 regulator-suspend-microvolt = <1500000>;
677 vcca1v8_codec: LDO_REG7 {
680 regulator-min-microvolt = <1800000>;
681 regulator-max-microvolt = <1800000>;
682 regulator-name = "vcca1v8_codec";
683 regulator-state-mem {
684 regulator-off-in-suspend;
691 regulator-min-microvolt = <3000000>;
692 regulator-max-microvolt = <3000000>;
693 regulator-name = "vcc_3v0";
694 regulator-state-mem {
695 regulator-on-in-suspend;
696 regulator-suspend-microvolt = <3000000>;
700 vcc3v3_s3: SWITCH_REG1 {
703 regulator-name = "vcc3v3_s3";
704 regulator-state-mem {
705 regulator-off-in-suspend;
709 vcc3v3_s0: SWITCH_REG2 {
712 regulator-name = "vcc3v3_s0";
713 regulator-state-mem {
714 regulator-off-in-suspend;
723 i2c-scl-rising-time-ns = <300>;
724 i2c-scl-falling-time-ns = <15>;
727 #sound-dai-cells = <0>;
728 compatible = "realtek,rt5640";
730 clocks = <&cru SCLK_I2S_8CH_OUT>;
731 clock-names = "mclk";
732 realtek,in1-differential;
733 pinctrl-names = "default";
734 pinctrl-0 = <&rt5640_hpcon>;
735 hp-con-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
736 //hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
737 io-channels = <&saradc 4>;
738 hp-det-adc-value = <500>;
745 i2c-scl-rising-time-ns = <450>;
746 i2c-scl-falling-time-ns = <15>;
751 i2c-scl-rising-time-ns = <600>;
752 i2c-scl-falling-time-ns = <20>;
755 compatible = "fairchild,fusb302";
757 pinctrl-names = "default";
758 pinctrl-0 = <&fusb0_int>;
759 int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
760 vbus-5v-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
764 gsl3680: gsl3680@41 {
765 compatible = "gslX680-pad";
767 screen_max_x = <1536>;
768 screen_max_y = <2048>;
769 touch-gpio = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
770 reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
775 compatible = "invensense,mpu6050";
777 mpu-int_config = <0x10>;
778 mpu-level_shifter = <0>;
779 mpu-orientation = <0 1 0 1 0 0 0 0 1>;
783 irq-gpio = <&gpio1 4 IRQ_TYPE_LEVEL_LOW>;
791 rockchip,i2s-broken-burst-len;
792 rockchip,playback-channels = <8>;
793 rockchip,capture-channels = <8>;
794 #sound-dai-cells = <0>;
799 rockchip,i2s-broken-burst-len;
800 rockchip,playback-channels = <2>;
801 rockchip,capture-channels = <2>;
802 #sound-dai-cells = <0>;
806 #sound-dai-cells = <0>;
813 bt656-supply = <&vcc1v8_dvp>; /* bt656_gpio2ab_ms */
814 audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */
815 sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
816 gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
824 ep-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
826 pinctrl-names = "default";
827 pinctrl-0 = <&pcie_clkreqn_cpm>;
833 pmu1830-supply = <&vcc_3v0>;
839 lcd_panel_reset: lcd-panel-reset {
840 rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_up>;
844 rockchip,pins = <1 1 RK_FUNC_GPIO &pcfg_pull_up>;
851 <1 17 RK_FUNC_GPIO &pcfg_pull_none>;
853 pcie_3g_drv: pcie-3g-drv {
855 <0 2 RK_FUNC_GPIO &pcfg_pull_up>;
860 vsel1_gpio: vsel1-gpio {
862 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
865 vsel2_gpio: vsel2-gpio {
867 <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
872 wifi_enable_h: wifi-enable-h {
874 <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
879 uart0_gpios: uart0-gpios {
881 <2 19 RK_FUNC_GPIO &pcfg_pull_none>;
886 rt5640_hpcon: rt5640-hpcon {
887 rockchip,pins = <4 21 RK_FUNC_GPIO &pcfg_pull_none>;
892 pmic_int_l: pmic-int-l {
894 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
897 pmic_dvs2: pmic-dvs2 {
899 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
904 host_vbus_drv: host-vbus-drv {
906 <4 25 RK_FUNC_GPIO &pcfg_pull_none>;
911 fusb0_int: fusb0-int {
912 rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
930 rockchip,power-ctrl =
931 <&gpio1 18 GPIO_ACTIVE_LOW>,
932 <&gpio1 14 GPIO_ACTIVE_HIGH>;
937 vref-supply = <&vccadc_ref>;
942 keep-power-in-suspend;
944 mmc-hs400-enhanced-strobe;
951 max-frequency = <150000000>;
958 vqmmc-supply = <&vcc_sd>;
959 pinctrl-names = "default";
960 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
965 max-frequency = <50000000>;
970 keep-power-in-suspend;
971 mmc-pwrseq = <&sdio_pwrseq>;
974 pinctrl-names = "default";
975 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
982 pinctrl-0 = <&spdif_bus_1>;
983 i2c-scl-rising-time-ns = <450>;
984 i2c-scl-falling-time-ns = <15>;
985 #sound-dai-cells = <0>;
998 /* tshut mode 0:CRU 1:GPIO */
999 rockchip,hw-tshut-mode = <1>;
1000 /* tshut polarity 0:LOW 1:HIGH */
1001 rockchip,hw-tshut-polarity = <1>;
1009 u2phy0_otg: otg-port {
1013 u2phy0_host: host-port {
1014 phy-supply = <&vcc5v0_host>;
1022 u2phy1_otg: otg-port {
1026 u2phy1_host: host-port {
1027 phy-supply = <&vcc5v0_host>;
1033 pinctrl-names = "default";
1034 pinctrl-0 = <&uart0_xfer &uart0_cts>;