2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "dt-bindings/pwm/pwm.h"
46 #include "rk3399.dtsi"
47 #include "rk3399-opp.dtsi"
48 #include "rk3399-linux.dtsi"
49 #include <dt-bindings/input/input.h>
52 model = "Rockchip RK3399 Firefly Board (Linux Opensource)";
53 compatible = "rockchip,rk3399-firefly-linux", "rockchip,rk3399";
55 backlight: backlight {
57 compatible = "pwm-backlight";
58 pwms = <&pwm0 0 25000 0>;
62 16 17 18 19 20 21 22 23
63 24 25 26 27 28 29 30 31
64 32 33 34 35 36 37 38 39
65 40 41 42 43 44 45 46 47
66 48 49 50 51 52 53 54 55
67 56 57 58 59 60 61 62 63
68 64 65 66 67 68 69 70 71
69 72 73 74 75 76 77 78 79
70 80 81 82 83 84 85 86 87
71 88 89 90 91 92 93 94 95
72 96 97 98 99 100 101 102 103
73 104 105 106 107 108 109 110 111
74 112 113 114 115 116 117 118 119
75 120 121 122 123 124 125 126 127
76 128 129 130 131 132 133 134 135
77 136 137 138 139 140 141 142 143
78 144 145 146 147 148 149 150 151
79 152 153 154 155 156 157 158 159
80 160 161 162 163 164 165 166 167
81 168 169 170 171 172 173 174 175
82 176 177 178 179 180 181 182 183
83 184 185 186 187 188 189 190 191
84 192 193 194 195 196 197 198 199
85 200 201 202 203 204 205 206 207
86 208 209 210 211 212 213 214 215
87 216 217 218 219 220 221 222 223
88 224 225 226 227 228 229 230 231
89 232 233 234 235 236 237 238 239
90 240 241 242 243 244 245 246 247
91 248 249 250 251 252 253 254 255>;
92 default-brightness-level = <200>;
95 clkin_gmac: external-gmac-clock {
96 compatible = "fixed-clock";
97 clock-frequency = <125000000>;
98 clock-output-names = "clkin_gmac";
102 dw_hdmi_audio: dw-hdmi-audio {
104 compatible = "rockchip,dw-hdmi-audio";
105 #sound-dai-cells = <0>;
108 edp_panel: edp-panel {
110 compatible = "sharp,lcd-f402", "panel-simple";
111 backlight = <&backlight>;
112 power-supply = <&vcc_lcd>;
113 enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&lcd_panel_reset>;
118 panel_in_edp: endpoint {
119 remote-endpoint = <&edp_out_panel>;
124 fiq_debugger: fiq-debugger {
125 compatible = "rockchip,fiq-debugger";
126 rockchip,serial-id = <2>;
127 rockchip,signal-irq = <182>;
128 rockchip,wake-irq = <0>;
129 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
130 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
131 pinctrl-names = "default";
132 pinctrl-0 = <&uart2c_xfer>;
136 compatible = "gpio-keys";
137 #address-cells = <1>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pwrbtn>;
145 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
146 linux,code = <KEY_POWER>;
147 label = "GPIO Key Power";
148 linux,input-type = <1>;
149 gpio-key,wakeup = <1>;
150 debounce-interval = <100>;
155 compatible = "simple-audio-card";
156 simple-audio-card,format = "i2s";
157 simple-audio-card,name = "rockchip,rt5640-codec";
158 simple-audio-card,mclk-fs = <256>;
159 simple-audio-card,widgets =
160 "Microphone", "Mic Jack",
161 "Headphone", "Headphone Jack";
162 simple-audio-card,routing =
163 "Mic Jack", "MICBIAS1",
165 "Headphone Jack", "HPOL",
166 "Headphone Jack", "HPOR";
167 simple-audio-card,cpu {
170 simple-audio-card,codec {
171 sound-dai = <&rt5640>;
175 hdmi_sound: hdmi-sound {
177 compatible = "simple-audio-card";
178 simple-audio-card,format = "i2s";
179 simple-audio-card,mclk-fs = <256>;
180 simple-audio-card,name = "rockchip,hdmi";
182 simple-audio-card,cpu {
185 simple-audio-card,codec {
186 sound-dai = <&dw_hdmi_audio>;
190 hdmi_codec: hdmi-codec {
191 compatible = "simple-audio-card";
192 simple-audio-card,format = "i2s";
193 simple-audio-card,mclk-fs = <256>;
194 simple-audio-card,name = "HDMI-CODEC";
196 simple-audio-card,cpu {
200 simple-audio-card,codec {
207 compatible = "simple-audio-card";
208 simple-audio-card,name = "ROCKCHIP,SPDIF";
209 simple-audio-card,cpu {
210 sound-dai = <&spdif>;
212 simple-audio-card,codec {
213 sound-dai = <&spdif_out>;
217 spdif_out: spdif-out {
219 compatible = "linux,spdif-dit";
220 #sound-dai-cells = <0>;
223 sdio_pwrseq: sdio-pwrseq {
224 compatible = "mmc-pwrseq-simple";
226 clock-names = "ext_clock";
227 pinctrl-names = "default";
228 pinctrl-0 = <&wifi_enable_h>;
231 * On the module itself this is one of these (depending
232 * on the actual card populated):
233 * - SDIO_RESET_L_WL_REG_ON
234 * - PDN (power down when low)
236 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
239 vcc3v3_pcie: vcc3v3-pcie-regulator {
240 compatible = "regulator-fixed";
244 gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pcie_drv>;
247 regulator-name = "vcc3v3_pcie";
250 vcc3v3_sys: vcc3v3-sys {
251 compatible = "regulator-fixed";
252 regulator-name = "vcc3v3_sys";
255 regulator-min-microvolt = <3300000>;
256 regulator-max-microvolt = <3300000>;
259 vcc5v0_host: vcc5v0-host-regulator {
260 compatible = "regulator-fixed";
262 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&host_vbus_drv>;
265 regulator-name = "vcc5v0_host";
269 vcc5v0_sys: vcc5v0-sys {
270 compatible = "regulator-fixed";
271 regulator-name = "vcc5v0_sys";
274 regulator-min-microvolt = <5000000>;
275 regulator-max-microvolt = <5000000>;
278 vcc_phy: vcc-phy-regulator {
279 compatible = "regulator-fixed";
280 regulator-name = "vcc_phy";
286 compatible = "pwm-regulator";
287 pwms = <&pwm2 0 25000 1>;
288 regulator-name = "vdd_log";
289 regulator-min-microvolt = <800000>;
290 regulator-max-microvolt = <1400000>;
294 /* for rockchip boot on */
295 rockchip,pwm_id= <2>;
296 rockchip,pwm_voltage = <1000000>;
299 vccadc_ref: vccadc-ref {
300 compatible = "regulator-fixed";
301 regulator-name = "vcc1v8_sys";
304 regulator-min-microvolt = <1800000>;
305 regulator-max-microvolt = <1800000>;
308 vcc_lcd: vcc-lcd-regulator {
309 compatible = "regulator-fixed";
313 gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&lcd_en>;
316 regulator-name = "vcc_lcd";
320 compatible = "wlan-platdata";
321 rockchip,grf = <&grf>;
322 wifi_chip_type = "ap6354";
324 WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
329 compatible = "bluetooth-platdata";
330 //wifi-bt-power-toggle;
331 uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */
332 pinctrl-names = "default", "rts_gpio";
333 pinctrl-0 = <&uart0_rts>;
334 pinctrl-1 = <&uart0_gpios>;
335 //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */
336 BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */
337 BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */
338 BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */
344 cpu-supply = <&vdd_cpu_l>;
348 cpu-supply = <&vdd_cpu_l>;
352 cpu-supply = <&vdd_cpu_l>;
356 cpu-supply = <&vdd_cpu_l>;
360 cpu-supply = <&vdd_cpu_b>;
364 cpu-supply = <&vdd_cpu_b>;
377 #address-cells = <1>;
380 edp_out_panel: endpoint@0 {
382 remote-endpoint = <&panel_in_edp>;
393 phy-supply = <&vcc_phy>;
395 clock_in_out = "input";
396 snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
397 snps,reset-active-low;
398 snps,reset-delays-us = <0 10000 50000>;
399 assigned-clocks = <&cru SCLK_RMII_SRC>;
400 assigned-clock-parents = <&clkin_gmac>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&rgmii_pins>;
410 mali-supply = <&vdd_gpu>;
414 #address-cells = <1>;
416 #sound-dai-cells = <0>;
422 i2c-scl-rising-time-ns = <168>;
423 i2c-scl-falling-time-ns = <4>;
424 clock-frequency = <400000>;
426 vdd_cpu_b: syr827@40 {
427 compatible = "silergy,syr827";
429 vin-supply = <&vcc5v0_sys>;
430 regulator-compatible = "fan53555-reg";
431 regulator-name = "vdd_cpu_b";
432 regulator-min-microvolt = <712500>;
433 regulator-max-microvolt = <1500000>;
434 regulator-ramp-delay = <1000>;
435 vsel-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
436 fcs,suspend-voltage-selector = <1>;
439 regulator-initial-state = <3>;
440 regulator-state-mem {
441 regulator-off-in-suspend;
446 compatible = "silergy,syr828";
448 vin-supply = <&vcc5v0_sys>;
449 regulator-compatible = "fan53555-reg";
450 regulator-name = "vdd_gpu";
451 regulator-min-microvolt = <712500>;
452 regulator-max-microvolt = <1500000>;
453 regulator-ramp-delay = <1000>;
454 fcs,suspend-voltage-selector = <1>;
457 regulator-initial-state = <3>;
458 regulator-state-mem {
459 regulator-off-in-suspend;
464 compatible = "rockchip,rk808";
466 interrupt-parent = <&gpio1>;
467 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
470 rockchip,system-power-controller;
473 clock-output-names = "xin32k", "rk808-clkout2";
475 vcc1-supply = <&vcc3v3_sys>;
476 vcc2-supply = <&vcc3v3_sys>;
477 vcc3-supply = <&vcc3v3_sys>;
478 vcc4-supply = <&vcc3v3_sys>;
479 vcc6-supply = <&vcc3v3_sys>;
480 vcc7-supply = <&vcc3v3_sys>;
481 vcc8-supply = <&vcc3v3_sys>;
482 vcc9-supply = <&vcc3v3_sys>;
483 vcc10-supply = <&vcc3v3_sys>;
484 vcc11-supply = <&vcc3v3_sys>;
485 vcc12-supply = <&vcc3v3_sys>;
486 vddio-supply = <&vcc1v8_pmu>;
489 vdd_center: DCDC_REG1 {
492 regulator-min-microvolt = <750000>;
493 regulator-max-microvolt = <1350000>;
494 regulator-ramp-delay = <6001>;
495 regulator-name = "vdd_center";
496 regulator-state-mem {
497 regulator-off-in-suspend;
501 vdd_cpu_l: DCDC_REG2 {
504 regulator-min-microvolt = <750000>;
505 regulator-max-microvolt = <1350000>;
506 regulator-ramp-delay = <6001>;
507 regulator-name = "vdd_cpu_l";
508 regulator-state-mem {
509 regulator-off-in-suspend;
516 regulator-name = "vcc_ddr";
517 regulator-state-mem {
518 regulator-on-in-suspend;
525 regulator-min-microvolt = <1800000>;
526 regulator-max-microvolt = <1800000>;
527 regulator-name = "vcc_1v8";
528 regulator-state-mem {
529 regulator-on-in-suspend;
530 regulator-suspend-microvolt = <1800000>;
534 vcc1v8_dvp: LDO_REG1 {
537 regulator-min-microvolt = <1800000>;
538 regulator-max-microvolt = <1800000>;
539 regulator-name = "vcc1v8_dvp";
540 regulator-state-mem {
541 regulator-off-in-suspend;
545 vcc3v0_tp: LDO_REG2 {
548 regulator-min-microvolt = <3000000>;
549 regulator-max-microvolt = <3000000>;
550 regulator-name = "vcc3v0_tp";
551 regulator-state-mem {
552 regulator-off-in-suspend;
556 vcc1v8_pmu: LDO_REG3 {
559 regulator-min-microvolt = <1800000>;
560 regulator-max-microvolt = <1800000>;
561 regulator-name = "vcc1v8_pmu";
562 regulator-state-mem {
563 regulator-on-in-suspend;
564 regulator-suspend-microvolt = <1800000>;
571 regulator-min-microvolt = <1800000>;
572 regulator-max-microvolt = <3300000>;
573 regulator-name = "vcc_sd";
574 regulator-state-mem {
575 regulator-on-in-suspend;
576 regulator-suspend-microvolt = <3300000>;
580 vcca3v0_codec: LDO_REG5 {
583 regulator-min-microvolt = <3000000>;
584 regulator-max-microvolt = <3000000>;
585 regulator-name = "vcca3v0_codec";
586 regulator-state-mem {
587 regulator-off-in-suspend;
594 regulator-min-microvolt = <1500000>;
595 regulator-max-microvolt = <1500000>;
596 regulator-name = "vcc_1v5";
597 regulator-state-mem {
598 regulator-on-in-suspend;
599 regulator-suspend-microvolt = <1500000>;
603 vcca1v8_codec: LDO_REG7 {
606 regulator-min-microvolt = <1800000>;
607 regulator-max-microvolt = <1800000>;
608 regulator-name = "vcca1v8_codec";
609 regulator-state-mem {
610 regulator-off-in-suspend;
617 regulator-min-microvolt = <3000000>;
618 regulator-max-microvolt = <3000000>;
619 regulator-name = "vcc_3v0";
620 regulator-state-mem {
621 regulator-on-in-suspend;
622 regulator-suspend-microvolt = <3000000>;
626 vcc3v3_s3: SWITCH_REG1 {
629 regulator-name = "vcc3v3_s3";
630 regulator-state-mem {
631 regulator-off-in-suspend;
635 vcc3v3_s0: SWITCH_REG2 {
638 regulator-name = "vcc3v3_s0";
639 regulator-state-mem {
640 regulator-off-in-suspend;
649 i2c-scl-rising-time-ns = <300>;
650 i2c-scl-falling-time-ns = <15>;
653 #sound-dai-cells = <0>;
654 compatible = "realtek,rt5640";
656 clocks = <&cru SCLK_I2S_8CH_OUT>;
657 clock-names = "mclk";
658 realtek,in1-differential;
659 pinctrl-names = "default";
660 pinctrl-0 = <&rt5640_hpcon>;
661 hp-con-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
662 //hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
663 io-channels = <&saradc 4>;
664 hp-det-adc-value = <500>;
670 i2c-scl-rising-time-ns = <450>;
671 i2c-scl-falling-time-ns = <15>;
676 i2c-scl-rising-time-ns = <600>;
677 i2c-scl-falling-time-ns = <20>;
680 compatible = "fairchild,fusb302";
682 pinctrl-names = "default";
683 pinctrl-0 = <&fusb0_int>;
684 int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
685 vbus-5v-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
689 gsl3680: gsl3680@41 {
691 compatible = "gslX680-pad";
693 screen_max_x = <1536>;
694 screen_max_y = <2048>;
695 touch-gpio = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
696 reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
701 compatible = "invensense,mpu6050";
703 mpu-int_config = <0x10>;
704 mpu-level_shifter = <0>;
705 mpu-orientation = <0 1 0 1 0 0 0 0 1>;
709 irq-gpio = <&gpio1 4 IRQ_TYPE_LEVEL_LOW>;
716 rockchip,i2s-broken-burst-len;
717 rockchip,playback-channels = <8>;
718 rockchip,capture-channels = <8>;
719 #sound-dai-cells = <0>;
724 rockchip,i2s-broken-burst-len;
725 rockchip,playback-channels = <2>;
726 rockchip,capture-channels = <2>;
727 #sound-dai-cells = <0>;
731 #sound-dai-cells = <0>;
738 bt656-supply = <&vcc1v8_dvp>; /* bt656_gpio2ab_ms */
739 audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */
740 sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
741 gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
749 ep-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
751 pinctrl-names = "default";
752 pinctrl-0 = <&pcie_clkreqn_cpm>;
758 pmu1830-supply = <&vcc_3v0>;
764 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
769 lcd_panel_reset: lcd-panel-reset {
770 rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_up>;
774 rockchip,pins = <1 1 RK_FUNC_GPIO &pcfg_pull_up>;
781 <1 17 RK_FUNC_GPIO &pcfg_pull_none>;
783 pcie_3g_drv: pcie-3g-drv {
785 <0 2 RK_FUNC_GPIO &pcfg_pull_up>;
790 vsel1_gpio: vsel1-gpio {
792 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
795 vsel2_gpio: vsel2-gpio {
797 <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
802 wifi_enable_h: wifi-enable-h {
804 <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
809 uart0_gpios: uart0-gpios {
811 <2 19 RK_FUNC_GPIO &pcfg_pull_none>;
816 rt5640_hpcon: rt5640-hpcon {
817 rockchip,pins = <4 21 RK_FUNC_GPIO &pcfg_pull_none>;
822 pmic_int_l: pmic-int-l {
824 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
827 pmic_dvs2: pmic-dvs2 {
829 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
834 host_vbus_drv: host-vbus-drv {
836 <4 25 RK_FUNC_GPIO &pcfg_pull_none>;
841 fusb0_int: fusb0-int {
842 rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
860 rockchip,power-ctrl =
861 <&gpio1 18 GPIO_ACTIVE_LOW>,
862 <&gpio1 14 GPIO_ACTIVE_HIGH>;
871 vref-supply = <&vccadc_ref>;
876 keep-power-in-suspend;
878 mmc-hs400-enhanced-strobe;
885 max-frequency = <150000000>;
892 vqmmc-supply = <&vcc_sd>;
893 pinctrl-names = "default";
894 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
899 max-frequency = <50000000>;
904 keep-power-in-suspend;
905 mmc-pwrseq = <&sdio_pwrseq>;
908 pinctrl-names = "default";
909 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
916 pinctrl-0 = <&spdif_bus_1>;
917 i2c-scl-rising-time-ns = <450>;
918 i2c-scl-falling-time-ns = <15>;
919 #sound-dai-cells = <0>;
932 /* tshut mode 0:CRU 1:GPIO */
933 rockchip,hw-tshut-mode = <1>;
934 /* tshut polarity 0:LOW 1:HIGH */
935 rockchip,hw-tshut-polarity = <1>;
943 u2phy0_otg: otg-port {
947 u2phy0_host: host-port {
948 phy-supply = <&vcc5v0_host>;
956 u2phy1_otg: otg-port {
960 u2phy1_host: host-port {
961 phy-supply = <&vcc5v0_host>;
967 pinctrl-names = "default";
968 pinctrl-0 = <&uart0_xfer &uart0_cts>;