2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "dt-bindings/pwm/pwm.h"
46 #include "rk3399.dtsi"
47 #include "rk3399-opp.dtsi"
48 #include "rk3399-linux.dtsi"
49 #include <dt-bindings/input/input.h>
52 model = "Rockchip RK3399 Firefly Board (Linux Opensource)";
53 compatible = "rockchip,rk3399-firefly-mini-linux", "rockchip,rk3399";
55 backlight: backlight {
57 compatible = "pwm-backlight";
58 pwms = <&pwm1 0 25000 0>;
62 16 17 18 19 20 21 22 23
63 24 25 26 27 28 29 30 31
64 32 33 34 35 36 37 38 39
65 40 41 42 43 44 45 46 47
66 48 49 50 51 52 53 54 55
67 56 57 58 59 60 61 62 63
68 64 65 66 67 68 69 70 71
69 72 73 74 75 76 77 78 79
70 80 81 82 83 84 85 86 87
71 88 89 90 91 92 93 94 95
72 96 97 98 99 100 101 102 103
73 104 105 106 107 108 109 110 111
74 112 113 114 115 116 117 118 119
75 120 121 122 123 124 125 126 127
76 128 129 130 131 132 133 134 135
77 136 137 138 139 140 141 142 143
78 144 145 146 147 148 149 150 151
79 152 153 154 155 156 157 158 159
80 160 161 162 163 164 165 166 167
81 168 169 170 171 172 173 174 175
82 176 177 178 179 180 181 182 183
83 184 185 186 187 188 189 190 191
84 192 193 194 195 196 197 198 199
85 200 201 202 203 204 205 206 207
86 208 209 210 211 212 213 214 215
87 216 217 218 219 220 221 222 223
88 224 225 226 227 228 229 230 231
89 232 233 234 235 236 237 238 239
90 240 241 242 243 244 245 246 247
91 248 249 250 251 252 253 254 255>;
92 default-brightness-level = <200>;
95 clkin_gmac: external-gmac-clock {
96 compatible = "fixed-clock";
97 clock-frequency = <125000000>;
98 clock-output-names = "clkin_gmac";
102 dw_hdmi_audio: dw-hdmi-audio {
104 compatible = "rockchip,dw-hdmi-audio";
105 #sound-dai-cells = <0>;
108 edp_panel: edp-panel {
110 compatible = "sharp,lcd-f402", "panel-simple";
111 backlight = <&backlight>;
112 power-supply = <&vcc_lcd>;
113 enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&lcd_panel_reset>;
118 panel_in_edp: endpoint {
119 remote-endpoint = <&edp_out_panel>;
124 fiq_debugger: fiq-debugger {
125 compatible = "rockchip,fiq-debugger";
126 rockchip,serial-id = <2>;
127 rockchip,signal-irq = <182>;
128 rockchip,wake-irq = <0>;
129 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
130 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
131 pinctrl-names = "default";
132 pinctrl-0 = <&uart2c_xfer>;
136 compatible = "gpio-keys";
137 #address-cells = <1>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pwrbtn>;
145 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
146 linux,code = <KEY_POWER>;
147 label = "GPIO Key Power";
148 linux,input-type = <1>;
149 gpio-key,wakeup = <1>;
150 debounce-interval = <100>;
156 compatible = "simple-audio-card";
157 simple-audio-card,format = "i2s";
158 simple-audio-card,name = "rockchip,rt5640-codec";
159 simple-audio-card,mclk-fs = <256>;
160 simple-audio-card,widgets =
161 "Microphone", "Mic Jack",
162 "Headphone", "Headphone Jack";
163 simple-audio-card,routing =
164 "Mic Jack", "MICBIAS1",
166 "Headphone Jack", "HPOL",
167 "Headphone Jack", "HPOR";
168 simple-audio-card,cpu {
171 simple-audio-card,codec {
172 sound-dai = <&rt5640>;
177 compatible = "simple-audio-card";
178 simple-audio-card,format = "i2s";
179 simple-audio-card,name = "rockchip,es8323-codec";
180 simple-audio-card,mclk-fs = <256>;
181 simple-audio-card,widgets =
182 "Microphone","Mic Jack",
183 "Headphone","Headphone Jack";
184 simple-audio-card,routing =
185 "Mic Jack","MICBIAS1",
187 "Headphone Jack","HPOL",
188 "Headphone Jack","HPOR";
189 simple-audio-card,cpu {
192 simple-audio-card,codec {
193 sound-dai = <&es8323>;
197 hdmi_sound: hdmi-sound {
199 compatible = "simple-audio-card";
200 simple-audio-card,format = "i2s";
201 simple-audio-card,mclk-fs = <256>;
202 simple-audio-card,name = "rockchip,hdmi";
204 simple-audio-card,cpu {
207 simple-audio-card,codec {
208 sound-dai = <&dw_hdmi_audio>;
212 hdmi_codec: hdmi-codec {
213 compatible = "simple-audio-card";
214 simple-audio-card,format = "i2s";
215 simple-audio-card,mclk-fs = <256>;
216 simple-audio-card,name = "HDMI-CODEC";
218 simple-audio-card,cpu {
221 simple-audio-card,codec {
226 sdio_pwrseq: sdio-pwrseq {
227 compatible = "mmc-pwrseq-simple";
229 clock-names = "ext_clock";
230 pinctrl-names = "default";
231 pinctrl-0 = <&wifi_enable_h>;
234 * On the module itself this is one of these (depending
235 * on the actual card populated):
236 * - SDIO_RESET_L_WL_REG_ON
237 * - PDN (power down when low)
239 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
242 vcc3v3_pcie: vcc3v3-pcie-regulator {
244 compatible = "regulator-fixed";
248 gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
249 pinctrl-names = "default";
250 pinctrl-0 = <&pcie_drv>;
251 regulator-name = "vcc3v3_pcie";
254 vcc3v3_sys: vcc3v3-sys {
255 compatible = "regulator-fixed";
256 regulator-name = "vcc3v3_sys";
259 regulator-min-microvolt = <3300000>;
260 regulator-max-microvolt = <3300000>;
263 vcc5v0_host: vcc5v0-host-regulator {
264 compatible = "regulator-fixed";
266 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&host_vbus_drv>;
269 regulator-name = "vcc5v0_host";
273 vbus_5v: vbus-5v-regulator {
274 compatible = "regulator-fixed";
278 gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&vbus_5v_drv>;
281 regulator-name = "vbus_5v";
284 vcc5v0_sys: vcc5v0-sys {
285 compatible = "regulator-fixed";
286 regulator-name = "vcc5v0_sys";
289 regulator-min-microvolt = <5000000>;
290 regulator-max-microvolt = <5000000>;
293 vcc_phy: vcc-phy-regulator {
294 compatible = "regulator-fixed";
295 regulator-name = "vcc_phy";
301 compatible = "pwm-regulator";
302 pwms = <&pwm2 0 25000 1>;
303 regulator-name = "vdd_log";
304 regulator-min-microvolt = <800000>;
305 regulator-max-microvolt = <1400000>;
309 /* for rockchip boot on */
310 rockchip,pwm_id= <2>;
311 rockchip,pwm_voltage = <1000000>;
314 vccadc_ref: vccadc-ref {
315 compatible = "regulator-fixed";
316 regulator-name = "vcc1v8_sys";
319 regulator-min-microvolt = <1800000>;
320 regulator-max-microvolt = <1800000>;
323 vcc_lcd: vcc-lcd-regulator {
324 compatible = "regulator-fixed";
328 gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&lcd_en>;
331 regulator-name = "vcc_lcd";
335 compatible = "wlan-platdata";
336 rockchip,grf = <&grf>;
337 wifi_chip_type = "ap6212";
339 WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
344 compatible = "bluetooth-platdata";
345 //wifi-bt-power-toggle;
347 clock-names = "ext_clock";
348 uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */
349 pinctrl-names = "default", "rts_gpio";
350 pinctrl-0 = <&uart0_rts>;
351 pinctrl-1 = <&uart0_gpios>;
352 //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */
353 BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */
354 BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */
355 BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */
360 compatible = "gpio-leds";
362 label = "firefly:blue:power";
363 linux,default-trigger = "ir-power-click";
364 default-state = "on";
365 gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&led_power>;
370 label = "firefly:yellow:user";
371 linux,default-trigger = "ir-user-click";
372 default-state = "off";
373 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&led_user>;
382 dsi_panel: dsi_panel {
383 compatible ="simple-panel-dsi";
385 //enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
386 //reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
387 dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>;
388 dsi,format = <MIPI_DSI_FMT_RGB888>;
390 delay,prepare = <10>;
399 delay,prepare = <10>;
401 delay,unpreapre = <0>;
410 panel-init-sequence = [
414 panel-exit-sequence = [
419 disp_timings: display-timings {
420 native-mode = <&timing0>;
422 clock-frequency = <64000000>;
425 hsync-len = <5>; //20, 50
426 hback-porch = <25>; //50, 56
427 hfront-porch = <150>;//50, 30
430 vfront-porch = <100>;
434 pixelclk-active = <0>;
441 cpu-supply = <&vdd_cpu_l>;
445 cpu-supply = <&vdd_cpu_l>;
449 cpu-supply = <&vdd_cpu_l>;
453 cpu-supply = <&vdd_cpu_l>;
457 cpu-supply = <&vdd_cpu_b>;
461 cpu-supply = <&vdd_cpu_b>;
474 #address-cells = <1>;
477 edp_out_panel: endpoint@0 {
479 remote-endpoint = <&panel_in_edp>;
490 phy-supply = <&vcc_phy>;
492 clock_in_out = "input";
493 snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
494 snps,reset-active-low;
495 snps,reset-delays-us = <0 10000 50000>;
496 assigned-clocks = <&cru SCLK_RMII_SRC>;
497 assigned-clock-parents = <&clkin_gmac>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&rgmii_pins>;
507 mali-supply = <&vdd_gpu>;
511 #address-cells = <1>;
513 #sound-dai-cells = <0>;
519 i2c-scl-rising-time-ns = <168>;
520 i2c-scl-falling-time-ns = <4>;
521 clock-frequency = <400000>;
523 vdd_cpu_b: syr827@40 {
524 compatible = "silergy,syr827";
526 vin-supply = <&vcc5v0_sys>;
527 regulator-compatible = "fan53555-reg";
528 regulator-name = "vdd_cpu_b";
529 regulator-min-microvolt = <712500>;
530 regulator-max-microvolt = <1500000>;
531 regulator-ramp-delay = <1000>;
532 vsel-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
533 fcs,suspend-voltage-selector = <1>;
536 regulator-initial-state = <3>;
537 regulator-state-mem {
538 regulator-off-in-suspend;
543 compatible = "silergy,syr828";
545 vin-supply = <&vcc5v0_sys>;
546 regulator-compatible = "fan53555-reg";
547 regulator-name = "vdd_gpu";
548 regulator-min-microvolt = <712500>;
549 regulator-max-microvolt = <1500000>;
550 regulator-ramp-delay = <1000>;
551 fcs,suspend-voltage-selector = <1>;
554 regulator-initial-state = <3>;
555 regulator-state-mem {
556 regulator-off-in-suspend;
561 compatible = "rockchip,rk808";
563 interrupt-parent = <&gpio1>;
564 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
567 rockchip,system-power-controller;
570 clock-output-names = "xin32k", "rk808-clkout2";
572 vcc1-supply = <&vcc3v3_sys>;
573 vcc2-supply = <&vcc3v3_sys>;
574 vcc3-supply = <&vcc3v3_sys>;
575 vcc4-supply = <&vcc3v3_sys>;
576 vcc6-supply = <&vcc3v3_sys>;
577 vcc7-supply = <&vcc3v3_sys>;
578 vcc8-supply = <&vcc3v3_sys>;
579 vcc9-supply = <&vcc3v3_sys>;
580 vcc10-supply = <&vcc3v3_sys>;
581 vcc11-supply = <&vcc3v3_sys>;
582 vcc12-supply = <&vcc3v3_sys>;
583 vddio-supply = <&vcc1v8_pmu>;
586 vdd_center: DCDC_REG1 {
589 regulator-min-microvolt = <750000>;
590 regulator-max-microvolt = <1350000>;
591 regulator-ramp-delay = <6001>;
592 regulator-name = "vdd_center";
593 regulator-state-mem {
594 regulator-off-in-suspend;
598 vdd_cpu_l: DCDC_REG2 {
601 regulator-min-microvolt = <750000>;
602 regulator-max-microvolt = <1350000>;
603 regulator-ramp-delay = <6001>;
604 regulator-name = "vdd_cpu_l";
605 regulator-state-mem {
606 regulator-off-in-suspend;
613 regulator-name = "vcc_ddr";
614 regulator-state-mem {
615 regulator-on-in-suspend;
622 regulator-min-microvolt = <1800000>;
623 regulator-max-microvolt = <1800000>;
624 regulator-name = "vcc_1v8";
625 regulator-state-mem {
626 regulator-on-in-suspend;
627 regulator-suspend-microvolt = <1800000>;
631 vcc1v8_dvp: LDO_REG1 {
634 regulator-min-microvolt = <1800000>;
635 regulator-max-microvolt = <1800000>;
636 regulator-name = "vcc1v8_dvp";
637 regulator-state-mem {
638 regulator-off-in-suspend;
642 vcc2v8_dvp: LDO_REG2 {
643 //regulator-always-on;
645 regulator-min-microvolt = <2800000>;
646 regulator-max-microvolt = <2800000>;
647 regulator-name = "vcc2v8_dvp";
648 regulator-state-mem {
649 regulator-off-in-suspend;
653 vcc1v8_pmu: LDO_REG3 {
656 regulator-min-microvolt = <1800000>;
657 regulator-max-microvolt = <1800000>;
658 regulator-name = "vcc1v8_pmu";
659 regulator-state-mem {
660 regulator-on-in-suspend;
661 regulator-suspend-microvolt = <1800000>;
668 regulator-min-microvolt = <1800000>;
669 regulator-max-microvolt = <3300000>;
670 regulator-name = "vcc_sd";
671 regulator-state-mem {
672 regulator-on-in-suspend;
673 regulator-suspend-microvolt = <3300000>;
677 vcca3v0_codec: LDO_REG5 {
680 regulator-min-microvolt = <3000000>;
681 regulator-max-microvolt = <3000000>;
682 regulator-name = "vcca3v0_codec";
683 regulator-state-mem {
684 regulator-off-in-suspend;
691 regulator-min-microvolt = <1500000>;
692 regulator-max-microvolt = <1500000>;
693 regulator-name = "vcc_1v5";
694 regulator-state-mem {
695 regulator-on-in-suspend;
696 regulator-suspend-microvolt = <1500000>;
700 vcca1v8_codec: LDO_REG7 {
703 regulator-min-microvolt = <1800000>;
704 regulator-max-microvolt = <1800000>;
705 regulator-name = "vcca1v8_codec";
706 regulator-state-mem {
707 regulator-off-in-suspend;
714 regulator-min-microvolt = <3000000>;
715 regulator-max-microvolt = <3000000>;
716 regulator-name = "vcc_3v0";
717 regulator-state-mem {
718 regulator-on-in-suspend;
719 regulator-suspend-microvolt = <3000000>;
723 vcc3v3_s3: SWITCH_REG1 {
726 regulator-name = "vcc3v3_s3";
727 regulator-state-mem {
728 regulator-off-in-suspend;
732 vcc3v3_s0: SWITCH_REG2 {
735 regulator-name = "vcc3v3_s0";
736 regulator-state-mem {
737 regulator-off-in-suspend;
746 i2c-scl-rising-time-ns = <300>;
747 i2c-scl-falling-time-ns = <15>;
750 compatible = "everest,es8323";
752 ear-con-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
753 hp-det-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
755 #sound-dai-cells = <0>;
756 system-clock-frequency = <11289600>;
757 clocks = <&cru SCLK_I2S_8CH_OUT>;
758 clock-names = "mclk";
759 pinctrl-names = "default";
760 pinctrl-0 = <&es8323_earcon &es8323_hpdet>;
764 #sound-dai-cells = <0>;
765 compatible = "realtek,rt5640";
767 clocks = <&cru SCLK_I2S_8CH_OUT>;
768 clock-names = "mclk";
769 realtek,in1-differential;
770 pinctrl-names = "default";
771 pinctrl-0 = <&rt5640_hpcon>;
772 hp-con-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
773 //hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
774 io-channels = <&saradc 4>;
775 hp-det-adc-value = <500>;
781 i2c-scl-rising-time-ns = <450>;
782 i2c-scl-falling-time-ns = <15>;
787 i2c-scl-rising-time-ns = <475>;
788 i2c-scl-falling-time-ns = <26>;
791 compatible = "fairchild,fusb302";
793 pinctrl-names = "default";
794 pinctrl-0 = <&fusb0_int>;
795 int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
796 vbus-5v-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
800 gsl3680: gsl3680@40 {
802 compatible = "gslX680";
804 screen_max_x = <1536>;
805 screen_max_y = <2048>;
806 touch-gpio = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>;
807 reset-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
812 compatible = "invensense,mpu6050";
814 mpu-int_config = <0x10>;
815 mpu-level_shifter = <0>;
816 mpu-orientation = <0 1 0 1 0 0 0 0 1>;
820 irq-gpio = <&gpio1 4 IRQ_TYPE_LEVEL_LOW>;
827 rockchip,i2s-broken-burst-len;
828 rockchip,playback-channels = <8>;
829 rockchip,capture-channels = <8>;
830 #sound-dai-cells = <0>;
835 rockchip,i2s-broken-burst-len;
836 rockchip,playback-channels = <2>;
837 rockchip,capture-channels = <2>;
838 #sound-dai-cells = <0>;
839 assigned-clocks = <&cru SCLK_I2S1_DIV>, <&cru SCLK_I2S_8CH>;
840 assigned-clock-parents = <&cru PLL_GPLL>, <&cru SCLK_I2S1_8CH>;
844 #sound-dai-cells = <0>;
851 bt656-supply = <&vcc_3v0>; /* bt656_gpio2ab_ms */
852 audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */
853 sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
854 gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
862 ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
864 pinctrl-names = "default";
865 pinctrl-0 = <&pcie_clkreqn_cpm>;
871 pmu1830-supply = <&vcc_3v0>;
877 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
882 lcd_panel_reset: lcd-panel-reset {
883 rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_up>;
887 rockchip,pins = <1 1 RK_FUNC_GPIO &pcfg_pull_up>;
894 <1 17 RK_FUNC_GPIO &pcfg_pull_none>;
896 pcie_3g_drv: pcie-3g-drv {
898 <0 2 RK_FUNC_GPIO &pcfg_pull_up>;
903 vsel1_gpio: vsel1-gpio {
905 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
908 vsel2_gpio: vsel2-gpio {
910 <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
915 wifi_enable_h: wifi-enable-h {
917 <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
922 uart0_gpios: uart0-gpios {
924 <2 19 RK_FUNC_GPIO &pcfg_pull_none>,
925 <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
930 led_power: led-power {
931 rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>;
935 rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_none>;
939 rt5640_hpcon: rt5640-hpcon {
940 rockchip,pins = <4 21 RK_FUNC_GPIO &pcfg_pull_none>;
945 es8323_hpdet: es8323-hpdet {
946 rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_up>;
948 es8323_earcon: es8323-earcon {
949 rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
954 pmic_int_l: pmic-int-l {
956 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
959 pmic_dvs2: pmic-dvs2 {
961 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
966 host_vbus_drv: host-vbus-drv {
968 <1 0 RK_FUNC_GPIO &pcfg_pull_none>;
973 fusb0_int: fusb0-int {
974 rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
979 vbus_5v_drv: vbus-5v-drv {
980 rockchip,pins = <1 3 RK_FUNC_GPIO &pcfg_pull_up>;
998 rockchip,power-ctrl =
999 <&gpio1 18 GPIO_ACTIVE_LOW>,
1000 <&gpio1 14 GPIO_ACTIVE_HIGH>;
1004 status = "disabled";
1009 logo,mode = "center";
1013 status = "disabled";
1015 phys = <&tcphy0_dp>;
1019 status = "disabled";
1024 vref-supply = <&vccadc_ref>;
1029 keep-power-in-suspend;
1031 mmc-hs400-enhanced-strobe;
1038 max-frequency = <150000000>;
1045 vqmmc-supply = <&vcc_sd>;
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
1052 max-frequency = <50000000>;
1057 keep-power-in-suspend;
1058 mmc-pwrseq = <&sdio_pwrseq>;
1061 pinctrl-names = "default";
1062 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
1068 //extcon = <&fusb0>;
1077 /* tshut mode 0:CRU 1:GPIO */
1078 rockchip,hw-tshut-mode = <1>;
1079 /* tshut polarity 0:LOW 1:HIGH */
1080 rockchip,hw-tshut-polarity = <1>;
1086 //extcon = <&fusb0>;
1088 u2phy0_otg: otg-port {
1092 u2phy0_host: host-port {
1093 phy-supply = <&vcc5v0_host>;
1101 u2phy1_otg: otg-port {
1105 u2phy1_host: host-port {
1106 phy-supply = <&vcc5v0_host>;
1113 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 0>;
1114 compatible = "rockchip,remotectl-pwm";
1115 remote_pwm_id = <3>;
1116 handle_cpu_id = <0>;
1119 rockchip,usercode = <0xff00>;
1120 rockchip,key_table =
1126 <0xf4 KEY_VOLUMEUP>,
1127 <0xa7 KEY_VOLUMEDOWN>,
1137 pinctrl-names = "default";
1138 pinctrl-0 = <&uart0_xfer &uart0_cts>;
1148 //extcon = <&fusb0>;
1157 //dr_mode = "peripheral";