2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
45 #include "dt-bindings/pwm/pwm.h"
46 #include "rk3399.dtsi"
47 #include "rk3399-opp.dtsi"
48 #include "rk3399-linux.dtsi"
49 #include <dt-bindings/input/input.h>
52 model = "Rockchip RK3399 Firefly Board (Linux Opensource)";
53 compatible = "rockchip,rk3399-firefly-mini-linux", "rockchip,rk3399";
55 backlight: backlight {
57 compatible = "pwm-backlight";
58 pwms = <&pwm0 0 25000 0>;
62 16 17 18 19 20 21 22 23
63 24 25 26 27 28 29 30 31
64 32 33 34 35 36 37 38 39
65 40 41 42 43 44 45 46 47
66 48 49 50 51 52 53 54 55
67 56 57 58 59 60 61 62 63
68 64 65 66 67 68 69 70 71
69 72 73 74 75 76 77 78 79
70 80 81 82 83 84 85 86 87
71 88 89 90 91 92 93 94 95
72 96 97 98 99 100 101 102 103
73 104 105 106 107 108 109 110 111
74 112 113 114 115 116 117 118 119
75 120 121 122 123 124 125 126 127
76 128 129 130 131 132 133 134 135
77 136 137 138 139 140 141 142 143
78 144 145 146 147 148 149 150 151
79 152 153 154 155 156 157 158 159
80 160 161 162 163 164 165 166 167
81 168 169 170 171 172 173 174 175
82 176 177 178 179 180 181 182 183
83 184 185 186 187 188 189 190 191
84 192 193 194 195 196 197 198 199
85 200 201 202 203 204 205 206 207
86 208 209 210 211 212 213 214 215
87 216 217 218 219 220 221 222 223
88 224 225 226 227 228 229 230 231
89 232 233 234 235 236 237 238 239
90 240 241 242 243 244 245 246 247
91 248 249 250 251 252 253 254 255>;
92 default-brightness-level = <200>;
95 clkin_gmac: external-gmac-clock {
96 compatible = "fixed-clock";
97 clock-frequency = <125000000>;
98 clock-output-names = "clkin_gmac";
102 dw_hdmi_audio: dw-hdmi-audio {
104 compatible = "rockchip,dw-hdmi-audio";
105 #sound-dai-cells = <0>;
108 edp_panel: edp-panel {
110 compatible = "sharp,lcd-f402", "panel-simple";
111 backlight = <&backlight>;
112 power-supply = <&vcc_lcd>;
113 enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&lcd_panel_reset>;
118 panel_in_edp: endpoint {
119 remote-endpoint = <&edp_out_panel>;
124 fiq_debugger: fiq-debugger {
125 compatible = "rockchip,fiq-debugger";
126 rockchip,serial-id = <2>;
127 rockchip,signal-irq = <182>;
128 rockchip,wake-irq = <0>;
129 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
130 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
131 pinctrl-names = "default";
132 pinctrl-0 = <&uart2c_xfer>;
136 compatible = "gpio-keys";
137 #address-cells = <1>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pwrbtn>;
145 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
146 linux,code = <KEY_POWER>;
147 label = "GPIO Key Power";
148 linux,input-type = <1>;
149 gpio-key,wakeup = <1>;
150 debounce-interval = <100>;
156 compatible = "simple-audio-card";
157 simple-audio-card,format = "i2s";
158 simple-audio-card,name = "rockchip,rt5640-codec";
159 simple-audio-card,mclk-fs = <256>;
160 simple-audio-card,widgets =
161 "Microphone", "Mic Jack",
162 "Headphone", "Headphone Jack";
163 simple-audio-card,routing =
164 "Mic Jack", "MICBIAS1",
166 "Headphone Jack", "HPOL",
167 "Headphone Jack", "HPOR";
168 simple-audio-card,cpu {
171 simple-audio-card,codec {
172 sound-dai = <&rt5640>;
177 compatible = "simple-audio-card";
178 simple-audio-card,format = "i2s";
179 simple-audio-card,name = "rockchip,es8323-codec";
180 simple-audio-card,mclk-fs = <256>;
181 simple-audio-card,widgets =
182 "Microphone","Mic Jack",
183 "Headphone","Headphone Jack";
184 simple-audio-card,routing =
185 "Mic Jack","MICBIAS1",
187 "Headphone Jack","HPOL",
188 "Headphone Jack","HPOR";
189 simple-audio-card,cpu {
192 simple-audio-card,codec {
193 sound-dai = <&es8323>;
198 hdmi_sound: hdmi-sound {
200 compatible = "simple-audio-card";
201 simple-audio-card,format = "i2s";
202 simple-audio-card,mclk-fs = <256>;
203 simple-audio-card,name = "rockchip,hdmi";
205 simple-audio-card,cpu {
208 simple-audio-card,codec {
209 sound-dai = <&dw_hdmi_audio>;
213 hdmi_codec: hdmi-codec {
214 compatible = "simple-audio-card";
215 simple-audio-card,format = "i2s";
216 simple-audio-card,mclk-fs = <256>;
217 simple-audio-card,name = "HDMI-CODEC";
219 simple-audio-card,cpu {
223 simple-audio-card,codec {
228 sdio_pwrseq: sdio-pwrseq {
229 compatible = "mmc-pwrseq-simple";
231 clock-names = "ext_clock";
232 pinctrl-names = "default";
233 pinctrl-0 = <&wifi_enable_h>;
236 * On the module itself this is one of these (depending
237 * on the actual card populated):
238 * - SDIO_RESET_L_WL_REG_ON
239 * - PDN (power down when low)
241 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
244 vcc3v3_pcie: vcc3v3-pcie-regulator {
246 compatible = "regulator-fixed";
250 gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pcie_drv>;
253 regulator-name = "vcc3v3_pcie";
256 vcc3v3_sys: vcc3v3-sys {
257 compatible = "regulator-fixed";
258 regulator-name = "vcc3v3_sys";
261 regulator-min-microvolt = <3300000>;
262 regulator-max-microvolt = <3300000>;
265 vcc5v0_host: vcc5v0-host-regulator {
266 compatible = "regulator-fixed";
268 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&host_vbus_drv>;
271 regulator-name = "vcc5v0_host";
275 vcc5v0_sys: vcc5v0-sys {
276 compatible = "regulator-fixed";
277 regulator-name = "vcc5v0_sys";
280 regulator-min-microvolt = <5000000>;
281 regulator-max-microvolt = <5000000>;
284 vcc_phy: vcc-phy-regulator {
285 compatible = "regulator-fixed";
286 regulator-name = "vcc_phy";
292 compatible = "pwm-regulator";
293 pwms = <&pwm2 0 25000 1>;
294 regulator-name = "vdd_log";
295 regulator-min-microvolt = <800000>;
296 regulator-max-microvolt = <1400000>;
300 /* for rockchip boot on */
301 rockchip,pwm_id= <2>;
302 rockchip,pwm_voltage = <1000000>;
305 vccadc_ref: vccadc-ref {
306 compatible = "regulator-fixed";
307 regulator-name = "vcc1v8_sys";
310 regulator-min-microvolt = <1800000>;
311 regulator-max-microvolt = <1800000>;
314 vcc_lcd: vcc-lcd-regulator {
315 compatible = "regulator-fixed";
319 gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&lcd_en>;
322 regulator-name = "vcc_lcd";
326 compatible = "wlan-platdata";
327 rockchip,grf = <&grf>;
328 wifi_chip_type = "ap6212";
330 WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
335 compatible = "bluetooth-platdata";
336 //wifi-bt-power-toggle;
338 clock-names = "ext_clock";
339 uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */
340 pinctrl-names = "default", "rts_gpio";
341 pinctrl-0 = <&uart0_rts>;
342 pinctrl-1 = <&uart0_gpios>;
343 //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */
344 BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */
345 BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */
346 BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */
352 compatible = "gpio-leds";
354 label = "firefly:blue:power";
355 linux,default-trigger = "ir-power-click";
356 default-state = "on";
357 gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&led_power>;
362 label = "firefly:yellow:user";
363 linux,default-trigger = "ir-user-click";
364 default-state = "off";
365 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&led_user>;
373 cpu-supply = <&vdd_cpu_l>;
377 cpu-supply = <&vdd_cpu_l>;
381 cpu-supply = <&vdd_cpu_l>;
385 cpu-supply = <&vdd_cpu_l>;
389 cpu-supply = <&vdd_cpu_b>;
393 cpu-supply = <&vdd_cpu_b>;
406 #address-cells = <1>;
409 edp_out_panel: endpoint@0 {
411 remote-endpoint = <&panel_in_edp>;
422 phy-supply = <&vcc_phy>;
424 clock_in_out = "input";
425 snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
426 snps,reset-active-low;
427 snps,reset-delays-us = <0 10000 50000>;
428 assigned-clocks = <&cru SCLK_RMII_SRC>;
429 assigned-clock-parents = <&clkin_gmac>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&rgmii_pins>;
439 mali-supply = <&vdd_gpu>;
443 #address-cells = <1>;
445 #sound-dai-cells = <0>;
451 i2c-scl-rising-time-ns = <168>;
452 i2c-scl-falling-time-ns = <4>;
453 clock-frequency = <400000>;
455 vdd_cpu_b: syr827@40 {
456 compatible = "silergy,syr827";
458 vin-supply = <&vcc5v0_sys>;
459 regulator-compatible = "fan53555-reg";
460 regulator-name = "vdd_cpu_b";
461 regulator-min-microvolt = <712500>;
462 regulator-max-microvolt = <1500000>;
463 regulator-ramp-delay = <1000>;
464 vsel-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
465 fcs,suspend-voltage-selector = <1>;
468 regulator-initial-state = <3>;
469 regulator-state-mem {
470 regulator-off-in-suspend;
475 compatible = "silergy,syr828";
477 vin-supply = <&vcc5v0_sys>;
478 regulator-compatible = "fan53555-reg";
479 regulator-name = "vdd_gpu";
480 regulator-min-microvolt = <712500>;
481 regulator-max-microvolt = <1500000>;
482 regulator-ramp-delay = <1000>;
483 fcs,suspend-voltage-selector = <1>;
486 regulator-initial-state = <3>;
487 regulator-state-mem {
488 regulator-off-in-suspend;
493 compatible = "rockchip,rk808";
495 interrupt-parent = <&gpio1>;
496 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
497 pinctrl-names = "default";
498 pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
499 rockchip,system-power-controller;
502 clock-output-names = "xin32k", "rk808-clkout2";
504 vcc1-supply = <&vcc3v3_sys>;
505 vcc2-supply = <&vcc3v3_sys>;
506 vcc3-supply = <&vcc3v3_sys>;
507 vcc4-supply = <&vcc3v3_sys>;
508 vcc6-supply = <&vcc3v3_sys>;
509 vcc7-supply = <&vcc3v3_sys>;
510 vcc8-supply = <&vcc3v3_sys>;
511 vcc9-supply = <&vcc3v3_sys>;
512 vcc10-supply = <&vcc3v3_sys>;
513 vcc11-supply = <&vcc3v3_sys>;
514 vcc12-supply = <&vcc3v3_sys>;
515 vddio-supply = <&vcc1v8_pmu>;
518 vdd_center: DCDC_REG1 {
521 regulator-min-microvolt = <750000>;
522 regulator-max-microvolt = <1350000>;
523 regulator-ramp-delay = <6001>;
524 regulator-name = "vdd_center";
525 regulator-state-mem {
526 regulator-off-in-suspend;
530 vdd_cpu_l: DCDC_REG2 {
533 regulator-min-microvolt = <750000>;
534 regulator-max-microvolt = <1350000>;
535 regulator-ramp-delay = <6001>;
536 regulator-name = "vdd_cpu_l";
537 regulator-state-mem {
538 regulator-off-in-suspend;
545 regulator-name = "vcc_ddr";
546 regulator-state-mem {
547 regulator-on-in-suspend;
554 regulator-min-microvolt = <1800000>;
555 regulator-max-microvolt = <1800000>;
556 regulator-name = "vcc_1v8";
557 regulator-state-mem {
558 regulator-on-in-suspend;
559 regulator-suspend-microvolt = <1800000>;
563 vcc1v8_dvp: LDO_REG1 {
566 regulator-min-microvolt = <1800000>;
567 regulator-max-microvolt = <1800000>;
568 regulator-name = "vcc1v8_dvp";
569 regulator-state-mem {
570 regulator-off-in-suspend;
574 vcc2v8_dvp: LDO_REG2 {
575 //regulator-always-on;
577 regulator-min-microvolt = <2800000>;
578 regulator-max-microvolt = <2800000>;
579 regulator-name = "vcc2v8_dvp";
580 regulator-state-mem {
581 regulator-off-in-suspend;
585 vcc1v8_pmu: LDO_REG3 {
588 regulator-min-microvolt = <1800000>;
589 regulator-max-microvolt = <1800000>;
590 regulator-name = "vcc1v8_pmu";
591 regulator-state-mem {
592 regulator-on-in-suspend;
593 regulator-suspend-microvolt = <1800000>;
600 regulator-min-microvolt = <1800000>;
601 regulator-max-microvolt = <3300000>;
602 regulator-name = "vcc_sd";
603 regulator-state-mem {
604 regulator-on-in-suspend;
605 regulator-suspend-microvolt = <3300000>;
609 vcca3v0_codec: LDO_REG5 {
612 regulator-min-microvolt = <3000000>;
613 regulator-max-microvolt = <3000000>;
614 regulator-name = "vcca3v0_codec";
615 regulator-state-mem {
616 regulator-off-in-suspend;
623 regulator-min-microvolt = <1500000>;
624 regulator-max-microvolt = <1500000>;
625 regulator-name = "vcc_1v5";
626 regulator-state-mem {
627 regulator-on-in-suspend;
628 regulator-suspend-microvolt = <1500000>;
632 vcca1v8_codec: LDO_REG7 {
635 regulator-min-microvolt = <1800000>;
636 regulator-max-microvolt = <1800000>;
637 regulator-name = "vcca1v8_codec";
638 regulator-state-mem {
639 regulator-off-in-suspend;
646 regulator-min-microvolt = <3000000>;
647 regulator-max-microvolt = <3000000>;
648 regulator-name = "vcc_3v0";
649 regulator-state-mem {
650 regulator-on-in-suspend;
651 regulator-suspend-microvolt = <3000000>;
655 vcc3v3_s3: SWITCH_REG1 {
658 regulator-name = "vcc3v3_s3";
659 regulator-state-mem {
660 regulator-off-in-suspend;
664 vcc3v3_s0: SWITCH_REG2 {
667 regulator-name = "vcc3v3_s0";
668 regulator-state-mem {
669 regulator-off-in-suspend;
678 i2c-scl-rising-time-ns = <300>;
679 i2c-scl-falling-time-ns = <15>;
682 compatible = "everest,es8323";
684 ear-con-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
685 hp-det-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
687 #sound-dai-cells = <0>;
688 system-clock-frequency = <11289600>;
689 clocks = <&cru SCLK_I2S_8CH_OUT>;
690 clock-names = "mclk";
691 pinctrl-names = "default";
692 pinctrl-0 = <&es8323_earcon &es8323_hpdet>;
696 #sound-dai-cells = <0>;
697 compatible = "realtek,rt5640";
699 clocks = <&cru SCLK_I2S_8CH_OUT>;
700 clock-names = "mclk";
701 realtek,in1-differential;
702 pinctrl-names = "default";
703 pinctrl-0 = <&rt5640_hpcon>;
704 hp-con-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
705 //hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
706 io-channels = <&saradc 4>;
707 hp-det-adc-value = <500>;
713 i2c-scl-rising-time-ns = <450>;
714 i2c-scl-falling-time-ns = <15>;
719 i2c-scl-rising-time-ns = <475>;
720 i2c-scl-falling-time-ns = <26>;
723 compatible = "fairchild,fusb302";
725 pinctrl-names = "default";
726 pinctrl-0 = <&fusb0_int>;
727 int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
728 vbus-5v-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
732 gsl3680: gsl3680@41 {
734 compatible = "gslX680-pad";
736 screen_max_x = <1536>;
737 screen_max_y = <2048>;
738 touch-gpio = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
739 reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
744 compatible = "invensense,mpu6050";
746 mpu-int_config = <0x10>;
747 mpu-level_shifter = <0>;
748 mpu-orientation = <0 1 0 1 0 0 0 0 1>;
752 irq-gpio = <&gpio1 4 IRQ_TYPE_LEVEL_LOW>;
759 rockchip,i2s-broken-burst-len;
760 rockchip,playback-channels = <8>;
761 rockchip,capture-channels = <8>;
762 #sound-dai-cells = <0>;
767 rockchip,i2s-broken-burst-len;
768 rockchip,playback-channels = <2>;
769 rockchip,capture-channels = <2>;
770 #sound-dai-cells = <0>;
775 #sound-dai-cells = <0>;
782 bt656-supply = <&vcc_3v0>; /* bt656_gpio2ab_ms */
783 audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */
784 sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
785 gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
793 ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
795 pinctrl-names = "default";
796 pinctrl-0 = <&pcie_clkreqn_cpm>;
802 pmu1830-supply = <&vcc_3v0>;
808 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
813 lcd_panel_reset: lcd-panel-reset {
814 rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_up>;
818 rockchip,pins = <1 1 RK_FUNC_GPIO &pcfg_pull_up>;
825 <1 17 RK_FUNC_GPIO &pcfg_pull_none>;
827 pcie_3g_drv: pcie-3g-drv {
829 <0 2 RK_FUNC_GPIO &pcfg_pull_up>;
835 vsel1_gpio: vsel1-gpio {
837 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
840 vsel2_gpio: vsel2-gpio {
842 <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
847 wifi_enable_h: wifi-enable-h {
849 <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
854 uart0_gpios: uart0-gpios {
856 <2 19 RK_FUNC_GPIO &pcfg_pull_none>,
857 <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
862 led_power: led-power {
863 rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>;
867 rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_none>;
872 rt5640_hpcon: rt5640-hpcon {
873 rockchip,pins = <4 21 RK_FUNC_GPIO &pcfg_pull_none>;
878 es8323_hpdet: es8323-hpdet {
879 rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_up>;
881 es8323_earcon: es8323-earcon {
882 rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
887 pmic_int_l: pmic-int-l {
889 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
892 pmic_dvs2: pmic-dvs2 {
894 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
900 host_vbus_drv: host-vbus-drv {
902 <1 0 RK_FUNC_GPIO &pcfg_pull_none>;
908 fusb0_int: fusb0-int {
909 rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
927 rockchip,power-ctrl =
928 <&gpio1 18 GPIO_ACTIVE_LOW>,
929 <&gpio1 14 GPIO_ACTIVE_HIGH>;
938 logo,mode = "center";
953 vref-supply = <&vccadc_ref>;
958 keep-power-in-suspend;
960 mmc-hs400-enhanced-strobe;
967 max-frequency = <150000000>;
974 vqmmc-supply = <&vcc_sd>;
975 pinctrl-names = "default";
976 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
981 max-frequency = <50000000>;
986 keep-power-in-suspend;
987 mmc-pwrseq = <&sdio_pwrseq>;
990 pinctrl-names = "default";
991 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
1006 /* tshut mode 0:CRU 1:GPIO */
1007 rockchip,hw-tshut-mode = <1>;
1008 /* tshut polarity 0:LOW 1:HIGH */
1009 rockchip,hw-tshut-polarity = <1>;
1017 u2phy0_otg: otg-port {
1021 u2phy0_host: host-port {
1022 phy-supply = <&vcc5v0_host>;
1030 u2phy1_otg: otg-port {
1034 u2phy1_host: host-port {
1035 phy-supply = <&vcc5v0_host>;
1042 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 0>;
1043 compatible = "rockchip,remotectl-pwm";
1044 remote_pwm_id = <3>;
1045 handle_cpu_id = <0>;
1048 rockchip,usercode = <0xff00>;
1049 rockchip,key_table =
1055 <0xf4 KEY_VOLUMEUP>,
1056 <0xa7 KEY_VOLUMEDOWN>,
1066 pinctrl-names = "default";
1067 pinctrl-0 = <&uart0_xfer &uart0_cts>;
1127 /* 0 means ion, 1 means drm */