2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "dt-bindings/pwm/pwm.h"
44 #include "rk3399.dtsi"
47 compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
49 backlight: backlight {
51 compatible = "pwm-backlight";
52 pwms = <&pwm0 0 25000 0>;
56 16 17 18 19 20 21 22 23
57 24 25 26 27 28 29 30 31
58 32 33 34 35 36 37 38 39
59 40 41 42 43 44 45 46 47
60 48 49 50 51 52 53 54 55
61 56 57 58 59 60 61 62 63
62 64 65 66 67 68 69 70 71
63 72 73 74 75 76 77 78 79
64 80 81 82 83 84 85 86 87
65 88 89 90 91 92 93 94 95
66 96 97 98 99 100 101 102 103
67 104 105 106 107 108 109 110 111
68 112 113 114 115 116 117 118 119
69 120 121 122 123 124 125 126 127
70 128 129 130 131 132 133 134 135
71 136 137 138 139 140 141 142 143
72 144 145 146 147 148 149 150 151
73 152 153 154 155 156 157 158 159
74 160 161 162 163 164 165 166 167
75 168 169 170 171 172 173 174 175
76 176 177 178 179 180 181 182 183
77 184 185 186 187 188 189 190 191
78 192 193 194 195 196 197 198 199
79 200 201 202 203 204 205 206 207
80 208 209 210 211 212 213 214 215
81 216 217 218 219 220 221 222 223
82 224 225 226 227 228 229 230 231
83 232 233 234 235 236 237 238 239
84 240 241 242 243 244 245 246 247
85 248 249 250 251 252 253 254 255>;
86 default-brightness-level = <200>;
89 clkin_gmac: external-gmac-clock {
90 compatible = "fixed-clock";
91 clock-frequency = <125000000>;
92 clock-output-names = "clkin_gmac";
96 dw_hdmi_audio: dw-hdmi-audio {
98 compatible = "rockchip,dw-hdmi-audio";
99 #sound-dai-cells = <0>;
102 hdmi_sound: hdmi-sound {
104 compatible = "simple-audio-card";
105 simple-audio-card,format = "i2s";
106 simple-audio-card,mclk-fs = <256>;
107 simple-audio-card,name = "rockchip,hdmi";
109 simple-audio-card,cpu {
112 simple-audio-card,codec {
113 sound-dai = <&dw_hdmi_audio>;
118 compatible = "rockchip,rk3399-io-voltage-domain";
119 rockchip,grf = <&grf>;
121 bt656-supply = <&vcc_3v0>; /* bt656_gpio2ab_ms */
122 audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */
123 sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
124 gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
128 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
129 rockchip,grf = <&pmugrf>;
130 pmu1830-supply = <&vcc_3v0>;
133 sdio_pwrseq: sdio-pwrseq {
134 compatible = "mmc-pwrseq-simple";
136 clock-names = "ext_clock";
137 pinctrl-names = "default";
138 pinctrl-0 = <&wifi_enable_h>;
141 * On the module itself this is one of these (depending
142 * on the actual card populated):
143 * - SDIO_RESET_L_WL_REG_ON
144 * - PDN (power down when low)
146 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
149 vcc3v3_sys: vcc3v3-sys {
150 compatible = "regulator-fixed";
151 regulator-name = "vcc3v3_sys";
154 regulator-min-microvolt = <3300000>;
155 regulator-max-microvolt = <3300000>;
158 vcc5v0_host: vcc5v0-host-regulator {
159 compatible = "regulator-fixed";
161 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&host_vbus_drv>;
164 regulator-name = "vcc5v0_host";
167 vcc5v0_sys: vcc5v0-sys {
168 compatible = "regulator-fixed";
169 regulator-name = "vcc5v0_sys";
172 regulator-min-microvolt = <5000000>;
173 regulator-max-microvolt = <5000000>;
176 vcc_phy: vcc-phy-regulator {
177 compatible = "regulator-fixed";
178 regulator-name = "vcc_phy";
184 compatible = "pwm-regulator";
185 pwms = <&pwm2 0 25000 0>;
186 regulator-name = "vdd_log";
187 regulator-min-microvolt = <800000>;
188 regulator-max-microvolt = <1400000>;
192 /* for rockchip boot on */
193 rockchip,pwm_id= <2>;
194 rockchip,pwm_voltage = <1000000>;
199 cpu-supply = <&vdd_cpu_l>;
203 cpu-supply = <&vdd_cpu_l>;
207 cpu-supply = <&vdd_cpu_l>;
211 cpu-supply = <&vdd_cpu_l>;
215 cpu-supply = <&vdd_cpu_b>;
219 cpu-supply = <&vdd_cpu_b>;
223 freq-sel = <200000000>;
230 phy-supply = <&vcc_phy>;
232 clock_in_out = "input";
233 snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
234 snps,reset-active-low;
235 snps,reset-delays-us = <0 10000 50000>;
236 assigned-clocks = <&cru SCLK_RMII_SRC>;
237 assigned-clock-parents = <&clkin_gmac>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&rgmii_pins>;
247 mali-supply = <&vdd_gpu>;
252 i2c-scl-rising-time-ns = <168>;
253 i2c-scl-falling-time-ns = <4>;
254 clock-frequency = <400000>;
256 vdd_cpu_b: syr827@40 {
257 compatible = "silergy,syr827";
259 vin-supply = <&vcc5v0_sys>;
260 regulator-compatible = "fan53555-reg";
261 regulator-name = "vdd_cpu_b";
262 regulator-min-microvolt = <712500>;
263 regulator-max-microvolt = <1500000>;
264 regulator-ramp-delay = <1000>;
265 fcs,suspend-voltage-selector = <1>;
268 regulator-initial-state = <3>;
269 regulator-state-mem {
270 regulator-off-in-suspend;
275 compatible = "silergy,syr828";
277 vin-supply = <&vcc5v0_sys>;
278 regulator-compatible = "fan53555-reg";
279 regulator-name = "vdd_gpu";
280 regulator-min-microvolt = <712500>;
281 regulator-max-microvolt = <1500000>;
282 regulator-ramp-delay = <1000>;
283 fcs,suspend-voltage-selector = <1>;
286 regulator-initial-state = <3>;
287 regulator-state-mem {
288 regulator-off-in-suspend;
293 compatible = "rockchip,rk808";
295 interrupt-parent = <&gpio1>;
296 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
299 rockchip,system-power-controller;
302 clock-output-names = "xin32k", "rk808-clkout2";
304 vcc1-supply = <&vcc3v3_sys>;
305 vcc2-supply = <&vcc3v3_sys>;
306 vcc3-supply = <&vcc3v3_sys>;
307 vcc4-supply = <&vcc3v3_sys>;
308 vcc6-supply = <&vcc3v3_sys>;
309 vcc7-supply = <&vcc3v3_sys>;
310 vcc8-supply = <&vcc3v3_sys>;
311 vcc9-supply = <&vcc3v3_sys>;
312 vcc10-supply = <&vcc3v3_sys>;
313 vcc11-supply = <&vcc3v3_sys>;
314 vcc12-supply = <&vcc3v3_sys>;
315 vddio-supply = <&vcc1v8_pmu>;
318 vdd_center: DCDC_REG1 {
321 regulator-min-microvolt = <750000>;
322 regulator-max-microvolt = <1350000>;
323 regulator-ramp-delay = <6001>;
324 regulator-name = "vdd_center";
325 regulator-state-mem {
326 regulator-off-in-suspend;
330 vdd_cpu_l: DCDC_REG2 {
333 regulator-min-microvolt = <750000>;
334 regulator-max-microvolt = <1350000>;
335 regulator-ramp-delay = <6001>;
336 regulator-name = "vdd_cpu_l";
337 regulator-state-mem {
338 regulator-off-in-suspend;
345 regulator-name = "vcc_ddr";
346 regulator-state-mem {
347 regulator-on-in-suspend;
354 regulator-min-microvolt = <1800000>;
355 regulator-max-microvolt = <1800000>;
356 regulator-name = "vcc_1v8";
357 regulator-state-mem {
358 regulator-on-in-suspend;
359 regulator-suspend-microvolt = <1800000>;
363 vcc1v8_dvp: LDO_REG1 {
366 regulator-min-microvolt = <1800000>;
367 regulator-max-microvolt = <1800000>;
368 regulator-name = "vcc1v8_dvp";
369 regulator-state-mem {
370 regulator-off-in-suspend;
374 vcc3v0_tp: LDO_REG2 {
377 regulator-min-microvolt = <3000000>;
378 regulator-max-microvolt = <3000000>;
379 regulator-name = "vcc3v0_tp";
380 regulator-state-mem {
381 regulator-off-in-suspend;
385 vcc1v8_pmu: LDO_REG3 {
388 regulator-min-microvolt = <1800000>;
389 regulator-max-microvolt = <1800000>;
390 regulator-name = "vcc1v8_pmu";
391 regulator-state-mem {
392 regulator-on-in-suspend;
393 regulator-suspend-microvolt = <1800000>;
400 regulator-min-microvolt = <1800000>;
401 regulator-max-microvolt = <3300000>;
402 regulator-name = "vcc_sd";
403 regulator-state-mem {
404 regulator-on-in-suspend;
405 regulator-suspend-microvolt = <3300000>;
409 vcca3v0_codec: LDO_REG5 {
412 regulator-min-microvolt = <3000000>;
413 regulator-max-microvolt = <3000000>;
414 regulator-name = "vcca3v0_codec";
415 regulator-state-mem {
416 regulator-off-in-suspend;
423 regulator-min-microvolt = <1500000>;
424 regulator-max-microvolt = <1500000>;
425 regulator-name = "vcc_1v5";
426 regulator-state-mem {
427 regulator-on-in-suspend;
428 regulator-suspend-microvolt = <1500000>;
432 vcca1v8_codec: LDO_REG7 {
435 regulator-min-microvolt = <1800000>;
436 regulator-max-microvolt = <1800000>;
437 regulator-name = "vcca1v8_codec";
438 regulator-state-mem {
439 regulator-off-in-suspend;
446 regulator-min-microvolt = <3000000>;
447 regulator-max-microvolt = <3000000>;
448 regulator-name = "vcc_3v0";
449 regulator-state-mem {
450 regulator-on-in-suspend;
451 regulator-suspend-microvolt = <3000000>;
455 vcc3v3_s3: SWITCH_REG1 {
458 regulator-name = "vcc3v3_s3";
459 regulator-state-mem {
460 regulator-off-in-suspend;
464 vcc3v3_s0: SWITCH_REG2 {
467 regulator-name = "vcc3v3_s0";
468 regulator-state-mem {
469 regulator-off-in-suspend;
478 i2c-scl-rising-time-ns = <475>;
479 i2c-scl-falling-time-ns = <26>;
482 compatible = "fairchild,fusb302";
484 pinctrl-names = "default";
485 pinctrl-0 = <&fusb0_int>;
486 int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
493 rockchip,i2s-broken-burst-len;
494 rockchip,playback-channels = <8>;
495 rockchip,capture-channels = <8>;
496 #sound-dai-cells = <0>;
500 #sound-dai-cells = <0>;
505 assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
506 assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
507 assigned-clock-rates = <100000000>;
508 ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&pcie_clkreqn>;
528 keep-power-in-suspend;
529 mmc-hs400-enhanced-strobe;
534 clock-frequency = <50000000>;
535 clock-freq-min-max = <200000 50000000>;
541 keep-power-in-suspend;
542 mmc-pwrseq = <&sdio_pwrseq>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
552 clock-frequency = <150000000>;
553 clock-freq-min-max = <100000 150000000>;
561 vqmmc-supply = <&vcc_sd>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
581 /* tshut mode 0:CRU 1:GPIO */
582 rockchip,hw-tshut-mode = <1>;
583 /* tshut polarity 0:LOW 1:HIGH */
584 rockchip,hw-tshut-polarity = <1>;
592 u2phy0_otg: otg-port {
596 u2phy0_host: host-port {
597 phy-supply = <&vcc5v0_host>;
605 u2phy1_otg: otg-port {
609 u2phy1_host: host-port {
610 phy-supply = <&vcc5v0_host>;
655 opp-hz = /bits/ 64 <408000000>;
656 opp-microvolt = <800000>;
657 clock-latency-ns = <40000>;
660 opp-hz = /bits/ 64 <600000000>;
661 opp-microvolt = <800000>;
664 opp-hz = /bits/ 64 <816000000>;
665 opp-microvolt = <800000>;
668 opp-hz = /bits/ 64 <1008000000>;
669 opp-microvolt = <875000>;
672 opp-hz = /bits/ 64 <1200000000>;
673 opp-microvolt = <925000>;
676 opp-hz = /bits/ 64 <1416000000>;
677 opp-microvolt = <1050000>;
683 opp-hz = /bits/ 64 <408000000>;
684 opp-microvolt = <800000>;
685 clock-latency-ns = <40000>;
688 opp-hz = /bits/ 64 <600000000>;
689 opp-microvolt = <800000>;
692 opp-hz = /bits/ 64 <816000000>;
693 opp-microvolt = <825000>;
696 opp-hz = /bits/ 64 <1008000000>;
697 opp-microvolt = <875000>;
700 opp-hz = /bits/ 64 <1200000000>;
701 opp-microvolt = <950000>;
704 opp-hz = /bits/ 64 <1416000000>;
705 opp-microvolt = <1025000>;
708 opp-hz = /bits/ 64 <1608000000>;
709 opp-microvolt = <1100000>;
712 opp-hz = /bits/ 64 <1800000000>;
713 opp-microvolt = <1175000>;
716 opp-hz = /bits/ 64 <1992000000>;
717 opp-microvolt = <1250000>;
726 518 335 /* 1008MHz */
727 617 428 /* 1200MHz */
728 728 573 /* 1416MHz */
729 827 724 /* 1608MHz */
730 925 900 /* 1800MHz */
731 1024 1108 /* 1992MHz */
762 518 335 /* 1008MHz */
763 617 428 /* 1200MHz */
764 728 573 /* 1416MHz */
765 827 724 /* 1608MHz */
766 925 900 /* 1800MHz */
767 1024 1108 /* 1992MHz */
795 opp-hz = /bits/ 64 <200000000>;
796 opp-microvolt = <800000>;
799 opp-hz = /bits/ 64 <300000000>;
800 opp-microvolt = <800000>;
803 opp-hz = /bits/ 64 <400000000>;
804 opp-microvolt = <800000>;
807 opp-hz = /bits/ 64 <500000000>;
808 opp-microvolt = <900000>;
811 opp-hz = /bits/ 64 <600000000>;
812 opp-microvolt = <900000>;
815 opp-hz = /bits/ 64 <800000000>;
816 opp-microvolt = <1000000>;
822 pmic_int_l: pmic-int-l {
824 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
827 pmic_dvs2: pmic-dvs2 {
829 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
834 host_vbus_drv: host-vbus-drv {
836 <4 25 RK_FUNC_GPIO &pcfg_pull_none>;
841 fusb0_int: fusb0-int {
842 rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;