arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/suspend/rockchip-rk3399.h>
  51 #include <dt-bindings/thermal/thermal.h>
  52
  53 #include "rk3399-dram-default-timing.dtsi"
  54
  55 / {
  56         compatible = "rockchip,rk3399";
  57
  58         interrupt-parent = <&gic>;
  59         #address-cells = <2>;
  60         #size-cells = <2>;
  61
  62         aliases {
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67                 i2c4 = &i2c4;
  68                 i2c5 = &i2c5;
  69                 i2c6 = &i2c6;
  70                 i2c7 = &i2c7;
  71                 i2c8 = &i2c8;
  72                 serial0 = &uart0;
  73                 serial1 = &uart1;
  74                 serial2 = &uart2;
  75                 serial3 = &uart3;
  76                 serial4 = &uart4;
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         dynamic-power-coefficient = <100>;
 116                         clocks = <&cru ARMCLKL>;
 117                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 118                 };
 119
 120                 cpu_l1: cpu@1 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53", "arm,armv8";
 123                         reg = <0x0 0x1>;
 124                         enable-method = "psci";
 125                         clocks = <&cru ARMCLKL>;
 126                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 127                 };
 128
 129                 cpu_l2: cpu@2 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a53", "arm,armv8";
 132                         reg = <0x0 0x2>;
 133                         enable-method = "psci";
 134                         clocks = <&cru ARMCLKL>;
 135                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 136                 };
 137
 138                 cpu_l3: cpu@3 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a53", "arm,armv8";
 141                         reg = <0x0 0x3>;
 142                         enable-method = "psci";
 143                         clocks = <&cru ARMCLKL>;
 144                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 145                 };
 146
 147                 cpu_b0: cpu@100 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a72", "arm,armv8";
 150                         reg = <0x0 0x100>;
 151                         enable-method = "psci";
 152                         #cooling-cells = <2>; /* min followed by max */
 153                         dynamic-power-coefficient = <436>;
 154                         clocks = <&cru ARMCLKB>;
 155                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 156                 };
 157
 158                 cpu_b1: cpu@101 {
 159                         device_type = "cpu";
 160                         compatible = "arm,cortex-a72", "arm,armv8";
 161                         reg = <0x0 0x101>;
 162                         enable-method = "psci";
 163                         clocks = <&cru ARMCLKB>;
 164                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 165                 };
 166
 167                 idle-states {
 168                         entry-method = "psci";
 169
 170                         CPU_SLEEP: cpu-sleep {
 171                                 compatible = "arm,idle-state";
 172                                 local-timer-stop;
 173                                 arm,psci-suspend-param = <0x0010000>;
 174                                 entry-latency-us = <120>;
 175                                 exit-latency-us = <250>;
 176                                 min-residency-us = <900>;
 177                         };
 178
 179                         CLUSTER_SLEEP: cluster-sleep {
 180                                 compatible = "arm,idle-state";
 181                                 local-timer-stop;
 182                                 arm,psci-suspend-param = <0x1010000>;
 183                                 entry-latency-us = <400>;
 184                                 exit-latency-us = <500>;
 185                                 min-residency-us = <2000>;
 186                         };
 187                 };
 188         };
 189
 190         pmu_a53 {
 191                 compatible = "arm,cortex-a53-pmu";
 192                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 193         };
 194
 195         pmu_a72 {
 196                 compatible = "arm,cortex-a72-pmu";
 197                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 198         };
 199
 200         psci {
 201                 compatible = "arm,psci-1.0";
 202                 method = "smc";
 203         };
 204
 205         timer {
 206                 compatible = "arm,armv8-timer";
 207                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 208                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 209                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 210                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 211         };
 212
 213         xin24m: xin24m {
 214                 compatible = "fixed-clock";
 215                 clock-frequency = <24000000>;
 216                 clock-output-names = "xin24m";
 217                 #clock-cells = <0>;
 218         };
 219
 220         dummy_cpll: dummy_cpll {
 221                 compatible = "fixed-clock";
 222                 clock-frequency = <0>;
 223                 clock-output-names = "dummy_cpll";
 224                 #clock-cells = <0>;
 225         };
 226
 227         dummy_vpll: dummy_vpll {
 228                 compatible = "fixed-clock";
 229                 clock-frequency = <0>;
 230                 clock-output-names = "dummy_vpll";
 231                 #clock-cells = <0>;
 232         };
 233
 234         amba {
 235                 compatible = "arm,amba-bus";
 236                 #address-cells = <2>;
 237                 #size-cells = <2>;
 238                 ranges;
 239
 240                 dmac_bus: dma-controller@ff6d0000 {
 241                         compatible = "arm,pl330", "arm,primecell";
 242                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 243                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 244                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 245                         #dma-cells = <1>;
 246                         clocks = <&cru ACLK_DMAC0_PERILP>;
 247                         clock-names = "apb_pclk";
 248                         peripherals-req-type-burst;
 249                 };
 250
 251                 dmac_peri: dma-controller@ff6e0000 {
 252                         compatible = "arm,pl330", "arm,primecell";
 253                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 254                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 255                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 256                         #dma-cells = <1>;
 257                         clocks = <&cru ACLK_DMAC1_PERILP>;
 258                         clock-names = "apb_pclk";
 259                         peripherals-req-type-burst;
 260                 };
 261         };
 262
 263         gmac: ethernet@fe300000 {
 264                 compatible = "rockchip,rk3399-gmac";
 265                 reg = <0x0 0xfe300000 0x0 0x10000>;
 266                 rockchip,grf = <&grf>;
 267                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 268                 interrupt-names = "macirq";
 269                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 270                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 271                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 272                          <&cru PCLK_GMAC>;
 273                 clock-names = "stmmaceth", "mac_clk_rx",
 274                               "mac_clk_tx", "clk_mac_ref",
 275                               "clk_mac_refout", "aclk_mac",
 276                               "pclk_mac";
 277                 resets = <&cru SRST_A_GMAC>;
 278                 reset-names = "stmmaceth";
 279                 power-domains = <&power RK3399_PD_GMAC>;
 280                 status = "disabled";
 281         };
 282
 283         sdio0: dwmmc@fe310000 {
 284                 compatible = "rockchip,rk3399-dw-mshc",
 285                              "rockchip,rk3288-dw-mshc";
 286                 reg = <0x0 0xfe310000 0x0 0x4000>;
 287                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 288                 clock-freq-min-max = <400000 150000000>;
 289                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 290                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 291                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 292                 fifo-depth = <0x100>;
 293                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 294                 status = "disabled";
 295         };
 296
 297         sdmmc: dwmmc@fe320000 {
 298                 compatible = "rockchip,rk3399-dw-mshc",
 299                              "rockchip,rk3288-dw-mshc";
 300                 reg = <0x0 0xfe320000 0x0 0x4000>;
 301                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 302                 clock-freq-min-max = <400000 150000000>;
 303                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 304                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 305                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 306                 fifo-depth = <0x100>;
 307                 power-domains = <&power RK3399_PD_SD>;
 308                 status = "disabled";
 309         };
 310
 311         sdhci: sdhci@fe330000 {
 312                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 313                 reg = <0x0 0xfe330000 0x0 0x10000>;
 314                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 315                 arasan,soc-ctl-syscon = <&grf>;
 316                 assigned-clocks = <&cru SCLK_EMMC>;
 317                 assigned-clock-rates = <200000000>;
 318                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 319                 clock-names = "clk_xin", "clk_ahb";
 320                 clock-output-names = "emmc_cardclock";
 321                 #clock-cells = <0>;
 322                 phys = <&emmc_phy>;
 323                 phy-names = "phy_arasan";
 324                 power-domains = <&power RK3399_PD_EMMC>;
 325                 status = "disabled";
 326         };
 327
 328         usb_host0_ehci: usb@fe380000 {
 329                 compatible = "generic-ehci";
 330                 reg = <0x0 0xfe380000 0x0 0x20000>;
 331                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 332                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 333                          <&cru SCLK_USBPHY0_480M_SRC>;
 334                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 335                 phys = <&u2phy0_host>;
 336                 phy-names = "usb";
 337                 power-domains = <&power RK3399_PD_PERIHP>;
 338                 status = "disabled";
 339         };
 340
 341         usb_host0_ohci: usb@fe3a0000 {
 342                 compatible = "generic-ohci";
 343                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 344                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 345                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 346                          <&cru SCLK_USBPHY0_480M_SRC>;
 347                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 348                 phys = <&u2phy0_host>;
 349                 phy-names = "usb";
 350                 power-domains = <&power RK3399_PD_PERIHP>;
 351                 status = "disabled";
 352         };
 353
 354         usb_host1_ehci: usb@fe3c0000 {
 355                 compatible = "generic-ehci";
 356                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 357                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 358                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 359                          <&cru SCLK_USBPHY1_480M_SRC>;
 360                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 361                 phys = <&u2phy1_host>;
 362                 phy-names = "usb";
 363                 power-domains = <&power RK3399_PD_PERIHP>;
 364                 status = "disabled";
 365         };
 366
 367         usb_host1_ohci: usb@fe3e0000 {
 368                 compatible = "generic-ohci";
 369                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 370                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 371                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 372                          <&cru SCLK_USBPHY1_480M_SRC>;
 373                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 374                 phys = <&u2phy1_host>;
 375                 phy-names = "usb";
 376                 power-domains = <&power RK3399_PD_PERIHP>;
 377                 status = "disabled";
 378         };
 379
 380         usbdrd3_0: usb@fe800000 {
 381                 compatible = "rockchip,rk3399-dwc3";
 382                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 383                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 384                 clock-names = "ref_clk", "suspend_clk",
 385                               "bus_clk", "grf_clk";
 386                 power-domains = <&power RK3399_PD_USB3>;
 387                 resets = <&cru SRST_A_USB3_OTG0>;
 388                 reset-names = "usb3-otg";
 389                 #address-cells = <2>;
 390                 #size-cells = <2>;
 391                 ranges;
 392                 status = "disabled";
 393                 usbdrd_dwc3_0: dwc3@fe800000 {
 394                         compatible = "snps,dwc3";
 395                         reg = <0x0 0xfe800000 0x0 0x100000>;
 396                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 397                         dr_mode = "otg";
 398                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 399                         phy-names = "usb2-phy", "usb3-phy";
 400                         phy_type = "utmi_wide";
 401                         snps,dis_enblslpm_quirk;
 402                         snps,dis-u2-freeclk-exists-quirk;
 403                         snps,dis_u2_susphy_quirk;
 404                         snps,dis-del-phy-power-chg-quirk;
 405                         snps,tx-ipgap-linecheck-dis-quirk;
 406                         snps,xhci-slow-suspend-quirk;
 407                         snps,usb3-warm-reset-on-resume-quirk;
 408                         status = "disabled";
 409                 };
 410         };
 411
 412         usbdrd3_1: usb@fe900000 {
 413                 compatible = "rockchip,rk3399-dwc3";
 414                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 415                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 416                 clock-names = "ref_clk", "suspend_clk",
 417                               "bus_clk", "grf_clk";
 418                 power-domains = <&power RK3399_PD_USB3>;
 419                 resets = <&cru SRST_A_USB3_OTG1>;
 420                 reset-names = "usb3-otg";
 421                 #address-cells = <2>;
 422                 #size-cells = <2>;
 423                 ranges;
 424                 status = "disabled";
 425                 usbdrd_dwc3_1: dwc3@fe900000 {
 426                         compatible = "snps,dwc3";
 427                         reg = <0x0 0xfe900000 0x0 0x100000>;
 428                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 429                         dr_mode = "host";
 430                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 431                         phy-names = "usb2-phy", "usb3-phy";
 432                         phy_type = "utmi_wide";
 433                         snps,dis_enblslpm_quirk;
 434                         snps,dis-u2-freeclk-exists-quirk;
 435                         snps,dis_u2_susphy_quirk;
 436                         snps,dis-del-phy-power-chg-quirk;
 437                         snps,tx-ipgap-linecheck-dis-quirk;
 438                         snps,xhci-slow-suspend-quirk;
 439                         snps,usb3-warm-reset-on-resume-quirk;
 440                         status = "disabled";
 441                 };
 442         };
 443
 444         cdn_dp: dp@fec00000 {
 445                 compatible = "rockchip,rk3399-cdn-dp";
 446                 reg = <0x0 0xfec00000 0x0 0x100000>;
 447                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 448                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 449                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 450                 clock-names = "core-clk", "pclk", "spdif", "grf";
 451                 assigned-clocks = <&cru SCLK_DP_CORE>;
 452                 assigned-clock-rates = <100000000>;
 453                 power-domains = <&power RK3399_PD_HDCP>;
 454                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 455                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 456                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 457                 reset-names = "spdif", "dptx", "apb", "core";
 458                 rockchip,grf = <&grf>;
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 #sound-dai-cells = <1>;
 462                 status = "disabled";
 463
 464                 ports {
 465                         #address-cells = <1>;
 466                         #size-cells = <0>;
 467
 468                         dp_in: port {
 469                                 #address-cells = <1>;
 470                                 #size-cells = <0>;
 471                                 dp_in_vopb: endpoint@0 {
 472                                         reg = <0>;
 473                                         remote-endpoint = <&vopb_out_dp>;
 474                                 };
 475
 476                                 dp_in_vopl: endpoint@1 {
 477                                         reg = <1>;
 478                                         remote-endpoint = <&vopl_out_dp>;
 479                                 };
 480                         };
 481                 };
 482         };
 483
 484         gic: interrupt-controller@fee00000 {
 485                 compatible = "arm,gic-v3";
 486                 #interrupt-cells = <4>;
 487                 #address-cells = <2>;
 488                 #size-cells = <2>;
 489                 ranges;
 490                 interrupt-controller;
 491
 492                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 493                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 494                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 495                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 496                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 497                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 498                 its: interrupt-controller@fee20000 {
 499                         compatible = "arm,gic-v3-its";
 500                         msi-controller;
 501                         reg = <0x0 0xfee20000 0x0 0x20000>;
 502                 };
 503
 504                 ppi-partitions {
 505                         ppi_cluster0: interrupt-partition-0 {
 506                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 507                         };
 508
 509                         ppi_cluster1: interrupt-partition-1 {
 510                                 affinity = <&cpu_b0 &cpu_b1>;
 511                         };
 512                 };
 513         };
 514
 515         saradc: saradc@ff100000 {
 516                 compatible = "rockchip,rk3399-saradc";
 517                 reg = <0x0 0xff100000 0x0 0x100>;
 518                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 519                 #io-channel-cells = <1>;
 520                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 521                 clock-names = "saradc", "apb_pclk";
 522                 resets = <&cru SRST_P_SARADC>;
 523                 reset-names = "saradc-apb";
 524                 status = "disabled";
 525         };
 526
 527         i2c0: i2c@ff3c0000 {
 528                 compatible = "rockchip,rk3399-i2c";
 529                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 530                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 531                 clock-names = "i2c", "pclk";
 532                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&i2c0_xfer>;
 535                 #address-cells = <1>;
 536                 #size-cells = <0>;
 537                 status = "disabled";
 538         };
 539
 540         i2c1: i2c@ff110000 {
 541                 compatible = "rockchip,rk3399-i2c";
 542                 reg = <0x0 0xff110000 0x0 0x1000>;
 543                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 544                 clock-names = "i2c", "pclk";
 545                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&i2c1_xfer>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 status = "disabled";
 551         };
 552
 553         i2c2: i2c@ff120000 {
 554                 compatible = "rockchip,rk3399-i2c";
 555                 reg = <0x0 0xff120000 0x0 0x1000>;
 556                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 557                 clock-names = "i2c", "pclk";
 558                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&i2c2_xfer>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 status = "disabled";
 564         };
 565
 566         i2c3: i2c@ff130000 {
 567                 compatible = "rockchip,rk3399-i2c";
 568                 reg = <0x0 0xff130000 0x0 0x1000>;
 569                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 570                 clock-names = "i2c", "pclk";
 571                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&i2c3_xfer>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 status = "disabled";
 577         };
 578
 579         i2c5: i2c@ff140000 {
 580                 compatible = "rockchip,rk3399-i2c";
 581                 reg = <0x0 0xff140000 0x0 0x1000>;
 582                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 583                 clock-names = "i2c", "pclk";
 584                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&i2c5_xfer>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 status = "disabled";
 590         };
 591
 592         i2c6: i2c@ff150000 {
 593                 compatible = "rockchip,rk3399-i2c";
 594                 reg = <0x0 0xff150000 0x0 0x1000>;
 595                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 596                 clock-names = "i2c", "pclk";
 597                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&i2c6_xfer>;
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602                 status = "disabled";
 603         };
 604
 605         i2c7: i2c@ff160000 {
 606                 compatible = "rockchip,rk3399-i2c";
 607                 reg = <0x0 0xff160000 0x0 0x1000>;
 608                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 609                 clock-names = "i2c", "pclk";
 610                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 611                 pinctrl-names = "default";
 612                 pinctrl-0 = <&i2c7_xfer>;
 613                 #address-cells = <1>;
 614                 #size-cells = <0>;
 615                 status = "disabled";
 616         };
 617
 618         uart0: serial@ff180000 {
 619                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 620                 reg = <0x0 0xff180000 0x0 0x100>;
 621                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 622                 clock-names = "baudclk", "apb_pclk";
 623                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 624                 reg-shift = <2>;
 625                 reg-io-width = <4>;
 626                 pinctrl-names = "default";
 627                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 628                 status = "disabled";
 629         };
 630
 631         uart1: serial@ff190000 {
 632                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 633                 reg = <0x0 0xff190000 0x0 0x100>;
 634                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 635                 clock-names = "baudclk", "apb_pclk";
 636                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 637                 reg-shift = <2>;
 638                 reg-io-width = <4>;
 639                 pinctrl-names = "default";
 640                 pinctrl-0 = <&uart1_xfer>;
 641                 status = "disabled";
 642         };
 643
 644         uart2: serial@ff1a0000 {
 645                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 646                 reg = <0x0 0xff1a0000 0x0 0x100>;
 647                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 648                 clock-names = "baudclk", "apb_pclk";
 649                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 650                 reg-shift = <2>;
 651                 reg-io-width = <4>;
 652                 pinctrl-names = "default";
 653                 pinctrl-0 = <&uart2c_xfer>;
 654                 status = "disabled";
 655         };
 656
 657         uart3: serial@ff1b0000 {
 658                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 659                 reg = <0x0 0xff1b0000 0x0 0x100>;
 660                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 661                 clock-names = "baudclk", "apb_pclk";
 662                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 663                 reg-shift = <2>;
 664                 reg-io-width = <4>;
 665                 pinctrl-names = "default";
 666                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 667                 status = "disabled";
 668         };
 669
 670         spi0: spi@ff1c0000 {
 671                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 672                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 673                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 674                 clock-names = "spiclk", "apb_pclk";
 675                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 676                 pinctrl-names = "default";
 677                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 678                 #address-cells = <1>;
 679                 #size-cells = <0>;
 680                 status = "disabled";
 681         };
 682
 683         spi1: spi@ff1d0000 {
 684                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 685                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 686                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 687                 clock-names = "spiclk", "apb_pclk";
 688                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 689                 pinctrl-names = "default";
 690                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 691                 #address-cells = <1>;
 692                 #size-cells = <0>;
 693                 status = "disabled";
 694         };
 695
 696         spi2: spi@ff1e0000 {
 697                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 698                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 699                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 700                 clock-names = "spiclk", "apb_pclk";
 701                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 702                 pinctrl-names = "default";
 703                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 704                 #address-cells = <1>;
 705                 #size-cells = <0>;
 706                 status = "disabled";
 707         };
 708
 709         spi4: spi@ff1f0000 {
 710                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 711                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 712                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 713                 clock-names = "spiclk", "apb_pclk";
 714                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 715                 pinctrl-names = "default";
 716                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 717                 #address-cells = <1>;
 718                 #size-cells = <0>;
 719                 status = "disabled";
 720         };
 721
 722         spi5: spi@ff200000 {
 723                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 724                 reg = <0x0 0xff200000 0x0 0x1000>;
 725                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 726                 clock-names = "spiclk", "apb_pclk";
 727                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 728                 pinctrl-names = "default";
 729                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 730                 #address-cells = <1>;
 731                 #size-cells = <0>;
 732                 status = "disabled";
 733         };
 734
 735         thermal_zones: thermal-zones {
 736                 soc_thermal: soc-thermal {
 737                         polling-delay-passive = <20>; /* milliseconds */
 738                         polling-delay = <1000>; /* milliseconds */
 739                         sustainable-power = <1000>; /* milliwatts */
 740
 741                         thermal-sensors = <&tsadc 0>;
 742
 743                         trips {
 744                                 threshold: trip-point@0 {
 745                                         temperature = <70000>; /* millicelsius */
 746                                         hysteresis = <2000>; /* millicelsius */
 747                                         type = "passive";
 748                                 };
 749                                 target: trip-point@1 {
 750                                         temperature = <85000>; /* millicelsius */
 751                                         hysteresis = <2000>; /* millicelsius */
 752                                         type = "passive";
 753                                 };
 754                                 soc_crit: soc-crit {
 755                                         temperature = <95000>; /* millicelsius */
 756                                         hysteresis = <2000>; /* millicelsius */
 757                                         type = "critical";
 758                                 };
 759                         };
 760
 761                         cooling-maps {
 762                                 map0 {
 763                                         trip = <&target>;
 764                                         cooling-device =
 765                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 766                                         contribution = <4096>;
 767                                 };
 768                                 map1 {
 769                                         trip = <&target>;
 770                                         cooling-device =
 771                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 772                                         contribution = <1024>;
 773                                 };
 774                                 map2 {
 775                                         trip = <&target>;
 776                                         cooling-device =
 777                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 778                                         contribution = <4096>;
 779                                 };
 780                         };
 781                 };
 782
 783                 gpu_thermal: gpu-thermal {
 784                         polling-delay-passive = <100>; /* milliseconds */
 785                         polling-delay = <1000>; /* milliseconds */
 786
 787                         thermal-sensors = <&tsadc 1>;
 788                 };
 789         };
 790
 791         tsadc: tsadc@ff260000 {
 792                 compatible = "rockchip,rk3399-tsadc";
 793                 reg = <0x0 0xff260000 0x0 0x100>;
 794                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 795                 rockchip,grf = <&grf>;
 796                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 797                 clock-names = "tsadc", "apb_pclk";
 798                 assigned-clocks = <&cru SCLK_TSADC>;
 799                 assigned-clock-rates = <750000>;
 800                 resets = <&cru SRST_TSADC>;
 801                 reset-names = "tsadc-apb";
 802                 pinctrl-names = "init", "default", "sleep";
 803                 pinctrl-0 = <&otp_gpio>;
 804                 pinctrl-1 = <&otp_out>;
 805                 pinctrl-2 = <&otp_gpio>;
 806                 #thermal-sensor-cells = <1>;
 807                 rockchip,hw-tshut-temp = <95000>;
 808                 status = "disabled";
 809         };
 810
 811         qos_emmc: qos@ffa58000 {
 812                 compatible = "syscon";
 813                 reg = <0x0 0xffa58000 0x0 0x20>;
 814         };
 815
 816         qos_gmac: qos@ffa5c000 {
 817                 compatible = "syscon";
 818                 reg = <0x0 0xffa5c000 0x0 0x20>;
 819         };
 820
 821         qos_pcie: qos@ffa60080 {
 822                 compatible = "syscon";
 823                 reg = <0x0 0xffa60080 0x0 0x20>;
 824         };
 825
 826         qos_usb_host0: qos@ffa60100 {
 827                 compatible = "syscon";
 828                 reg = <0x0 0xffa60100 0x0 0x20>;
 829         };
 830
 831         qos_usb_host1: qos@ffa60180 {
 832                 compatible = "syscon";
 833                 reg = <0x0 0xffa60180 0x0 0x20>;
 834         };
 835
 836         qos_usb_otg0: qos@ffa70000 {
 837                 compatible = "syscon";
 838                 reg = <0x0 0xffa70000 0x0 0x20>;
 839         };
 840
 841         qos_usb_otg1: qos@ffa70080 {
 842                 compatible = "syscon";
 843                 reg = <0x0 0xffa70080 0x0 0x20>;
 844         };
 845
 846         qos_sd: qos@ffa74000 {
 847                 compatible = "syscon";
 848                 reg = <0x0 0xffa74000 0x0 0x20>;
 849         };
 850
 851         qos_sdioaudio: qos@ffa76000 {
 852                 compatible = "syscon";
 853                 reg = <0x0 0xffa76000 0x0 0x20>;
 854         };
 855
 856         qos_hdcp: qos@ffa90000 {
 857                 compatible = "syscon";
 858                 reg = <0x0 0xffa90000 0x0 0x20>;
 859         };
 860
 861         qos_iep: qos@ffa98000 {
 862                 compatible = "syscon";
 863                 reg = <0x0 0xffa98000 0x0 0x20>;
 864         };
 865
 866         qos_isp0_m0: qos@ffaa0000 {
 867                 compatible = "syscon";
 868                 reg = <0x0 0xffaa0000 0x0 0x20>;
 869         };
 870
 871         qos_isp0_m1: qos@ffaa0080 {
 872                 compatible = "syscon";
 873                 reg = <0x0 0xffaa0080 0x0 0x20>;
 874         };
 875
 876         qos_isp1_m0: qos@ffaa8000 {
 877                 compatible = "syscon";
 878                 reg = <0x0 0xffaa8000 0x0 0x20>;
 879         };
 880
 881         qos_isp1_m1: qos@ffaa8080 {
 882                 compatible = "syscon";
 883                 reg = <0x0 0xffaa8080 0x0 0x20>;
 884         };
 885
 886         qos_rga_r: qos@ffab0000 {
 887                 compatible = "syscon";
 888                 reg = <0x0 0xffab0000 0x0 0x20>;
 889         };
 890
 891         qos_rga_w: qos@ffab0080 {
 892                 compatible = "syscon";
 893                 reg = <0x0 0xffab0080 0x0 0x20>;
 894         };
 895
 896         qos_video_m0: qos@ffab8000 {
 897                 compatible = "syscon";
 898                 reg = <0x0 0xffab8000 0x0 0x20>;
 899         };
 900
 901         qos_video_m1_r: qos@ffac0000 {
 902                 compatible = "syscon";
 903                 reg = <0x0 0xffac0000 0x0 0x20>;
 904         };
 905
 906         qos_video_m1_w: qos@ffac0080 {
 907                 compatible = "syscon";
 908                 reg = <0x0 0xffac0080 0x0 0x20>;
 909         };
 910
 911         qos_vop_big_r: qos@ffac8000 {
 912                 compatible = "syscon";
 913                 reg = <0x0 0xffac8000 0x0 0x20>;
 914         };
 915
 916         qos_vop_big_w: qos@ffac8080 {
 917                 compatible = "syscon";
 918                 reg = <0x0 0xffac8080 0x0 0x20>;
 919         };
 920
 921         qos_vop_little: qos@ffad0000 {
 922                 compatible = "syscon";
 923                 reg = <0x0 0xffad0000 0x0 0x20>;
 924         };
 925
 926         qos_perihp: qos@ffad8080 {
 927                 compatible = "syscon";
 928                 reg = <0x0 0xffad8080 0x0 0x20>;
 929         };
 930
 931         qos_gpu: qos@ffae0000 {
 932                 compatible = "syscon";
 933                 reg = <0x0 0xffae0000 0x0 0x20>;
 934         };
 935
 936         pmu: power-management@ff310000 {
 937                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 938                 reg = <0x0 0xff310000 0x0 0x1000>;
 939
 940                 /*
 941                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 942                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 943                  * Some of the power domains are grouped together for every
 944                  * voltage domain.
 945                  * The detail contents as below.
 946                  */
 947                 power: power-controller {
 948                         compatible = "rockchip,rk3399-power-controller";
 949                         #power-domain-cells = <1>;
 950                         #address-cells = <1>;
 951                         #size-cells = <0>;
 952
 953                         /* These power domains are grouped by VD_CENTER */
 954                         pd_iep@RK3399_PD_IEP {
 955                                 reg = <RK3399_PD_IEP>;
 956                                 clocks = <&cru ACLK_IEP>,
 957                                          <&cru HCLK_IEP>;
 958                                 pm_qos = <&qos_iep>;
 959                         };
 960                         pd_rga@RK3399_PD_RGA {
 961                                 reg = <RK3399_PD_RGA>;
 962                                 clocks = <&cru ACLK_RGA>,
 963                                          <&cru HCLK_RGA>;
 964                                 pm_qos = <&qos_rga_r>,
 965                                          <&qos_rga_w>;
 966                         };
 967                         pd_vcodec@RK3399_PD_VCODEC {
 968                                 reg = <RK3399_PD_VCODEC>;
 969                                 clocks = <&cru ACLK_VCODEC>,
 970                                          <&cru HCLK_VCODEC>;
 971                                 pm_qos = <&qos_video_m0>;
 972                         };
 973                         pd_vdu@RK3399_PD_VDU {
 974                                 reg = <RK3399_PD_VDU>;
 975                                 clocks = <&cru ACLK_VDU>,
 976                                          <&cru HCLK_VDU>;
 977                                 pm_qos = <&qos_video_m1_r>,
 978                                          <&qos_video_m1_w>;
 979                         };
 980
 981                         /* These power domains are grouped by VD_GPU */
 982                         pd_gpu@RK3399_PD_GPU {
 983                                 reg = <RK3399_PD_GPU>;
 984                                 clocks = <&cru ACLK_GPU>;
 985                                 pm_qos = <&qos_gpu>;
 986                         };
 987
 988                         /* These power domains are grouped by VD_LOGIC */
 989                         pd_edp@RK3399_PD_EDP {
 990                                 reg = <RK3399_PD_EDP>;
 991                                 clocks = <&cru PCLK_EDP_CTRL>;
 992                         };
 993                         pd_emmc@RK3399_PD_EMMC {
 994                                 reg = <RK3399_PD_EMMC>;
 995                                 clocks = <&cru ACLK_EMMC>;
 996                                 pm_qos = <&qos_emmc>;
 997                         };
 998                         pd_gmac@RK3399_PD_GMAC {
 999                                 reg = <RK3399_PD_GMAC>;
1000                                 clocks = <&cru ACLK_GMAC>,
1001                                          <&cru PCLK_GMAC>;
1002                                 pm_qos = <&qos_gmac>;
1003                         };
1004                         pd_perihp@RK3399_PD_PERIHP {
1005                                 reg = <RK3399_PD_PERIHP>;
1006                                 #address-cells = <1>;
1007                                 #size-cells = <0>;
1008                                 clocks = <&cru ACLK_PERIHP>;
1009                                 pm_qos = <&qos_perihp>,
1010                                          <&qos_pcie>,
1011                                          <&qos_usb_host0>,
1012                                          <&qos_usb_host1>;
1013
1014                                 pd_sd@RK3399_PD_SD {
1015                                         reg = <RK3399_PD_SD>;
1016                                         clocks = <&cru HCLK_SDMMC>,
1017                                                  <&cru SCLK_SDMMC>;
1018                                         pm_qos = <&qos_sd>;
1019                                 };
1020                         };
1021                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1022                                 reg = <RK3399_PD_SDIOAUDIO>;
1023                                 clocks = <&cru HCLK_SDIO>;
1024                                 pm_qos = <&qos_sdioaudio>;
1025                         };
1026                         pd_usb3@RK3399_PD_USB3 {
1027                                 reg = <RK3399_PD_USB3>;
1028                                 clocks = <&cru ACLK_USB3>;
1029                                 pm_qos = <&qos_usb_otg0>,
1030                                          <&qos_usb_otg1>;
1031                         };
1032                         pd_vio@RK3399_PD_VIO {
1033                                 reg = <RK3399_PD_VIO>;
1034                                 #address-cells = <1>;
1035                                 #size-cells = <0>;
1036
1037                                 pd_hdcp@RK3399_PD_HDCP {
1038                                         reg = <RK3399_PD_HDCP>;
1039                                         clocks = <&cru ACLK_HDCP>,
1040                                                  <&cru HCLK_HDCP>,
1041                                                  <&cru PCLK_HDCP>;
1042                                         pm_qos = <&qos_hdcp>;
1043                                 };
1044                                 pd_isp0@RK3399_PD_ISP0 {
1045                                         reg = <RK3399_PD_ISP0>;
1046                                         clocks = <&cru ACLK_ISP0>,
1047                                                  <&cru HCLK_ISP0>;
1048                                         pm_qos = <&qos_isp0_m0>,
1049                                                  <&qos_isp0_m1>;
1050                                 };
1051                                 pd_isp1@RK3399_PD_ISP1 {
1052                                         reg = <RK3399_PD_ISP1>;
1053                                         clocks = <&cru ACLK_ISP1>,
1054                                                  <&cru HCLK_ISP1>;
1055                                         pm_qos = <&qos_isp1_m0>,
1056                                                  <&qos_isp1_m1>;
1057                                 };
1058                                 pd_tcpc0@RK3399_PD_TCPC0 {
1059                                         reg = <RK3399_PD_TCPD0>;
1060                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1061                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1062                                 };
1063                                 pd_tcpc1@RK3399_PD_TCPC1 {
1064                                         reg = <RK3399_PD_TCPD1>;
1065                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1066                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1067                                 };
1068                                 pd_vo@RK3399_PD_VO {
1069                                         reg = <RK3399_PD_VO>;
1070                                         #address-cells = <1>;
1071                                         #size-cells = <0>;
1072
1073                                         pd_vopb@RK3399_PD_VOPB {
1074                                                 reg = <RK3399_PD_VOPB>;
1075                                                 clocks = <&cru ACLK_VOP0>,
1076                                                          <&cru HCLK_VOP0>;
1077                                                 pm_qos = <&qos_vop_big_r>,
1078                                                          <&qos_vop_big_w>;
1079                                         };
1080                                         pd_vopl@RK3399_PD_VOPL {
1081                                                 reg = <RK3399_PD_VOPL>;
1082                                                 clocks = <&cru ACLK_VOP1>,
1083                                                          <&cru HCLK_VOP1>;
1084                                                 pm_qos = <&qos_vop_little>;
1085                                         };
1086                                 };
1087                         };
1088                 };
1089         };
1090
1091         pmugrf: syscon@ff320000 {
1092                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1093                 reg = <0x0 0xff320000 0x0 0x1000>;
1094                 #address-cells = <1>;
1095                 #size-cells = <1>;
1096
1097                 pmu_io_domains: io-domains {
1098                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1099                         status = "disabled";
1100                 };
1101
1102                 reboot-mode {
1103                         compatible = "syscon-reboot-mode";
1104                         offset = <0x300>;
1105                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
1106                         mode-charge = <BOOT_CHARGING>;
1107                         mode-fastboot = <BOOT_FASTBOOT>;
1108                         mode-loader = <BOOT_BL_DOWNLOAD>;
1109                         mode-normal = <BOOT_NORMAL>;
1110                         mode-recovery = <BOOT_RECOVERY>;
1111                         mode-ums = <BOOT_UMS>;
1112                 };
1113
1114                 pmu_pvtm: pmu-pvtm {
1115                         compatible = "rockchip,rk3399-pmu-pvtm";
1116                         clocks = <&pmucru SCLK_PVTM_PMU>;
1117                         clock-names = "pmu";
1118                         status = "disabled";
1119                 };
1120         };
1121
1122         spi3: spi@ff350000 {
1123                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1124                 reg = <0x0 0xff350000 0x0 0x1000>;
1125                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1126                 clock-names = "spiclk", "apb_pclk";
1127                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1128                 pinctrl-names = "default";
1129                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1130                 #address-cells = <1>;
1131                 #size-cells = <0>;
1132                 status = "disabled";
1133         };
1134
1135         uart4: serial@ff370000 {
1136                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1137                 reg = <0x0 0xff370000 0x0 0x100>;
1138                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1139                 clock-names = "baudclk", "apb_pclk";
1140                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1141                 reg-shift = <2>;
1142                 reg-io-width = <4>;
1143                 pinctrl-names = "default";
1144                 pinctrl-0 = <&uart4_xfer>;
1145                 status = "disabled";
1146         };
1147
1148         i2c4: i2c@ff3d0000 {
1149                 compatible = "rockchip,rk3399-i2c";
1150                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1151                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1152                 clock-names = "i2c", "pclk";
1153                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1154                 pinctrl-names = "default";
1155                 pinctrl-0 = <&i2c4_xfer>;
1156                 #address-cells = <1>;
1157                 #size-cells = <0>;
1158                 status = "disabled";
1159         };
1160
1161         i2c8: i2c@ff3e0000 {
1162                 compatible = "rockchip,rk3399-i2c";
1163                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1164                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1165                 clock-names = "i2c", "pclk";
1166                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1167                 pinctrl-names = "default";
1168                 pinctrl-0 = <&i2c8_xfer>;
1169                 #address-cells = <1>;
1170                 #size-cells = <0>;
1171                 status = "disabled";
1172         };
1173
1174         pcie_phy: phy@e220 {
1175                 compatible = "rockchip,rk3399-pcie-phy";
1176                 #phy-cells = <0>;
1177                 rockchip,grf = <&grf>;
1178                 clocks = <&cru SCLK_PCIEPHY_REF>;
1179                 clock-names = "refclk";
1180                 resets = <&cru SRST_PCIEPHY>;
1181                 reset-names = "phy";
1182                 status = "disabled";
1183         };
1184
1185         pcie0: pcie@f8000000 {
1186                 compatible = "rockchip,rk3399-pcie";
1187                 #address-cells = <3>;
1188                 #size-cells = <2>;
1189                 aspm-no-l0s;
1190                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1191                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1192                 clock-names = "aclk", "aclk-perf",
1193                               "hclk", "pm";
1194                 bus-range = <0x0 0x1>;
1195                 max-link-speed = <1>;
1196                 linux,pci-domain = <0>;
1197                 msi-map = <0x0 &its 0x0 0x1000>;
1198                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1199                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1200                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1201                 interrupt-names = "sys", "legacy", "client";
1202                 #interrupt-cells = <1>;
1203                 interrupt-map-mask = <0 0 0 7>;
1204                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1205                                 <0 0 0 2 &pcie0_intc 1>,
1206                                 <0 0 0 3 &pcie0_intc 2>,
1207                                 <0 0 0 4 &pcie0_intc 3>;
1208                 phys = <&pcie_phy>;
1209                 phy-names = "pcie-phy";
1210                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1211                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1212                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1213                       <0x0 0xfd000000 0x0 0x1000000>;
1214                 reg-names = "axi-base", "apb-base";
1215                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1216                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1217                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1218                          <&cru SRST_A_PCIE>;
1219                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1220                               "pm", "pclk", "aclk";
1221                 status = "disabled";
1222                 pcie0_intc: interrupt-controller {
1223                         interrupt-controller;
1224                         #address-cells = <0>;
1225                         #interrupt-cells = <1>;
1226                 };
1227         };
1228
1229         pwm0: pwm@ff420000 {
1230                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1231                 reg = <0x0 0xff420000 0x0 0x10>;
1232                 #pwm-cells = <3>;
1233                 pinctrl-names = "default";
1234                 pinctrl-0 = <&pwm0_pin>;
1235                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1236                 clock-names = "pwm";
1237                 status = "disabled";
1238         };
1239
1240         pwm1: pwm@ff420010 {
1241                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1242                 reg = <0x0 0xff420010 0x0 0x10>;
1243                 #pwm-cells = <3>;
1244                 pinctrl-names = "default";
1245                 pinctrl-0 = <&pwm1_pin>;
1246                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1247                 clock-names = "pwm";
1248                 status = "disabled";
1249         };
1250
1251         pwm2: pwm@ff420020 {
1252                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1253                 reg = <0x0 0xff420020 0x0 0x10>;
1254                 #pwm-cells = <3>;
1255                 pinctrl-names = "default";
1256                 pinctrl-0 = <&pwm2_pin>;
1257                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1258                 clock-names = "pwm";
1259                 status = "disabled";
1260         };
1261
1262         pwm3: pwm@ff420030 {
1263                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1264                 reg = <0x0 0xff420030 0x0 0x10>;
1265                 #pwm-cells = <3>;
1266                 pinctrl-names = "default";
1267                 pinctrl-0 = <&pwm3a_pin>;
1268                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1269                 clock-names = "pwm";
1270                 status = "disabled";
1271         };
1272
1273         dfi: dfi@ff630000 {
1274                 reg = <0x00 0xff630000 0x00 0x4000>;
1275                 compatible = "rockchip,rk3399-dfi";
1276                 rockchip,pmu = <&pmugrf>;
1277                 clocks = <&cru PCLK_DDR_MON>;
1278                 clock-names = "pclk_ddr_mon";
1279                 status = "disabled";
1280         };
1281
1282         dmc: dmc {
1283                 compatible = "rockchip,rk3399-dmc";
1284                 devfreq-events = <&dfi>;
1285                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1286                 clocks = <&cru SCLK_DDRCLK>;
1287                 clock-names = "dmc_clk";
1288                 ddr_timing = <&ddr_timing>;
1289                 status = "disabled";
1290         };
1291
1292         vpu: vpu_service@ff650000 {
1293                 compatible = "rockchip,vpu_service";
1294                 rockchip,grf = <&grf>;
1295                 iommus = <&vpu_mmu>;
1296                 iommu_enabled = <1>;
1297                 reg = <0x0 0xff650000 0x0 0x800>;
1298                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
1299                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1300                 interrupt-names = "irq_dec", "irq_enc";
1301                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1302                 clock-names = "aclk_vcodec", "hclk_vcodec";
1303                 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1304                 reset-names = "video_h", "video_a";
1305                 power-domains = <&power RK3399_PD_VCODEC>;
1306                 name = "vpu_service";
1307                 dev_mode = <0>;
1308                 /* 0 means ion, 1 means drm */
1309                 allocator = <1>;
1310                 status = "disabled";
1311         };
1312
1313         vpu_mmu: iommu@ff650800 {
1314                 compatible = "rockchip,iommu";
1315                 reg = <0x0 0xff650800 0x0 0x40>;
1316                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1317                 interrupt-names = "vpu_mmu";
1318                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1319                 clock-names = "aclk", "hclk";
1320                 power-domains = <&power RK3399_PD_VCODEC>;
1321                 #iommu-cells = <0>;
1322         };
1323
1324         rkvdec: rkvdec@ff660000 {
1325                 compatible = "rockchip,rkvdec";
1326                 rockchip,grf = <&grf>;
1327                 iommus = <&vdec_mmu>;
1328                 iommu_enabled = <1>;
1329                 reg = <0x0 0xff660000 0x0 0x400>;
1330                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1331                 interrupt-names = "irq_dec";
1332                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1333                          <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1334                 clock-names = "aclk_vcodec", "hclk_vcodec",
1335                               "clk_cabac", "clk_core";
1336                 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
1337                 reset-names = "video_h", "video_a";
1338                 power-domains = <&power RK3399_PD_VDU>;
1339                 dev_mode = <2>;
1340                 name = "rkvdec";
1341                 /* 0 means ion, 1 means drm */
1342                 allocator = <1>;
1343                 status = "disabled";
1344         };
1345
1346         vdec_mmu: iommu@ff660480 {
1347                 compatible = "rockchip,iommu";
1348                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1349                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1350                 interrupt-names = "vdec_mmu";
1351                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1352                 clock-names = "aclk", "hclk";
1353                 power-domains = <&power RK3399_PD_VDU>;
1354                 #iommu-cells = <0>;
1355         };
1356
1357         iep: iep@ff670000 {
1358                 compatible = "rockchip,iep";
1359                 iommu_enabled = <1>;
1360                 iommus = <&iep_mmu>;
1361                 reg = <0x0 0xff670000 0x0 0x800>;
1362                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1363                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1364                 clock-names = "aclk_iep", "hclk_iep";
1365                 power-domains = <&power RK3399_PD_IEP>;
1366                 allocator = <1>;
1367                 version = <2>;
1368                 status = "disabled";
1369         };
1370
1371         iep_mmu: iommu@ff670800 {
1372                 compatible = "rockchip,iommu";
1373                 reg = <0x0 0xff670800 0x0 0x40>;
1374                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1375                 interrupt-names = "iep_mmu";
1376                 #iommu-cells = <0>;
1377                 status = "disabled";
1378         };
1379
1380         rga: rga@ff680000 {
1381                 compatible = "rockchip,rk3399-rga";
1382                 reg = <0x0 0xff680000 0x0 0x10000>;
1383                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1384                 interrupt-names = "rga";
1385                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1386                 clock-names = "aclk", "hclk", "sclk";
1387                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1388                 reset-names = "core", "axi", "ahb";
1389                 power-domains = <&power RK3399_PD_RGA>;
1390                 status = "disabled";
1391         };
1392
1393         efuse0: efuse@ff690000 {
1394                 compatible = "rockchip,rk3399-efuse";
1395                 reg = <0x0 0xff690000 0x0 0x80>;
1396                 #address-cells = <1>;
1397                 #size-cells = <1>;
1398                 clocks = <&cru PCLK_EFUSE1024NS>;
1399                 clock-names = "pclk_efuse";
1400
1401                 /* Data cells */
1402                 efuse_id: id {
1403                         reg = <0x07 0x10>;
1404                 };
1405                 cpul_leakage: cpul-leakage {
1406                         reg = <0x1a 0x1>;
1407                 };
1408                 cpub_leakage: cpub-leakage {
1409                         reg = <0x17 0x1>;
1410                 };
1411                 gpu_leakage: gpu-leakage {
1412                         reg = <0x18 0x1>;
1413                 };
1414                 center_leakage: center-leakage {
1415                         reg = <0x19 0x1>;
1416                 };
1417                 logic_leakage: logic-leakage {
1418                         reg = <0x1b 0x1>;
1419                 };
1420                 wafer_info: wafer-info {
1421                         reg = <0x1c 0x1>;
1422                 };
1423         };
1424
1425         pmucru: pmu-clock-controller@ff750000 {
1426                 compatible = "rockchip,rk3399-pmucru";
1427                 reg = <0x0 0xff750000 0x0 0x1000>;
1428                 #clock-cells = <1>;
1429                 #reset-cells = <1>;
1430                 assigned-clocks = <&pmucru PLL_PPLL>;
1431                 assigned-clock-rates = <676000000>;
1432         };
1433
1434         cru: clock-controller@ff760000 {
1435                 compatible = "rockchip,rk3399-cru";
1436                 reg = <0x0 0xff760000 0x0 0x1000>;
1437                 #clock-cells = <1>;
1438                 #reset-cells = <1>;
1439                 assigned-clocks =
1440                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1441                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1442                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1443                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1444                         <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1445                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1446                         <&cru PCLK_PERIHP>,
1447                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1448                         <&cru PCLK_PERILP0>,
1449                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1450                 assigned-clock-rates =
1451                          <400000000>,  <200000000>,
1452                          <400000000>,  <200000000>,
1453                          <816000000>, <816000000>,
1454                          <594000000>,  <800000000>,
1455                          <200000000>, <1000000000>,
1456                          <150000000>,   <75000000>,
1457                           <37500000>,
1458                          <100000000>,  <100000000>,
1459                           <50000000>,
1460                          <100000000>,   <50000000>;
1461         };
1462
1463         grf: syscon@ff770000 {
1464                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1465                 reg = <0x0 0xff770000 0x0 0x10000>;
1466                 #address-cells = <1>;
1467                 #size-cells = <1>;
1468
1469                 io_domains: io-domains {
1470                         compatible = "rockchip,rk3399-io-voltage-domain";
1471                         status = "disabled";
1472                 };
1473
1474                 emmc_phy: phy@f780 {
1475                         compatible = "rockchip,rk3399-emmc-phy";
1476                         reg = <0xf780 0x24>;
1477                         clocks = <&sdhci>;
1478                         clock-names = "emmcclk";
1479                         #phy-cells = <0>;
1480                         status = "disabled";
1481                 };
1482
1483                 u2phy0: usb2-phy@e450 {
1484                         compatible = "rockchip,rk3399-usb2phy";
1485                         reg = <0xe450 0x10>;
1486                         clocks = <&cru SCLK_USB2PHY0_REF>;
1487                         clock-names = "phyclk";
1488                         #clock-cells = <0>;
1489                         clock-output-names = "clk_usbphy0_480m";
1490                         status = "disabled";
1491
1492                         u2phy0_otg: otg-port {
1493                                 #phy-cells = <0>;
1494                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1495                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1496                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1497                                 interrupt-names = "otg-bvalid", "otg-id",
1498                                                   "linestate";
1499                                 status = "disabled";
1500                         };
1501
1502                         u2phy0_host: host-port {
1503                                 #phy-cells = <0>;
1504                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1505                                 interrupt-names = "linestate";
1506                                 status = "disabled";
1507                         };
1508                 };
1509
1510                 u2phy1: usb2-phy@e460 {
1511                         compatible = "rockchip,rk3399-usb2phy";
1512                         reg = <0xe460 0x10>;
1513                         clocks = <&cru SCLK_USB2PHY1_REF>;
1514                         clock-names = "phyclk";
1515                         #clock-cells = <0>;
1516                         clock-output-names = "clk_usbphy1_480m";
1517                         status = "disabled";
1518
1519                         u2phy1_otg: otg-port {
1520                                 #phy-cells = <0>;
1521                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1522                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1523                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1524                                 interrupt-names = "otg-bvalid", "otg-id",
1525                                                   "linestate";
1526                                 status = "disabled";
1527                         };
1528
1529                         u2phy1_host: host-port {
1530                                 #phy-cells = <0>;
1531                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1532                                 interrupt-names = "linestate";
1533                                 status = "disabled";
1534                         };
1535                 };
1536
1537                 pvtm: pvtm {
1538                         compatible = "rockchip,rk3399-pvtm";
1539                         clocks = <&cru SCLK_PVTM_CORE_L>,
1540                                  <&cru SCLK_PVTM_CORE_B>,
1541                                  <&cru SCLK_PVTM_GPU>,
1542                                  <&cru SCLK_PVTM_DDR>;
1543                         clock-names = "core_l", "core_b", "gpu", "ddr";
1544                         status = "disabled";
1545                 };
1546         };
1547
1548         tcphy0: phy@ff7c0000 {
1549                 compatible = "rockchip,rk3399-typec-phy";
1550                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1551                 rockchip,grf = <&grf>;
1552                 #phy-cells = <1>;
1553                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1554                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1555                 clock-names = "tcpdcore", "tcpdphy-ref";
1556                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1557                 assigned-clock-rates = <50000000>;
1558                 power-domains = <&power RK3399_PD_TCPD0>;
1559                 resets = <&cru SRST_UPHY0>,
1560                          <&cru SRST_UPHY0_PIPE_L00>,
1561                          <&cru SRST_P_UPHY0_TCPHY>;
1562                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1563                 rockchip,typec-conn-dir = <0xe580 0 16>;
1564                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1565                 rockchip,usb3-host-disable = <0x2434 0 16>;
1566                 rockchip,usb3-host-port = <0x2434 12 28>;
1567                 rockchip,external-psm = <0xe588 14 30>;
1568                 rockchip,pipe-status = <0xe5c0 0 0>;
1569                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1570                 status = "disabled";
1571
1572                 tcphy0_dp: dp-port {
1573                         #phy-cells = <0>;
1574                 };
1575
1576                 tcphy0_usb3: usb3-port {
1577                         #phy-cells = <0>;
1578                 };
1579         };
1580
1581         tcphy1: phy@ff800000 {
1582                 compatible = "rockchip,rk3399-typec-phy";
1583                 reg = <0x0 0xff800000 0x0 0x40000>;
1584                 rockchip,grf = <&grf>;
1585                 #phy-cells = <1>;
1586                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1587                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1588                 clock-names = "tcpdcore", "tcpdphy-ref";
1589                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1590                 assigned-clock-rates = <50000000>;
1591                 power-domains = <&power RK3399_PD_TCPD1>;
1592                 resets = <&cru SRST_UPHY1>,
1593                          <&cru SRST_UPHY1_PIPE_L00>,
1594                          <&cru SRST_P_UPHY1_TCPHY>;
1595                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1596                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1597                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1598                 rockchip,usb3-host-disable = <0x2444 0 16>;
1599                 rockchip,usb3-host-port = <0x2444 12 28>;
1600                 rockchip,external-psm = <0xe594 14 30>;
1601                 rockchip,pipe-status = <0xe5c0 16 16>;
1602                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1603                 status = "disabled";
1604
1605                 tcphy1_dp: dp-port {
1606                         #phy-cells = <0>;
1607                 };
1608
1609                 tcphy1_usb3: usb3-port {
1610                         #phy-cells = <0>;
1611                 };
1612         };
1613
1614         watchdog@ff848000 {
1615                 compatible = "snps,dw-wdt";
1616                 reg = <0x0 0xff848000 0x0 0x100>;
1617                 clocks = <&cru PCLK_WDT>;
1618                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1619         };
1620
1621         rktimer: rktimer@ff850000 {
1622                 compatible = "rockchip,rk3399-timer";
1623                 reg = <0x0 0xff850000 0x0 0x1000>;
1624                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1625                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1626                 clock-names = "pclk", "timer";
1627         };
1628
1629         spdif: spdif@ff870000 {
1630                 compatible = "rockchip,rk3399-spdif";
1631                 reg = <0x0 0xff870000 0x0 0x1000>;
1632                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1633                 dmas = <&dmac_bus 7>;
1634                 dma-names = "tx";
1635                 clock-names = "mclk", "hclk";
1636                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1637                 pinctrl-names = "default";
1638                 pinctrl-0 = <&spdif_bus>;
1639                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1640                 status = "disabled";
1641         };
1642
1643         i2s0: i2s@ff880000 {
1644                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1645                 reg = <0x0 0xff880000 0x0 0x1000>;
1646                 rockchip,grf = <&grf>;
1647                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1648                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1649                 dma-names = "tx", "rx";
1650                 clock-names = "i2s_clk", "i2s_hclk";
1651                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1652                 pinctrl-names = "default";
1653                 pinctrl-0 = <&i2s0_8ch_bus>;
1654                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1655                 status = "disabled";
1656         };
1657
1658         i2s1: i2s@ff890000 {
1659                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1660                 reg = <0x0 0xff890000 0x0 0x1000>;
1661                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1662                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1663                 dma-names = "tx", "rx";
1664                 clock-names = "i2s_clk", "i2s_hclk";
1665                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1666                 pinctrl-names = "default";
1667                 pinctrl-0 = <&i2s1_2ch_bus>;
1668                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1669                 status = "disabled";
1670         };
1671
1672         i2s2: i2s@ff8a0000 {
1673                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1674                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1675                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1676                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1677                 dma-names = "tx", "rx";
1678                 clock-names = "i2s_clk", "i2s_hclk";
1679                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1680                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1681                 status = "disabled";
1682         };
1683
1684         gpu: gpu@ff9a0000 {
1685                 compatible = "arm,malit860",
1686                              "arm,malit86x",
1687                              "arm,malit8xx",
1688                              "arm,mali-midgard";
1689
1690                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1691
1692                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1693                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1694                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1695                 interrupt-names = "GPU", "JOB", "MMU";
1696
1697                 clocks = <&cru ACLK_GPU>;
1698                 clock-names = "clk_mali";
1699                 #cooling-cells = <2>; /* min followed by max */
1700                 power-domains = <&power RK3399_PD_GPU>;
1701                 power-off-delay-ms = <200>;
1702                 status = "disabled";
1703
1704                 gpu_power_model: power_model {
1705                         compatible = "arm,mali-simple-power-model";
1706                         voltage = <900>;
1707                         frequency = <500>;
1708                         static-power = <300>;
1709                         dynamic-power = <396>;
1710                         ts = <32000 4700 (-80) 2>;
1711                         thermal-zone = "gpu-thermal";
1712                 };
1713         };
1714
1715         vopl: vop@ff8f0000 {
1716                 compatible = "rockchip,rk3399-vop-lit";
1717                 reg = <0x0 0xff8f0000 0x0 0x1ffc>, <0x0 0xff8f2000 0x0 0x400>;
1718                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1719                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>, <&cru DCLK_VOP1_DIV>;
1720                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
1721                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1722                 reset-names = "axi", "ahb", "dclk";
1723                 power-domains = <&power RK3399_PD_VOPL>;
1724                 iommus = <&vopl_mmu>;
1725                 status = "disabled";
1726
1727                 vopl_out: port {
1728                         #address-cells = <1>;
1729                         #size-cells = <0>;
1730
1731                         vopl_out_mipi: endpoint@0 {
1732                                 reg = <0>;
1733                                 remote-endpoint = <&mipi_in_vopl>;
1734                         };
1735
1736                         vopl_out_edp: endpoint@1 {
1737                                 reg = <1>;
1738                                 remote-endpoint = <&edp_in_vopl>;
1739                         };
1740
1741                         vopl_out_hdmi: endpoint@2 {
1742                                 reg = <2>;
1743                                 remote-endpoint = <&hdmi_in_vopl>;
1744                         };
1745
1746                         vopl_out_dp: endpoint@3 {
1747                                 reg = <3>;
1748                                 remote-endpoint = <&dp_in_vopl>;
1749                         };
1750                 };
1751         };
1752
1753         vop1_pwm: voppwm@ff8f01a0 {
1754                 compatible = "rockchip,vop-pwm";
1755                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1756                 #pwm-cells = <3>;
1757                 pinctrl-names = "default";
1758                 pinctrl-0 = <&vop1_pwm_pin>;
1759                 clocks = <&cru SCLK_VOP1_PWM>;
1760                 clock-names = "pwm";
1761                 status = "disabled";
1762         };
1763
1764         vopl_mmu: iommu@ff8f3f00 {
1765                 compatible = "rockchip,iommu";
1766                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1767                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1768                 interrupt-names = "vopl_mmu";
1769                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1770                 clock-names = "aclk", "hclk";
1771                 power-domains = <&power RK3399_PD_VOPL>;
1772                 #iommu-cells = <0>;
1773                 status = "disabled";
1774         };
1775
1776         vopb: vop@ff900000 {
1777                 compatible = "rockchip,rk3399-vop-big";
1778                 reg = <0x0 0xff900000 0x0 0x1ffc>, <0x0 0xff902000 0x0 0x1000>;
1779                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1780                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>, <&cru DCLK_VOP0_DIV>;
1781                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
1782                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1783                 reset-names = "axi", "ahb", "dclk";
1784                 power-domains = <&power RK3399_PD_VOPB>;
1785                 iommus = <&vopb_mmu>;
1786                 status = "disabled";
1787
1788                 vopb_out: port {
1789                         #address-cells = <1>;
1790                         #size-cells = <0>;
1791
1792                         vopb_out_edp: endpoint@0 {
1793                                 reg = <0>;
1794                                 remote-endpoint = <&edp_in_vopb>;
1795                         };
1796
1797                         vopb_out_mipi: endpoint@1 {
1798                                 reg = <1>;
1799                                 remote-endpoint = <&mipi_in_vopb>;
1800                         };
1801
1802                         vopb_out_hdmi: endpoint@2 {
1803                                 reg = <2>;
1804                                 remote-endpoint = <&hdmi_in_vopb>;
1805                         };
1806
1807                         vopb_out_dp: endpoint@3 {
1808                                 reg = <3>;
1809                                 remote-endpoint = <&dp_in_vopb>;
1810                         };
1811                 };
1812         };
1813
1814         vop0_pwm: voppwm@ff9001a0 {
1815                 compatible = "rockchip,vop-pwm";
1816                 reg = <0x0 0xff9001a0 0x0 0x10>;
1817                 #pwm-cells = <3>;
1818                 pinctrl-names = "default";
1819                 pinctrl-0 = <&vop0_pwm_pin>;
1820                 clocks = <&cru SCLK_VOP0_PWM>;
1821                 clock-names = "pwm";
1822                 status = "disabled";
1823         };
1824
1825         vopb_mmu: iommu@ff903f00 {
1826                 compatible = "rockchip,iommu";
1827                 reg = <0x0 0xff903f00 0x0 0x100>;
1828                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1829                 interrupt-names = "vopb_mmu";
1830                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1831                 clock-names = "aclk", "hclk";
1832                 power-domains = <&power RK3399_PD_VOPB>;
1833                 #iommu-cells = <0>;
1834                 status = "disabled";
1835         };
1836
1837         isp0_mmu: iommu@ff914000 {
1838                 compatible = "rockchip,iommu";
1839                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1840                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1841                 interrupt-names = "isp0_mmu";
1842                 #iommu-cells = <0>;
1843                 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1844                 clock-names = "aclk", "hclk";
1845                 power-domains = <&power RK3399_PD_ISP0>;
1846                 rk_iommu,disable_reset_quirk;
1847                 status = "disabled";
1848         };
1849
1850         isp1_mmu: iommu@ff924000 {
1851                 compatible = "rockchip,iommu";
1852                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1853                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1854                 interrupt-names = "isp1_mmu";
1855                 #iommu-cells = <0>;
1856                 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1857                 clock-names = "aclk", "hclk";
1858                 power-domains = <&power RK3399_PD_ISP1>;
1859                 rk_iommu,disable_reset_quirk;
1860                 status = "disabled";
1861         };
1862
1863         hdmi: hdmi@ff940000 {
1864                 compatible = "rockchip,rk3399-dw-hdmi";
1865                 reg = <0x0 0xff940000 0x0 0x20000>;
1866                 reg-io-width = <4>;
1867                 rockchip,grf = <&grf>;
1868                 pinctrl-names = "default";
1869                 pinctrl-0 = <&hdmi_i2c_xfer>;
1870                 power-domains = <&power RK3399_PD_HDCP>;
1871                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1872                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1873                 clock-names = "iahb", "isfr", "vpll", "grf";
1874                 status = "disabled";
1875
1876                 ports {
1877                         hdmi_in: port {
1878                                 #address-cells = <1>;
1879                                 #size-cells = <0>;
1880                                 hdmi_in_vopb: endpoint@0 {
1881                                         reg = <0>;
1882                                         remote-endpoint = <&vopb_out_hdmi>;
1883                                 };
1884                                 hdmi_in_vopl: endpoint@1 {
1885                                         reg = <1>;
1886                                         remote-endpoint = <&vopl_out_hdmi>;
1887                                 };
1888                         };
1889                 };
1890         };
1891
1892         mipi_dsi: mipi@ff960000 {
1893                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1894                 reg = <0x0 0xff960000 0x0 0x8000>;
1895                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1896                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1897                          <&cru SCLK_DPHY_TX0_CFG>;
1898                 clock-names = "ref", "pclk", "phy_cfg";
1899                 power-domains = <&power RK3399_PD_VIO>;
1900                 rockchip,grf = <&grf>;
1901                 #address-cells = <1>;
1902                 #size-cells = <0>;
1903                 status = "disabled";
1904
1905                 ports {
1906                         #address-cells = <1>;
1907                         #size-cells = <0>;
1908                         reg = <1>;
1909
1910                         mipi_in: port {
1911                                 #address-cells = <1>;
1912                                 #size-cells = <0>;
1913
1914                                 mipi_in_vopb: endpoint@0 {
1915                                         reg = <0>;
1916                                         remote-endpoint = <&vopb_out_mipi>;
1917                                 };
1918                                 mipi_in_vopl: endpoint@1 {
1919                                         reg = <1>;
1920                                         remote-endpoint = <&vopl_out_mipi>;
1921                                 };
1922                         };
1923                 };
1924         };
1925
1926         edp: edp@ff970000 {
1927                 compatible = "rockchip,rk3399-edp";
1928                 reg = <0x0 0xff970000 0x0 0x8000>;
1929                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1930                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1931                 clock-names = "dp", "pclk";
1932                 power-domains = <&power RK3399_PD_EDP>;
1933                 resets = <&cru SRST_P_EDP_CTRL>;
1934                 reset-names = "dp";
1935                 rockchip,grf = <&grf>;
1936                 status = "disabled";
1937                 pinctrl-names = "default";
1938                 pinctrl-0 = <&edp_hpd>;
1939
1940                 ports {
1941                         #address-cells = <1>;
1942                         #size-cells = <0>;
1943
1944                         edp_in: port@0 {
1945                                 reg = <0>;
1946                                 #address-cells = <1>;
1947                                 #size-cells = <0>;
1948
1949                                 edp_in_vopb: endpoint@0 {
1950                                         reg = <0>;
1951                                         remote-endpoint = <&vopb_out_edp>;
1952                                 };
1953
1954                                 edp_in_vopl: endpoint@1 {
1955                                         reg = <1>;
1956                                         remote-endpoint = <&vopl_out_edp>;
1957                                 };
1958                         };
1959                 };
1960         };
1961
1962         display_subsystem: display-subsystem {
1963                 compatible = "rockchip,display-subsystem";
1964                 ports = <&vopl_out>, <&vopb_out>;
1965                 clocks = <&cru PLL_VPLL>, <&cru PLL_CPLL>;
1966                 clock-names = "hdmi-tmds-pll", "default-vop-pll";
1967                 status = "disabled";
1968         };
1969
1970         pinctrl: pinctrl {
1971                 compatible = "rockchip,rk3399-pinctrl";
1972                 rockchip,grf = <&grf>;
1973                 rockchip,pmu = <&pmugrf>;
1974                 #address-cells = <0x2>;
1975                 #size-cells = <0x2>;
1976                 ranges;
1977
1978                 gpio0: gpio0@ff720000 {
1979                         compatible = "rockchip,gpio-bank";
1980                         reg = <0x0 0xff720000 0x0 0x100>;
1981                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1982                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1983
1984                         gpio-controller;
1985                         #gpio-cells = <0x2>;
1986
1987                         interrupt-controller;
1988                         #interrupt-cells = <0x2>;
1989                 };
1990
1991                 gpio1: gpio1@ff730000 {
1992                         compatible = "rockchip,gpio-bank";
1993                         reg = <0x0 0xff730000 0x0 0x100>;
1994                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1995                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1996
1997                         gpio-controller;
1998                         #gpio-cells = <0x2>;
1999
2000                         interrupt-controller;
2001                         #interrupt-cells = <0x2>;
2002                 };
2003
2004                 gpio2: gpio2@ff780000 {
2005                         compatible = "rockchip,gpio-bank";
2006                         reg = <0x0 0xff780000 0x0 0x100>;
2007                         clocks = <&cru PCLK_GPIO2>;
2008                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
2009
2010                         gpio-controller;
2011                         #gpio-cells = <0x2>;
2012
2013                         interrupt-controller;
2014                         #interrupt-cells = <0x2>;
2015                 };
2016
2017                 gpio3: gpio3@ff788000 {
2018                         compatible = "rockchip,gpio-bank";
2019                         reg = <0x0 0xff788000 0x0 0x100>;
2020                         clocks = <&cru PCLK_GPIO3>;
2021                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
2022
2023                         gpio-controller;
2024                         #gpio-cells = <0x2>;
2025
2026                         interrupt-controller;
2027                         #interrupt-cells = <0x2>;
2028                 };
2029
2030                 gpio4: gpio4@ff790000 {
2031                         compatible = "rockchip,gpio-bank";
2032                         reg = <0x0 0xff790000 0x0 0x100>;
2033                         clocks = <&cru PCLK_GPIO4>;
2034                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2035
2036                         gpio-controller;
2037                         #gpio-cells = <0x2>;
2038
2039                         interrupt-controller;
2040                         #interrupt-cells = <0x2>;
2041                 };
2042
2043                 pcfg_pull_up: pcfg-pull-up {
2044                         bias-pull-up;
2045                 };
2046
2047                 pcfg_pull_down: pcfg-pull-down {
2048                         bias-pull-down;
2049                 };
2050
2051                 pcfg_pull_none: pcfg-pull-none {
2052                         bias-disable;
2053                 };
2054
2055                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2056                         bias-pull-up;
2057                         drive-strength = <20>;
2058                 };
2059
2060                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2061                         bias-disable;
2062                         drive-strength = <20>;
2063                 };
2064
2065                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2066                         bias-disable;
2067                         drive-strength = <18>;
2068                 };
2069
2070                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2071                         bias-disable;
2072                         drive-strength = <12>;
2073                 };
2074
2075                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2076                         bias-pull-up;
2077                         drive-strength = <8>;
2078                 };
2079
2080                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2081                         bias-pull-down;
2082                         drive-strength = <4>;
2083                 };
2084
2085                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2086                         bias-pull-up;
2087                         drive-strength = <2>;
2088                 };
2089
2090                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2091                         bias-pull-down;
2092                         drive-strength = <12>;
2093                 };
2094
2095                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2096                         bias-disable;
2097                         drive-strength = <13>;
2098                 };
2099
2100                 pcfg_output_high: pcfg-output-high {
2101                         output-high;
2102                 };
2103
2104                 pcfg_output_low: pcfg-output-low {
2105                         output-low;
2106                 };
2107
2108                 pcfg_input: pcfg-input {
2109                         input-enable;
2110                 };
2111
2112                 emmc {
2113                         emmc_pwr: emmc-pwr {
2114                                 rockchip,pins =
2115                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
2116                         };
2117                 };
2118
2119                 gmac {
2120                         rgmii_pins: rgmii-pins {
2121                                 rockchip,pins =
2122                                         /* mac_txclk */
2123                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2124                                         /* mac_rxclk */
2125                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2126                                         /* mac_mdio */
2127                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2128                                         /* mac_txen */
2129                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2130                                         /* mac_clk */
2131                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2132                                         /* mac_rxdv */
2133                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2134                                         /* mac_mdc */
2135                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2136                                         /* mac_rxd1 */
2137                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2138                                         /* mac_rxd0 */
2139                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2140                                         /* mac_txd1 */
2141                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2142                                         /* mac_txd0 */
2143                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2144                                         /* mac_rxd3 */
2145                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2146                                         /* mac_rxd2 */
2147                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2148                                         /* mac_txd3 */
2149                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2150                                         /* mac_txd2 */
2151                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2152                         };
2153
2154                         rmii_pins: rmii-pins {
2155                                 rockchip,pins =
2156                                         /* mac_mdio */
2157                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2158                                         /* mac_txen */
2159                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2160                                         /* mac_clk */
2161                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2162                                         /* mac_rxer */
2163                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2164                                         /* mac_rxdv */
2165                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2166                                         /* mac_mdc */
2167                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2168                                         /* mac_rxd1 */
2169                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2170                                         /* mac_rxd0 */
2171                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2172                                         /* mac_txd1 */
2173                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2174                                         /* mac_txd0 */
2175                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2176                         };
2177                 };
2178
2179                 i2c0 {
2180                         i2c0_xfer: i2c0-xfer {
2181                                 rockchip,pins =
2182                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2183                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2184                         };
2185                 };
2186
2187                 i2c1 {
2188                         i2c1_xfer: i2c1-xfer {
2189                                 rockchip,pins =
2190                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2191                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2192                         };
2193                 };
2194
2195                 i2c2 {
2196                         i2c2_xfer: i2c2-xfer {
2197                                 rockchip,pins =
2198                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2199                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2200                         };
2201                 };
2202
2203                 i2c3 {
2204                         i2c3_xfer: i2c3-xfer {
2205                                 rockchip,pins =
2206                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2207                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2208                         };
2209
2210                         i2c3_gpio: i2c3_gpio {
2211                                 rockchip,pins =
2212                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2213                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2214                         };
2215
2216                 };
2217
2218                 i2c4 {
2219                         i2c4_xfer: i2c4-xfer {
2220                                 rockchip,pins =
2221                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2222                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2223                         };
2224                 };
2225
2226                 i2c5 {
2227                         i2c5_xfer: i2c5-xfer {
2228                                 rockchip,pins =
2229                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2230                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2231                         };
2232                 };
2233
2234                 i2c6 {
2235                         i2c6_xfer: i2c6-xfer {
2236                                 rockchip,pins =
2237                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2238                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2239                         };
2240                 };
2241
2242                 i2c7 {
2243                         i2c7_xfer: i2c7-xfer {
2244                                 rockchip,pins =
2245                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2246                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2247                         };
2248                 };
2249
2250                 i2c8 {
2251                         i2c8_xfer: i2c8-xfer {
2252                                 rockchip,pins =
2253                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2254                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2255                         };
2256                 };
2257
2258                 i2s0 {
2259                         i2s0_8ch_bus: i2s0-8ch-bus {
2260                                 rockchip,pins =
2261                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2262                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2263                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2264                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2265                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2266                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2267                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2268                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2269                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2270                         };
2271                 };
2272
2273                 i2s1 {
2274                         i2s1_2ch_bus: i2s1-2ch-bus {
2275                                 rockchip,pins =
2276                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2277                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2278                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2279                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2280                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2281                         };
2282                 };
2283
2284                 sdio0 {
2285                         sdio0_bus1: sdio0-bus1 {
2286                                 rockchip,pins =
2287                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2288                         };
2289
2290                         sdio0_bus4: sdio0-bus4 {
2291                                 rockchip,pins =
2292                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2293                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2294                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2295                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2296                         };
2297
2298                         sdio0_cmd: sdio0-cmd {
2299                                 rockchip,pins =
2300                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2301                         };
2302
2303                         sdio0_clk: sdio0-clk {
2304                                 rockchip,pins =
2305                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2306                         };
2307
2308                         sdio0_cd: sdio0-cd {
2309                                 rockchip,pins =
2310                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2311                         };
2312
2313                         sdio0_pwr: sdio0-pwr {
2314                                 rockchip,pins =
2315                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2316                         };
2317
2318                         sdio0_bkpwr: sdio0-bkpwr {
2319                                 rockchip,pins =
2320                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2321                         };
2322
2323                         sdio0_wp: sdio0-wp {
2324                                 rockchip,pins =
2325                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2326                         };
2327
2328                         sdio0_int: sdio0-int {
2329                                 rockchip,pins =
2330                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2331                         };
2332                 };
2333
2334                 sdmmc {
2335                         sdmmc_bus1: sdmmc-bus1 {
2336                                 rockchip,pins =
2337                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2338                         };
2339
2340                         sdmmc_bus4: sdmmc-bus4 {
2341                                 rockchip,pins =
2342                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2343                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2344                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2345                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2346                         };
2347
2348                         sdmmc_clk: sdmmc-clk {
2349                                 rockchip,pins =
2350                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2351                         };
2352
2353                         sdmmc_cmd: sdmmc-cmd {
2354                                 rockchip,pins =
2355                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2356                         };
2357
2358                         sdmmc_cd: sdmcc-cd {
2359                                 rockchip,pins =
2360                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2361                         };
2362
2363                         sdmmc_wp: sdmmc-wp {
2364                                 rockchip,pins =
2365                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2366                         };
2367                 };
2368
2369                 spdif {
2370                         spdif_bus: spdif-bus {
2371                                 rockchip,pins =
2372                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2373                         };
2374
2375                         spdif_bus_1: spdif-bus-1 {
2376                                 rockchip,pins =
2377                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2378                         };
2379                 };
2380
2381                 spi0 {
2382                         spi0_clk: spi0-clk {
2383                                 rockchip,pins =
2384                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2385                         };
2386                         spi0_cs0: spi0-cs0 {
2387                                 rockchip,pins =
2388                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2389                         };
2390                         spi0_cs1: spi0-cs1 {
2391                                 rockchip,pins =
2392                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2393                         };
2394                         spi0_tx: spi0-tx {
2395                                 rockchip,pins =
2396                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2397                         };
2398                         spi0_rx: spi0-rx {
2399                                 rockchip,pins =
2400                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2401                         };
2402                 };
2403
2404                 spi1 {
2405                         spi1_clk: spi1-clk {
2406                                 rockchip,pins =
2407                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2408                         };
2409                         spi1_cs0: spi1-cs0 {
2410                                 rockchip,pins =
2411                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2412                         };
2413                         spi1_rx: spi1-rx {
2414                                 rockchip,pins =
2415                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2416                         };
2417                         spi1_tx: spi1-tx {
2418                                 rockchip,pins =
2419                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2420                         };
2421                 };
2422
2423                 spi2 {
2424                         spi2_clk: spi2-clk {
2425                                 rockchip,pins =
2426                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2427                         };
2428                         spi2_cs0: spi2-cs0 {
2429                                 rockchip,pins =
2430                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2431                         };
2432                         spi2_rx: spi2-rx {
2433                                 rockchip,pins =
2434                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2435                         };
2436                         spi2_tx: spi2-tx {
2437                                 rockchip,pins =
2438                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2439                         };
2440                 };
2441
2442                 spi3 {
2443                         spi3_clk: spi3-clk {
2444                                 rockchip,pins =
2445                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2446                         };
2447                         spi3_cs0: spi3-cs0 {
2448                                 rockchip,pins =
2449                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2450                         };
2451                         spi3_rx: spi3-rx {
2452                                 rockchip,pins =
2453                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2454                         };
2455                         spi3_tx: spi3-tx {
2456                                 rockchip,pins =
2457                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2458                         };
2459                 };
2460
2461                 spi4 {
2462                         spi4_clk: spi4-clk {
2463                                 rockchip,pins =
2464                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2465                         };
2466                         spi4_cs0: spi4-cs0 {
2467                                 rockchip,pins =
2468                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2469                         };
2470                         spi4_rx: spi4-rx {
2471                                 rockchip,pins =
2472                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2473                         };
2474                         spi4_tx: spi4-tx {
2475                                 rockchip,pins =
2476                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2477                         };
2478                 };
2479
2480                 spi5 {
2481                         spi5_clk: spi5-clk {
2482                                 rockchip,pins =
2483                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2484                         };
2485                         spi5_cs0: spi5-cs0 {
2486                                 rockchip,pins =
2487                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2488                         };
2489                         spi5_rx: spi5-rx {
2490                                 rockchip,pins =
2491                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2492                         };
2493                         spi5_tx: spi5-tx {
2494                                 rockchip,pins =
2495                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2496                         };
2497                 };
2498
2499                 tsadc {
2500                         otp_gpio: otp-gpio {
2501                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2502                         };
2503
2504                         otp_out: otp-out {
2505                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2506                         };
2507                 };
2508
2509                 uart0 {
2510                         uart0_xfer: uart0-xfer {
2511                                 rockchip,pins =
2512                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2513                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2514                         };
2515
2516                         uart0_cts: uart0-cts {
2517                                 rockchip,pins =
2518                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2519                         };
2520
2521                         uart0_rts: uart0-rts {
2522                                 rockchip,pins =
2523                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2524                         };
2525                 };
2526
2527                 uart1 {
2528                         uart1_xfer: uart1-xfer {
2529                                 rockchip,pins =
2530                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2531                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2532                         };
2533                 };
2534
2535                 uart2a {
2536                         uart2a_xfer: uart2a-xfer {
2537                                 rockchip,pins =
2538                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2539                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2540                         };
2541                 };
2542
2543                 uart2b {
2544                         uart2b_xfer: uart2b-xfer {
2545                                 rockchip,pins =
2546                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2547                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2548                         };
2549                 };
2550
2551                 uart2c {
2552                         uart2c_xfer: uart2c-xfer {
2553                                 rockchip,pins =
2554                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2555                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2556                         };
2557                 };
2558
2559                 uart3 {
2560                         uart3_xfer: uart3-xfer {
2561                                 rockchip,pins =
2562                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2563                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2564                         };
2565
2566                         uart3_cts: uart3-cts {
2567                                 rockchip,pins =
2568                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2569                         };
2570
2571                         uart3_rts: uart3-rts {
2572                                 rockchip,pins =
2573                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2574                         };
2575                 };
2576
2577                 uart4 {
2578                         uart4_xfer: uart4-xfer {
2579                                 rockchip,pins =
2580                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2581                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2582                         };
2583                 };
2584
2585                 uarthdcp {
2586                         uarthdcp_xfer: uarthdcp-xfer {
2587                                 rockchip,pins =
2588                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2589                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2590                         };
2591                 };
2592
2593                 pwm0 {
2594                         pwm0_pin: pwm0-pin {
2595                                 rockchip,pins =
2596                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2597                         };
2598
2599                         vop0_pwm_pin: vop0-pwm-pin {
2600                                 rockchip,pins =
2601                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2602                         };
2603                 };
2604
2605                 pwm1 {
2606                         pwm1_pin: pwm1-pin {
2607                                 rockchip,pins =
2608                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2609                         };
2610
2611                         vop1_pwm_pin: vop1-pwm-pin {
2612                                 rockchip,pins =
2613                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2614                         };
2615                 };
2616
2617                 pwm2 {
2618                         pwm2_pin: pwm2-pin {
2619                                 rockchip,pins =
2620                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2621                         };
2622                 };
2623
2624                 pwm3a {
2625                         pwm3a_pin: pwm3a-pin {
2626                                 rockchip,pins =
2627                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2628                         };
2629                 };
2630
2631                 pwm3b {
2632                         pwm3b_pin: pwm3b-pin {
2633                                 rockchip,pins =
2634                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2635                         };
2636                 };
2637
2638                 edp {
2639                         edp_hpd: edp-hpd {
2640                                 rockchip,pins =
2641                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2642                         };
2643                 };
2644
2645                 hdmi {
2646                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2647                                 rockchip,pins =
2648                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2649                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2650                         };
2651
2652                         hdmi_cec: hdmi-cec {
2653                                 rockchip,pins =
2654                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2655                         };
2656                 };
2657
2658                 pcie {
2659                         pcie_clkreqn: pci-clkreqn {
2660                                 rockchip,pins =
2661                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2662                         };
2663
2664                         pcie_clkreqnb: pci-clkreqnb {
2665                                 rockchip,pins =
2666                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2667                         };
2668
2669                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2670                                 /*
2671                                  * Since our pcie doesn't support
2672                                  * ClockPM(CPM), we want to hack this as
2673                                  * gpio, so the EP could be able to
2674                                  * de-assert it along and make ClockPM(CPM)
2675                                  * work.
2676                                  */
2677                                 rockchip,pins =
2678                                         <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
2679                         };
2680
2681                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2682                                 rockchip,pins =
2683                                         <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
2684                         };
2685                 };
2686         };
2687
2688         rockchip_suspend: rockchip-suspend {
2689                 compatible = "rockchip,pm-rk3399";
2690                 status = "disabled";
2691                 rockchip,sleep-debug-en = <0>;
2692                 rockchip,virtual-poweroff = <0>;
2693                 rockchip,sleep-mode-config = <
2694                         (0
2695                         | RKPM_SLP_ARMPD
2696                         | RKPM_SLP_PERILPPD
2697                         | RKPM_SLP_DDR_RET
2698                         | RKPM_SLP_PLLPD
2699                         | RKPM_SLP_OSC_DIS
2700                         | RKPM_SLP_CENTER_PD
2701                         | RKPM_SLP_AP_PWROFF
2702                         )
2703                 >;
2704                 rockchip,wakeup-config = <
2705                         (0
2706                         | RKPM_GPIO_WKUP_EN
2707                         )
2708                 >;
2709         };
2710 };