arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 i2c6 = &i2c6;
  66                 i2c7 = &i2c7;
  67                 i2c8 = &i2c8;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73         };
  74
  75         psci {
  76                 compatible = "arm,psci-1.0";
  77                 method = "smc";
  78         };
  79
  80         cpus {
  81                 #address-cells = <2>;
  82                 #size-cells = <0>;
  83
  84                 cpu-map {
  85                         cluster0 {
  86                                 core0 {
  87                                         cpu = <&cpu_l0>;
  88                                 };
  89                                 core1 {
  90                                         cpu = <&cpu_l1>;
  91                                 };
  92                                 core2 {
  93                                         cpu = <&cpu_l2>;
  94                                 };
  95                                 core3 {
  96                                         cpu = <&cpu_l3>;
  97                                 };
  98                         };
  99
 100                         cluster1 {
 101                                 core0 {
 102                                         cpu = <&cpu_b0>;
 103                                 };
 104                                 core1 {
 105                                         cpu = <&cpu_b1>;
 106                                 };
 107                         };
 108                 };
 109
 110                 cpu_l0: cpu@0 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a53", "arm,armv8";
 113                         reg = <0x0 0x0>;
 114                         enable-method = "psci";
 115                         #cooling-cells = <2>; /* min followed by max */
 116                         clocks = <&cru ARMCLKL>;
 117                         cpu-idle-states = <&cpu_sleep>;
 118                         operating-points-v2 = <&cluster0_opp>;
 119                 };
 120
 121                 cpu_l1: cpu@1 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a53", "arm,armv8";
 124                         reg = <0x0 0x1>;
 125                         enable-method = "psci";
 126                         clocks = <&cru ARMCLKL>;
 127                         cpu-idle-states = <&cpu_sleep>;
 128                         operating-points-v2 = <&cluster0_opp>;
 129                 };
 130
 131                 cpu_l2: cpu@2 {
 132                         device_type = "cpu";
 133                         compatible = "arm,cortex-a53", "arm,armv8";
 134                         reg = <0x0 0x2>;
 135                         enable-method = "psci";
 136                         clocks = <&cru ARMCLKL>;
 137                         cpu-idle-states = <&cpu_sleep>;
 138                         operating-points-v2 = <&cluster0_opp>;
 139                 };
 140
 141                 cpu_l3: cpu@3 {
 142                         device_type = "cpu";
 143                         compatible = "arm,cortex-a53", "arm,armv8";
 144                         reg = <0x0 0x3>;
 145                         enable-method = "psci";
 146                         clocks = <&cru ARMCLKL>;
 147                         cpu-idle-states = <&cpu_sleep>;
 148                         operating-points-v2 = <&cluster0_opp>;
 149                 };
 150
 151                 cpu_b0: cpu@100 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a72", "arm,armv8";
 154                         reg = <0x0 0x100>;
 155                         enable-method = "psci";
 156                         #cooling-cells = <2>; /* min followed by max */
 157                         clocks = <&cru ARMCLKB>;
 158                         cpu-idle-states = <&cpu_sleep>;
 159                         operating-points-v2 = <&cluster1_opp>;
 160                 };
 161
 162                 cpu_b1: cpu@101 {
 163                         device_type = "cpu";
 164                         compatible = "arm,cortex-a72", "arm,armv8";
 165                         reg = <0x0 0x101>;
 166                         enable-method = "psci";
 167                         clocks = <&cru ARMCLKB>;
 168                         cpu-idle-states = <&cpu_sleep>;
 169                         operating-points-v2 = <&cluster1_opp>;
 170                 };
 171
 172                 idle-states {
 173                         entry-method = "psci";
 174                         cpu_sleep: cpu-sleep-0 {
 175                                 compatible = "arm,idle-state";
 176                                 local-timer-stop;
 177                                 arm,psci-suspend-param = <0x0010000>;
 178                                 entry-latency-us = <350>;
 179                                 exit-latency-us = <600>;
 180                                 min-residency-us = <1150>;
 181                         };
 182                 };
 183         };
 184
 185         cluster0_opp: opp_table0 {
 186                 compatible = "operating-points-v2";
 187                 opp-shared;
 188
 189                 opp00 {
 190                         opp-hz = /bits/ 64 <408000000>;
 191                         opp-microvolt = <800000>;
 192                         clock-latency-ns = <40000>;
 193                 };
 194                 opp01 {
 195                         opp-hz = /bits/ 64 <600000000>;
 196                         opp-microvolt = <800000>;
 197                 };
 198                 opp02 {
 199                         opp-hz = /bits/ 64 <816000000>;
 200                         opp-microvolt = <800000>;
 201                 };
 202                 opp03 {
 203                         opp-hz = /bits/ 64 <1008000000>;
 204                         opp-microvolt = <875000>;
 205                 };
 206                 opp04 {
 207                         opp-hz = /bits/ 64 <1200000000>;
 208                         opp-microvolt = <925000>;
 209                 };
 210                 opp05 {
 211                         opp-hz = /bits/ 64 <1416000000>;
 212                         opp-microvolt = <1025000>;
 213                 };
 214         };
 215
 216         cluster1_opp: opp_table1 {
 217                 compatible = "operating-points-v2";
 218                 opp-shared;
 219
 220                 opp00 {
 221                         opp-hz = /bits/ 64 <408000000>;
 222                         opp-microvolt = <800000>;
 223                         clock-latency-ns = <40000>;
 224                 };
 225                 opp01 {
 226                         opp-hz = /bits/ 64 <600000000>;
 227                         opp-microvolt = <800000>;
 228                 };
 229                 opp02 {
 230                         opp-hz = /bits/ 64 <816000000>;
 231                         opp-microvolt = <800000>;
 232                 };
 233                 opp03 {
 234                         opp-hz = /bits/ 64 <1008000000>;
 235                         opp-microvolt = <850000>;
 236                 };
 237                 opp04 {
 238                         opp-hz = /bits/ 64 <1200000000>;
 239                         opp-microvolt = <925000>;
 240                 };
 241         };
 242
 243         timer {
 244                 compatible = "arm,armv8-timer";
 245                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 246                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 247                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 248                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 249         };
 250
 251         arm-pmu {
 252                 compatible = "arm,armv8-pmuv3";
 253                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 254         };
 255
 256         xin24m: xin24m {
 257                 compatible = "fixed-clock";
 258                 #clock-cells = <0>;
 259                 clock-frequency = <24000000>;
 260                 clock-output-names = "xin24m";
 261         };
 262
 263         amba {
 264                 compatible = "arm,amba-bus";
 265                 #address-cells = <2>;
 266                 #size-cells = <2>;
 267                 ranges;
 268
 269                 dmac_bus: dma-controller@ff6d0000 {
 270                         compatible = "arm,pl330", "arm,primecell";
 271                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 272                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 273                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 274                         #dma-cells = <1>;
 275                         clocks = <&cru ACLK_DMAC0_PERILP>;
 276                         clock-names = "apb_pclk";
 277                 };
 278
 279                 dmac_peri: dma-controller@ff6e0000 {
 280                         compatible = "arm,pl330", "arm,primecell";
 281                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 282                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 283                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 284                         #dma-cells = <1>;
 285                         clocks = <&cru ACLK_DMAC1_PERILP>;
 286                         clock-names = "apb_pclk";
 287                 };
 288         };
 289
 290         gmac: eth@fe300000 {
 291                 compatible = "rockchip,rk3399-gmac";
 292                 reg = <0x0 0xfe300000 0x0 0x10000>;
 293                 rockchip,grf = <&grf>;
 294                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 295                 interrupt-names = "macirq";
 296                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 297                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 298                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 299                          <&cru PCLK_GMAC>;
 300                 clock-names = "stmmaceth", "mac_clk_rx",
 301                               "mac_clk_tx", "clk_mac_ref",
 302                               "clk_mac_refout", "aclk_mac",
 303                               "pclk_mac";
 304                 resets = <&cru SRST_A_GMAC>;
 305                 reset-names = "stmmaceth";
 306                 status = "disabled";
 307         };
 308
 309         emmc_phy: phy {
 310                 compatible = "rockchip,rk3399-emmc-phy";
 311                 reg-offset = <0xf780>;
 312                 #phy-cells = <0>;
 313                 rockchip,grf = <&grf>;
 314                 ctrl-base = <0xfe330000>;
 315                 status = "disabled";
 316         };
 317
 318         sdio0: dwmmc@fe310000 {
 319                 compatible = "rockchip,rk3399-dw-mshc",
 320                              "rockchip,rk3288-dw-mshc";
 321                 reg = <0x0 0xfe310000 0x0 0x4000>;
 322                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 323                 clock-freq-min-max = <400000 150000000>;
 324                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 325                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 326                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 327                 fifo-depth = <0x100>;
 328                 status = "disabled";
 329         };
 330
 331         sdmmc: dwmmc@fe320000 {
 332                 compatible = "rockchip,rk3399-dw-mshc",
 333                              "rockchip,rk3288-dw-mshc";
 334                 reg = <0x0 0xfe320000 0x0 0x4000>;
 335                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 336                 clock-freq-min-max = <400000 150000000>;
 337                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 338                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 339                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 340                 fifo-depth = <0x100>;
 341                 status = "disabled";
 342         };
 343
 344         sdhci: sdhci@fe330000 {
 345                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 346                 reg = <0x0 0xfe330000 0x0 0x10000>;
 347                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 348                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 349                 clock-names = "clk_xin", "clk_ahb";
 350                 assigned-clocks = <&cru SCLK_EMMC>;
 351                 assigned-clock-parents = <&cru PLL_CPLL>;
 352                 assigned-clock-rates = <200000000>;
 353                 phys = <&emmc_phy>;
 354                 phy-names = "phy_arasan";
 355                 status = "disabled";
 356         };
 357
 358         usb2phy: usb2phy {
 359                 compatible = "rockchip,rk3399-usb-phy";
 360                 rockchip,grf = <&grf>;
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363
 364                 usb2phy0: usb2-phy0 {
 365                         #phy-cells = <0>;
 366                         #clock-cells = <0>;
 367                         reg = <0xe458>;
 368                 };
 369
 370                 usb2phy1: usb2-phy1 {
 371                         #phy-cells = <0>;
 372                         #clock-cells = <0>;
 373                         reg = <0xe468>;
 374                 };
 375         };
 376
 377         usb_host0_ehci: usb@fe380000 {
 378                 compatible = "generic-ehci";
 379                 reg = <0x0 0xfe380000 0x0 0x20000>;
 380                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 381                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 382                 clock-names = "hclk_host0", "hclk_host0_arb";
 383                 phys = <&usb2phy0>;
 384                 phy-names = "usb2_phy0";
 385                 status = "disabled";
 386         };
 387
 388         usb_host0_ohci: usb@fe3a0000 {
 389                 compatible = "generic-ohci";
 390                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 391                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 392                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 393                 clock-names = "hclk_host0", "hclk_host0_arb";
 394                 status = "disabled";
 395         };
 396
 397         usb_host1_ehci: usb@fe3c0000 {
 398                 compatible = "generic-ehci";
 399                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 400                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 401                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 402                 clock-names = "hclk_host1", "hclk_host1_arb";
 403                 phys = <&usb2phy1>;
 404                 phy-names = "usb2_phy1";
 405                 status = "disabled";
 406         };
 407
 408         usb_host1_ohci: usb@fe3e0000 {
 409                 compatible = "generic-ohci";
 410                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 411                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 412                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 413                 clock-names = "hclk_host1", "hclk_host1_arb";
 414                 status = "disabled";
 415         };
 416
 417         usbdrd3_0: usb@fe800000 {
 418                 compatible = "rockchip,dwc3";
 419                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 420                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 421                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 422                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 423                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 424                               "aclk_usb3", "aclk_usb3_grf";
 425                 #address-cells = <2>;
 426                 #size-cells = <2>;
 427                 ranges;
 428                 status = "disabled";
 429                 usbdrd_dwc3_0: dwc3 {
 430                         compatible = "snps,dwc3";
 431                         reg = <0x0 0xfe800000 0x0 0x100000>;
 432                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 433                         dr_mode = "otg";
 434                         tx-fifo-resize;
 435                         snps,dis_enblslpm_quirk;
 436                         snps,phyif_utmi_16_bits;
 437                         snps,dis_u2_freeclk_exists_quirk;
 438                         snps,dis_del_phy_power_chg_quirk;
 439                         status = "disabled";
 440                 };
 441         };
 442
 443         usbdrd3_1: usb@fe900000 {
 444                 compatible = "rockchip,dwc3";
 445                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 446                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 447                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 448                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 449                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 450                               "aclk_usb3", "aclk_usb3_grf";
 451                 #address-cells = <2>;
 452                 #size-cells = <2>;
 453                 ranges;
 454                 status = "disabled";
 455                 usbdrd_dwc3_1: dwc3 {
 456                         compatible = "snps,dwc3";
 457                         reg = <0x0 0xfe900000 0x0 0x100000>;
 458                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 459                         dr_mode = "otg";
 460                         tx-fifo-resize;
 461                         snps,dis_enblslpm_quirk;
 462                         snps,phyif_utmi_16_bits;
 463                         snps,dis_u2_freeclk_exists_quirk;
 464                         snps,dis_del_phy_power_chg_quirk;
 465                         status = "disabled";
 466                 };
 467         };
 468
 469         gic: interrupt-controller@fee00000 {
 470                 compatible = "arm,gic-v3";
 471                 #interrupt-cells = <3>;
 472                 #address-cells = <2>;
 473                 #size-cells = <2>;
 474                 ranges;
 475                 interrupt-controller;
 476
 477                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 478                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 479                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 480                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 481                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 482                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 483                 its: interrupt-controller@fee20000 {
 484                         compatible = "arm,gic-v3-its";
 485                         msi-controller;
 486                         reg = <0x0 0xfee20000 0x0 0x20000>;
 487                 };
 488         };
 489
 490         saradc: saradc@ff100000 {
 491                 compatible = "rockchip,rk3399-saradc";
 492                 reg = <0x0 0xff100000 0x0 0x100>;
 493                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 494                 #io-channel-cells = <1>;
 495                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 496                 clock-names = "saradc", "apb_pclk";
 497                 status = "disabled";
 498         };
 499
 500         i2c0: i2c@ff3c0000 {
 501                 compatible = "rockchip,rk3399-i2c";
 502                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 503                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 504                 clock-names = "i2c", "pclk";
 505                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 506                 pinctrl-names = "default";
 507                 pinctrl-0 = <&i2c0_xfer>;
 508                 #address-cells = <1>;
 509                 #size-cells = <0>;
 510                 status = "disabled";
 511         };
 512
 513         i2c1: i2c@ff110000 {
 514                 compatible = "rockchip,rk3399-i2c";
 515                 reg = <0x0 0xff110000 0x0 0x1000>;
 516                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 517                 clock-names = "i2c", "pclk";
 518                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 519                 pinctrl-names = "default";
 520                 pinctrl-0 = <&i2c1_xfer>;
 521                 #address-cells = <1>;
 522                 #size-cells = <0>;
 523                 status = "disabled";
 524         };
 525
 526         i2c2: i2c@ff120000 {
 527                 compatible = "rockchip,rk3399-i2c";
 528                 reg = <0x0 0xff120000 0x0 0x1000>;
 529                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 530                 clock-names = "i2c", "pclk";
 531                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 532                 pinctrl-names = "default";
 533                 pinctrl-0 = <&i2c2_xfer>;
 534                 #address-cells = <1>;
 535                 #size-cells = <0>;
 536                 status = "disabled";
 537         };
 538
 539         i2c3: i2c@ff130000 {
 540                 compatible = "rockchip,rk3399-i2c";
 541                 reg = <0x0 0xff130000 0x0 0x1000>;
 542                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 543                 clock-names = "i2c", "pclk";
 544                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 545                 pinctrl-names = "default";
 546                 pinctrl-0 = <&i2c3_xfer>;
 547                 #address-cells = <1>;
 548                 #size-cells = <0>;
 549                 status = "disabled";
 550         };
 551
 552         i2c5: i2c@ff140000 {
 553                 compatible = "rockchip,rk3399-i2c";
 554                 reg = <0x0 0xff140000 0x0 0x1000>;
 555                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 556                 clock-names = "i2c", "pclk";
 557                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 558                 pinctrl-names = "default";
 559                 pinctrl-0 = <&i2c5_xfer>;
 560                 #address-cells = <1>;
 561                 #size-cells = <0>;
 562                 status = "disabled";
 563         };
 564
 565         i2c6: i2c@ff150000 {
 566                 compatible = "rockchip,rk3399-i2c";
 567                 reg = <0x0 0xff150000 0x0 0x1000>;
 568                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 569                 clock-names = "i2c", "pclk";
 570                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 571                 pinctrl-names = "default";
 572                 pinctrl-0 = <&i2c6_xfer>;
 573                 #address-cells = <1>;
 574                 #size-cells = <0>;
 575                 status = "disabled";
 576         };
 577
 578         i2c7: i2c@ff160000 {
 579                 compatible = "rockchip,rk3399-i2c";
 580                 reg = <0x0 0xff160000 0x0 0x1000>;
 581                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 582                 clock-names = "i2c", "pclk";
 583                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 584                 pinctrl-names = "default";
 585                 pinctrl-0 = <&i2c7_xfer>;
 586                 #address-cells = <1>;
 587                 #size-cells = <0>;
 588                 status = "disabled";
 589         };
 590
 591         uart0: serial@ff180000 {
 592                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 593                 reg = <0x0 0xff180000 0x0 0x100>;
 594                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 595                 clock-names = "baudclk", "apb_pclk";
 596                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 597                 reg-shift = <2>;
 598                 reg-io-width = <4>;
 599                 pinctrl-names = "default";
 600                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 601                 status = "disabled";
 602         };
 603
 604         uart1: serial@ff190000 {
 605                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 606                 reg = <0x0 0xff190000 0x0 0x100>;
 607                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 608                 clock-names = "baudclk", "apb_pclk";
 609                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 610                 reg-shift = <2>;
 611                 reg-io-width = <4>;
 612                 pinctrl-names = "default";
 613                 pinctrl-0 = <&uart1_xfer>;
 614                 status = "disabled";
 615         };
 616
 617         uart2: serial@ff1a0000 {
 618                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 619                 reg = <0x0 0xff1a0000 0x0 0x100>;
 620                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 621                 clock-names = "baudclk", "apb_pclk";
 622                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 623                 reg-shift = <2>;
 624                 reg-io-width = <4>;
 625                 pinctrl-names = "default";
 626                 pinctrl-0 = <&uart2c_xfer>;
 627                 status = "disabled";
 628         };
 629
 630         uart3: serial@ff1b0000 {
 631                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 632                 reg = <0x0 0xff1b0000 0x0 0x100>;
 633                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 634                 clock-names = "baudclk", "apb_pclk";
 635                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 636                 reg-shift = <2>;
 637                 reg-io-width = <4>;
 638                 pinctrl-names = "default";
 639                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 640                 status = "disabled";
 641         };
 642
 643         spi0: spi@ff1c0000 {
 644                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 645                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 646                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 647                 clock-names = "spiclk", "apb_pclk";
 648                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 649                 pinctrl-names = "default";
 650                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 651                 #address-cells = <1>;
 652                 #size-cells = <0>;
 653                 status = "disabled";
 654         };
 655
 656         spi1: spi@ff1d0000 {
 657                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 658                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 659                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 660                 clock-names = "spiclk", "apb_pclk";
 661                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 662                 pinctrl-names = "default";
 663                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 664                 #address-cells = <1>;
 665                 #size-cells = <0>;
 666                 status = "disabled";
 667         };
 668
 669         spi2: spi@ff1e0000 {
 670                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 671                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 672                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 673                 clock-names = "spiclk", "apb_pclk";
 674                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 675                 pinctrl-names = "default";
 676                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 677                 #address-cells = <1>;
 678                 #size-cells = <0>;
 679                 status = "disabled";
 680         };
 681
 682         spi4: spi@ff1f0000 {
 683                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 684                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 685                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 686                 clock-names = "spiclk", "apb_pclk";
 687                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 688                 pinctrl-names = "default";
 689                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 690                 #address-cells = <1>;
 691                 #size-cells = <0>;
 692                 status = "disabled";
 693         };
 694
 695         spi5: spi@ff200000 {
 696                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 697                 reg = <0x0 0xff200000 0x0 0x1000>;
 698                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 699                 clock-names = "spiclk", "apb_pclk";
 700                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 701                 pinctrl-names = "default";
 702                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 703                 #address-cells = <1>;
 704                 #size-cells = <0>;
 705                 status = "disabled";
 706         };
 707
 708         thermal-zones {
 709                 cpu {
 710                         polling-delay-passive = <100>; /* milliseconds */
 711                         polling-delay = <1000>; /* milliseconds */
 712
 713                         thermal-sensors = <&tsadc 0>;
 714
 715                         trips {
 716                                 cpu_alert0: cpu_alert0 {
 717                                         temperature = <70000>; /* millicelsius */
 718                                         hysteresis = <2000>; /* millicelsius */
 719                                         type = "passive";
 720                                 };
 721                                 cpu_alert1: cpu_alert1 {
 722                                         temperature = <75000>; /* millicelsius */
 723                                         hysteresis = <2000>; /* millicelsius */
 724                                         type = "passive";
 725                                 };
 726                                 cpu_crit: cpu_crit {
 727                                         temperature = <95000>; /* millicelsius */
 728                                         hysteresis = <2000>; /* millicelsius */
 729                                         type = "critical";
 730                                 };
 731                         };
 732
 733                         cooling-maps {
 734                                 map0 {
 735                                         trip = <&cpu_alert0>;
 736                                         cooling-device =
 737                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 738                                 };
 739                                 map1 {
 740                                         trip = <&cpu_alert1>;
 741                                         cooling-device =
 742                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 743                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 744                                 };
 745                         };
 746                 };
 747
 748                 gpu {
 749                         polling-delay-passive = <100>; /* milliseconds */
 750                         polling-delay = <1000>; /* milliseconds */
 751
 752                         thermal-sensors = <&tsadc 1>;
 753
 754                         trips {
 755                                 gpu_alert0: gpu_alert0 {
 756                                         temperature = <75000>; /* millicelsius */
 757                                         hysteresis = <2000>; /* millicelsius */
 758                                         type = "passive";
 759                                 };
 760                                 gpu_crit: gpu_crit {
 761                                         temperature = <95000>; /* millicelsius */
 762                                         hysteresis = <2000>; /* millicelsius */
 763                                         type = "critical";
 764                                 };
 765                         };
 766
 767                         cooling-maps {
 768                                 map0 {
 769                                         trip = <&gpu_alert0>;
 770                                         cooling-device =
 771                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 772                                 };
 773                         };
 774                 };
 775         };
 776
 777         tsadc: tsadc@ff260000 {
 778                 compatible = "rockchip,rk3399-tsadc";
 779                 reg = <0x0 0xff260000 0x0 0x100>;
 780                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 781                 rockchip,grf = <&grf>;
 782                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 783                 clock-names = "tsadc", "apb_pclk";
 784                 assigned-clocks = <&cru SCLK_TSADC>;
 785                 assigned-clock-rates = <750000>;
 786                 resets = <&cru SRST_TSADC>;
 787                 reset-names = "tsadc-apb";
 788                 pinctrl-names = "init", "default", "sleep";
 789                 pinctrl-0 = <&otp_gpio>;
 790                 pinctrl-1 = <&otp_out>;
 791                 pinctrl-2 = <&otp_gpio>;
 792                 #thermal-sensor-cells = <1>;
 793                 rockchip,hw-tshut-temp = <95000>;
 794                 status = "disabled";
 795         };
 796
 797         pmu: power-management@ff310000 {
 798                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 799                 reg = <0x0 0xff310000 0x0 0x1000>;
 800
 801                 power: power-controller {
 802                         status = "disabled";
 803                         compatible = "rockchip,rk3399-power-controller";
 804                         #power-domain-cells = <1>;
 805                         #address-cells = <1>;
 806                         #size-cells = <0>;
 807
 808                         pd_center {
 809                                 reg = <RK3399_PD_CENTER>;
 810                                 #address-cells = <1>;
 811                                 #size-cells = <0>;
 812
 813                                 pd_vdu {
 814                                         reg = <RK3399_PD_VDU>;
 815                                 };
 816                                 pd_vcodec {
 817                                         reg = <RK3399_PD_VCODEC>;
 818                                 };
 819                                 pd_iep {
 820                                         reg = <RK3399_PD_IEP>;
 821                                 };
 822                                 pd_rga {
 823                                         reg = <RK3399_PD_RGA>;
 824                                 };
 825                         };
 826                         pd_vio {
 827                                 reg = <RK3399_PD_VIO>;
 828                                 #address-cells = <1>;
 829                                 #size-cells = <0>;
 830
 831                                 pd_isp0 {
 832                                         reg = <RK3399_PD_ISP0>;
 833                                 };
 834                                 pd_isp1 {
 835                                         reg = <RK3399_PD_ISP1>;
 836                                 };
 837                                 pd_hdcp {
 838                                         reg = <RK3399_PD_HDCP>;
 839                                 };
 840                                 pd_vo {
 841                                         reg = <RK3399_PD_VO>;
 842                                         #address-cells = <1>;
 843                                         #size-cells = <0>;
 844
 845                                         pd_vopb {
 846                                                 reg = <RK3399_PD_VOPB>;
 847                                         };
 848                                         pd_vopl {
 849                                                 reg = <RK3399_PD_VOPL>;
 850                                         };
 851                                 };
 852                         };
 853                         pd_gpu {
 854                                 reg = <RK3399_PD_GPU>;
 855                         };
 856                 };
 857         };
 858
 859         pmugrf: syscon@ff320000 {
 860                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 861                 reg = <0x0 0xff320000 0x0 0x1000>;
 862         };
 863
 864         spi3: spi@ff350000 {
 865                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 866                 reg = <0x0 0xff350000 0x0 0x1000>;
 867                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 868                 clock-names = "spiclk", "apb_pclk";
 869                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 870                 pinctrl-names = "default";
 871                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 872                 #address-cells = <1>;
 873                 #size-cells = <0>;
 874                 status = "disabled";
 875         };
 876
 877         uart4: serial@ff370000 {
 878                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 879                 reg = <0x0 0xff370000 0x0 0x100>;
 880                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 881                 clock-names = "baudclk", "apb_pclk";
 882                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 883                 reg-shift = <2>;
 884                 reg-io-width = <4>;
 885                 pinctrl-names = "default";
 886                 pinctrl-0 = <&uart4_xfer>;
 887                 status = "disabled";
 888         };
 889
 890         i2c4: i2c@ff3d0000 {
 891                 compatible = "rockchip,rk3399-i2c";
 892                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 893                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 894                 clock-names = "i2c", "pclk";
 895                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 896                 pinctrl-names = "default";
 897                 pinctrl-0 = <&i2c4_xfer>;
 898                 #address-cells = <1>;
 899                 #size-cells = <0>;
 900                 status = "disabled";
 901         };
 902
 903         i2c8: i2c@ff3e0000 {
 904                 compatible = "rockchip,rk3399-i2c";
 905                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 906                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 907                 clock-names = "i2c", "pclk";
 908                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 909                 pinctrl-names = "default";
 910                 pinctrl-0 = <&i2c8_xfer>;
 911                 #address-cells = <1>;
 912                 #size-cells = <0>;
 913                 status = "disabled";
 914         };
 915
 916         pwm0: pwm@ff420000 {
 917                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 918                 reg = <0x0 0xff420000 0x0 0x10>;
 919                 #pwm-cells = <3>;
 920                 pinctrl-names = "default";
 921                 pinctrl-0 = <&pwm0_pin>;
 922                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 923                 clock-names = "pwm";
 924                 status = "disabled";
 925         };
 926
 927         pwm1: pwm@ff420010 {
 928                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 929                 reg = <0x0 0xff420010 0x0 0x10>;
 930                 #pwm-cells = <3>;
 931                 pinctrl-names = "default";
 932                 pinctrl-0 = <&pwm1_pin>;
 933                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 934                 clock-names = "pwm";
 935                 status = "disabled";
 936         };
 937
 938         pwm2: pwm@ff420020 {
 939                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 940                 reg = <0x0 0xff420020 0x0 0x10>;
 941                 #pwm-cells = <3>;
 942                 pinctrl-names = "default";
 943                 pinctrl-0 = <&pwm2_pin>;
 944                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 945                 clock-names = "pwm";
 946                 status = "disabled";
 947         };
 948
 949         pwm3: pwm@ff420030 {
 950                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 951                 reg = <0x0 0xff420030 0x0 0x10>;
 952                 #pwm-cells = <3>;
 953                 pinctrl-names = "default";
 954                 pinctrl-0 = <&pwm3a_pin>;
 955                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 956                 clock-names = "pwm";
 957                 status = "disabled";
 958         };
 959
 960         rga: rga@ff680000 {
 961                 compatible = "rockchip,rk3399-rga";
 962                 reg = <0x0 0xff680000 0x0 0x10000>;
 963                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 964                 interrupt-names = "rga";
 965                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
 966                 clock-names = "aclk", "hclk", "sclk";
 967                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
 968                 reset-names = "core", "axi", "ahb";
 969                 status = "disabled";
 970         };
 971
 972         pmucru: pmu-clock-controller@ff750000 {
 973                 compatible = "rockchip,rk3399-pmucru";
 974                 reg = <0x0 0xff750000 0x0 0x1000>;
 975                 #clock-cells = <1>;
 976                 #reset-cells = <1>;
 977                 assigned-clocks = <&pmucru PLL_PPLL>;
 978                 assigned-clock-rates = <676000000>;
 979         };
 980
 981         cru: clock-controller@ff760000 {
 982                 compatible = "rockchip,rk3399-cru";
 983                 reg = <0x0 0xff760000 0x0 0x1000>;
 984                 #clock-cells = <1>;
 985                 #reset-cells = <1>;
 986                 assigned-clocks =
 987                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
 988                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
 989                         <&cru ARMCLKL>, <&cru ARMCLKB>,
 990                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 991                         <&cru PLL_NPLL>,
 992                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 993                         <&cru PCLK_PERIHP>,
 994                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 995                         <&cru PCLK_PERILP0>,
 996                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 997                 assigned-clock-rates =
 998                          <400000000>,  <200000000>,
 999                          <400000000>,  <200000000>,
1000                          <816000000>, <1008000000>,
1001                          <594000000>,  <800000000>,
1002                         <1000000000>,
1003                          <150000000>,   <75000000>,
1004                           <37500000>,
1005                          <100000000>,  <100000000>,
1006                           <50000000>,
1007                          <100000000>,   <50000000>;
1008         };
1009
1010         grf: syscon@ff770000 {
1011                 compatible = "rockchip,rk3399-grf", "syscon";
1012                 reg = <0x0 0xff770000 0x0 0x10000>;
1013         };
1014
1015         watchdog@ff840000 {
1016                 compatible = "snps,dw-wdt";
1017                 reg = <0x0 0xff840000 0x0 0x100>;
1018                 clocks = <&cru PCLK_WDT>;
1019                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1020         };
1021
1022         spdif: spdif@ff870000 {
1023                 compatible = "rockchip,rk3399-spdif";
1024                 reg = <0x0 0xff870000 0x0 0x1000>;
1025                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1026                 dmas = <&dmac_bus 7>;
1027                 dma-names = "tx";
1028                 clock-names = "mclk", "hclk";
1029                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1030                 pinctrl-names = "default";
1031                 pinctrl-0 = <&spdif_bus>;
1032                 status = "disabled";
1033         };
1034
1035         i2s0: i2s@ff880000 {
1036                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1037                 reg = <0x0 0xff880000 0x0 0x1000>;
1038                 rockchip,grf = <&grf>;
1039                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1040                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1041                 dma-names = "tx", "rx";
1042                 clock-names = "i2s_clk", "i2s_hclk";
1043                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1044                 pinctrl-names = "default";
1045                 pinctrl-0 = <&i2s0_8ch_bus>;
1046                 status = "disabled";
1047         };
1048
1049         i2s1: i2s@ff890000 {
1050                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1051                 reg = <0x0 0xff890000 0x0 0x1000>;
1052                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1053                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1054                 dma-names = "tx", "rx";
1055                 clock-names = "i2s_clk", "i2s_hclk";
1056                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1057                 pinctrl-names = "default";
1058                 pinctrl-0 = <&i2s1_2ch_bus>;
1059                 status = "disabled";
1060         };
1061
1062         i2s2: i2s@ff8a0000 {
1063                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1064                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1065                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1066                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1067                 dma-names = "tx", "rx";
1068                 clock-names = "i2s_clk", "i2s_hclk";
1069                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1070                 status = "disabled";
1071         };
1072
1073         gpu: gpu@ff9a0000 {
1074                 compatible = "arm,malit860",
1075                              "arm,malit86x",
1076                              "arm,malit8xx",
1077                              "arm,mali-midgard";
1078
1079                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1080
1081                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1082                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1083                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1084                 interrupt-names = "GPU", "JOB", "MMU";
1085
1086                 clocks = <&cru ACLK_GPU>;
1087                 clock-names = "clk_mali";
1088                 #cooling-cells = <2>; /* min followed by max */
1089                 operating-points-v2 = <&gpu_opp_table>;
1090
1091                 status = "disabled";
1092
1093                 power_model {
1094                         compatible = "arm,mali-simple-power-model";
1095                         voltage = <900>;
1096                         frequency = <500>;
1097                         static-power = <500>;
1098                         dynamic-power = <1500>;
1099                         ts = <20000 2000 (-20) 2>;
1100                         thermal-zone = "gpu";
1101                 };
1102         };
1103
1104         gpu_opp_table: gpu_opp_table {
1105                 compatible = "operating-points-v2";
1106                 opp-shared;
1107
1108                 opp00 {
1109                         opp-hz = /bits/ 64 <200000000>;
1110                         opp-microvolt = <900000>;
1111                 };
1112                 opp01 {
1113                         opp-hz = /bits/ 64 <300000000>;
1114                         opp-microvolt = <900000>;
1115                 };
1116                 opp02 {
1117                         opp-hz = /bits/ 64 <400000000>;
1118                         opp-microvolt = <900000>;
1119                 };
1120
1121         };
1122
1123         vopl: vop@ff8f0000 {
1124                 compatible = "rockchip,rk3399-vop-lit";
1125                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1126                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1127                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1128                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1129                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1130                 reset-names = "axi", "ahb", "dclk";
1131                 iommus = <&vopl_mmu>;
1132                 status = "disabled";
1133
1134                 vopl_out: port {
1135                         #address-cells = <1>;
1136                         #size-cells = <0>;
1137
1138                         vopl_out_mipi: endpoint@0 {
1139                                 reg = <0>;
1140                                 remote-endpoint = <&mipi_in_vopl>;
1141                         };
1142
1143                         vopl_out_edp: endpoint@1 {
1144                                 reg = <1>;
1145                                 remote-endpoint = <&edp_in_vopl>;
1146                         };
1147                 };
1148         };
1149
1150         vopl_mmu: iommu@ff8f3f00 {
1151                 compatible = "rockchip,iommu";
1152                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1153                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1154                 interrupt-names = "vopl_mmu";
1155                 #iommu-cells = <0>;
1156                 status = "disabled";
1157         };
1158
1159         vopb: vop@ff900000 {
1160                 compatible = "rockchip,rk3399-vop-big";
1161                 reg = <0x0 0xff900000 0x0 0x3efc>;
1162                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1163                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1164                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1165                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1166                 reset-names = "axi", "ahb", "dclk";
1167                 iommus = <&vopb_mmu>;
1168                 status = "disabled";
1169
1170                 vopb_out: port {
1171                         #address-cells = <1>;
1172                         #size-cells = <0>;
1173
1174                         vopb_out_edp: endpoint@0 {
1175                                 reg = <0>;
1176                                 remote-endpoint = <&edp_in_vopb>;
1177                         };
1178
1179                         vopb_out_mipi: endpoint@1 {
1180                                 reg = <1>;
1181                                 remote-endpoint = <&mipi_in_vopb>;
1182                         };
1183                 };
1184         };
1185
1186         vopb_mmu: iommu@ff903f00 {
1187                 compatible = "rockchip,iommu";
1188                 reg = <0x0 0xff903f00 0x0 0x100>;
1189                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1190                 interrupt-names = "vopb_mmu";
1191                 #iommu-cells = <0>;
1192                 status = "disabled";
1193         };
1194
1195         mipi_dsi: mipi@ff960000 {
1196                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1197                 reg = <0x0 0xff960000 0x0 0x8000>;
1198                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1199                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1200                          <&cru SCLK_DPHY_TX0_CFG>;
1201                 clock-names = "ref", "pclk", "phy_cfg";
1202                 rockchip,grf = <&grf>;
1203                 #address-cells = <1>;
1204                 #size-cells = <0>;
1205                 status = "disabled";
1206
1207                 ports {
1208                         #address-cells = <1>;
1209                         #size-cells = <0>;
1210                         reg = <1>;
1211
1212                         mipi_in: port {
1213                                 #address-cells = <1>;
1214                                 #size-cells = <0>;
1215
1216                                 mipi_in_vopb: endpoint@0 {
1217                                         reg = <0>;
1218                                         remote-endpoint = <&vopb_out_mipi>;
1219                                 };
1220                                 mipi_in_vopl: endpoint@1 {
1221                                         reg = <1>;
1222                                         remote-endpoint = <&vopl_out_mipi>;
1223                                 };
1224                         };
1225                 };
1226         };
1227
1228         edp: edp@ff970000 {
1229                 compatible = "rockchip,rk3399-edp";
1230                 reg = <0x0 0xff970000 0x0 0x8000>;
1231                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1232                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1233                 clock-names = "dp", "pclk";
1234                 resets = <&cru SRST_P_EDP_CTRL>;
1235                 reset-names = "dp";
1236                 rockchip,grf = <&grf>;
1237                 status = "disabled";
1238                 pinctrl-names = "default";
1239                 pinctrl-0 = <&edp_hpd>;
1240
1241                 ports {
1242                         #address-cells = <1>;
1243                         #size-cells = <0>;
1244
1245                         edp_in: port@0 {
1246                                 reg = <0>;
1247                                 #address-cells = <1>;
1248                                 #size-cells = <0>;
1249
1250                                 edp_in_vopb: endpoint@0 {
1251                                         reg = <0>;
1252                                         remote-endpoint = <&vopb_out_edp>;
1253                                 };
1254
1255                                 edp_in_vopl: endpoint@1 {
1256                                         reg = <1>;
1257                                         remote-endpoint = <&vopl_out_edp>;
1258                                 };
1259                         };
1260                 };
1261         };
1262
1263         display_subsystem: display-subsystem {
1264                 compatible = "rockchip,display-subsystem";
1265                 ports = <&vopl_out>, <&vopb_out>;
1266                 status = "disabled";
1267         };
1268
1269         pinctrl: pinctrl {
1270                 compatible = "rockchip,rk3399-pinctrl";
1271                 rockchip,grf = <&grf>;
1272                 rockchip,pmu = <&pmugrf>;
1273                 #address-cells = <0x2>;
1274                 #size-cells = <0x2>;
1275                 ranges;
1276
1277                 gpio0: gpio0@ff720000 {
1278                         compatible = "rockchip,gpio-bank";
1279                         reg = <0x0 0xff720000 0x0 0x100>;
1280                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1281                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1282
1283                         gpio-controller;
1284                         #gpio-cells = <0x2>;
1285
1286                         interrupt-controller;
1287                         #interrupt-cells = <0x2>;
1288                 };
1289
1290                 gpio1: gpio1@ff730000 {
1291                         compatible = "rockchip,gpio-bank";
1292                         reg = <0x0 0xff730000 0x0 0x100>;
1293                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1294                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1295
1296                         gpio-controller;
1297                         #gpio-cells = <0x2>;
1298
1299                         interrupt-controller;
1300                         #interrupt-cells = <0x2>;
1301                 };
1302
1303                 gpio2: gpio2@ff780000 {
1304                         compatible = "rockchip,gpio-bank";
1305                         reg = <0x0 0xff780000 0x0 0x100>;
1306                         clocks = <&cru PCLK_GPIO2>;
1307                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1308
1309                         gpio-controller;
1310                         #gpio-cells = <0x2>;
1311
1312                         interrupt-controller;
1313                         #interrupt-cells = <0x2>;
1314                 };
1315
1316                 gpio3: gpio3@ff788000 {
1317                         compatible = "rockchip,gpio-bank";
1318                         reg = <0x0 0xff788000 0x0 0x100>;
1319                         clocks = <&cru PCLK_GPIO3>;
1320                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1321
1322                         gpio-controller;
1323                         #gpio-cells = <0x2>;
1324
1325                         interrupt-controller;
1326                         #interrupt-cells = <0x2>;
1327                 };
1328
1329                 gpio4: gpio4@ff790000 {
1330                         compatible = "rockchip,gpio-bank";
1331                         reg = <0x0 0xff790000 0x0 0x100>;
1332                         clocks = <&cru PCLK_GPIO4>;
1333                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1334
1335                         gpio-controller;
1336                         #gpio-cells = <0x2>;
1337
1338                         interrupt-controller;
1339                         #interrupt-cells = <0x2>;
1340                 };
1341
1342                 pcfg_pull_up: pcfg-pull-up {
1343                         bias-pull-up;
1344                 };
1345
1346                 pcfg_pull_down: pcfg-pull-down {
1347                         bias-pull-down;
1348                 };
1349
1350                 pcfg_pull_none: pcfg-pull-none {
1351                         bias-disable;
1352                 };
1353
1354                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1355                         bias-disable;
1356                         drive-strength = <12>;
1357                 };
1358
1359                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1360                         bias-pull-up;
1361                         drive-strength = <8>;
1362                 };
1363
1364                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1365                         bias-pull-down;
1366                         drive-strength = <4>;
1367                 };
1368
1369                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1370                         bias-pull-up;
1371                         drive-strength = <2>;
1372                 };
1373
1374                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1375                         bias-pull-down;
1376                         drive-strength = <12>;
1377                 };
1378
1379                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1380                         bias-disable;
1381                         drive-strength = <13>;
1382                 };
1383
1384                 emmc {
1385                         emmc_pwr: emmc-pwr {
1386                                 rockchip,pins =
1387                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1388                         };
1389                 };
1390
1391                 gmac {
1392                         rgmii_pins: rgmii-pins {
1393                                 rockchip,pins =
1394                                         /* mac_txclk */
1395                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1396                                         /* mac_rxclk */
1397                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1398                                         /* mac_mdio */
1399                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1400                                         /* mac_txen */
1401                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1402                                         /* mac_clk */
1403                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1404                                         /* mac_rxdv */
1405                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1406                                         /* mac_mdc */
1407                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1408                                         /* mac_rxd1 */
1409                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1410                                         /* mac_rxd0 */
1411                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1412                                         /* mac_txd1 */
1413                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1414                                         /* mac_txd0 */
1415                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1416                                         /* mac_rxd3 */
1417                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1418                                         /* mac_rxd2 */
1419                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1420                                         /* mac_txd3 */
1421                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1422                                         /* mac_txd2 */
1423                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1424                         };
1425
1426                         rmii_pins: rmii-pins {
1427                                 rockchip,pins =
1428                                         /* mac_mdio */
1429                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1430                                         /* mac_txen */
1431                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1432                                         /* mac_clk */
1433                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1434                                         /* mac_rxer */
1435                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1436                                         /* mac_rxdv */
1437                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1438                                         /* mac_mdc */
1439                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1440                                         /* mac_rxd1 */
1441                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1442                                         /* mac_rxd0 */
1443                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1444                                         /* mac_txd1 */
1445                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1446                                         /* mac_txd0 */
1447                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1448                         };
1449                 };
1450
1451                 i2c0 {
1452                         i2c0_xfer: i2c0-xfer {
1453                                 rockchip,pins =
1454                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1455                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1456                         };
1457                 };
1458
1459                 i2c1 {
1460                         i2c1_xfer: i2c1-xfer {
1461                                 rockchip,pins =
1462                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1463                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1464                         };
1465                 };
1466
1467                 i2c2 {
1468                         i2c2_xfer: i2c2-xfer {
1469                                 rockchip,pins =
1470                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1471                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1472                         };
1473                 };
1474
1475                 i2c3 {
1476                         i2c3_xfer: i2c3-xfer {
1477                                 rockchip,pins =
1478                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1479                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1480                         };
1481
1482                         i2c3_gpio: i2c3_gpio {
1483                                 rockchip,pins =
1484                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1485                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1486                         };
1487
1488                 };
1489
1490                 i2c4 {
1491                         i2c4_xfer: i2c4-xfer {
1492                                 rockchip,pins =
1493                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1494                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1495                         };
1496                 };
1497
1498                 i2c5 {
1499                         i2c5_xfer: i2c5-xfer {
1500                                 rockchip,pins =
1501                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1502                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1503                         };
1504                 };
1505
1506                 i2c6 {
1507                         i2c6_xfer: i2c6-xfer {
1508                                 rockchip,pins =
1509                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1510                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1511                         };
1512                 };
1513
1514                 i2c7 {
1515                         i2c7_xfer: i2c7-xfer {
1516                                 rockchip,pins =
1517                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1518                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1519                         };
1520                 };
1521
1522                 i2c8 {
1523                         i2c8_xfer: i2c8-xfer {
1524                                 rockchip,pins =
1525                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1526                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1527                         };
1528                 };
1529
1530                 i2s0 {
1531                         i2s0_8ch_bus: i2s0-8ch-bus {
1532                                 rockchip,pins =
1533                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1534                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1535                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1536                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1537                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1538                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1539                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1540                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1541                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1542                         };
1543                 };
1544
1545                 i2s1 {
1546                         i2s1_2ch_bus: i2s1-2ch-bus {
1547                                 rockchip,pins =
1548                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1549                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1550                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1551                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1552                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1553                         };
1554                 };
1555
1556                 sdio0 {
1557                         sdio0_bus1: sdio0-bus1 {
1558                                 rockchip,pins =
1559                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1560                         };
1561
1562                         sdio0_bus4: sdio0-bus4 {
1563                                 rockchip,pins =
1564                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1565                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1566                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1567                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1568                         };
1569
1570                         sdio0_cmd: sdio0-cmd {
1571                                 rockchip,pins =
1572                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1573                         };
1574
1575                         sdio0_clk: sdio0-clk {
1576                                 rockchip,pins =
1577                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1578                         };
1579
1580                         sdio0_cd: sdio0-cd {
1581                                 rockchip,pins =
1582                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1583                         };
1584
1585                         sdio0_pwr: sdio0-pwr {
1586                                 rockchip,pins =
1587                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1588                         };
1589
1590                         sdio0_bkpwr: sdio0-bkpwr {
1591                                 rockchip,pins =
1592                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1593                         };
1594
1595                         sdio0_wp: sdio0-wp {
1596                                 rockchip,pins =
1597                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1598                         };
1599
1600                         sdio0_int: sdio0-int {
1601                                 rockchip,pins =
1602                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1603                         };
1604                 };
1605
1606                 sdmmc {
1607                         sdmmc_bus1: sdmmc-bus1 {
1608                                 rockchip,pins =
1609                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1610                         };
1611
1612                         sdmmc_bus4: sdmmc-bus4 {
1613                                 rockchip,pins =
1614                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1615                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1616                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1617                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1618                         };
1619
1620                         sdmmc_clk: sdmmc-clk {
1621                                 rockchip,pins =
1622                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1623                         };
1624
1625                         sdmmc_cmd: sdmmc-cmd {
1626                                 rockchip,pins =
1627                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1628                         };
1629
1630                         sdmmc_cd: sdmcc-cd {
1631                                 rockchip,pins =
1632                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1633                         };
1634
1635                         sdmmc_wp: sdmmc-wp {
1636                                 rockchip,pins =
1637                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1638                         };
1639                 };
1640
1641                 spdif {
1642                         spdif_bus: spdif-bus {
1643                                 rockchip,pins =
1644                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1645                         };
1646                 };
1647
1648                 spi0 {
1649                         spi0_clk: spi0-clk {
1650                                 rockchip,pins =
1651                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1652                         };
1653                         spi0_cs0: spi0-cs0 {
1654                                 rockchip,pins =
1655                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1656                         };
1657                         spi0_cs1: spi0-cs1 {
1658                                 rockchip,pins =
1659                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1660                         };
1661                         spi0_tx: spi0-tx {
1662                                 rockchip,pins =
1663                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1664                         };
1665                         spi0_rx: spi0-rx {
1666                                 rockchip,pins =
1667                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1668                         };
1669                 };
1670
1671                 spi1 {
1672                         spi1_clk: spi1-clk {
1673                                 rockchip,pins =
1674                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1675                         };
1676                         spi1_cs0: spi1-cs0 {
1677                                 rockchip,pins =
1678                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1679                         };
1680                         spi1_rx: spi1-rx {
1681                                 rockchip,pins =
1682                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1683                         };
1684                         spi1_tx: spi1-tx {
1685                                 rockchip,pins =
1686                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1687                         };
1688                 };
1689
1690                 spi2 {
1691                         spi2_clk: spi2-clk {
1692                                 rockchip,pins =
1693                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1694                         };
1695                         spi2_cs0: spi2-cs0 {
1696                                 rockchip,pins =
1697                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1698                         };
1699                         spi2_rx: spi2-rx {
1700                                 rockchip,pins =
1701                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1702                         };
1703                         spi2_tx: spi2-tx {
1704                                 rockchip,pins =
1705                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1706                         };
1707                 };
1708
1709                 spi3 {
1710                         spi3_clk: spi3-clk {
1711                                 rockchip,pins =
1712                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1713                         };
1714                         spi3_cs0: spi3-cs0 {
1715                                 rockchip,pins =
1716                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1717                         };
1718                         spi3_rx: spi3-rx {
1719                                 rockchip,pins =
1720                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1721                         };
1722                         spi3_tx: spi3-tx {
1723                                 rockchip,pins =
1724                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1725                         };
1726                 };
1727
1728                 spi4 {
1729                         spi4_clk: spi4-clk {
1730                                 rockchip,pins =
1731                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1732                         };
1733                         spi4_cs0: spi4-cs0 {
1734                                 rockchip,pins =
1735                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1736                         };
1737                         spi4_rx: spi4-rx {
1738                                 rockchip,pins =
1739                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1740                         };
1741                         spi4_tx: spi4-tx {
1742                                 rockchip,pins =
1743                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1744                         };
1745                 };
1746
1747                 spi5 {
1748                         spi5_clk: spi5-clk {
1749                                 rockchip,pins =
1750                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1751                         };
1752                         spi5_cs0: spi5-cs0 {
1753                                 rockchip,pins =
1754                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1755                         };
1756                         spi5_rx: spi5-rx {
1757                                 rockchip,pins =
1758                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1759                         };
1760                         spi5_tx: spi5-tx {
1761                                 rockchip,pins =
1762                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1763                         };
1764                 };
1765
1766                 tsadc {
1767                         otp_gpio: otp-gpio {
1768                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1769                         };
1770
1771                         otp_out: otp-out {
1772                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1773                         };
1774                 };
1775
1776                 uart0 {
1777                         uart0_xfer: uart0-xfer {
1778                                 rockchip,pins =
1779                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1780                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1781                         };
1782
1783                         uart0_cts: uart0-cts {
1784                                 rockchip,pins =
1785                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1786                         };
1787
1788                         uart0_rts: uart0-rts {
1789                                 rockchip,pins =
1790                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1791                         };
1792                 };
1793
1794                 uart1 {
1795                         uart1_xfer: uart1-xfer {
1796                                 rockchip,pins =
1797                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1798                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1799                         };
1800                 };
1801
1802                 uart2a {
1803                         uart2a_xfer: uart2a-xfer {
1804                                 rockchip,pins =
1805                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1806                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1807                         };
1808                 };
1809
1810                 uart2b {
1811                         uart2b_xfer: uart2b-xfer {
1812                                 rockchip,pins =
1813                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1814                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1815                         };
1816                 };
1817
1818                 uart2c {
1819                         uart2c_xfer: uart2c-xfer {
1820                                 rockchip,pins =
1821                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1822                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1823                         };
1824                 };
1825
1826                 uart3 {
1827                         uart3_xfer: uart3-xfer {
1828                                 rockchip,pins =
1829                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1830                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1831                         };
1832
1833                         uart3_cts: uart3-cts {
1834                                 rockchip,pins =
1835                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1836                         };
1837
1838                         uart3_rts: uart3-rts {
1839                                 rockchip,pins =
1840                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1841                         };
1842                 };
1843
1844                 uart4 {
1845                         uart4_xfer: uart4-xfer {
1846                                 rockchip,pins =
1847                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1848                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1849                         };
1850                 };
1851
1852                 uarthdcp {
1853                         uarthdcp_xfer: uarthdcp-xfer {
1854                                 rockchip,pins =
1855                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1856                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1857                         };
1858                 };
1859
1860                 pwm0 {
1861                         pwm0_pin: pwm0-pin {
1862                                 rockchip,pins =
1863                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1864                         };
1865
1866                         vop0_pwm_pin: vop0-pwm-pin {
1867                                 rockchip,pins =
1868                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1869                         };
1870                 };
1871
1872                 pwm1 {
1873                         pwm1_pin: pwm1-pin {
1874                                 rockchip,pins =
1875                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1876                         };
1877
1878                         vop1_pwm_pin: vop1-pwm-pin {
1879                                 rockchip,pins =
1880                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1881                         };
1882                 };
1883
1884                 pwm2 {
1885                         pwm2_pin: pwm2-pin {
1886                                 rockchip,pins =
1887                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1888                         };
1889                 };
1890
1891                 pwm3a {
1892                         pwm3a_pin: pwm3a-pin {
1893                                 rockchip,pins =
1894                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1895                         };
1896                 };
1897
1898                 pwm3b {
1899                         pwm3b_pin: pwm3b-pin {
1900                                 rockchip,pins =
1901                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1902                         };
1903                 };
1904
1905                 edp {
1906                         edp_hpd: edp-hpd {
1907                                 rockchip,pins =
1908                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
1909                         };
1910                 };
1911
1912                 hdmi {
1913                         hdmi_i2c_xfer: hdmi-i2c-xfer {
1914                                 rockchip,pins =
1915                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
1916                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
1917                         };
1918
1919                         hdmi_cec: hdmi-cec {
1920                                 rockchip,pins =
1921                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
1922                         };
1923                 };
1924         };
1925 };