arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 i2c6 = &i2c6;
  65                 i2c7 = &i2c7;
  66                 i2c8 = &i2c8;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         clocks = <&cru ARMCLKL>;
 116                         operating-points-v2 = <&cluster0_opp>;
 117                 };
 118
 119                 cpu_l1: cpu@1 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         reg = <0x0 0x1>;
 123                         enable-method = "psci";
 124                         clocks = <&cru ARMCLKL>;
 125                         operating-points-v2 = <&cluster0_opp>;
 126                 };
 127
 128                 cpu_l2: cpu@2 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x2>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135                 };
 136
 137                 cpu_l3: cpu@3 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x3>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster0_opp>;
 144                 };
 145
 146                 cpu_b0: cpu@100 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a72", "arm,armv8";
 149                         reg = <0x0 0x100>;
 150                         enable-method = "psci";
 151                         #cooling-cells = <2>; /* min followed by max */
 152                         clocks = <&cru ARMCLKB>;
 153                         operating-points-v2 = <&cluster1_opp>;
 154                 };
 155
 156                 cpu_b1: cpu@101 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a72", "arm,armv8";
 159                         reg = <0x0 0x101>;
 160                         enable-method = "psci";
 161                         clocks = <&cru ARMCLKB>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164         };
 165
 166         cluster0_opp: opp_table0 {
 167                 compatible = "operating-points-v2";
 168                 opp-shared;
 169
 170                 opp00 {
 171                         opp-hz = /bits/ 64 <408000000>;
 172                         opp-microvolt = <800000>;
 173                         clock-latency-ns = <40000>;
 174                 };
 175                 opp01 {
 176                         opp-hz = /bits/ 64 <600000000>;
 177                         opp-microvolt = <800000>;
 178                 };
 179                 opp02 {
 180                         opp-hz = /bits/ 64 <816000000>;
 181                         opp-microvolt = <800000>;
 182                 };
 183                 opp03 {
 184                         opp-hz = /bits/ 64 <1008000000>;
 185                         opp-microvolt = <875000>;
 186                 };
 187                 opp04 {
 188                         opp-hz = /bits/ 64 <1200000000>;
 189                         opp-microvolt = <925000>;
 190                 };
 191                 opp05 {
 192                         opp-hz = /bits/ 64 <1416000000>;
 193                         opp-microvolt = <1025000>;
 194                 };
 195         };
 196
 197         cluster1_opp: opp_table1 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp00 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp01 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp02 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp03 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <850000>;
 217                 };
 218                 opp04 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222         };
 223
 224         timer {
 225                 compatible = "arm,armv8-timer";
 226                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 227                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 228                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 229                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 230         };
 231
 232         arm-pmu {
 233                 compatible = "arm,armv8-pmuv3";
 234                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 235         };
 236
 237         xin24m: xin24m {
 238                 compatible = "fixed-clock";
 239                 #clock-cells = <0>;
 240                 clock-frequency = <24000000>;
 241                 clock-output-names = "xin24m";
 242         };
 243
 244         amba {
 245                 compatible = "arm,amba-bus";
 246                 #address-cells = <2>;
 247                 #size-cells = <2>;
 248                 ranges;
 249
 250                 dmac_bus: dma-controller@ff6d0000 {
 251                         compatible = "arm,pl330", "arm,primecell";
 252                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 253                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 254                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 255                         #dma-cells = <1>;
 256                         clocks = <&cru ACLK_DMAC0_PERILP>;
 257                         clock-names = "apb_pclk";
 258                 };
 259
 260                 dmac_peri: dma-controller@ff6e0000 {
 261                         compatible = "arm,pl330", "arm,primecell";
 262                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 263                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 264                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 265                         #dma-cells = <1>;
 266                         clocks = <&cru ACLK_DMAC1_PERILP>;
 267                         clock-names = "apb_pclk";
 268                 };
 269         };
 270
 271         gmac: eth@fe300000 {
 272                 compatible = "rockchip,rk3399-gmac";
 273                 reg = <0x0 0xfe300000 0x0 0x10000>;
 274                 rockchip,grf = <&grf>;
 275                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 276                 interrupt-names = "macirq";
 277                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 278                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 279                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 280                          <&cru PCLK_GMAC>;
 281                 clock-names = "stmmaceth", "mac_clk_rx",
 282                               "mac_clk_tx", "clk_mac_ref",
 283                               "clk_mac_refout", "aclk_mac",
 284                               "pclk_mac";
 285                 resets = <&cru SRST_A_GMAC>;
 286                 reset-names = "stmmaceth";
 287                 status = "disabled";
 288         };
 289
 290         emmc_phy: phy {
 291                 compatible = "rockchip,rk3399-emmc-phy";
 292                 reg-offset = <0xf780>;
 293                 #phy-cells = <0>;
 294                 rockchip,grf = <&grf>;
 295                 status = "disabled";
 296         };
 297
 298         sdio0: dwmmc@fe310000 {
 299                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 300                 reg = <0x0 0xfe310000 0x0 0x4000>;
 301                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 302                 clock-freq-min-max = <400000 150000000>;
 303                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 304                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 305                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 306                 fifo-depth = <0x100>;
 307                 status = "disabled";
 308         };
 309
 310         sdmmc: dwmmc@fe320000 {
 311                 compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
 312                 reg = <0x0 0xfe320000 0x0 0x4000>;
 313                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 314                 clock-freq-min-max = <400000 150000000>;
 315                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 316                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 317                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 318                 fifo-depth = <0x100>;
 319                 status = "disabled";
 320         };
 321
 322         sdhci: sdhci@fe330000 {
 323                 compatible = "arasan,sdhci-5.1";
 324                 reg = <0x0 0xfe330000 0x0 0x10000>;
 325                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 326                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 327                 clock-names = "clk_xin", "clk_ahb";
 328                 phys = <&emmc_phy>;
 329                 phy-names = "phy_arasan";
 330                 status = "disabled";
 331         };
 332
 333         usb2phy: usb2phy {
 334                 compatible = "rockchip,rk3399-usb-phy";
 335                 rockchip,grf = <&grf>;
 336                 #address-cells = <1>;
 337                 #size-cells = <0>;
 338
 339                 usb2phy0: usb2-phy0 {
 340                         #phy-cells = <0>;
 341                         #clock-cells = <0>;
 342                         reg = <0xe458>;
 343                 };
 344
 345                 usb2phy1: usb2-phy1 {
 346                         #phy-cells = <0>;
 347                         #clock-cells = <0>;
 348                         reg = <0xe468>;
 349                 };
 350         };
 351
 352         usb_host0_echi: usb@fe380000 {
 353                 compatible = "generic-ehci";
 354                 reg = <0x0 0xfe380000 0x0 0x20000>;
 355                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 356                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 357                 clock-names = "hclk_host0", "hclk_host0_arb";
 358                 phys = <&usb2phy0>;
 359                 phy-names = "usb2_phy0";
 360                 status = "disabled";
 361         };
 362
 363         usb_host0_ohci: usb@fe3a0000 {
 364                 compatible = "generic-ohci";
 365                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 366                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 368                 clock-names = "hclk_host0", "hclk_host0_arb";
 369                 status = "disabled";
 370         };
 371
 372         usb_host1_echi: usb@fe3c0000 {
 373                 compatible = "generic-ehci";
 374                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 375                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 376                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 377                 clock-names = "hclk_host1", "hclk_host1_arb";
 378                 phys = <&usb2phy1>;
 379                 phy-names = "usb2_phy1";
 380                 status = "disabled";
 381         };
 382
 383         usb_host1_ohci: usb@fe3e0000 {
 384                 compatible = "generic-ohci";
 385                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 386                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 387                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 388                 clock-names = "hclk_host1", "hclk_host1_arb";
 389                 status = "disabled";
 390         };
 391
 392         usbdrd3_0: usb@fe800000 {
 393                 compatible = "rockchip,dwc3";
 394                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 395                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 396                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 397                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 398                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 399                               "aclk_usb3", "aclk_usb3_grf";
 400                 #address-cells = <2>;
 401                 #size-cells = <2>;
 402                 ranges;
 403                 status = "disabled";
 404                 usbdrd_dwc3_0: dwc3 {
 405                         compatible = "snps,dwc3";
 406                         reg = <0x0 0xfe800000 0x0 0x100000>;
 407                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 408                         dr_mode = "otg";
 409                         tx-fifo-resize;
 410                         snps,dis_enblslpm_quirk;
 411                         snps,phyif_utmi_16_bits;
 412                         snps,dis_u2_freeclk_exists_quirk;
 413                         snps,dis_del_phy_power_chg_quirk;
 414                         status = "disabled";
 415                 };
 416         };
 417
 418         usbdrd3_1: usb@fe900000 {
 419                 compatible = "rockchip,dwc3";
 420                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 421                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 422                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 423                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 424                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 425                               "aclk_usb3", "aclk_usb3_grf";
 426                 #address-cells = <2>;
 427                 #size-cells = <2>;
 428                 ranges;
 429                 status = "disabled";
 430                 usbdrd_dwc3_1: dwc3 {
 431                         compatible = "snps,dwc3";
 432                         reg = <0x0 0xfe900000 0x0 0x100000>;
 433                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 434                         dr_mode = "otg";
 435                         tx-fifo-resize;
 436                         snps,dis_enblslpm_quirk;
 437                         snps,phyif_utmi_16_bits;
 438                         snps,dis_u2_freeclk_exists_quirk;
 439                         snps,dis_del_phy_power_chg_quirk;
 440                         status = "disabled";
 441                 };
 442         };
 443
 444         gic: interrupt-controller@fee00000 {
 445                 compatible = "arm,gic-v3";
 446                 #interrupt-cells = <3>;
 447                 #address-cells = <2>;
 448                 #size-cells = <2>;
 449                 ranges;
 450                 interrupt-controller;
 451
 452                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 453                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 454                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 455                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 456                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 457                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 458                 its: interrupt-controller@fee20000 {
 459                         compatible = "arm,gic-v3-its";
 460                         msi-controller;
 461                         reg = <0x0 0xfee20000 0x0 0x20000>;
 462                 };
 463         };
 464
 465         saradc: saradc@ff100000 {
 466                 compatible = "rockchip,rk3399-saradc";
 467                 reg = <0x0 0xff100000 0x0 0x100>;
 468                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 469                 #io-channel-cells = <1>;
 470                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 471                 clock-names = "saradc", "apb_pclk";
 472                 status = "disabled";
 473         };
 474
 475         i2c0: i2c@ff3c0000 {
 476                 compatible = "rockchip,rk3399-i2c";
 477                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 478                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 479                 clock-names = "i2c", "pclk";
 480                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 481                 pinctrl-names = "default";
 482                 pinctrl-0 = <&i2c0_xfer>;
 483                 #address-cells = <1>;
 484                 #size-cells = <0>;
 485                 status = "disabled";
 486         };
 487
 488         i2c1: i2c@ff110000 {
 489                 compatible = "rockchip,rk3399-i2c";
 490                 reg = <0x0 0xff110000 0x0 0x1000>;
 491                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 492                 clock-names = "i2c", "pclk";
 493                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 494                 pinctrl-names = "default";
 495                 pinctrl-0 = <&i2c1_xfer>;
 496                 #address-cells = <1>;
 497                 #size-cells = <0>;
 498                 status = "disabled";
 499         };
 500
 501         i2c2: i2c@ff120000 {
 502                 compatible = "rockchip,rk3399-i2c";
 503                 reg = <0x0 0xff120000 0x0 0x1000>;
 504                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 505                 clock-names = "i2c", "pclk";
 506                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 507                 pinctrl-names = "default";
 508                 pinctrl-0 = <&i2c2_xfer>;
 509                 #address-cells = <1>;
 510                 #size-cells = <0>;
 511                 status = "disabled";
 512         };
 513
 514         i2c3: i2c@ff130000 {
 515                 compatible = "rockchip,rk3399-i2c";
 516                 reg = <0x0 0xff130000 0x0 0x1000>;
 517                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 518                 clock-names = "i2c", "pclk";
 519                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&i2c3_xfer>;
 522                 #address-cells = <1>;
 523                 #size-cells = <0>;
 524                 status = "disabled";
 525         };
 526
 527         i2c5: i2c@ff140000 {
 528                 compatible = "rockchip,rk3399-i2c";
 529                 reg = <0x0 0xff140000 0x0 0x1000>;
 530                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 531                 clock-names = "i2c", "pclk";
 532                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&i2c5_xfer>;
 535                 #address-cells = <1>;
 536                 #size-cells = <0>;
 537                 status = "disabled";
 538         };
 539
 540         i2c6: i2c@ff150000 {
 541                 compatible = "rockchip,rk3399-i2c";
 542                 reg = <0x0 0xff150000 0x0 0x1000>;
 543                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 544                 clock-names = "i2c", "pclk";
 545                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&i2c6_xfer>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 status = "disabled";
 551         };
 552
 553         i2c7: i2c@ff160000 {
 554                 compatible = "rockchip,rk3399-i2c";
 555                 reg = <0x0 0xff160000 0x0 0x1000>;
 556                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 557                 clock-names = "i2c", "pclk";
 558                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&i2c7_xfer>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 status = "disabled";
 564         };
 565
 566         uart0: serial@ff180000 {
 567                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 568                 reg = <0x0 0xff180000 0x0 0x100>;
 569                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 570                 clock-names = "baudclk", "apb_pclk";
 571                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 572                 reg-shift = <2>;
 573                 reg-io-width = <4>;
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 576                 status = "disabled";
 577         };
 578
 579         uart1: serial@ff190000 {
 580                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 581                 reg = <0x0 0xff190000 0x0 0x100>;
 582                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 583                 clock-names = "baudclk", "apb_pclk";
 584                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 585                 reg-shift = <2>;
 586                 reg-io-width = <4>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&uart1_xfer>;
 589                 status = "disabled";
 590         };
 591
 592         uart2: serial@ff1a0000 {
 593                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 594                 reg = <0x0 0xff1a0000 0x0 0x100>;
 595                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 596                 clock-names = "baudclk", "apb_pclk";
 597                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 598                 reg-shift = <2>;
 599                 reg-io-width = <4>;
 600                 pinctrl-names = "default";
 601                 pinctrl-0 = <&uart2c_xfer>;
 602                 status = "disabled";
 603         };
 604
 605         uart3: serial@ff1b0000 {
 606                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 607                 reg = <0x0 0xff1b0000 0x0 0x100>;
 608                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 609                 clock-names = "baudclk", "apb_pclk";
 610                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 611                 reg-shift = <2>;
 612                 reg-io-width = <4>;
 613                 pinctrl-names = "default";
 614                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 615                 status = "disabled";
 616         };
 617
 618         spi0: spi@ff1c0000 {
 619                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 620                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 621                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 622                 clock-names = "spiclk", "apb_pclk";
 623                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 624                 pinctrl-names = "default";
 625                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 626                 #address-cells = <1>;
 627                 #size-cells = <0>;
 628                 status = "disabled";
 629         };
 630
 631         spi1: spi@ff1d0000 {
 632                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 633                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 634                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 635                 clock-names = "spiclk", "apb_pclk";
 636                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 639                 #address-cells = <1>;
 640                 #size-cells = <0>;
 641                 status = "disabled";
 642         };
 643
 644         spi2: spi@ff1e0000 {
 645                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 646                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 647                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 648                 clock-names = "spiclk", "apb_pclk";
 649                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 650                 pinctrl-names = "default";
 651                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 652                 #address-cells = <1>;
 653                 #size-cells = <0>;
 654                 status = "disabled";
 655         };
 656
 657         spi4: spi@ff1f0000 {
 658                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 659                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 660                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 661                 clock-names = "spiclk", "apb_pclk";
 662                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 663                 pinctrl-names = "default";
 664                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 665                 #address-cells = <1>;
 666                 #size-cells = <0>;
 667                 status = "disabled";
 668         };
 669
 670         spi5: spi@ff200000 {
 671                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 672                 reg = <0x0 0xff200000 0x0 0x1000>;
 673                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 674                 clock-names = "spiclk", "apb_pclk";
 675                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 676                 pinctrl-names = "default";
 677                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 678                 #address-cells = <1>;
 679                 #size-cells = <0>;
 680                 status = "disabled";
 681         };
 682
 683         thermal-zones {
 684                 cpu {
 685                         polling-delay-passive = <100>; /* milliseconds */
 686                         polling-delay = <1000>; /* milliseconds */
 687
 688                         thermal-sensors = <&tsadc 0>;
 689
 690                         trips {
 691                                 cpu_alert0: cpu_alert0 {
 692                                         temperature = <70000>; /* millicelsius */
 693                                         hysteresis = <2000>; /* millicelsius */
 694                                         type = "passive";
 695                                 };
 696                                 cpu_alert1: cpu_alert1 {
 697                                         temperature = <75000>; /* millicelsius */
 698                                         hysteresis = <2000>; /* millicelsius */
 699                                         type = "passive";
 700                                 };
 701                                 cpu_crit: cpu_crit {
 702                                         temperature = <95000>; /* millicelsius */
 703                                         hysteresis = <2000>; /* millicelsius */
 704                                         type = "critical";
 705                                 };
 706                         };
 707
 708                         cooling-maps {
 709                                 map0 {
 710                                         trip = <&cpu_alert0>;
 711                                         cooling-device =
 712                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 713                                 };
 714                                 map1 {
 715                                         trip = <&cpu_alert1>;
 716                                         cooling-device =
 717                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 718                                 };
 719                         };
 720                 };
 721
 722                 gpu {
 723                         polling-delay-passive = <100>; /* milliseconds */
 724                         polling-delay = <1000>; /* milliseconds */
 725
 726                         thermal-sensors = <&tsadc 1>;
 727
 728                         trips {
 729                                 gpu_alert0: gpu_alert0 {
 730                                         temperature = <75000>; /* millicelsius */
 731                                         hysteresis = <2000>; /* millicelsius */
 732                                         type = "passive";
 733                                 };
 734                                 gpu_crit: gpu_crit {
 735                                         temperature = <950000>; /* millicelsius */
 736                                         hysteresis = <2000>; /* millicelsius */
 737                                         type = "critical";
 738                                 };
 739                         };
 740
 741                         cooling-maps {
 742                                 map0 {
 743                                         trip = <&gpu_alert0>;
 744                                         cooling-device =
 745                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 746                                 };
 747                         };
 748                 };
 749         };
 750
 751         tsadc: tsadc@ff260000 {
 752                 compatible = "rockchip,rk3399-tsadc";
 753                 reg = <0x0 0xff260000 0x0 0x100>;
 754                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 755                 rockchip,grf = <&grf>;
 756                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 757                 clock-names = "tsadc", "apb_pclk";
 758                 assigned-clocks = <&cru SCLK_TSADC>;
 759                 assigned-clock-rates = <750000>;
 760                 resets = <&cru SRST_TSADC>;
 761                 reset-names = "tsadc-apb";
 762                 pinctrl-names = "init", "default", "sleep";
 763                 pinctrl-0 = <&otp_gpio>;
 764                 pinctrl-1 = <&otp_out>;
 765                 pinctrl-2 = <&otp_gpio>;
 766                 #thermal-sensor-cells = <1>;
 767                 rockchip,hw-tshut-temp = <95000>;
 768                 status = "disabled";
 769         };
 770
 771         pmu: power-management@ff31000 {
 772                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 773                 reg = <0x0 0xff310000 0x0 0x1000>;
 774
 775                 power: power-controller {
 776                         status = "disabled";
 777                         compatible = "rockchip,rk3399-power-controller";
 778                         #power-domain-cells = <1>;
 779                         #address-cells = <1>;
 780                         #size-cells = <0>;
 781
 782                         pd_center {
 783                                 reg = <RK3399_PD_CENTER>;
 784                                 #address-cells = <1>;
 785                                 #size-cells = <0>;
 786
 787                                 pd_vdu {
 788                                         reg = <RK3399_PD_VDU>;
 789                                 };
 790                                 pd_vcodec {
 791                                         reg = <RK3399_PD_VCODEC>;
 792                                 };
 793                                 pd_iep {
 794                                         reg = <RK3399_PD_IEP>;
 795                                 };
 796                                 pd_rga {
 797                                         reg = <RK3399_PD_RGA>;
 798                                 };
 799                         };
 800                         pd_vio {
 801                                 reg = <RK3399_PD_VIO>;
 802                                 #address-cells = <1>;
 803                                 #size-cells = <0>;
 804
 805                                 pd_isp0 {
 806                                         reg = <RK3399_PD_ISP0>;
 807                                 };
 808                                 pd_isp1 {
 809                                         reg = <RK3399_PD_ISP1>;
 810                                 };
 811                                 pd_hdcp {
 812                                         reg = <RK3399_PD_HDCP>;
 813                                 };
 814                                 pd_vo {
 815                                         reg = <RK3399_PD_VO>;
 816                                         #address-cells = <1>;
 817                                         #size-cells = <0>;
 818
 819                                         pd_vopb {
 820                                                 reg = <RK3399_PD_VOPB>;
 821                                         };
 822                                         pd_vopl {
 823                                                 reg = <RK3399_PD_VOPL>;
 824                                         };
 825                                 };
 826                         };
 827                         pd_gpu {
 828                                 reg = <RK3399_PD_GPU>;
 829                         };
 830                 };
 831         };
 832
 833         pmugrf: syscon@ff320000 {
 834                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 835                 reg = <0x0 0xff320000 0x0 0x1000>;
 836         };
 837
 838         spi3: spi@ff350000 {
 839                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 840                 reg = <0x0 0xff350000 0x0 0x1000>;
 841                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 842                 clock-names = "spiclk", "apb_pclk";
 843                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 844                 pinctrl-names = "default";
 845                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 846                 #address-cells = <1>;
 847                 #size-cells = <0>;
 848                 status = "disabled";
 849         };
 850
 851         uart4: serial@ff370000 {
 852                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 853                 reg = <0x0 0xff370000 0x0 0x100>;
 854                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 855                 clock-names = "baudclk", "apb_pclk";
 856                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 857                 reg-shift = <2>;
 858                 reg-io-width = <4>;
 859                 pinctrl-names = "default";
 860                 pinctrl-0 = <&uart4_xfer>;
 861                 status = "disabled";
 862         };
 863
 864         i2c4: i2c@ff3d0000 {
 865                 compatible = "rockchip,rk3399-i2c";
 866                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 867                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 868                 clock-names = "i2c", "pclk";
 869                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 870                 pinctrl-names = "default";
 871                 pinctrl-0 = <&i2c4_xfer>;
 872                 #address-cells = <1>;
 873                 #size-cells = <0>;
 874                 status = "disabled";
 875         };
 876
 877         i2c8: i2c@ff3e0000 {
 878                 compatible = "rockchip,rk3399-i2c";
 879                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 880                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 881                 clock-names = "i2c", "pclk";
 882                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 883                 pinctrl-names = "default";
 884                 pinctrl-0 = <&i2c8_xfer>;
 885                 #address-cells = <1>;
 886                 #size-cells = <0>;
 887                 status = "disabled";
 888         };
 889
 890         pwm0: pwm@ff420000 {
 891                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 892                 reg = <0x0 0xff420000 0x0 0x10>;
 893                 #pwm-cells = <3>;
 894                 pinctrl-names = "default";
 895                 pinctrl-0 = <&pwm0_pin>;
 896                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 897                 clock-names = "pwm";
 898                 status = "disabled";
 899         };
 900
 901         pwm1: pwm@ff420010 {
 902                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 903                 reg = <0x0 0xff420010 0x0 0x10>;
 904                 #pwm-cells = <3>;
 905                 pinctrl-names = "default";
 906                 pinctrl-0 = <&pwm1_pin>;
 907                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 908                 clock-names = "pwm";
 909                 status = "disabled";
 910         };
 911
 912         pwm2: pwm@ff420020 {
 913                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 914                 reg = <0x0 0xff420020 0x0 0x10>;
 915                 #pwm-cells = <3>;
 916                 pinctrl-names = "default";
 917                 pinctrl-0 = <&pwm2_pin>;
 918                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 919                 clock-names = "pwm";
 920                 status = "disabled";
 921         };
 922
 923         pwm3: pwm@ff420030 {
 924                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 925                 reg = <0x0 0xff420030 0x0 0x10>;
 926                 #pwm-cells = <3>;
 927                 pinctrl-names = "default";
 928                 pinctrl-0 = <&pwm3a_pin>;
 929                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 930                 clock-names = "pwm";
 931                 status = "disabled";
 932         };
 933
 934         pmucru: pmu-clock-controller@ff750000 {
 935                 compatible = "rockchip,rk3399-pmucru";
 936                 reg = <0x0 0xff750000 0x0 0x1000>;
 937                 #clock-cells = <1>;
 938                 #reset-cells = <1>;
 939                 assigned-clocks = <&pmucru PLL_PPLL>;
 940                 assigned-clock-rates = <676000000>;
 941         };
 942
 943         cru: clock-controller@ff760000 {
 944                 compatible = "rockchip,rk3399-cru";
 945                 reg = <0x0 0xff760000 0x0 0x1000>;
 946                 #clock-cells = <1>;
 947                 #reset-cells = <1>;
 948                 assigned-clocks =
 949                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
 950                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
 951                         <&cru ARMCLKL>, <&cru ARMCLKB>,
 952                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 953                         <&cru PLL_NPLL>,
 954                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 955                         <&cru PCLK_PERIHP>,
 956                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 957                         <&cru PCLK_PERILP0>,
 958                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
 959                 assigned-clock-rates =
 960                          <400000000>,  <200000000>,
 961                          <400000000>,  <200000000>,
 962                          <816000000>, <1008000000>,
 963                          <594000000>,  <800000000>,
 964                         <1000000000>,
 965                          <150000000>,   <75000000>,
 966                           <37500000>,
 967                          <100000000>,  <100000000>,
 968                           <50000000>,
 969                          <100000000>,   <50000000>;
 970         };
 971
 972         grf: syscon@ff770000 {
 973                 compatible = "rockchip,rk3399-grf", "syscon";
 974                 reg = <0x0 0xff770000 0x0 0x10000>;
 975         };
 976
 977         wdt0: watchdog@ff840000 {
 978                 compatible = "snps,dw-wdt";
 979                 reg = <0x0 0xff840000 0x0 0x100>;
 980                 clocks = <&cru PCLK_WDT>;
 981                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 982                 status = "disabled";
 983         };
 984
 985         spdif: spdif@ff870000 {
 986                 compatible = "rockchip,rk3399-spdif";
 987                 reg = <0x0 0xff870000 0x0 0x1000>;
 988                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 989                 dmas = <&dmac_bus 7>;
 990                 dma-names = "tx";
 991                 clock-names = "mclk", "hclk";
 992                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 993                 pinctrl-names = "default";
 994                 pinctrl-0 = <&spdif_bus>;
 995                 status = "disabled";
 996         };
 997
 998         i2s0: i2s@ff880000 {
 999                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1000                 reg = <0x0 0xff880000 0x0 0x1000>;
1001                 rockchip,grf = <&grf>;
1002                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1003                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1004                 dma-names = "tx", "rx";
1005                 clock-names = "i2s_clk", "i2s_hclk";
1006                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1007                 pinctrl-names = "default";
1008                 pinctrl-0 = <&i2s0_8ch_bus>;
1009                 status = "disabled";
1010         };
1011
1012         i2s1: i2s@ff890000 {
1013                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1014                 reg = <0x0 0xff890000 0x0 0x1000>;
1015                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1016                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1017                 dma-names = "tx", "rx";
1018                 clock-names = "i2s_clk", "i2s_hclk";
1019                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1020                 pinctrl-names = "default";
1021                 pinctrl-0 = <&i2s1_2ch_bus>;
1022                 status = "disabled";
1023         };
1024
1025         i2s2: i2s@ff8a0000 {
1026                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1027                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1028                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1029                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1030                 dma-names = "tx", "rx";
1031                 clock-names = "i2s_clk", "i2s_hclk";
1032                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1033                 status = "disabled";
1034         };
1035
1036         gpu: gpu@ff9a0000 {
1037                 compatible = "arm,malit860",
1038                              "arm,malit86x",
1039                              "arm,malit8xx",
1040                              "arm,mali-midgard";
1041
1042                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1043
1044                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1045                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1046                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1047                 interrupt-names = "GPU", "JOB", "MMU";
1048
1049                 clocks = <&cru ACLK_GPU>;
1050                 clock-names = "clk_mali";
1051                 #cooling-cells = <2>; /* min followed by max */
1052                 operating-points-v2 = <&gpu_opp_table>;
1053                 status = "disabled";
1054         };
1055
1056         gpu_opp_table: gpu_opp_table {
1057                 compatible = "operating-points-v2";
1058                 opp-shared;
1059
1060                 opp00 {
1061                         opp-hz = /bits/ 64 <200000000>;
1062                         opp-microvolt = <900000>;
1063                 };
1064                 opp01 {
1065                         opp-hz = /bits/ 64 <300000000>;
1066                         opp-microvolt = <900000>;
1067                 };
1068                 opp02 {
1069                         opp-hz = /bits/ 64 <400000000>;
1070                         opp-microvolt = <900000>;
1071                 };
1072
1073         };
1074
1075         vopl: vop@ff8f0000 {
1076                 compatible = "rockchip,rk3399-vop-lit";
1077                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1078                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1079                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1080                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1081                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1082                 reset-names = "axi", "ahb", "dclk";
1083                 iommus = <&vopl_mmu>;
1084                 status = "disabled";
1085
1086                 vopl_out: port {
1087                         #address-cells = <1>;
1088                         #size-cells = <0>;
1089
1090                         vopl_out_mipi: endpoint@0 {
1091                                 reg = <0>;
1092                                 remote-endpoint = <&mipi_in_vopl>;
1093                         };
1094
1095                         vopl_out_edp: endpoint@1 {
1096                                 reg = <1>;
1097                                 remote-endpoint = <&edp_in_vopl>;
1098                         };
1099                 };
1100         };
1101
1102         vopl_mmu: iommu@ff8f3f00 {
1103                 compatible = "rockchip,iommu";
1104                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1105                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1106                 interrupt-names = "vopl_mmu";
1107                 #iommu-cells = <0>;
1108                 status = "disabled";
1109         };
1110
1111         vopb: vop@ff900000 {
1112                 compatible = "rockchip,rk3399-vop-big";
1113                 reg = <0x0 0xff900000 0x0 0x3efc>;
1114                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1115                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1116                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1117                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1118                 reset-names = "axi", "ahb", "dclk";
1119                 iommus = <&vopb_mmu>;
1120                 status = "disabled";
1121
1122                 vopb_out: port {
1123                         #address-cells = <1>;
1124                         #size-cells = <0>;
1125
1126                         vopb_out_edp: endpoint@0 {
1127                                 reg = <0>;
1128                                 remote-endpoint = <&edp_in_vopb>;
1129                         };
1130
1131                         vopb_out_mipi: endpoint@1 {
1132                                 reg = <1>;
1133                                 remote-endpoint = <&mipi_in_vopb>;
1134                         };
1135                 };
1136         };
1137
1138         vopb_mmu: iommu@ff903f00 {
1139                 compatible = "rockchip,iommu";
1140                 reg = <0x0 0xff903f00 0x0 0x100>;
1141                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1142                 interrupt-names = "vopb_mmu";
1143                 #iommu-cells = <0>;
1144                 status = "disabled";
1145         };
1146
1147         mipi_dsi: mipi@ff960000 {
1148                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1149                 reg = <0x0 0xff960000 0x0 0x8000>;
1150                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1151                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1152                          <&cru SCLK_DPHY_TX0_CFG>;
1153                 clock-names = "ref", "pclk", "phy_cfg";
1154                 rockchip,grf = <&grf>;
1155                 #address-cells = <1>;
1156                 #size-cells = <0>;
1157                 status = "disabled";
1158
1159                 ports {
1160                         #address-cells = <1>;
1161                         #size-cells = <0>;
1162                         reg = <1>;
1163
1164                         mipi_in: port {
1165                                 #address-cells = <1>;
1166                                 #size-cells = <0>;
1167
1168                                 mipi_in_vopb: endpoint@0 {
1169                                         reg = <0>;
1170                                         remote-endpoint = <&vopb_out_mipi>;
1171                                 };
1172                                 mipi_in_vopl: endpoint@1 {
1173                                         reg = <1>;
1174                                         remote-endpoint = <&vopl_out_mipi>;
1175                                 };
1176                         };
1177                 };
1178         };
1179
1180         edp: edp@ff970000 {
1181                 compatible = "rockchip,rk3399-edp";
1182                 reg = <0x0 0xff970000 0x0 0x8000>;
1183                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1184                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1185                 clock-names = "dp", "pclk";
1186                 resets = <&cru SRST_P_EDP_CTRL>;
1187                 reset-names = "dp";
1188                 rockchip,grf = <&grf>;
1189                 status = "disabled";
1190                 pinctrl-names = "default";
1191                 pinctrl-0 = <&edp_hpd>;
1192
1193                 ports {
1194                         #address-cells = <1>;
1195                         #size-cells = <0>;
1196
1197                         edp_in: port@0 {
1198                                 reg = <0>;
1199                                 #address-cells = <1>;
1200                                 #size-cells = <0>;
1201
1202                                 edp_in_vopb: endpoint@0 {
1203                                         reg = <0>;
1204                                         remote-endpoint = <&vopb_out_edp>;
1205                                 };
1206
1207                                 edp_in_vopl: endpoint@1 {
1208                                         reg = <1>;
1209                                         remote-endpoint = <&vopl_out_edp>;
1210                                 };
1211                         };
1212                 };
1213         };
1214
1215         display_subsystem: display-subsystem {
1216                 compatible = "rockchip,display-subsystem";
1217                 ports = <&vopl_out>, <&vopb_out>;
1218                 status = "disabled";
1219         };
1220
1221         pinctrl: pinctrl {
1222                 compatible = "rockchip,rk3399-pinctrl";
1223                 rockchip,grf = <&grf>;
1224                 rockchip,pmu = <&pmugrf>;
1225                 #address-cells = <0x2>;
1226                 #size-cells = <0x2>;
1227                 ranges;
1228
1229                 gpio0: gpio0@ff720000 {
1230                         compatible = "rockchip,gpio-bank";
1231                         reg = <0x0 0xff720000 0x0 0x100>;
1232                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1233                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1234
1235                         gpio-controller;
1236                         #gpio-cells = <0x2>;
1237
1238                         interrupt-controller;
1239                         #interrupt-cells = <0x2>;
1240                 };
1241
1242                 gpio1: gpio1@ff730000 {
1243                         compatible = "rockchip,gpio-bank";
1244                         reg = <0x0 0xff730000 0x0 0x100>;
1245                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1246                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1247
1248                         gpio-controller;
1249                         #gpio-cells = <0x2>;
1250
1251                         interrupt-controller;
1252                         #interrupt-cells = <0x2>;
1253                 };
1254
1255                 gpio2: gpio2@ff780000 {
1256                         compatible = "rockchip,gpio-bank";
1257                         reg = <0x0 0xff780000 0x0 0x100>;
1258                         clocks = <&cru PCLK_GPIO2>;
1259                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1260
1261                         gpio-controller;
1262                         #gpio-cells = <0x2>;
1263
1264                         interrupt-controller;
1265                         #interrupt-cells = <0x2>;
1266                 };
1267
1268                 gpio3: gpio3@ff788000 {
1269                         compatible = "rockchip,gpio-bank";
1270                         reg = <0x0 0xff788000 0x0 0x100>;
1271                         clocks = <&cru PCLK_GPIO3>;
1272                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1273
1274                         gpio-controller;
1275                         #gpio-cells = <0x2>;
1276
1277                         interrupt-controller;
1278                         #interrupt-cells = <0x2>;
1279                 };
1280
1281                 gpio4: gpio4@ff790000 {
1282                         compatible = "rockchip,gpio-bank";
1283                         reg = <0x0 0xff790000 0x0 0x100>;
1284                         clocks = <&cru PCLK_GPIO4>;
1285                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1286
1287                         gpio-controller;
1288                         #gpio-cells = <0x2>;
1289
1290                         interrupt-controller;
1291                         #interrupt-cells = <0x2>;
1292                 };
1293
1294                 pcfg_pull_up: pcfg-pull-up {
1295                         bias-pull-up;
1296                 };
1297
1298                 pcfg_pull_down: pcfg-pull-down {
1299                         bias-pull-down;
1300                 };
1301
1302                 pcfg_pull_none: pcfg-pull-none {
1303                         bias-disable;
1304                 };
1305
1306                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1307                         bias-disable;
1308                         drive-strength = <12>;
1309                 };
1310
1311                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1312                         bias-pull-up;
1313                         drive-strength = <8>;
1314                 };
1315
1316                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1317                         bias-pull-down;
1318                         drive-strength = <4>;
1319                 };
1320
1321                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1322                         bias-pull-up;
1323                         drive-strength = <2>;
1324                 };
1325
1326                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1327                         bias-pull-down;
1328                         drive-strength = <12>;
1329                 };
1330
1331                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1332                         bias-disable;
1333                         drive-strength = <13>;
1334                 };
1335
1336                 emmc {
1337                         emmc_pwr: emmc-pwr {
1338                                 rockchip,pins =
1339                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1340                         };
1341                 };
1342
1343                 gmac {
1344                         rgmii_pins: rgmii-pins {
1345                                 rockchip,pins =
1346                                         /* mac_txclk */
1347                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1348                                         /* mac_rxclk */
1349                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1350                                         /* mac_mdio */
1351                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1352                                         /* mac_txen */
1353                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1354                                         /* mac_clk */
1355                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1356                                         /* mac_rxdv */
1357                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1358                                         /* mac_mdc */
1359                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1360                                         /* mac_rxd1 */
1361                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1362                                         /* mac_rxd0 */
1363                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1364                                         /* mac_txd1 */
1365                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1366                                         /* mac_txd0 */
1367                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1368                                         /* mac_rxd3 */
1369                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1370                                         /* mac_rxd2 */
1371                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1372                                         /* mac_txd3 */
1373                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1374                                         /* mac_txd2 */
1375                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1376                         };
1377
1378                         rmii_pins: rmii-pins {
1379                                 rockchip,pins =
1380                                         /* mac_mdio */
1381                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1382                                         /* mac_txen */
1383                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1384                                         /* mac_clk */
1385                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1386                                         /* mac_rxer */
1387                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1388                                         /* mac_rxdv */
1389                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1390                                         /* mac_mdc */
1391                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1392                                         /* mac_rxd1 */
1393                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1394                                         /* mac_rxd0 */
1395                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1396                                         /* mac_txd1 */
1397                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1398                                         /* mac_txd0 */
1399                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1400                         };
1401                 };
1402
1403                 i2c0 {
1404                         i2c0_xfer: i2c0-xfer {
1405                                 rockchip,pins =
1406                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1407                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1408                         };
1409                 };
1410
1411                 i2c1 {
1412                         i2c1_xfer: i2c1-xfer {
1413                                 rockchip,pins =
1414                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1415                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1416                         };
1417                 };
1418
1419                 i2c2 {
1420                         i2c2_xfer: i2c2-xfer {
1421                                 rockchip,pins =
1422                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1423                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1424                         };
1425                 };
1426
1427                 i2c3 {
1428                         i2c3_xfer: i2c3-xfer {
1429                                 rockchip,pins =
1430                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1431                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1432                         };
1433                 };
1434
1435                 i2c4 {
1436                         i2c4_xfer: i2c4-xfer {
1437                                 rockchip,pins =
1438                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1439                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1440                         };
1441                 };
1442
1443                 i2c5 {
1444                         i2c5_xfer: i2c5-xfer {
1445                                 rockchip,pins =
1446                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1447                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1448                         };
1449                 };
1450
1451                 i2c6 {
1452                         i2c6_xfer: i2c6-xfer {
1453                                 rockchip,pins =
1454                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1455                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1456                         };
1457                 };
1458
1459                 i2c7 {
1460                         i2c7_xfer: i2c7-xfer {
1461                                 rockchip,pins =
1462                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1463                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1464                         };
1465                 };
1466
1467                 i2c8 {
1468                         i2c8_xfer: i2c8-xfer {
1469                                 rockchip,pins =
1470                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1471                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1472                         };
1473                 };
1474
1475                 i2s0 {
1476                         i2s0_8ch_bus: i2s0-8ch-bus {
1477                                 rockchip,pins =
1478                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1479                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1480                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1481                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1482                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1483                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1484                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1485                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1486                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1487                         };
1488                 };
1489
1490                 i2s1 {
1491                         i2s1_2ch_bus: i2s1-2ch-bus {
1492                                 rockchip,pins =
1493                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1494                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1495                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1496                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1497                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1498                         };
1499                 };
1500
1501                 sdio0 {
1502                         sdio0_bus1: sdio0-bus1 {
1503                                 rockchip,pins =
1504                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1505                         };
1506
1507                         sdio0_bus4: sdio0-bus4 {
1508                                 rockchip,pins =
1509                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1510                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1511                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1512                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1513                         };
1514
1515                         sdio0_cmd: sdio0-cmd {
1516                                 rockchip,pins =
1517                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1518                         };
1519
1520                         sdio0_clk: sdio0-clk {
1521                                 rockchip,pins =
1522                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1523                         };
1524
1525                         sdio0_cd: sdio0-cd {
1526                                 rockchip,pins =
1527                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1528                         };
1529
1530                         sdio0_pwr: sdio0-pwr {
1531                                 rockchip,pins =
1532                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1533                         };
1534
1535                         sdio0_bkpwr: sdio0-bkpwr {
1536                                 rockchip,pins =
1537                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1538                         };
1539
1540                         sdio0_wp: sdio0-wp {
1541                                 rockchip,pins =
1542                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1543                         };
1544
1545                         sdio0_int: sdio0-int {
1546                                 rockchip,pins =
1547                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1548                         };
1549                 };
1550
1551                 sdmmc {
1552                         sdmmc_bus1: sdmmc-bus1 {
1553                                 rockchip,pins =
1554                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1555                         };
1556
1557                         sdmmc_bus4: sdmmc-bus4 {
1558                                 rockchip,pins =
1559                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1560                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1561                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1562                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1563                         };
1564
1565                         sdmmc_clk: sdmmc-clk {
1566                                 rockchip,pins =
1567                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1568                         };
1569
1570                         sdmmc_cmd: sdmmc-cmd {
1571                                 rockchip,pins =
1572                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1573                         };
1574
1575                         sdmmc_cd: sdmcc-cd {
1576                                 rockchip,pins =
1577                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1578                         };
1579
1580                         sdmmc_wp: sdmmc-wp {
1581                                 rockchip,pins =
1582                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1583                         };
1584                 };
1585
1586                 spdif {
1587                         spdif_bus: spdif-bus {
1588                                 rockchip,pins =
1589                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1590                         };
1591                 };
1592
1593                 spi0 {
1594                         spi0_clk: spi0-clk {
1595                                 rockchip,pins =
1596                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1597                         };
1598                         spi0_cs0: spi0-cs0 {
1599                                 rockchip,pins =
1600                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1601                         };
1602                         spi0_cs1: spi0-cs1 {
1603                                 rockchip,pins =
1604                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1605                         };
1606                         spi0_tx: spi0-tx {
1607                                 rockchip,pins =
1608                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1609                         };
1610                         spi0_rx: spi0-rx {
1611                                 rockchip,pins =
1612                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1613                         };
1614                 };
1615
1616                 spi1 {
1617                         spi1_clk: spi1-clk {
1618                                 rockchip,pins =
1619                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1620                         };
1621                         spi1_cs0: spi1-cs0 {
1622                                 rockchip,pins =
1623                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1624                         };
1625                         spi1_rx: spi1-rx {
1626                                 rockchip,pins =
1627                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1628                         };
1629                         spi1_tx: spi1-tx {
1630                                 rockchip,pins =
1631                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1632                         };
1633                 };
1634
1635                 spi2 {
1636                         spi2_clk: spi2-clk {
1637                                 rockchip,pins =
1638                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1639                         };
1640                         spi2_cs0: spi2-cs0 {
1641                                 rockchip,pins =
1642                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1643                         };
1644                         spi2_rx: spi2-rx {
1645                                 rockchip,pins =
1646                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1647                         };
1648                         spi2_tx: spi2-tx {
1649                                 rockchip,pins =
1650                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1651                         };
1652                 };
1653
1654                 spi3 {
1655                         spi3_clk: spi3-clk {
1656                                 rockchip,pins =
1657                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1658                         };
1659                         spi3_cs0: spi3-cs0 {
1660                                 rockchip,pins =
1661                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1662                         };
1663                         spi3_rx: spi3-rx {
1664                                 rockchip,pins =
1665                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1666                         };
1667                         spi3_tx: spi3-tx {
1668                                 rockchip,pins =
1669                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1670                         };
1671                 };
1672
1673                 spi4 {
1674                         spi4_clk: spi4-clk {
1675                                 rockchip,pins =
1676                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1677                         };
1678                         spi4_cs0: spi4-cs0 {
1679                                 rockchip,pins =
1680                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1681                         };
1682                         spi4_rx: spi4-rx {
1683                                 rockchip,pins =
1684                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1685                         };
1686                         spi4_tx: spi4-tx {
1687                                 rockchip,pins =
1688                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1689                         };
1690                 };
1691
1692                 spi5 {
1693                         spi5_clk: spi5-clk {
1694                                 rockchip,pins =
1695                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1696                         };
1697                         spi5_cs0: spi5-cs0 {
1698                                 rockchip,pins =
1699                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1700                         };
1701                         spi5_rx: spi5-rx {
1702                                 rockchip,pins =
1703                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1704                         };
1705                         spi5_tx: spi5-tx {
1706                                 rockchip,pins =
1707                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1708                         };
1709                 };
1710
1711                 tsadc {
1712                         otp_gpio: otp-gpio {
1713                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1714                         };
1715
1716                         otp_out: otp-out {
1717                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1718                         };
1719                 };
1720
1721                 uart0 {
1722                         uart0_xfer: uart0-xfer {
1723                                 rockchip,pins =
1724                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1725                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1726                         };
1727
1728                         uart0_cts: uart0-cts {
1729                                 rockchip,pins =
1730                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1731                         };
1732
1733                         uart0_rts: uart0-rts {
1734                                 rockchip,pins =
1735                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1736                         };
1737                 };
1738
1739                 uart1 {
1740                         uart1_xfer: uart1-xfer {
1741                                 rockchip,pins =
1742                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1743                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1744                         };
1745                 };
1746
1747                 uart2a {
1748                         uart2a_xfer: uart2a-xfer {
1749                                 rockchip,pins =
1750                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1751                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1752                         };
1753                 };
1754
1755                 uart2b {
1756                         uart2b_xfer: uart2b-xfer {
1757                                 rockchip,pins =
1758                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1759                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1760                         };
1761                 };
1762
1763                 uart2c {
1764                         uart2c_xfer: uart2c-xfer {
1765                                 rockchip,pins =
1766                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1767                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1768                         };
1769                 };
1770
1771                 uart3 {
1772                         uart3_xfer: uart3-xfer {
1773                                 rockchip,pins =
1774                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1775                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1776                         };
1777
1778                         uart3_cts: uart3-cts {
1779                                 rockchip,pins =
1780                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1781                         };
1782
1783                         uart3_rts: uart3-rts {
1784                                 rockchip,pins =
1785                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1786                         };
1787                 };
1788
1789                 uart4 {
1790                         uart4_xfer: uart4-xfer {
1791                                 rockchip,pins =
1792                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1793                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1794                         };
1795                 };
1796
1797                 uarthdcp {
1798                         uarthdcp_xfer: uarthdcp-xfer {
1799                                 rockchip,pins =
1800                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1801                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1802                         };
1803                 };
1804
1805                 pwm0 {
1806                         pwm0_pin: pwm0-pin {
1807                                 rockchip,pins =
1808                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1809                         };
1810
1811                         vop0_pwm_pin: vop0-pwm-pin {
1812                                 rockchip,pins =
1813                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1814                         };
1815                 };
1816
1817                 pwm1 {
1818                         pwm1_pin: pwm1-pin {
1819                                 rockchip,pins =
1820                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1821                         };
1822
1823                         vop1_pwm_pin: vop1-pwm-pin {
1824                                 rockchip,pins =
1825                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1826                         };
1827                 };
1828
1829                 pwm2 {
1830                         pwm2_pin: pwm2-pin {
1831                                 rockchip,pins =
1832                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1833                         };
1834                 };
1835
1836                 pwm3a {
1837                         pwm3a_pin: pwm3a-pin {
1838                                 rockchip,pins =
1839                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1840                         };
1841                 };
1842
1843                 pwm3b {
1844                         pwm3b_pin: pwm3b-pin {
1845                                 rockchip,pins =
1846                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1847                         };
1848                 };
1849
1850                 edp {
1851                         edp_hpd: edp-hpd {
1852                                 rockchip,pins =
1853                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
1854                         };
1855                 };
1856         };
1857 };