arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <100>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <436>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp@408000000 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp@600000000 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp@816000000 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp@1008000000 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp@1200000000 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp@1416000000 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp@408000000 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp@600000000 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp@816000000 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp@1008000000 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp@1200000000 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 261         };
 262
 263         pmu_a53 {
 264                 compatible = "arm,cortex-a53-pmu";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 266         };
 267
 268         pmu_a72 {
 269                 compatible = "arm,cortex-a72-pmu";
 270                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 271         };
 272
 273         xin24m: xin24m {
 274                 compatible = "fixed-clock";
 275                 #clock-cells = <0>;
 276                 clock-frequency = <24000000>;
 277                 clock-output-names = "xin24m";
 278         };
 279
 280         amba {
 281                 compatible = "arm,amba-bus";
 282                 #address-cells = <2>;
 283                 #size-cells = <2>;
 284                 ranges;
 285
 286                 dmac_bus: dma-controller@ff6d0000 {
 287                         compatible = "arm,pl330", "arm,primecell";
 288                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 289                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 290                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 291                         #dma-cells = <1>;
 292                         clocks = <&cru ACLK_DMAC0_PERILP>;
 293                         clock-names = "apb_pclk";
 294                         peripherals-req-type-burst;
 295                 };
 296
 297                 dmac_peri: dma-controller@ff6e0000 {
 298                         compatible = "arm,pl330", "arm,primecell";
 299                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 300                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 301                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 302                         #dma-cells = <1>;
 303                         clocks = <&cru ACLK_DMAC1_PERILP>;
 304                         clock-names = "apb_pclk";
 305                         peripherals-req-type-burst;
 306                 };
 307         };
 308
 309         gmac: eth@fe300000 {
 310                 compatible = "rockchip,rk3399-gmac";
 311                 reg = <0x0 0xfe300000 0x0 0x10000>;
 312                 rockchip,grf = <&grf>;
 313                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 314                 interrupt-names = "macirq";
 315                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 316                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 317                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 318                          <&cru PCLK_GMAC>;
 319                 clock-names = "stmmaceth", "mac_clk_rx",
 320                               "mac_clk_tx", "clk_mac_ref",
 321                               "clk_mac_refout", "aclk_mac",
 322                               "pclk_mac";
 323                 resets = <&cru SRST_A_GMAC>;
 324                 reset-names = "stmmaceth";
 325                 status = "disabled";
 326         };
 327
 328         emmc_phy: phy {
 329                 compatible = "rockchip,rk3399-emmc-phy";
 330                 reg-offset = <0xf780>;
 331                 #phy-cells = <0>;
 332                 rockchip,grf = <&grf>;
 333                 ctrl-base = <0xfe330000>;
 334                 status = "disabled";
 335         };
 336
 337         sdio0: dwmmc@fe310000 {
 338                 compatible = "rockchip,rk3399-dw-mshc",
 339                              "rockchip,rk3288-dw-mshc";
 340                 reg = <0x0 0xfe310000 0x0 0x4000>;
 341                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 342                 clock-freq-min-max = <400000 150000000>;
 343                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 344                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 345                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 346                 fifo-depth = <0x100>;
 347                 status = "disabled";
 348         };
 349
 350         sdmmc: dwmmc@fe320000 {
 351                 compatible = "rockchip,rk3399-dw-mshc",
 352                              "rockchip,rk3288-dw-mshc";
 353                 reg = <0x0 0xfe320000 0x0 0x4000>;
 354                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 355                 clock-freq-min-max = <400000 150000000>;
 356                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 357                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 358                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 359                 fifo-depth = <0x100>;
 360                 status = "disabled";
 361         };
 362
 363         sdhci: sdhci@fe330000 {
 364                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 365                 reg = <0x0 0xfe330000 0x0 0x10000>;
 366                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 367                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 368                 clock-names = "clk_xin", "clk_ahb";
 369                 assigned-clocks = <&cru SCLK_EMMC>;
 370                 assigned-clock-parents = <&cru PLL_CPLL>;
 371                 assigned-clock-rates = <200000000>;
 372                 phys = <&emmc_phy>;
 373                 phy-names = "phy_arasan";
 374                 status = "disabled";
 375         };
 376
 377         usb_host0_ehci: usb@fe380000 {
 378                 compatible = "generic-ehci";
 379                 reg = <0x0 0xfe380000 0x0 0x20000>;
 380                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 381                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 382                          <&cru SCLK_USBPHY0_480M_SRC>;
 383                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 384                 phys = <&u2phy0_host>;
 385                 phy-names = "usb";
 386                 status = "disabled";
 387         };
 388
 389         usb_host0_ohci: usb@fe3a0000 {
 390                 compatible = "generic-ohci";
 391                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 392                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 393                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 394                          <&cru SCLK_USBPHY0_480M_SRC>;
 395                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 396                 phys = <&u2phy0_host>;
 397                 phy-names = "usb";
 398                 status = "disabled";
 399         };
 400
 401         usb_host1_ehci: usb@fe3c0000 {
 402                 compatible = "generic-ehci";
 403                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 404                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 405                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 406                          <&cru SCLK_USBPHY1_480M_SRC>;
 407                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 408                 phys = <&u2phy1_host>;
 409                 phy-names = "usb";
 410                 status = "disabled";
 411         };
 412
 413         usb_host1_ohci: usb@fe3e0000 {
 414                 compatible = "generic-ohci";
 415                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 416                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 417                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 418                          <&cru SCLK_USBPHY1_480M_SRC>;
 419                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 420                 phys = <&u2phy1_host>;
 421                 phy-names = "usb";
 422                 status = "disabled";
 423         };
 424
 425         usbdrd3_0: usb@fe800000 {
 426                 compatible = "rockchip,dwc3";
 427                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 428                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 429                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 430                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 431                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 432                               "aclk_usb3", "aclk_usb3_grf";
 433                 #address-cells = <2>;
 434                 #size-cells = <2>;
 435                 ranges;
 436                 status = "disabled";
 437                 usbdrd_dwc3_0: dwc3@fe800000 {
 438                         compatible = "snps,dwc3";
 439                         reg = <0x0 0xfe800000 0x0 0x100000>;
 440                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 441                         dr_mode = "otg";
 442                         snps,dis_enblslpm_quirk;
 443                         snps,phyif_utmi_16_bits;
 444                         snps,dis_u2_freeclk_exists_quirk;
 445                         snps,dis_del_phy_power_chg_quirk;
 446                         snps,xhci_slow_suspend_quirk;
 447                         status = "disabled";
 448                 };
 449         };
 450
 451         usbdrd3_1: usb@fe900000 {
 452                 compatible = "rockchip,dwc3";
 453                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 454                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 455                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 456                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 457                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 458                               "aclk_usb3", "aclk_usb3_grf";
 459                 #address-cells = <2>;
 460                 #size-cells = <2>;
 461                 ranges;
 462                 status = "disabled";
 463                 usbdrd_dwc3_1: dwc3@fe900000 {
 464                         compatible = "snps,dwc3";
 465                         reg = <0x0 0xfe900000 0x0 0x100000>;
 466                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 467                         dr_mode = "otg";
 468                         snps,dis_enblslpm_quirk;
 469                         snps,phyif_utmi_16_bits;
 470                         snps,dis_u2_freeclk_exists_quirk;
 471                         snps,dis_del_phy_power_chg_quirk;
 472                         snps,xhci_slow_suspend_quirk;
 473                         status = "disabled";
 474                 };
 475         };
 476
 477         gic: interrupt-controller@fee00000 {
 478                 compatible = "arm,gic-v3";
 479                 #interrupt-cells = <4>;
 480                 #address-cells = <2>;
 481                 #size-cells = <2>;
 482                 ranges;
 483                 interrupt-controller;
 484
 485                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 486                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 487                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 488                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 489                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 490                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 491                 its: interrupt-controller@fee20000 {
 492                         compatible = "arm,gic-v3-its";
 493                         msi-controller;
 494                         reg = <0x0 0xfee20000 0x0 0x20000>;
 495                 };
 496
 497                 ppi-partitions {
 498                         part0: interrupt-partition-0 {
 499                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 500                         };
 501
 502                         part1: interrupt-partition-1 {
 503                                 affinity = <&cpu_b0 &cpu_b1>;
 504                         };
 505                 };
 506         };
 507
 508         saradc: saradc@ff100000 {
 509                 compatible = "rockchip,rk3399-saradc";
 510                 reg = <0x0 0xff100000 0x0 0x100>;
 511                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 512                 #io-channel-cells = <1>;
 513                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 514                 clock-names = "saradc", "apb_pclk";
 515                 status = "disabled";
 516         };
 517
 518         i2c0: i2c@ff3c0000 {
 519                 compatible = "rockchip,rk3399-i2c";
 520                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 521                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 522                 clock-names = "i2c", "pclk";
 523                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 524                 pinctrl-names = "default";
 525                 pinctrl-0 = <&i2c0_xfer>;
 526                 #address-cells = <1>;
 527                 #size-cells = <0>;
 528                 status = "disabled";
 529         };
 530
 531         i2c1: i2c@ff110000 {
 532                 compatible = "rockchip,rk3399-i2c";
 533                 reg = <0x0 0xff110000 0x0 0x1000>;
 534                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 535                 clock-names = "i2c", "pclk";
 536                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&i2c1_xfer>;
 539                 #address-cells = <1>;
 540                 #size-cells = <0>;
 541                 status = "disabled";
 542         };
 543
 544         i2c2: i2c@ff120000 {
 545                 compatible = "rockchip,rk3399-i2c";
 546                 reg = <0x0 0xff120000 0x0 0x1000>;
 547                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 548                 clock-names = "i2c", "pclk";
 549                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&i2c2_xfer>;
 552                 #address-cells = <1>;
 553                 #size-cells = <0>;
 554                 status = "disabled";
 555         };
 556
 557         i2c3: i2c@ff130000 {
 558                 compatible = "rockchip,rk3399-i2c";
 559                 reg = <0x0 0xff130000 0x0 0x1000>;
 560                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 561                 clock-names = "i2c", "pclk";
 562                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&i2c3_xfer>;
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567                 status = "disabled";
 568         };
 569
 570         i2c5: i2c@ff140000 {
 571                 compatible = "rockchip,rk3399-i2c";
 572                 reg = <0x0 0xff140000 0x0 0x1000>;
 573                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 574                 clock-names = "i2c", "pclk";
 575                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&i2c5_xfer>;
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 status = "disabled";
 581         };
 582
 583         i2c6: i2c@ff150000 {
 584                 compatible = "rockchip,rk3399-i2c";
 585                 reg = <0x0 0xff150000 0x0 0x1000>;
 586                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 587                 clock-names = "i2c", "pclk";
 588                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 589                 pinctrl-names = "default";
 590                 pinctrl-0 = <&i2c6_xfer>;
 591                 #address-cells = <1>;
 592                 #size-cells = <0>;
 593                 status = "disabled";
 594         };
 595
 596         i2c7: i2c@ff160000 {
 597                 compatible = "rockchip,rk3399-i2c";
 598                 reg = <0x0 0xff160000 0x0 0x1000>;
 599                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 600                 clock-names = "i2c", "pclk";
 601                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 602                 pinctrl-names = "default";
 603                 pinctrl-0 = <&i2c7_xfer>;
 604                 #address-cells = <1>;
 605                 #size-cells = <0>;
 606                 status = "disabled";
 607         };
 608
 609         uart0: serial@ff180000 {
 610                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 611                 reg = <0x0 0xff180000 0x0 0x100>;
 612                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 613                 clock-names = "baudclk", "apb_pclk";
 614                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 615                 reg-shift = <2>;
 616                 reg-io-width = <4>;
 617                 pinctrl-names = "default";
 618                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 619                 status = "disabled";
 620         };
 621
 622         uart1: serial@ff190000 {
 623                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 624                 reg = <0x0 0xff190000 0x0 0x100>;
 625                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 626                 clock-names = "baudclk", "apb_pclk";
 627                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 628                 reg-shift = <2>;
 629                 reg-io-width = <4>;
 630                 pinctrl-names = "default";
 631                 pinctrl-0 = <&uart1_xfer>;
 632                 status = "disabled";
 633         };
 634
 635         uart2: serial@ff1a0000 {
 636                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 637                 reg = <0x0 0xff1a0000 0x0 0x100>;
 638                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 639                 clock-names = "baudclk", "apb_pclk";
 640                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 641                 reg-shift = <2>;
 642                 reg-io-width = <4>;
 643                 pinctrl-names = "default";
 644                 pinctrl-0 = <&uart2c_xfer>;
 645                 status = "disabled";
 646         };
 647
 648         uart3: serial@ff1b0000 {
 649                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 650                 reg = <0x0 0xff1b0000 0x0 0x100>;
 651                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 652                 clock-names = "baudclk", "apb_pclk";
 653                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 654                 reg-shift = <2>;
 655                 reg-io-width = <4>;
 656                 pinctrl-names = "default";
 657                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 658                 status = "disabled";
 659         };
 660
 661         spi0: spi@ff1c0000 {
 662                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 663                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 664                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 665                 clock-names = "spiclk", "apb_pclk";
 666                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 667                 pinctrl-names = "default";
 668                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 669                 #address-cells = <1>;
 670                 #size-cells = <0>;
 671                 status = "disabled";
 672         };
 673
 674         spi1: spi@ff1d0000 {
 675                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 676                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 677                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 678                 clock-names = "spiclk", "apb_pclk";
 679                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 680                 pinctrl-names = "default";
 681                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 682                 #address-cells = <1>;
 683                 #size-cells = <0>;
 684                 status = "disabled";
 685         };
 686
 687         spi2: spi@ff1e0000 {
 688                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 689                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 690                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 691                 clock-names = "spiclk", "apb_pclk";
 692                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 693                 pinctrl-names = "default";
 694                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 695                 #address-cells = <1>;
 696                 #size-cells = <0>;
 697                 status = "disabled";
 698         };
 699
 700         spi4: spi@ff1f0000 {
 701                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 702                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 703                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 704                 clock-names = "spiclk", "apb_pclk";
 705                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 706                 pinctrl-names = "default";
 707                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 708                 #address-cells = <1>;
 709                 #size-cells = <0>;
 710                 status = "disabled";
 711         };
 712
 713         spi5: spi@ff200000 {
 714                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 715                 reg = <0x0 0xff200000 0x0 0x1000>;
 716                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 717                 clock-names = "spiclk", "apb_pclk";
 718                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 719                 pinctrl-names = "default";
 720                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 721                 #address-cells = <1>;
 722                 #size-cells = <0>;
 723                 status = "disabled";
 724         };
 725
 726         thermal-zones {
 727                 soc_thermal: soc-thermal {
 728                         polling-delay-passive = <20>; /* milliseconds */
 729                         polling-delay = <1000>; /* milliseconds */
 730                         sustainable-power = <1000>; /* milliwatts */
 731
 732                         thermal-sensors = <&tsadc 0>;
 733
 734                         trips {
 735                                 threshold: trip-point@0 {
 736                                         temperature = <70000>; /* millicelsius */
 737                                         hysteresis = <2000>; /* millicelsius */
 738                                         type = "passive";
 739                                 };
 740                                 target: trip-point@1 {
 741                                         temperature = <85000>; /* millicelsius */
 742                                         hysteresis = <2000>; /* millicelsius */
 743                                         type = "passive";
 744                                 };
 745                                 soc_crit: soc-crit {
 746                                         temperature = <95000>; /* millicelsius */
 747                                         hysteresis = <2000>; /* millicelsius */
 748                                         type = "critical";
 749                                 };
 750                         };
 751
 752                         cooling-maps {
 753                                 map0 {
 754                                         trip = <&target>;
 755                                         cooling-device =
 756                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 757                                         contribution = <4096>;
 758                                 };
 759                                 map1 {
 760                                         trip = <&target>;
 761                                         cooling-device =
 762                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 763                                         contribution = <1024>;
 764                                 };
 765                                 map2 {
 766                                         trip = <&target>;
 767                                         cooling-device =
 768                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 769                                         contribution = <4096>;
 770                                 };
 771                         };
 772                 };
 773
 774                 gpu_thermal: gpu-thermal {
 775                         polling-delay-passive = <100>; /* milliseconds */
 776                         polling-delay = <1000>; /* milliseconds */
 777
 778                         thermal-sensors = <&tsadc 1>;
 779                 };
 780         };
 781
 782         tsadc: tsadc@ff260000 {
 783                 compatible = "rockchip,rk3399-tsadc";
 784                 reg = <0x0 0xff260000 0x0 0x100>;
 785                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 786                 rockchip,grf = <&grf>;
 787                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 788                 clock-names = "tsadc", "apb_pclk";
 789                 assigned-clocks = <&cru SCLK_TSADC>;
 790                 assigned-clock-rates = <750000>;
 791                 resets = <&cru SRST_TSADC>;
 792                 reset-names = "tsadc-apb";
 793                 pinctrl-names = "init", "default", "sleep";
 794                 pinctrl-0 = <&otp_gpio>;
 795                 pinctrl-1 = <&otp_out>;
 796                 pinctrl-2 = <&otp_gpio>;
 797                 #thermal-sensor-cells = <1>;
 798                 rockchip,hw-tshut-temp = <95000>;
 799                 status = "disabled";
 800         };
 801
 802         qos_hdcp: qos@ffa90000 {
 803                 compatible = "syscon";
 804                 reg = <0x0 0xffa90000 0x0 0x20>;
 805         };
 806
 807         qos_iep: qos@ffa98000 {
 808                 compatible = "syscon";
 809                 reg = <0x0 0xffa98000 0x0 0x20>;
 810         };
 811
 812         qos_isp0_m0: qos@ffaa0000 {
 813                 compatible = "syscon";
 814                 reg = <0x0 0xffaa0000 0x0 0x20>;
 815         };
 816
 817         qos_isp0_m1: qos@ffaa0080 {
 818                 compatible = "syscon";
 819                 reg = <0x0 0xffaa0080 0x0 0x20>;
 820         };
 821
 822         qos_isp1_m0: qos@ffaa8000 {
 823                 compatible = "syscon";
 824                 reg = <0x0 0xffaa8000 0x0 0x20>;
 825         };
 826
 827         qos_isp1_m1: qos@ffaa8080 {
 828                 compatible = "syscon";
 829                 reg = <0x0 0xffaa8080 0x0 0x20>;
 830         };
 831
 832         qos_rga_r: qos@ffab0000 {
 833                 compatible = "syscon";
 834                 reg = <0x0 0xffab0000 0x0 0x20>;
 835         };
 836
 837         qos_rga_w: qos@ffab0080 {
 838                 compatible = "syscon";
 839                 reg = <0x0 0xffab0080 0x0 0x20>;
 840         };
 841
 842         qos_video_m0: qos@ffab8000 {
 843                 compatible = "syscon";
 844                 reg = <0x0 0xffab8000 0x0 0x20>;
 845         };
 846
 847         qos_video_m1_r: qos@ffac0000 {
 848                 compatible = "syscon";
 849                 reg = <0x0 0xffac0000 0x0 0x20>;
 850         };
 851
 852         qos_video_m1_w: qos@ffac0080 {
 853                 compatible = "syscon";
 854                 reg = <0x0 0xffac0080 0x0 0x20>;
 855         };
 856
 857         qos_vop_big_r: qos@ffac8000 {
 858                 compatible = "syscon";
 859                 reg = <0x0 0xffac8000 0x0 0x20>;
 860         };
 861
 862         qos_vop_big_w: qos@ffac8080 {
 863                 compatible = "syscon";
 864                 reg = <0x0 0xffac8080 0x0 0x20>;
 865         };
 866
 867         qos_vop_little: qos@ffad0000 {
 868                 compatible = "syscon";
 869                 reg = <0x0 0xffad0000 0x0 0x20>;
 870         };
 871
 872         qos_gpu: qos@ffae0000 {
 873                 compatible = "syscon";
 874                 reg = <0x0 0xffae0000 0x0 0x20>;
 875         };
 876
 877         pmu: power-management@ff310000 {
 878                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 879                 reg = <0x0 0xff310000 0x0 0x1000>;
 880
 881                 /*
 882                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 883                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 884                  * Some of the power domains are grouped together for every
 885                  * voltage domain.
 886                  * The detail contents as below.
 887                  */
 888                 power: power-controller {
 889                         compatible = "rockchip,rk3399-power-controller";
 890                         #power-domain-cells = <1>;
 891                         #address-cells = <1>;
 892                         #size-cells = <0>;
 893
 894                         /* These power domains are grouped by VD_CENTER */
 895                         pd_iep@RK3399_PD_IEP {
 896                                 reg = <RK3399_PD_IEP>;
 897                                 clocks = <&cru ACLK_IEP>,
 898                                          <&cru HCLK_IEP>;
 899                                 pm_qos = <&qos_iep>;
 900                         };
 901                         pd_rga@RK3399_PD_RGA {
 902                                 reg = <RK3399_PD_RGA>;
 903                                 clocks = <&cru ACLK_RGA>,
 904                                          <&cru HCLK_RGA>;
 905                                 pm_qos = <&qos_rga_r>,
 906                                          <&qos_rga_w>;
 907                         };
 908                         pd_vcodec@RK3399_PD_VCODEC {
 909                                 reg = <RK3399_PD_VCODEC>;
 910                                 clocks = <&cru ACLK_VCODEC>,
 911                                          <&cru HCLK_VCODEC>;
 912                                 pm_qos = <&qos_video_m0>;
 913                         };
 914                         pd_vdu@RK3399_PD_VDU {
 915                                 reg = <RK3399_PD_VDU>;
 916                                 clocks = <&cru ACLK_VDU>,
 917                                          <&cru HCLK_VDU>;
 918                                 pm_qos = <&qos_video_m1_r>,
 919                                          <&qos_video_m1_w>;
 920                         };
 921
 922                         /* These power domains are grouped by VD_GPU */
 923                         pd_gpu@RK3399_PD_GPU {
 924                                 reg = <RK3399_PD_GPU>;
 925                                 clocks = <&cru ACLK_GPU>;
 926                                 pm_qos = <&qos_gpu>;
 927                         };
 928
 929                         /* These power domains are grouped by VD_LOGIC */
 930                         pd_vio@RK3399_PD_VIO {
 931                                 reg = <RK3399_PD_VIO>;
 932                                 #address-cells = <1>;
 933                                 #size-cells = <0>;
 934
 935                                 pd_hdcp@RK3399_PD_HDCP {
 936                                         reg = <RK3399_PD_HDCP>;
 937                                         clocks = <&cru ACLK_HDCP>,
 938                                                  <&cru HCLK_HDCP>,
 939                                                  <&cru PCLK_HDCP>;
 940                                         pm_qos = <&qos_hdcp>;
 941                                 };
 942                                 pd_isp0@RK3399_PD_ISP0 {
 943                                         reg = <RK3399_PD_ISP0>;
 944                                         clocks = <&cru ACLK_ISP0>,
 945                                                  <&cru HCLK_ISP0>;
 946                                         pm_qos = <&qos_isp0_m0>,
 947                                                  <&qos_isp0_m1>;
 948                                 };
 949                                 pd_isp1@RK3399_PD_ISP1 {
 950                                         reg = <RK3399_PD_ISP1>;
 951                                         clocks = <&cru ACLK_ISP1>,
 952                                                  <&cru HCLK_ISP1>;
 953                                         pm_qos = <&qos_isp1_m0>,
 954                                                  <&qos_isp1_m1>;
 955                                 };
 956                                 pd_vo@RK3399_PD_VO {
 957                                         reg = <RK3399_PD_VO>;
 958                                         #address-cells = <1>;
 959                                         #size-cells = <0>;
 960
 961                                         pd_vopb@RK3399_PD_VOPB {
 962                                                 reg = <RK3399_PD_VOPB>;
 963                                                 clocks = <&cru ACLK_VOP0>,
 964                                                          <&cru HCLK_VOP0>;
 965                                                 pm_qos = <&qos_vop_big_r>,
 966                                                          <&qos_vop_big_w>;
 967                                         };
 968                                         pd_vopl@RK3399_PD_VOPL {
 969                                                 reg = <RK3399_PD_VOPL>;
 970                                                 clocks = <&cru ACLK_VOP1>,
 971                                                          <&cru HCLK_VOP1>;
 972                                                 pm_qos = <&qos_vop_little>;
 973                                         };
 974                                 };
 975                         };
 976                 };
 977         };
 978
 979         pmugrf: syscon@ff320000 {
 980                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 981                 reg = <0x0 0xff320000 0x0 0x1000>;
 982
 983                 reboot-mode {
 984                         compatible = "syscon-reboot-mode";
 985                         offset = <0x300>;
 986                         mode-normal = <BOOT_NORMAL>;
 987                         mode-recovery = <BOOT_RECOVERY>;
 988                         mode-bootloader = <BOOT_FASTBOOT>;
 989                         mode-loader = <BOOT_LOADER>;
 990                 };
 991         };
 992
 993         spi3: spi@ff350000 {
 994                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 995                 reg = <0x0 0xff350000 0x0 0x1000>;
 996                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 997                 clock-names = "spiclk", "apb_pclk";
 998                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
 999                 pinctrl-names = "default";
1000                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1001                 #address-cells = <1>;
1002                 #size-cells = <0>;
1003                 status = "disabled";
1004         };
1005
1006         uart4: serial@ff370000 {
1007                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1008                 reg = <0x0 0xff370000 0x0 0x100>;
1009                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1010                 clock-names = "baudclk", "apb_pclk";
1011                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1012                 reg-shift = <2>;
1013                 reg-io-width = <4>;
1014                 pinctrl-names = "default";
1015                 pinctrl-0 = <&uart4_xfer>;
1016                 status = "disabled";
1017         };
1018
1019         i2c4: i2c@ff3d0000 {
1020                 compatible = "rockchip,rk3399-i2c";
1021                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1022                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1023                 clock-names = "i2c", "pclk";
1024                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1025                 pinctrl-names = "default";
1026                 pinctrl-0 = <&i2c4_xfer>;
1027                 #address-cells = <1>;
1028                 #size-cells = <0>;
1029                 status = "disabled";
1030         };
1031
1032         i2c8: i2c@ff3e0000 {
1033                 compatible = "rockchip,rk3399-i2c";
1034                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1035                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1036                 clock-names = "i2c", "pclk";
1037                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1038                 pinctrl-names = "default";
1039                 pinctrl-0 = <&i2c8_xfer>;
1040                 #address-cells = <1>;
1041                 #size-cells = <0>;
1042                 status = "disabled";
1043         };
1044
1045         pcie0: pcie@f8000000 {
1046                 compatible = "rockchip,rk3399-pcie";
1047                 #address-cells = <3>;
1048                 #size-cells = <2>;
1049                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1050                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1051                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1052                               "hclk_pcie", "clk_pciephy_ref";
1053                 bus-range = <0x0 0x1>;
1054                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1055                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1056                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1057                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1058                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1059                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1060                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1061                       < 0x0 0xfd000000 0x0 0x1000000 >;
1062                 reg-name = "axi-base", "apb-base";
1063                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1064                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1065                          <&cru SRST_PCIE_PIPE>;
1066                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1067                               "mgmt-sticky-rst", "pipe-rst";
1068                 rockchip,grf = <&grf>;
1069                 pcie-conf = <0xe220>;
1070                 pcie-status = <0xe2a4>;
1071                 pcie-laneoff = <0xe214>;
1072                 msi-parent = <&its>;
1073                 #interrupt-cells = <1>;
1074                 interrupt-map-mask = <0 0 0 7>;
1075                 interrupt-map = <0 0 0 1 &pcie0 1>,
1076                                 <0 0 0 2 &pcie0 2>,
1077                                 <0 0 0 3 &pcie0 3>,
1078                                 <0 0 0 4 &pcie0 4>;
1079                 status = "disabled";
1080                 pcie_intc: interrupt-controller {
1081                         interrupt-controller;
1082                         #address-cells = <0>;
1083                         #interrupt-cells = <1>;
1084                 };
1085         };
1086
1087         pwm0: pwm@ff420000 {
1088                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1089                 reg = <0x0 0xff420000 0x0 0x10>;
1090                 #pwm-cells = <3>;
1091                 pinctrl-names = "default";
1092                 pinctrl-0 = <&pwm0_pin>;
1093                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1094                 clock-names = "pwm";
1095                 status = "disabled";
1096         };
1097
1098         pwm1: pwm@ff420010 {
1099                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1100                 reg = <0x0 0xff420010 0x0 0x10>;
1101                 #pwm-cells = <3>;
1102                 pinctrl-names = "default";
1103                 pinctrl-0 = <&pwm1_pin>;
1104                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1105                 clock-names = "pwm";
1106                 status = "disabled";
1107         };
1108
1109         pwm2: pwm@ff420020 {
1110                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1111                 reg = <0x0 0xff420020 0x0 0x10>;
1112                 #pwm-cells = <3>;
1113                 pinctrl-names = "default";
1114                 pinctrl-0 = <&pwm2_pin>;
1115                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1116                 clock-names = "pwm";
1117                 status = "disabled";
1118         };
1119
1120         pwm3: pwm@ff420030 {
1121                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1122                 reg = <0x0 0xff420030 0x0 0x10>;
1123                 #pwm-cells = <3>;
1124                 pinctrl-names = "default";
1125                 pinctrl-0 = <&pwm3a_pin>;
1126                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1127                 clock-names = "pwm";
1128                 status = "disabled";
1129         };
1130
1131         rga: rga@ff680000 {
1132                 compatible = "rockchip,rk3399-rga";
1133                 reg = <0x0 0xff680000 0x0 0x10000>;
1134                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1135                 interrupt-names = "rga";
1136                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1137                 clock-names = "aclk", "hclk", "sclk";
1138                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1139                 reset-names = "core", "axi", "ahb";
1140                 status = "disabled";
1141         };
1142
1143         pmucru: pmu-clock-controller@ff750000 {
1144                 compatible = "rockchip,rk3399-pmucru";
1145                 reg = <0x0 0xff750000 0x0 0x1000>;
1146                 #clock-cells = <1>;
1147                 #reset-cells = <1>;
1148                 assigned-clocks = <&pmucru PLL_PPLL>;
1149                 assigned-clock-rates = <676000000>;
1150         };
1151
1152         cru: clock-controller@ff760000 {
1153                 compatible = "rockchip,rk3399-cru";
1154                 reg = <0x0 0xff760000 0x0 0x1000>;
1155                 #clock-cells = <1>;
1156                 #reset-cells = <1>;
1157                 assigned-clocks =
1158                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1159                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1160                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1161                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1162                         <&cru PLL_NPLL>,
1163                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1164                         <&cru PCLK_PERIHP>,
1165                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1166                         <&cru PCLK_PERILP0>,
1167                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1168                 assigned-clock-rates =
1169                          <400000000>,  <200000000>,
1170                          <400000000>,  <200000000>,
1171                          <816000000>, <816000000>,
1172                          <594000000>,  <800000000>,
1173                         <1000000000>,
1174                          <150000000>,   <75000000>,
1175                           <37500000>,
1176                          <100000000>,  <100000000>,
1177                           <50000000>,
1178                          <100000000>,   <50000000>;
1179         };
1180
1181         grf: syscon@ff770000 {
1182                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1183                 reg = <0x0 0xff770000 0x0 0x10000>;
1184                 #address-cells = <1>;
1185                 #size-cells = <1>;
1186
1187                 u2phy0: usb2-phy@e450 {
1188                         compatible = "rockchip,rk3399-usb2phy";
1189                         reg = <0xe450 0x10>;
1190                         clocks = <&cru SCLK_USB2PHY0_REF>;
1191                         clock-names = "phyclk";
1192                         #clock-cells = <0>;
1193                         clock-output-names = "clk_usbphy0_480m";
1194                         status = "disabled";
1195
1196                         u2phy0_otg: otg-port {
1197                                 #phy-cells = <0>;
1198                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1199                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1200                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1201                                 interrupt-names = "otg-bvalid", "otg-id",
1202                                                   "linestate";
1203                                 status = "disabled";
1204                         };
1205
1206                         u2phy0_host: host-port {
1207                                 #phy-cells = <0>;
1208                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1209                                 interrupt-names = "linestate";
1210                                 status = "disabled";
1211                         };
1212                 };
1213
1214                 u2phy1: usb2-phy@e460 {
1215                         compatible = "rockchip,rk3399-usb2phy";
1216                         reg = <0xe460 0x10>;
1217                         clocks = <&cru SCLK_USB2PHY1_REF>;
1218                         clock-names = "phyclk";
1219                         #clock-cells = <0>;
1220                         clock-output-names = "clk_usbphy1_480m";
1221                         status = "disabled";
1222
1223                         u2phy1_host: host-port {
1224                                 #phy-cells = <0>;
1225                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1226                                 interrupt-names = "linestate";
1227                                 status = "disabled";
1228                         };
1229                 };
1230         };
1231
1232         tcphy0: phy@ff7c0000 {
1233                 compatible = "rockchip,rk3399-typec-phy";
1234                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1235                 rockchip,grf = <&grf>;
1236                 #phy-cells = <0>;
1237                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1238                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1239                 clock-names = "tcpdcore", "tcpdphy-ref";
1240                 resets = <&cru SRST_UPHY0>,
1241                          <&cru SRST_UPHY0_PIPE_L00>,
1242                          <&cru SRST_P_UPHY0_TCPHY>;
1243                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1244                 rockchip,typec-conn-dir = <0xe580 0 16>;
1245                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1246                 rockchip,external-psm = <0xe588 14 30>;
1247                 rockchip,pipe-status = <0xe5c0 0 0>;
1248                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1249                 status = "disabled";
1250         };
1251
1252         tcphy1: phy@ff800000 {
1253                 compatible = "rockchip,rk3399-typec-phy";
1254                 reg = <0x0 0xff800000 0x0 0x40000>;
1255                 rockchip,grf = <&grf>;
1256                 #phy-cells = <0>;
1257                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1258                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1259                 clock-names = "tcpdcore", "tcpdphy-ref";
1260                 resets = <&cru SRST_UPHY1>,
1261                          <&cru SRST_UPHY1_PIPE_L00>,
1262                          <&cru SRST_P_UPHY1_TCPHY>;
1263                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1264                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1265                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1266                 rockchip,external-psm = <0xe594 14 30>;
1267                 rockchip,pipe-status = <0xe5c0 16 16>;
1268                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1269                 status = "disabled";
1270         };
1271
1272         watchdog@ff840000 {
1273                 compatible = "snps,dw-wdt";
1274                 reg = <0x0 0xff840000 0x0 0x100>;
1275                 clocks = <&cru PCLK_WDT>;
1276                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1277         };
1278
1279         rktimer: rktimer@ff850000 {
1280                 compatible = "rockchip,rk3399-timer";
1281                 reg = <0x0 0xff850000 0x0 0x1000>;
1282                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1283                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1284                 clock-names = "pclk", "timer";
1285         };
1286
1287         spdif: spdif@ff870000 {
1288                 compatible = "rockchip,rk3399-spdif";
1289                 reg = <0x0 0xff870000 0x0 0x1000>;
1290                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1291                 dmas = <&dmac_bus 7>;
1292                 dma-names = "tx";
1293                 clock-names = "mclk", "hclk";
1294                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1295                 pinctrl-names = "default";
1296                 pinctrl-0 = <&spdif_bus>;
1297                 status = "disabled";
1298         };
1299
1300         i2s0: i2s@ff880000 {
1301                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1302                 reg = <0x0 0xff880000 0x0 0x1000>;
1303                 rockchip,grf = <&grf>;
1304                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1305                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1306                 dma-names = "tx", "rx";
1307                 clock-names = "i2s_clk", "i2s_hclk";
1308                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1309                 pinctrl-names = "default";
1310                 pinctrl-0 = <&i2s0_8ch_bus>;
1311                 status = "disabled";
1312         };
1313
1314         i2s1: i2s@ff890000 {
1315                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1316                 reg = <0x0 0xff890000 0x0 0x1000>;
1317                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1318                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1319                 dma-names = "tx", "rx";
1320                 clock-names = "i2s_clk", "i2s_hclk";
1321                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1322                 pinctrl-names = "default";
1323                 pinctrl-0 = <&i2s1_2ch_bus>;
1324                 status = "disabled";
1325         };
1326
1327         i2s2: i2s@ff8a0000 {
1328                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1329                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1330                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1331                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1332                 dma-names = "tx", "rx";
1333                 clock-names = "i2s_clk", "i2s_hclk";
1334                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1335                 status = "disabled";
1336         };
1337
1338         gpu: gpu@ff9a0000 {
1339                 compatible = "arm,malit860",
1340                              "arm,malit86x",
1341                              "arm,malit8xx",
1342                              "arm,mali-midgard";
1343
1344                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1345
1346                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1347                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1348                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1349                 interrupt-names = "GPU", "JOB", "MMU";
1350
1351                 clocks = <&cru ACLK_GPU>;
1352                 clock-names = "clk_mali";
1353                 #cooling-cells = <2>; /* min followed by max */
1354                 operating-points-v2 = <&gpu_opp_table>;
1355                 power-domains = <&power RK3399_PD_GPU>;
1356                 power-off-delay-ms = <200>;
1357                 status = "disabled";
1358
1359                 gpu_power_model: power_model {
1360                         compatible = "arm,mali-simple-power-model";
1361                         voltage = <900>;
1362                         frequency = <500>;
1363                         static-power = <300>;
1364                         dynamic-power = <396>;
1365                         ts = <32000 4700 (-80) 2>;
1366                         thermal-zone = "gpu-thermal";
1367                 };
1368         };
1369
1370         gpu_opp_table: gpu_opp_table {
1371                 compatible = "operating-points-v2";
1372                 opp-shared;
1373
1374                 opp@200000000 {
1375                         opp-hz = /bits/ 64 <200000000>;
1376                         opp-microvolt = <900000>;
1377                 };
1378                 opp@300000000 {
1379                         opp-hz = /bits/ 64 <300000000>;
1380                         opp-microvolt = <900000>;
1381                 };
1382                 opp@400000000 {
1383                         opp-hz = /bits/ 64 <400000000>;
1384                         opp-microvolt = <900000>;
1385                 };
1386
1387         };
1388
1389         vopl: vop@ff8f0000 {
1390                 compatible = "rockchip,rk3399-vop-lit";
1391                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1392                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1393                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1394                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1395                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1396                 reset-names = "axi", "ahb", "dclk";
1397                 power-domains = <&power RK3399_PD_VOPL>;
1398                 iommus = <&vopl_mmu>;
1399                 status = "disabled";
1400
1401                 vopl_out: port {
1402                         #address-cells = <1>;
1403                         #size-cells = <0>;
1404
1405                         vopl_out_mipi: endpoint@0 {
1406                                 reg = <0>;
1407                                 remote-endpoint = <&mipi_in_vopl>;
1408                         };
1409
1410                         vopl_out_edp: endpoint@1 {
1411                                 reg = <1>;
1412                                 remote-endpoint = <&edp_in_vopl>;
1413                         };
1414
1415                         vopl_out_hdmi: endpoint@2 {
1416                                 reg = <2>;
1417                                 remote-endpoint = <&hdmi_in_vopl>;
1418                         };
1419                 };
1420         };
1421
1422         vopl_mmu: iommu@ff8f3f00 {
1423                 compatible = "rockchip,iommu";
1424                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1425                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1426                 interrupt-names = "vopl_mmu";
1427                 #iommu-cells = <0>;
1428                 status = "disabled";
1429         };
1430
1431         vopb: vop@ff900000 {
1432                 compatible = "rockchip,rk3399-vop-big";
1433                 reg = <0x0 0xff900000 0x0 0x3efc>;
1434                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1435                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1436                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1437                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1438                 reset-names = "axi", "ahb", "dclk";
1439                 power-domains = <&power RK3399_PD_VOPB>;
1440                 iommus = <&vopb_mmu>;
1441                 status = "disabled";
1442
1443                 vopb_out: port {
1444                         #address-cells = <1>;
1445                         #size-cells = <0>;
1446
1447                         vopb_out_edp: endpoint@0 {
1448                                 reg = <0>;
1449                                 remote-endpoint = <&edp_in_vopb>;
1450                         };
1451
1452                         vopb_out_mipi: endpoint@1 {
1453                                 reg = <1>;
1454                                 remote-endpoint = <&mipi_in_vopb>;
1455                         };
1456
1457                         vopb_out_hdmi: endpoint@2 {
1458                                 reg = <2>;
1459                                 remote-endpoint = <&hdmi_in_vopb>;
1460                         };
1461                 };
1462         };
1463
1464         vopb_mmu: iommu@ff903f00 {
1465                 compatible = "rockchip,iommu";
1466                 reg = <0x0 0xff903f00 0x0 0x100>;
1467                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1468                 interrupt-names = "vopb_mmu";
1469                 #iommu-cells = <0>;
1470                 status = "disabled";
1471         };
1472
1473         hdmi: hdmi@ff940000 {
1474                 compatible = "rockchip,rk3399-dw-hdmi";
1475                 reg = <0x0 0xff940000 0x0 0x20000>;
1476                 reg-io-width = <4>;
1477                 rockchip,grf = <&grf>;
1478                 power-domains = <&power RK3399_PD_HDCP>;
1479                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1480                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1481                 clock-names = "iahb", "isfr", "vpll", "grf";
1482                 status = "disabled";
1483
1484                 ports {
1485                         hdmi_in: port {
1486                                 #address-cells = <1>;
1487                                 #size-cells = <0>;
1488                                 hdmi_in_vopb: endpoint@0 {
1489                                         reg = <0>;
1490                                         remote-endpoint = <&vopb_out_hdmi>;
1491                                 };
1492                                 hdmi_in_vopl: endpoint@1 {
1493                                         reg = <1>;
1494                                         remote-endpoint = <&vopl_out_hdmi>;
1495                                 };
1496                         };
1497                 };
1498         };
1499
1500         mipi_dsi: mipi@ff960000 {
1501                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1502                 reg = <0x0 0xff960000 0x0 0x8000>;
1503                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1504                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1505                          <&cru SCLK_DPHY_TX0_CFG>;
1506                 clock-names = "ref", "pclk", "phy_cfg";
1507                 power-domains = <&power RK3399_PD_VIO>;
1508                 rockchip,grf = <&grf>;
1509                 #address-cells = <1>;
1510                 #size-cells = <0>;
1511                 status = "disabled";
1512
1513                 ports {
1514                         #address-cells = <1>;
1515                         #size-cells = <0>;
1516                         reg = <1>;
1517
1518                         mipi_in: port {
1519                                 #address-cells = <1>;
1520                                 #size-cells = <0>;
1521
1522                                 mipi_in_vopb: endpoint@0 {
1523                                         reg = <0>;
1524                                         remote-endpoint = <&vopb_out_mipi>;
1525                                 };
1526                                 mipi_in_vopl: endpoint@1 {
1527                                         reg = <1>;
1528                                         remote-endpoint = <&vopl_out_mipi>;
1529                                 };
1530                         };
1531                 };
1532         };
1533
1534         edp: edp@ff970000 {
1535                 compatible = "rockchip,rk3399-edp";
1536                 reg = <0x0 0xff970000 0x0 0x8000>;
1537                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1538                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1539                 clock-names = "dp", "pclk";
1540                 resets = <&cru SRST_P_EDP_CTRL>;
1541                 reset-names = "dp";
1542                 rockchip,grf = <&grf>;
1543                 status = "disabled";
1544                 pinctrl-names = "default";
1545                 pinctrl-0 = <&edp_hpd>;
1546
1547                 ports {
1548                         #address-cells = <1>;
1549                         #size-cells = <0>;
1550
1551                         edp_in: port@0 {
1552                                 reg = <0>;
1553                                 #address-cells = <1>;
1554                                 #size-cells = <0>;
1555
1556                                 edp_in_vopb: endpoint@0 {
1557                                         reg = <0>;
1558                                         remote-endpoint = <&vopb_out_edp>;
1559                                 };
1560
1561                                 edp_in_vopl: endpoint@1 {
1562                                         reg = <1>;
1563                                         remote-endpoint = <&vopl_out_edp>;
1564                                 };
1565                         };
1566                 };
1567         };
1568
1569         display_subsystem: display-subsystem {
1570                 compatible = "rockchip,display-subsystem";
1571                 ports = <&vopl_out>, <&vopb_out>;
1572                 status = "disabled";
1573         };
1574
1575         pinctrl: pinctrl {
1576                 compatible = "rockchip,rk3399-pinctrl";
1577                 rockchip,grf = <&grf>;
1578                 rockchip,pmu = <&pmugrf>;
1579                 #address-cells = <0x2>;
1580                 #size-cells = <0x2>;
1581                 ranges;
1582
1583                 gpio0: gpio0@ff720000 {
1584                         compatible = "rockchip,gpio-bank";
1585                         reg = <0x0 0xff720000 0x0 0x100>;
1586                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1587                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1588
1589                         gpio-controller;
1590                         #gpio-cells = <0x2>;
1591
1592                         interrupt-controller;
1593                         #interrupt-cells = <0x2>;
1594                 };
1595
1596                 gpio1: gpio1@ff730000 {
1597                         compatible = "rockchip,gpio-bank";
1598                         reg = <0x0 0xff730000 0x0 0x100>;
1599                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1600                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1601
1602                         gpio-controller;
1603                         #gpio-cells = <0x2>;
1604
1605                         interrupt-controller;
1606                         #interrupt-cells = <0x2>;
1607                 };
1608
1609                 gpio2: gpio2@ff780000 {
1610                         compatible = "rockchip,gpio-bank";
1611                         reg = <0x0 0xff780000 0x0 0x100>;
1612                         clocks = <&cru PCLK_GPIO2>;
1613                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1614
1615                         gpio-controller;
1616                         #gpio-cells = <0x2>;
1617
1618                         interrupt-controller;
1619                         #interrupt-cells = <0x2>;
1620                 };
1621
1622                 gpio3: gpio3@ff788000 {
1623                         compatible = "rockchip,gpio-bank";
1624                         reg = <0x0 0xff788000 0x0 0x100>;
1625                         clocks = <&cru PCLK_GPIO3>;
1626                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1627
1628                         gpio-controller;
1629                         #gpio-cells = <0x2>;
1630
1631                         interrupt-controller;
1632                         #interrupt-cells = <0x2>;
1633                 };
1634
1635                 gpio4: gpio4@ff790000 {
1636                         compatible = "rockchip,gpio-bank";
1637                         reg = <0x0 0xff790000 0x0 0x100>;
1638                         clocks = <&cru PCLK_GPIO4>;
1639                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1640
1641                         gpio-controller;
1642                         #gpio-cells = <0x2>;
1643
1644                         interrupt-controller;
1645                         #interrupt-cells = <0x2>;
1646                 };
1647
1648                 pcfg_pull_up: pcfg-pull-up {
1649                         bias-pull-up;
1650                 };
1651
1652                 pcfg_pull_down: pcfg-pull-down {
1653                         bias-pull-down;
1654                 };
1655
1656                 pcfg_pull_none: pcfg-pull-none {
1657                         bias-disable;
1658                 };
1659
1660                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1661                         bias-disable;
1662                         drive-strength = <12>;
1663                 };
1664
1665                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1666                         bias-pull-up;
1667                         drive-strength = <8>;
1668                 };
1669
1670                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1671                         bias-pull-down;
1672                         drive-strength = <4>;
1673                 };
1674
1675                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1676                         bias-pull-up;
1677                         drive-strength = <2>;
1678                 };
1679
1680                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1681                         bias-pull-down;
1682                         drive-strength = <12>;
1683                 };
1684
1685                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1686                         bias-disable;
1687                         drive-strength = <13>;
1688                 };
1689
1690                 emmc {
1691                         emmc_pwr: emmc-pwr {
1692                                 rockchip,pins =
1693                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1694                         };
1695                 };
1696
1697                 gmac {
1698                         rgmii_pins: rgmii-pins {
1699                                 rockchip,pins =
1700                                         /* mac_txclk */
1701                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1702                                         /* mac_rxclk */
1703                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1704                                         /* mac_mdio */
1705                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1706                                         /* mac_txen */
1707                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1708                                         /* mac_clk */
1709                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1710                                         /* mac_rxdv */
1711                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1712                                         /* mac_mdc */
1713                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1714                                         /* mac_rxd1 */
1715                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1716                                         /* mac_rxd0 */
1717                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1718                                         /* mac_txd1 */
1719                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1720                                         /* mac_txd0 */
1721                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1722                                         /* mac_rxd3 */
1723                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1724                                         /* mac_rxd2 */
1725                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1726                                         /* mac_txd3 */
1727                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1728                                         /* mac_txd2 */
1729                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1730                         };
1731
1732                         rmii_pins: rmii-pins {
1733                                 rockchip,pins =
1734                                         /* mac_mdio */
1735                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1736                                         /* mac_txen */
1737                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1738                                         /* mac_clk */
1739                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1740                                         /* mac_rxer */
1741                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1742                                         /* mac_rxdv */
1743                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1744                                         /* mac_mdc */
1745                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1746                                         /* mac_rxd1 */
1747                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1748                                         /* mac_rxd0 */
1749                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1750                                         /* mac_txd1 */
1751                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1752                                         /* mac_txd0 */
1753                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1754                         };
1755                 };
1756
1757                 i2c0 {
1758                         i2c0_xfer: i2c0-xfer {
1759                                 rockchip,pins =
1760                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1761                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1762                         };
1763                 };
1764
1765                 i2c1 {
1766                         i2c1_xfer: i2c1-xfer {
1767                                 rockchip,pins =
1768                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1769                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1770                         };
1771                 };
1772
1773                 i2c2 {
1774                         i2c2_xfer: i2c2-xfer {
1775                                 rockchip,pins =
1776                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1777                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1778                         };
1779                 };
1780
1781                 i2c3 {
1782                         i2c3_xfer: i2c3-xfer {
1783                                 rockchip,pins =
1784                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1785                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1786                         };
1787
1788                         i2c3_gpio: i2c3_gpio {
1789                                 rockchip,pins =
1790                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1791                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1792                         };
1793
1794                 };
1795
1796                 i2c4 {
1797                         i2c4_xfer: i2c4-xfer {
1798                                 rockchip,pins =
1799                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1800                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1801                         };
1802                 };
1803
1804                 i2c5 {
1805                         i2c5_xfer: i2c5-xfer {
1806                                 rockchip,pins =
1807                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1808                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1809                         };
1810                 };
1811
1812                 i2c6 {
1813                         i2c6_xfer: i2c6-xfer {
1814                                 rockchip,pins =
1815                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1816                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1817                         };
1818                 };
1819
1820                 i2c7 {
1821                         i2c7_xfer: i2c7-xfer {
1822                                 rockchip,pins =
1823                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1824                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1825                         };
1826                 };
1827
1828                 i2c8 {
1829                         i2c8_xfer: i2c8-xfer {
1830                                 rockchip,pins =
1831                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1832                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1833                         };
1834                 };
1835
1836                 i2s0 {
1837                         i2s0_8ch_bus: i2s0-8ch-bus {
1838                                 rockchip,pins =
1839                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1840                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1841                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1842                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1843                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1844                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1845                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1846                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1847                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1848                         };
1849                 };
1850
1851                 i2s1 {
1852                         i2s1_2ch_bus: i2s1-2ch-bus {
1853                                 rockchip,pins =
1854                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1855                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1856                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1857                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1858                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1859                         };
1860                 };
1861
1862                 sdio0 {
1863                         sdio0_bus1: sdio0-bus1 {
1864                                 rockchip,pins =
1865                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1866                         };
1867
1868                         sdio0_bus4: sdio0-bus4 {
1869                                 rockchip,pins =
1870                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1871                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1872                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1873                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1874                         };
1875
1876                         sdio0_cmd: sdio0-cmd {
1877                                 rockchip,pins =
1878                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1879                         };
1880
1881                         sdio0_clk: sdio0-clk {
1882                                 rockchip,pins =
1883                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1884                         };
1885
1886                         sdio0_cd: sdio0-cd {
1887                                 rockchip,pins =
1888                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1889                         };
1890
1891                         sdio0_pwr: sdio0-pwr {
1892                                 rockchip,pins =
1893                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1894                         };
1895
1896                         sdio0_bkpwr: sdio0-bkpwr {
1897                                 rockchip,pins =
1898                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1899                         };
1900
1901                         sdio0_wp: sdio0-wp {
1902                                 rockchip,pins =
1903                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1904                         };
1905
1906                         sdio0_int: sdio0-int {
1907                                 rockchip,pins =
1908                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1909                         };
1910                 };
1911
1912                 sdmmc {
1913                         sdmmc_bus1: sdmmc-bus1 {
1914                                 rockchip,pins =
1915                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1916                         };
1917
1918                         sdmmc_bus4: sdmmc-bus4 {
1919                                 rockchip,pins =
1920                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1921                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1922                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1923                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1924                         };
1925
1926                         sdmmc_clk: sdmmc-clk {
1927                                 rockchip,pins =
1928                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1929                         };
1930
1931                         sdmmc_cmd: sdmmc-cmd {
1932                                 rockchip,pins =
1933                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1934                         };
1935
1936                         sdmmc_cd: sdmcc-cd {
1937                                 rockchip,pins =
1938                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1939                         };
1940
1941                         sdmmc_wp: sdmmc-wp {
1942                                 rockchip,pins =
1943                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1944                         };
1945                 };
1946
1947                 spdif {
1948                         spdif_bus: spdif-bus {
1949                                 rockchip,pins =
1950                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1951                         };
1952
1953                         spdif_bus_1: spdif-bus-1 {
1954                                 rockchip,pins =
1955                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
1956                         };
1957                 };
1958
1959                 spi0 {
1960                         spi0_clk: spi0-clk {
1961                                 rockchip,pins =
1962                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1963                         };
1964                         spi0_cs0: spi0-cs0 {
1965                                 rockchip,pins =
1966                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1967                         };
1968                         spi0_cs1: spi0-cs1 {
1969                                 rockchip,pins =
1970                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1971                         };
1972                         spi0_tx: spi0-tx {
1973                                 rockchip,pins =
1974                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1975                         };
1976                         spi0_rx: spi0-rx {
1977                                 rockchip,pins =
1978                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1979                         };
1980                 };
1981
1982                 spi1 {
1983                         spi1_clk: spi1-clk {
1984                                 rockchip,pins =
1985                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1986                         };
1987                         spi1_cs0: spi1-cs0 {
1988                                 rockchip,pins =
1989                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1990                         };
1991                         spi1_rx: spi1-rx {
1992                                 rockchip,pins =
1993                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1994                         };
1995                         spi1_tx: spi1-tx {
1996                                 rockchip,pins =
1997                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1998                         };
1999                 };
2000
2001                 spi2 {
2002                         spi2_clk: spi2-clk {
2003                                 rockchip,pins =
2004                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2005                         };
2006                         spi2_cs0: spi2-cs0 {
2007                                 rockchip,pins =
2008                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2009                         };
2010                         spi2_rx: spi2-rx {
2011                                 rockchip,pins =
2012                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2013                         };
2014                         spi2_tx: spi2-tx {
2015                                 rockchip,pins =
2016                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2017                         };
2018                 };
2019
2020                 spi3 {
2021                         spi3_clk: spi3-clk {
2022                                 rockchip,pins =
2023                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2024                         };
2025                         spi3_cs0: spi3-cs0 {
2026                                 rockchip,pins =
2027                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2028                         };
2029                         spi3_rx: spi3-rx {
2030                                 rockchip,pins =
2031                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2032                         };
2033                         spi3_tx: spi3-tx {
2034                                 rockchip,pins =
2035                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2036                         };
2037                 };
2038
2039                 spi4 {
2040                         spi4_clk: spi4-clk {
2041                                 rockchip,pins =
2042                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2043                         };
2044                         spi4_cs0: spi4-cs0 {
2045                                 rockchip,pins =
2046                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2047                         };
2048                         spi4_rx: spi4-rx {
2049                                 rockchip,pins =
2050                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2051                         };
2052                         spi4_tx: spi4-tx {
2053                                 rockchip,pins =
2054                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2055                         };
2056                 };
2057
2058                 spi5 {
2059                         spi5_clk: spi5-clk {
2060                                 rockchip,pins =
2061                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2062                         };
2063                         spi5_cs0: spi5-cs0 {
2064                                 rockchip,pins =
2065                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2066                         };
2067                         spi5_rx: spi5-rx {
2068                                 rockchip,pins =
2069                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2070                         };
2071                         spi5_tx: spi5-tx {
2072                                 rockchip,pins =
2073                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2074                         };
2075                 };
2076
2077                 tsadc {
2078                         otp_gpio: otp-gpio {
2079                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2080                         };
2081
2082                         otp_out: otp-out {
2083                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2084                         };
2085                 };
2086
2087                 uart0 {
2088                         uart0_xfer: uart0-xfer {
2089                                 rockchip,pins =
2090                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2091                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2092                         };
2093
2094                         uart0_cts: uart0-cts {
2095                                 rockchip,pins =
2096                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2097                         };
2098
2099                         uart0_rts: uart0-rts {
2100                                 rockchip,pins =
2101                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2102                         };
2103                 };
2104
2105                 uart1 {
2106                         uart1_xfer: uart1-xfer {
2107                                 rockchip,pins =
2108                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2109                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2110                         };
2111                 };
2112
2113                 uart2a {
2114                         uart2a_xfer: uart2a-xfer {
2115                                 rockchip,pins =
2116                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2117                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2118                         };
2119                 };
2120
2121                 uart2b {
2122                         uart2b_xfer: uart2b-xfer {
2123                                 rockchip,pins =
2124                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2125                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2126                         };
2127                 };
2128
2129                 uart2c {
2130                         uart2c_xfer: uart2c-xfer {
2131                                 rockchip,pins =
2132                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2133                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2134                         };
2135                 };
2136
2137                 uart3 {
2138                         uart3_xfer: uart3-xfer {
2139                                 rockchip,pins =
2140                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2141                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2142                         };
2143
2144                         uart3_cts: uart3-cts {
2145                                 rockchip,pins =
2146                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2147                         };
2148
2149                         uart3_rts: uart3-rts {
2150                                 rockchip,pins =
2151                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2152                         };
2153                 };
2154
2155                 uart4 {
2156                         uart4_xfer: uart4-xfer {
2157                                 rockchip,pins =
2158                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2159                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2160                         };
2161                 };
2162
2163                 uarthdcp {
2164                         uarthdcp_xfer: uarthdcp-xfer {
2165                                 rockchip,pins =
2166                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2167                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2168                         };
2169                 };
2170
2171                 pwm0 {
2172                         pwm0_pin: pwm0-pin {
2173                                 rockchip,pins =
2174                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2175                         };
2176
2177                         vop0_pwm_pin: vop0-pwm-pin {
2178                                 rockchip,pins =
2179                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2180                         };
2181                 };
2182
2183                 pwm1 {
2184                         pwm1_pin: pwm1-pin {
2185                                 rockchip,pins =
2186                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2187                         };
2188
2189                         vop1_pwm_pin: vop1-pwm-pin {
2190                                 rockchip,pins =
2191                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2192                         };
2193                 };
2194
2195                 pwm2 {
2196                         pwm2_pin: pwm2-pin {
2197                                 rockchip,pins =
2198                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2199                         };
2200                 };
2201
2202                 pwm3a {
2203                         pwm3a_pin: pwm3a-pin {
2204                                 rockchip,pins =
2205                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2206                         };
2207                 };
2208
2209                 pwm3b {
2210                         pwm3b_pin: pwm3b-pin {
2211                                 rockchip,pins =
2212                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2213                         };
2214                 };
2215
2216                 edp {
2217                         edp_hpd: edp-hpd {
2218                                 rockchip,pins =
2219                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2220                         };
2221                 };
2222
2223                 hdmi {
2224                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2225                                 rockchip,pins =
2226                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2227                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2228                         };
2229
2230                         hdmi_cec: hdmi-cec {
2231                                 rockchip,pins =
2232                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2233                         };
2234                 };
2235
2236                 pcie {
2237                         pcie_clkreqn: pci-clkreqn {
2238                                 rockchip,pins =
2239                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2240                         };
2241
2242                         pcie_clkreqnb: pci-clkreqnb {
2243                                 rockchip,pins =
2244                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2245                         };
2246                 };
2247         };
2248 };