arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 #include "rk3399-dram-default-timing.dtsi"
  53
  54 / {
  55         compatible = "rockchip,rk3399";
  56
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 i2c6 = &i2c6;
  69                 i2c7 = &i2c7;
  70                 i2c8 = &i2c8;
  71                 serial0 = &uart0;
  72                 serial1 = &uart1;
  73                 serial2 = &uart2;
  74                 serial3 = &uart3;
  75                 serial4 = &uart4;
  76         };
  77
  78         psci {
  79                 compatible = "arm,psci-1.0";
  80                 method = "smc";
  81         };
  82
  83         cpus {
  84                 #address-cells = <2>;
  85                 #size-cells = <0>;
  86
  87                 cpu-map {
  88                         cluster0 {
  89                                 core0 {
  90                                         cpu = <&cpu_l0>;
  91                                 };
  92                                 core1 {
  93                                         cpu = <&cpu_l1>;
  94                                 };
  95                                 core2 {
  96                                         cpu = <&cpu_l2>;
  97                                 };
  98                                 core3 {
  99                                         cpu = <&cpu_l3>;
 100                                 };
 101                         };
 102
 103                         cluster1 {
 104                                 core0 {
 105                                         cpu = <&cpu_b0>;
 106                                 };
 107                                 core1 {
 108                                         cpu = <&cpu_b1>;
 109                                 };
 110                         };
 111                 };
 112
 113                 cpu_l0: cpu@0 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a53", "arm,armv8";
 116                         reg = <0x0 0x0>;
 117                         enable-method = "psci";
 118                         #cooling-cells = <2>; /* min followed by max */
 119                         dynamic-power-coefficient = <100>;
 120                         clocks = <&cru ARMCLKL>;
 121                         cpu-idle-states = <&cpu_sleep>;
 122                         operating-points-v2 = <&cluster0_opp>;
 123                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 124                 };
 125
 126                 cpu_l1: cpu@1 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a53", "arm,armv8";
 129                         reg = <0x0 0x1>;
 130                         enable-method = "psci";
 131                         clocks = <&cru ARMCLKL>;
 132                         cpu-idle-states = <&cpu_sleep>;
 133                         operating-points-v2 = <&cluster0_opp>;
 134                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 135                 };
 136
 137                 cpu_l2: cpu@2 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x2>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         cpu-idle-states = <&cpu_sleep>;
 144                         operating-points-v2 = <&cluster0_opp>;
 145                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 146                 };
 147
 148                 cpu_l3: cpu@3 {
 149                         device_type = "cpu";
 150                         compatible = "arm,cortex-a53", "arm,armv8";
 151                         reg = <0x0 0x3>;
 152                         enable-method = "psci";
 153                         clocks = <&cru ARMCLKL>;
 154                         cpu-idle-states = <&cpu_sleep>;
 155                         operating-points-v2 = <&cluster0_opp>;
 156                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 157                 };
 158
 159                 cpu_b0: cpu@100 {
 160                         device_type = "cpu";
 161                         compatible = "arm,cortex-a72", "arm,armv8";
 162                         reg = <0x0 0x100>;
 163                         enable-method = "psci";
 164                         #cooling-cells = <2>; /* min followed by max */
 165                         dynamic-power-coefficient = <436>;
 166                         clocks = <&cru ARMCLKB>;
 167                         cpu-idle-states = <&cpu_sleep>;
 168                         operating-points-v2 = <&cluster1_opp>;
 169                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 170                 };
 171
 172                 cpu_b1: cpu@101 {
 173                         device_type = "cpu";
 174                         compatible = "arm,cortex-a72", "arm,armv8";
 175                         reg = <0x0 0x101>;
 176                         enable-method = "psci";
 177                         clocks = <&cru ARMCLKB>;
 178                         cpu-idle-states = <&cpu_sleep>;
 179                         operating-points-v2 = <&cluster1_opp>;
 180                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 181                 };
 182
 183                 idle-states {
 184                         entry-method = "psci";
 185                         cpu_sleep: cpu-sleep-0 {
 186                                 compatible = "arm,idle-state";
 187                                 local-timer-stop;
 188                                 arm,psci-suspend-param = <0x0010000>;
 189                                 entry-latency-us = <350>;
 190                                 exit-latency-us = <600>;
 191                                 min-residency-us = <1150>;
 192                         };
 193                 };
 194
 195                 /include/ "rk3399-sched-energy.dtsi"
 196
 197         };
 198
 199         cluster0_opp: opp_table0 {
 200                 compatible = "operating-points-v2";
 201                 opp-shared;
 202
 203                 opp@408000000 {
 204                         opp-hz = /bits/ 64 <408000000>;
 205                         opp-microvolt = <800000>;
 206                         clock-latency-ns = <40000>;
 207                 };
 208                 opp@600000000 {
 209                         opp-hz = /bits/ 64 <600000000>;
 210                         opp-microvolt = <800000>;
 211                 };
 212                 opp@816000000 {
 213                         opp-hz = /bits/ 64 <816000000>;
 214                         opp-microvolt = <800000>;
 215                 };
 216                 opp@1008000000 {
 217                         opp-hz = /bits/ 64 <1008000000>;
 218                         opp-microvolt = <875000>;
 219                 };
 220                 opp@1200000000 {
 221                         opp-hz = /bits/ 64 <1200000000>;
 222                         opp-microvolt = <925000>;
 223                 };
 224                 opp@1416000000 {
 225                         opp-hz = /bits/ 64 <1416000000>;
 226                         opp-microvolt = <1025000>;
 227                 };
 228         };
 229
 230         cluster1_opp: opp_table1 {
 231                 compatible = "operating-points-v2";
 232                 opp-shared;
 233
 234                 opp@408000000 {
 235                         opp-hz = /bits/ 64 <408000000>;
 236                         opp-microvolt = <800000>;
 237                         clock-latency-ns = <40000>;
 238                 };
 239                 opp@600000000 {
 240                         opp-hz = /bits/ 64 <600000000>;
 241                         opp-microvolt = <800000>;
 242                 };
 243                 opp@816000000 {
 244                         opp-hz = /bits/ 64 <816000000>;
 245                         opp-microvolt = <800000>;
 246                 };
 247                 opp@1008000000 {
 248                         opp-hz = /bits/ 64 <1008000000>;
 249                         opp-microvolt = <850000>;
 250                 };
 251                 opp@1200000000 {
 252                         opp-hz = /bits/ 64 <1200000000>;
 253                         opp-microvolt = <925000>;
 254                 };
 255         };
 256
 257         timer {
 258                 compatible = "arm,armv8-timer";
 259                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 260                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 261                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 262                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 263         };
 264
 265         pmu_a53 {
 266                 compatible = "arm,cortex-a53-pmu";
 267                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
 268         };
 269
 270         pmu_a72 {
 271                 compatible = "arm,cortex-a72-pmu";
 272                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
 273         };
 274
 275         xin24m: xin24m {
 276                 compatible = "fixed-clock";
 277                 #clock-cells = <0>;
 278                 clock-frequency = <24000000>;
 279                 clock-output-names = "xin24m";
 280         };
 281
 282         amba {
 283                 compatible = "arm,amba-bus";
 284                 #address-cells = <2>;
 285                 #size-cells = <2>;
 286                 ranges;
 287
 288                 dmac_bus: dma-controller@ff6d0000 {
 289                         compatible = "arm,pl330", "arm,primecell";
 290                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 291                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 292                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 293                         #dma-cells = <1>;
 294                         clocks = <&cru ACLK_DMAC0_PERILP>;
 295                         clock-names = "apb_pclk";
 296                         peripherals-req-type-burst;
 297                 };
 298
 299                 dmac_peri: dma-controller@ff6e0000 {
 300                         compatible = "arm,pl330", "arm,primecell";
 301                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 302                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 303                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 304                         #dma-cells = <1>;
 305                         clocks = <&cru ACLK_DMAC1_PERILP>;
 306                         clock-names = "apb_pclk";
 307                         peripherals-req-type-burst;
 308                 };
 309         };
 310
 311         gmac: eth@fe300000 {
 312                 compatible = "rockchip,rk3399-gmac";
 313                 reg = <0x0 0xfe300000 0x0 0x10000>;
 314                 rockchip,grf = <&grf>;
 315                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 316                 interrupt-names = "macirq";
 317                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 318                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 319                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 320                          <&cru PCLK_GMAC>;
 321                 clock-names = "stmmaceth", "mac_clk_rx",
 322                               "mac_clk_tx", "clk_mac_ref",
 323                               "clk_mac_refout", "aclk_mac",
 324                               "pclk_mac";
 325                 resets = <&cru SRST_A_GMAC>;
 326                 reset-names = "stmmaceth";
 327                 power-domains = <&power RK3399_PD_GMAC>;
 328                 status = "disabled";
 329         };
 330
 331         sdio0: dwmmc@fe310000 {
 332                 compatible = "rockchip,rk3399-dw-mshc",
 333                              "rockchip,rk3288-dw-mshc";
 334                 reg = <0x0 0xfe310000 0x0 0x4000>;
 335                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 336                 clock-freq-min-max = <400000 150000000>;
 337                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 338                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 339                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 340                 fifo-depth = <0x100>;
 341                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 342                 status = "disabled";
 343         };
 344
 345         sdmmc: dwmmc@fe320000 {
 346                 compatible = "rockchip,rk3399-dw-mshc",
 347                              "rockchip,rk3288-dw-mshc";
 348                 reg = <0x0 0xfe320000 0x0 0x4000>;
 349                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 350                 clock-freq-min-max = <400000 150000000>;
 351                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 352                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 353                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 354                 fifo-depth = <0x100>;
 355                 power-domains = <&power RK3399_PD_SD>;
 356                 status = "disabled";
 357         };
 358
 359         sdhci: sdhci@fe330000 {
 360                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 361                 reg = <0x0 0xfe330000 0x0 0x10000>;
 362                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 363                 arasan,soc-ctl-syscon = <&grf>;
 364                 assigned-clocks = <&cru SCLK_EMMC>;
 365                 assigned-clock-rates = <200000000>;
 366                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 367                 clock-names = "clk_xin", "clk_ahb";
 368                 clock-output-names = "emmc_cardclock";
 369                 #clock-cells = <0>;
 370                 phys = <&emmc_phy>;
 371                 phy-names = "phy_arasan";
 372                 power-domains = <&power RK3399_PD_EMMC>;
 373                 status = "disabled";
 374         };
 375
 376         usb_host0_ehci: usb@fe380000 {
 377                 compatible = "generic-ehci";
 378                 reg = <0x0 0xfe380000 0x0 0x20000>;
 379                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 380                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 381                          <&cru SCLK_USBPHY0_480M_SRC>;
 382                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 383                 phys = <&u2phy0_host>;
 384                 phy-names = "usb";
 385                 power-domains = <&power RK3399_PD_PERIHP>;
 386                 status = "disabled";
 387         };
 388
 389         usb_host0_ohci: usb@fe3a0000 {
 390                 compatible = "generic-ohci";
 391                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 392                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 393                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 394                          <&cru SCLK_USBPHY0_480M_SRC>;
 395                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 396                 phys = <&u2phy0_host>;
 397                 phy-names = "usb";
 398                 power-domains = <&power RK3399_PD_PERIHP>;
 399                 status = "disabled";
 400         };
 401
 402         usb_host1_ehci: usb@fe3c0000 {
 403                 compatible = "generic-ehci";
 404                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 405                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 406                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 407                          <&cru SCLK_USBPHY1_480M_SRC>;
 408                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 409                 phys = <&u2phy1_host>;
 410                 phy-names = "usb";
 411                 power-domains = <&power RK3399_PD_PERIHP>;
 412                 status = "disabled";
 413         };
 414
 415         usb_host1_ohci: usb@fe3e0000 {
 416                 compatible = "generic-ohci";
 417                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 418                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 419                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 420                          <&cru SCLK_USBPHY1_480M_SRC>;
 421                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 422                 phys = <&u2phy1_host>;
 423                 phy-names = "usb";
 424                 power-domains = <&power RK3399_PD_PERIHP>;
 425                 status = "disabled";
 426         };
 427
 428         usbdrd3_0: usb@fe800000 {
 429                 compatible = "rockchip,rk3399-dwc3";
 430                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 431                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 432                 clock-names = "ref_clk", "suspend_clk",
 433                               "bus_clk", "grf_clk";
 434                 power-domains = <&power RK3399_PD_USB3>;
 435                 resets = <&cru SRST_A_USB3_OTG0>;
 436                 reset-names = "usb3-otg";
 437                 #address-cells = <2>;
 438                 #size-cells = <2>;
 439                 ranges;
 440                 status = "disabled";
 441                 usbdrd_dwc3_0: dwc3@fe800000 {
 442                         compatible = "snps,dwc3";
 443                         reg = <0x0 0xfe800000 0x0 0x100000>;
 444                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 445                         dr_mode = "otg";
 446                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 447                         phy-names = "usb2-phy", "usb3-phy";
 448                         phy_type = "utmi_wide";
 449                         snps,dis_enblslpm_quirk;
 450                         snps,dis-u2-freeclk-exists-quirk;
 451                         snps,dis_u2_susphy_quirk;
 452                         snps,dis-del-phy-power-chg-quirk;
 453                         snps,xhci-slow-suspend-quirk;
 454                         status = "disabled";
 455                 };
 456         };
 457
 458         usbdrd3_1: usb@fe900000 {
 459                 compatible = "rockchip,rk3399-dwc3";
 460                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 461                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 462                 clock-names = "ref_clk", "suspend_clk",
 463                               "bus_clk", "grf_clk";
 464                 power-domains = <&power RK3399_PD_USB3>;
 465                 resets = <&cru SRST_A_USB3_OTG1>;
 466                 reset-names = "usb3-otg";
 467                 #address-cells = <2>;
 468                 #size-cells = <2>;
 469                 ranges;
 470                 status = "disabled";
 471                 usbdrd_dwc3_1: dwc3@fe900000 {
 472                         compatible = "snps,dwc3";
 473                         reg = <0x0 0xfe900000 0x0 0x100000>;
 474                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 475                         dr_mode = "host";
 476                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 477                         phy-names = "usb2-phy", "usb3-phy";
 478                         phy_type = "utmi_wide";
 479                         snps,dis_enblslpm_quirk;
 480                         snps,dis-u2-freeclk-exists-quirk;
 481                         snps,dis_u2_susphy_quirk;
 482                         snps,dis-del-phy-power-chg-quirk;
 483                         snps,xhci-slow-suspend-quirk;
 484                         status = "disabled";
 485                 };
 486         };
 487
 488         gic: interrupt-controller@fee00000 {
 489                 compatible = "arm,gic-v3";
 490                 #interrupt-cells = <4>;
 491                 #address-cells = <2>;
 492                 #size-cells = <2>;
 493                 ranges;
 494                 interrupt-controller;
 495
 496                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 497                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 498                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 499                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 500                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 501                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 502                 its: interrupt-controller@fee20000 {
 503                         compatible = "arm,gic-v3-its";
 504                         msi-controller;
 505                         reg = <0x0 0xfee20000 0x0 0x20000>;
 506                 };
 507
 508                 ppi-partitions {
 509                         part0: interrupt-partition-0 {
 510                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 511                         };
 512
 513                         part1: interrupt-partition-1 {
 514                                 affinity = <&cpu_b0 &cpu_b1>;
 515                         };
 516                 };
 517         };
 518
 519         saradc: saradc@ff100000 {
 520                 compatible = "rockchip,rk3399-saradc";
 521                 reg = <0x0 0xff100000 0x0 0x100>;
 522                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 523                 #io-channel-cells = <1>;
 524                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 525                 clock-names = "saradc", "apb_pclk";
 526                 status = "disabled";
 527         };
 528
 529         i2c0: i2c@ff3c0000 {
 530                 compatible = "rockchip,rk3399-i2c";
 531                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 532                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 533                 clock-names = "i2c", "pclk";
 534                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 535                 pinctrl-names = "default";
 536                 pinctrl-0 = <&i2c0_xfer>;
 537                 #address-cells = <1>;
 538                 #size-cells = <0>;
 539                 status = "disabled";
 540         };
 541
 542         i2c1: i2c@ff110000 {
 543                 compatible = "rockchip,rk3399-i2c";
 544                 reg = <0x0 0xff110000 0x0 0x1000>;
 545                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 546                 clock-names = "i2c", "pclk";
 547                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 548                 pinctrl-names = "default";
 549                 pinctrl-0 = <&i2c1_xfer>;
 550                 #address-cells = <1>;
 551                 #size-cells = <0>;
 552                 status = "disabled";
 553         };
 554
 555         i2c2: i2c@ff120000 {
 556                 compatible = "rockchip,rk3399-i2c";
 557                 reg = <0x0 0xff120000 0x0 0x1000>;
 558                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 559                 clock-names = "i2c", "pclk";
 560                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 561                 pinctrl-names = "default";
 562                 pinctrl-0 = <&i2c2_xfer>;
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 status = "disabled";
 566         };
 567
 568         i2c3: i2c@ff130000 {
 569                 compatible = "rockchip,rk3399-i2c";
 570                 reg = <0x0 0xff130000 0x0 0x1000>;
 571                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 572                 clock-names = "i2c", "pclk";
 573                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&i2c3_xfer>;
 576                 #address-cells = <1>;
 577                 #size-cells = <0>;
 578                 status = "disabled";
 579         };
 580
 581         i2c5: i2c@ff140000 {
 582                 compatible = "rockchip,rk3399-i2c";
 583                 reg = <0x0 0xff140000 0x0 0x1000>;
 584                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 585                 clock-names = "i2c", "pclk";
 586                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&i2c5_xfer>;
 589                 #address-cells = <1>;
 590                 #size-cells = <0>;
 591                 status = "disabled";
 592         };
 593
 594         i2c6: i2c@ff150000 {
 595                 compatible = "rockchip,rk3399-i2c";
 596                 reg = <0x0 0xff150000 0x0 0x1000>;
 597                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 598                 clock-names = "i2c", "pclk";
 599                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 600                 pinctrl-names = "default";
 601                 pinctrl-0 = <&i2c6_xfer>;
 602                 #address-cells = <1>;
 603                 #size-cells = <0>;
 604                 status = "disabled";
 605         };
 606
 607         i2c7: i2c@ff160000 {
 608                 compatible = "rockchip,rk3399-i2c";
 609                 reg = <0x0 0xff160000 0x0 0x1000>;
 610                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 611                 clock-names = "i2c", "pclk";
 612                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 613                 pinctrl-names = "default";
 614                 pinctrl-0 = <&i2c7_xfer>;
 615                 #address-cells = <1>;
 616                 #size-cells = <0>;
 617                 status = "disabled";
 618         };
 619
 620         uart0: serial@ff180000 {
 621                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 622                 reg = <0x0 0xff180000 0x0 0x100>;
 623                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 624                 clock-names = "baudclk", "apb_pclk";
 625                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 626                 reg-shift = <2>;
 627                 reg-io-width = <4>;
 628                 pinctrl-names = "default";
 629                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 630                 status = "disabled";
 631         };
 632
 633         uart1: serial@ff190000 {
 634                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 635                 reg = <0x0 0xff190000 0x0 0x100>;
 636                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 637                 clock-names = "baudclk", "apb_pclk";
 638                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 639                 reg-shift = <2>;
 640                 reg-io-width = <4>;
 641                 pinctrl-names = "default";
 642                 pinctrl-0 = <&uart1_xfer>;
 643                 status = "disabled";
 644         };
 645
 646         uart2: serial@ff1a0000 {
 647                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 648                 reg = <0x0 0xff1a0000 0x0 0x100>;
 649                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 650                 clock-names = "baudclk", "apb_pclk";
 651                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 652                 reg-shift = <2>;
 653                 reg-io-width = <4>;
 654                 pinctrl-names = "default";
 655                 pinctrl-0 = <&uart2c_xfer>;
 656                 status = "disabled";
 657         };
 658
 659         uart3: serial@ff1b0000 {
 660                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 661                 reg = <0x0 0xff1b0000 0x0 0x100>;
 662                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 663                 clock-names = "baudclk", "apb_pclk";
 664                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 665                 reg-shift = <2>;
 666                 reg-io-width = <4>;
 667                 pinctrl-names = "default";
 668                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 669                 status = "disabled";
 670         };
 671
 672         spi0: spi@ff1c0000 {
 673                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 674                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 675                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 676                 clock-names = "spiclk", "apb_pclk";
 677                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 678                 pinctrl-names = "default";
 679                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 680                 #address-cells = <1>;
 681                 #size-cells = <0>;
 682                 status = "disabled";
 683         };
 684
 685         spi1: spi@ff1d0000 {
 686                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 687                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 688                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 689                 clock-names = "spiclk", "apb_pclk";
 690                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 691                 pinctrl-names = "default";
 692                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 693                 #address-cells = <1>;
 694                 #size-cells = <0>;
 695                 status = "disabled";
 696         };
 697
 698         spi2: spi@ff1e0000 {
 699                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 700                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 701                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 702                 clock-names = "spiclk", "apb_pclk";
 703                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 704                 pinctrl-names = "default";
 705                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 706                 #address-cells = <1>;
 707                 #size-cells = <0>;
 708                 status = "disabled";
 709         };
 710
 711         spi4: spi@ff1f0000 {
 712                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 713                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 714                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 715                 clock-names = "spiclk", "apb_pclk";
 716                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 717                 pinctrl-names = "default";
 718                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 719                 #address-cells = <1>;
 720                 #size-cells = <0>;
 721                 status = "disabled";
 722         };
 723
 724         spi5: spi@ff200000 {
 725                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 726                 reg = <0x0 0xff200000 0x0 0x1000>;
 727                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 728                 clock-names = "spiclk", "apb_pclk";
 729                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 730                 pinctrl-names = "default";
 731                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 732                 #address-cells = <1>;
 733                 #size-cells = <0>;
 734                 status = "disabled";
 735         };
 736
 737         thermal-zones {
 738                 soc_thermal: soc-thermal {
 739                         polling-delay-passive = <20>; /* milliseconds */
 740                         polling-delay = <1000>; /* milliseconds */
 741                         sustainable-power = <1000>; /* milliwatts */
 742
 743                         thermal-sensors = <&tsadc 0>;
 744
 745                         trips {
 746                                 threshold: trip-point@0 {
 747                                         temperature = <70000>; /* millicelsius */
 748                                         hysteresis = <2000>; /* millicelsius */
 749                                         type = "passive";
 750                                 };
 751                                 target: trip-point@1 {
 752                                         temperature = <85000>; /* millicelsius */
 753                                         hysteresis = <2000>; /* millicelsius */
 754                                         type = "passive";
 755                                 };
 756                                 soc_crit: soc-crit {
 757                                         temperature = <95000>; /* millicelsius */
 758                                         hysteresis = <2000>; /* millicelsius */
 759                                         type = "critical";
 760                                 };
 761                         };
 762
 763                         cooling-maps {
 764                                 map0 {
 765                                         trip = <&target>;
 766                                         cooling-device =
 767                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 768                                         contribution = <4096>;
 769                                 };
 770                                 map1 {
 771                                         trip = <&target>;
 772                                         cooling-device =
 773                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 774                                         contribution = <1024>;
 775                                 };
 776                                 map2 {
 777                                         trip = <&target>;
 778                                         cooling-device =
 779                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 780                                         contribution = <4096>;
 781                                 };
 782                         };
 783                 };
 784
 785                 gpu_thermal: gpu-thermal {
 786                         polling-delay-passive = <100>; /* milliseconds */
 787                         polling-delay = <1000>; /* milliseconds */
 788
 789                         thermal-sensors = <&tsadc 1>;
 790                 };
 791         };
 792
 793         tsadc: tsadc@ff260000 {
 794                 compatible = "rockchip,rk3399-tsadc";
 795                 reg = <0x0 0xff260000 0x0 0x100>;
 796                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 797                 rockchip,grf = <&grf>;
 798                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 799                 clock-names = "tsadc", "apb_pclk";
 800                 assigned-clocks = <&cru SCLK_TSADC>;
 801                 assigned-clock-rates = <750000>;
 802                 resets = <&cru SRST_TSADC>;
 803                 reset-names = "tsadc-apb";
 804                 pinctrl-names = "init", "default", "sleep";
 805                 pinctrl-0 = <&otp_gpio>;
 806                 pinctrl-1 = <&otp_out>;
 807                 pinctrl-2 = <&otp_gpio>;
 808                 #thermal-sensor-cells = <1>;
 809                 rockchip,hw-tshut-temp = <95000>;
 810                 status = "disabled";
 811         };
 812
 813         qos_emmc: qos@ffa58000 {
 814                 compatible = "syscon";
 815                 reg = <0x0 0xffa58000 0x0 0x20>;
 816         };
 817
 818         qos_gmac: qos@ffa5c000 {
 819                 compatible = "syscon";
 820                 reg = <0x0 0xffa5c000 0x0 0x20>;
 821         };
 822
 823         qos_pcie: qos@ffa60080 {
 824                 compatible = "syscon";
 825                 reg = <0x0 0xffa60080 0x0 0x20>;
 826         };
 827
 828         qos_usb_host0: qos@ffa60100 {
 829                 compatible = "syscon";
 830                 reg = <0x0 0xffa60100 0x0 0x20>;
 831         };
 832
 833         qos_usb_host1: qos@ffa60180 {
 834                 compatible = "syscon";
 835                 reg = <0x0 0xffa60180 0x0 0x20>;
 836         };
 837
 838         qos_usb_otg0: qos@ffa70000 {
 839                 compatible = "syscon";
 840                 reg = <0x0 0xffa70000 0x0 0x20>;
 841         };
 842
 843         qos_usb_otg1: qos@ffa70080 {
 844                 compatible = "syscon";
 845                 reg = <0x0 0xffa70080 0x0 0x20>;
 846         };
 847
 848         qos_sd: qos@ffa74000 {
 849                 compatible = "syscon";
 850                 reg = <0x0 0xffa74000 0x0 0x20>;
 851         };
 852
 853         qos_sdioaudio: qos@ffa76000 {
 854                 compatible = "syscon";
 855                 reg = <0x0 0xffa76000 0x0 0x20>;
 856         };
 857
 858         qos_hdcp: qos@ffa90000 {
 859                 compatible = "syscon";
 860                 reg = <0x0 0xffa90000 0x0 0x20>;
 861         };
 862
 863         qos_iep: qos@ffa98000 {
 864                 compatible = "syscon";
 865                 reg = <0x0 0xffa98000 0x0 0x20>;
 866         };
 867
 868         qos_isp0_m0: qos@ffaa0000 {
 869                 compatible = "syscon";
 870                 reg = <0x0 0xffaa0000 0x0 0x20>;
 871         };
 872
 873         qos_isp0_m1: qos@ffaa0080 {
 874                 compatible = "syscon";
 875                 reg = <0x0 0xffaa0080 0x0 0x20>;
 876         };
 877
 878         qos_isp1_m0: qos@ffaa8000 {
 879                 compatible = "syscon";
 880                 reg = <0x0 0xffaa8000 0x0 0x20>;
 881         };
 882
 883         qos_isp1_m1: qos@ffaa8080 {
 884                 compatible = "syscon";
 885                 reg = <0x0 0xffaa8080 0x0 0x20>;
 886         };
 887
 888         qos_rga_r: qos@ffab0000 {
 889                 compatible = "syscon";
 890                 reg = <0x0 0xffab0000 0x0 0x20>;
 891         };
 892
 893         qos_rga_w: qos@ffab0080 {
 894                 compatible = "syscon";
 895                 reg = <0x0 0xffab0080 0x0 0x20>;
 896         };
 897
 898         qos_video_m0: qos@ffab8000 {
 899                 compatible = "syscon";
 900                 reg = <0x0 0xffab8000 0x0 0x20>;
 901         };
 902
 903         qos_video_m1_r: qos@ffac0000 {
 904                 compatible = "syscon";
 905                 reg = <0x0 0xffac0000 0x0 0x20>;
 906         };
 907
 908         qos_video_m1_w: qos@ffac0080 {
 909                 compatible = "syscon";
 910                 reg = <0x0 0xffac0080 0x0 0x20>;
 911         };
 912
 913         qos_vop_big_r: qos@ffac8000 {
 914                 compatible = "syscon";
 915                 reg = <0x0 0xffac8000 0x0 0x20>;
 916         };
 917
 918         qos_vop_big_w: qos@ffac8080 {
 919                 compatible = "syscon";
 920                 reg = <0x0 0xffac8080 0x0 0x20>;
 921         };
 922
 923         qos_vop_little: qos@ffad0000 {
 924                 compatible = "syscon";
 925                 reg = <0x0 0xffad0000 0x0 0x20>;
 926         };
 927
 928         qos_perihp: qos@ffad8080 {
 929                 compatible = "syscon";
 930                 reg = <0x0 0xffad8080 0x0 0x20>;
 931         };
 932
 933         qos_gpu: qos@ffae0000 {
 934                 compatible = "syscon";
 935                 reg = <0x0 0xffae0000 0x0 0x20>;
 936         };
 937
 938         pmu: power-management@ff310000 {
 939                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 940                 reg = <0x0 0xff310000 0x0 0x1000>;
 941
 942                 /*
 943                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 944                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 945                  * Some of the power domains are grouped together for every
 946                  * voltage domain.
 947                  * The detail contents as below.
 948                  */
 949                 power: power-controller {
 950                         compatible = "rockchip,rk3399-power-controller";
 951                         #power-domain-cells = <1>;
 952                         #address-cells = <1>;
 953                         #size-cells = <0>;
 954
 955                         /* These power domains are grouped by VD_CENTER */
 956                         pd_iep@RK3399_PD_IEP {
 957                                 reg = <RK3399_PD_IEP>;
 958                                 clocks = <&cru ACLK_IEP>,
 959                                          <&cru HCLK_IEP>;
 960                                 pm_qos = <&qos_iep>;
 961                         };
 962                         pd_rga@RK3399_PD_RGA {
 963                                 reg = <RK3399_PD_RGA>;
 964                                 clocks = <&cru ACLK_RGA>,
 965                                          <&cru HCLK_RGA>;
 966                                 pm_qos = <&qos_rga_r>,
 967                                          <&qos_rga_w>;
 968                         };
 969                         pd_vcodec@RK3399_PD_VCODEC {
 970                                 reg = <RK3399_PD_VCODEC>;
 971                                 clocks = <&cru ACLK_VCODEC>,
 972                                          <&cru HCLK_VCODEC>;
 973                                 pm_qos = <&qos_video_m0>;
 974                         };
 975                         pd_vdu@RK3399_PD_VDU {
 976                                 reg = <RK3399_PD_VDU>;
 977                                 clocks = <&cru ACLK_VDU>,
 978                                          <&cru HCLK_VDU>;
 979                                 pm_qos = <&qos_video_m1_r>,
 980                                          <&qos_video_m1_w>;
 981                         };
 982
 983                         /* These power domains are grouped by VD_GPU */
 984                         pd_gpu@RK3399_PD_GPU {
 985                                 reg = <RK3399_PD_GPU>;
 986                                 clocks = <&cru ACLK_GPU>;
 987                                 pm_qos = <&qos_gpu>;
 988                         };
 989
 990                         /* These power domains are grouped by VD_LOGIC */
 991                         pd_edp@RK3399_PD_EDP {
 992                                 reg = <RK3399_PD_EDP>;
 993                                 clocks = <&cru PCLK_EDP_CTRL>;
 994                         };
 995                         pd_emmc@RK3399_PD_EMMC {
 996                                 reg = <RK3399_PD_EMMC>;
 997                                 clocks = <&cru ACLK_EMMC>;
 998                                 pm_qos = <&qos_emmc>;
 999                         };
1000                         pd_gmac@RK3399_PD_GMAC {
1001                                 reg = <RK3399_PD_GMAC>;
1002                                 clocks = <&cru ACLK_GMAC>;
1003                                 pm_qos = <&qos_gmac>;
1004                         };
1005                         pd_perihp@RK3399_PD_PERIHP {
1006                                 reg = <RK3399_PD_PERIHP>;
1007                                 #address-cells = <1>;
1008                                 #size-cells = <0>;
1009                                 clocks = <&cru ACLK_PERIHP>;
1010                                 pm_qos = <&qos_perihp>,
1011                                          <&qos_pcie>,
1012                                          <&qos_usb_host0>,
1013                                          <&qos_usb_host1>;
1014
1015                                 pd_sd@RK3399_PD_SD {
1016                                         reg = <RK3399_PD_SD>;
1017                                         clocks = <&cru HCLK_SDMMC>,
1018                                                  <&cru SCLK_SDMMC>;
1019                                         pm_qos = <&qos_sd>;
1020                                 };
1021                         };
1022                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1023                                 reg = <RK3399_PD_SDIOAUDIO>;
1024                                 clocks = <&cru HCLK_SDIO>;
1025                                 pm_qos = <&qos_sdioaudio>;
1026                         };
1027                         pd_usb3@RK3399_PD_USB3 {
1028                                 reg = <RK3399_PD_USB3>;
1029                                 clocks = <&cru ACLK_USB3>;
1030                                 pm_qos = <&qos_usb_otg0>,
1031                                          <&qos_usb_otg1>;
1032                         };
1033                         pd_vio@RK3399_PD_VIO {
1034                                 reg = <RK3399_PD_VIO>;
1035                                 #address-cells = <1>;
1036                                 #size-cells = <0>;
1037
1038                                 pd_hdcp@RK3399_PD_HDCP {
1039                                         reg = <RK3399_PD_HDCP>;
1040                                         clocks = <&cru ACLK_HDCP>,
1041                                                  <&cru HCLK_HDCP>,
1042                                                  <&cru PCLK_HDCP>;
1043                                         pm_qos = <&qos_hdcp>;
1044                                 };
1045                                 pd_isp0@RK3399_PD_ISP0 {
1046                                         reg = <RK3399_PD_ISP0>;
1047                                         clocks = <&cru ACLK_ISP0>,
1048                                                  <&cru HCLK_ISP0>;
1049                                         pm_qos = <&qos_isp0_m0>,
1050                                                  <&qos_isp0_m1>;
1051                                 };
1052                                 pd_isp1@RK3399_PD_ISP1 {
1053                                         reg = <RK3399_PD_ISP1>;
1054                                         clocks = <&cru ACLK_ISP1>,
1055                                                  <&cru HCLK_ISP1>;
1056                                         pm_qos = <&qos_isp1_m0>,
1057                                                  <&qos_isp1_m1>;
1058                                 };
1059                                 pd_vo@RK3399_PD_VO {
1060                                         reg = <RK3399_PD_VO>;
1061                                         #address-cells = <1>;
1062                                         #size-cells = <0>;
1063
1064                                         pd_vopb@RK3399_PD_VOPB {
1065                                                 reg = <RK3399_PD_VOPB>;
1066                                                 clocks = <&cru ACLK_VOP0>,
1067                                                          <&cru HCLK_VOP0>;
1068                                                 pm_qos = <&qos_vop_big_r>,
1069                                                          <&qos_vop_big_w>;
1070                                         };
1071                                         pd_vopl@RK3399_PD_VOPL {
1072                                                 reg = <RK3399_PD_VOPL>;
1073                                                 clocks = <&cru ACLK_VOP1>,
1074                                                          <&cru HCLK_VOP1>;
1075                                                 pm_qos = <&qos_vop_little>;
1076                                         };
1077                                 };
1078                         };
1079                 };
1080         };
1081
1082         pmugrf: syscon@ff320000 {
1083                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1084                 reg = <0x0 0xff320000 0x0 0x1000>;
1085
1086                 reboot-mode {
1087                         compatible = "syscon-reboot-mode";
1088                         offset = <0x300>;
1089                         mode-bootloader = <BOOT_LOADER>;
1090                         mode-charge = <BOOT_CHARGING>;
1091                         mode-fastboot = <BOOT_FASTBOOT>;
1092                         mode-loader = <BOOT_LOADER>;
1093                         mode-normal = <BOOT_NORMAL>;
1094                         mode-recovery = <BOOT_RECOVERY>;
1095                         mode-ums = <BOOT_UMS>;
1096                 };
1097         };
1098
1099         spi3: spi@ff350000 {
1100                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1101                 reg = <0x0 0xff350000 0x0 0x1000>;
1102                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1103                 clock-names = "spiclk", "apb_pclk";
1104                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1105                 pinctrl-names = "default";
1106                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1107                 #address-cells = <1>;
1108                 #size-cells = <0>;
1109                 status = "disabled";
1110         };
1111
1112         uart4: serial@ff370000 {
1113                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1114                 reg = <0x0 0xff370000 0x0 0x100>;
1115                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1116                 clock-names = "baudclk", "apb_pclk";
1117                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1118                 reg-shift = <2>;
1119                 reg-io-width = <4>;
1120                 pinctrl-names = "default";
1121                 pinctrl-0 = <&uart4_xfer>;
1122                 status = "disabled";
1123         };
1124
1125         i2c4: i2c@ff3d0000 {
1126                 compatible = "rockchip,rk3399-i2c";
1127                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1128                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1129                 clock-names = "i2c", "pclk";
1130                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1131                 pinctrl-names = "default";
1132                 pinctrl-0 = <&i2c4_xfer>;
1133                 #address-cells = <1>;
1134                 #size-cells = <0>;
1135                 status = "disabled";
1136         };
1137
1138         i2c8: i2c@ff3e0000 {
1139                 compatible = "rockchip,rk3399-i2c";
1140                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1141                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1142                 clock-names = "i2c", "pclk";
1143                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1144                 pinctrl-names = "default";
1145                 pinctrl-0 = <&i2c8_xfer>;
1146                 #address-cells = <1>;
1147                 #size-cells = <0>;
1148                 status = "disabled";
1149         };
1150
1151         pcie_phy: phy@e220 {
1152                 compatible = "rockchip,rk3399-pcie-phy";
1153                 #phy-cells = <0>;
1154                 rockchip,grf = <&grf>;
1155                 clocks = <&cru SCLK_PCIEPHY_REF>;
1156                 clock-names = "refclk";
1157                 resets = <&cru SRST_PCIEPHY>;
1158                 reset-names = "phy";
1159                 status = "disabled";
1160         };
1161
1162         pcie0: pcie@f8000000 {
1163                 compatible = "rockchip,rk3399-pcie";
1164                 #address-cells = <3>;
1165                 #size-cells = <2>;
1166                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1167                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1168                 clock-names = "aclk", "aclk-perf",
1169                               "hclk", "pm";
1170                 bus-range = <0x0 0x1>;
1171                 msi-map = <0x0 &its 0x0 0x1000>;
1172                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1173                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1174                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1175                 interrupt-names = "sys", "legacy", "client";
1176                 #interrupt-cells = <1>;
1177                 interrupt-map-mask = <0 0 0 7>;
1178                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1179                                 <0 0 0 2 &pcie0_intc 1>,
1180                                 <0 0 0 3 &pcie0_intc 2>,
1181                                 <0 0 0 4 &pcie0_intc 3>;
1182                 phys = <&pcie_phy>;
1183                 phy-names = "pcie-phy";
1184                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1185                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1186                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1187                       <0x0 0xfd000000 0x0 0x1000000>;
1188                 reg-names = "axi-base", "apb-base";
1189                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1190                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
1191                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
1192                 status = "disabled";
1193                 pcie0_intc: interrupt-controller {
1194                         interrupt-controller;
1195                         #address-cells = <0>;
1196                         #interrupt-cells = <1>;
1197                 };
1198         };
1199
1200         pwm0: pwm@ff420000 {
1201                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1202                 reg = <0x0 0xff420000 0x0 0x10>;
1203                 #pwm-cells = <3>;
1204                 pinctrl-names = "default";
1205                 pinctrl-0 = <&pwm0_pin>;
1206                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1207                 clock-names = "pwm";
1208                 status = "disabled";
1209         };
1210
1211         pwm1: pwm@ff420010 {
1212                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1213                 reg = <0x0 0xff420010 0x0 0x10>;
1214                 #pwm-cells = <3>;
1215                 pinctrl-names = "default";
1216                 pinctrl-0 = <&pwm1_pin>;
1217                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1218                 clock-names = "pwm";
1219                 status = "disabled";
1220         };
1221
1222         pwm2: pwm@ff420020 {
1223                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1224                 reg = <0x0 0xff420020 0x0 0x10>;
1225                 #pwm-cells = <3>;
1226                 pinctrl-names = "default";
1227                 pinctrl-0 = <&pwm2_pin>;
1228                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1229                 clock-names = "pwm";
1230                 status = "disabled";
1231         };
1232
1233         pwm3: pwm@ff420030 {
1234                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1235                 reg = <0x0 0xff420030 0x0 0x10>;
1236                 #pwm-cells = <3>;
1237                 pinctrl-names = "default";
1238                 pinctrl-0 = <&pwm3a_pin>;
1239                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1240                 clock-names = "pwm";
1241                 status = "disabled";
1242         };
1243
1244         dfi: dfi@ff630000 {
1245                 reg = <0x00 0xff630000 0x00 0x4000>;
1246                 compatible = "rockchip,rk3399-dfi";
1247                 rockchip,pmu = <&pmugrf>;
1248                 clocks = <&cru PCLK_DDR_MON>;
1249                 clock-names = "pclk_ddr_mon";
1250                 status = "disabled";
1251         };
1252
1253         dmc: dmc {
1254                 compatible = "rockchip,rk3399-dmc";
1255                 devfreq-events = <&dfi>;
1256                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1257                 clocks = <&cru SCLK_DDRCLK>;
1258                 clock-names = "dmc_clk";
1259                 ddr_timing = <&ddr_timing>;
1260                 operating-points-v2 = <&dmc_opp_table>;
1261                 status = "disabled";
1262         };
1263
1264         dmc_opp_table: dmc_opp_table {
1265                 compatible = "operating-points-v2";
1266
1267                 opp00 {
1268                         opp-hz = /bits/ 64 <666000000>;
1269                         opp-microvolt = <900000>;
1270                 };
1271         };
1272
1273         rga: rga@ff680000 {
1274                 compatible = "rockchip,rk3399-rga";
1275                 reg = <0x0 0xff680000 0x0 0x10000>;
1276                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1277                 interrupt-names = "rga";
1278                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1279                 clock-names = "aclk", "hclk", "sclk";
1280                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1281                 reset-names = "core", "axi", "ahb";
1282                 power-domains = <&power RK3399_PD_RGA>;
1283                 status = "disabled";
1284         };
1285
1286         efuse0: efuse@ff690000 {
1287                 compatible = "rockchip,rk3399-efuse";
1288                 reg = <0x0 0xff690000 0x0 0x80>;
1289                 #address-cells = <1>;
1290                 #size-cells = <1>;
1291                 clocks = <&cru PCLK_EFUSE1024NS>;
1292                 clock-names = "pclk_efuse";
1293
1294                 /* Data cells */
1295                 cpul_leakage: cpul-leakage {
1296                         reg = <0x1a 0x1>;
1297                 };
1298                 cpub_leakage: cpub-leakage {
1299                         reg = <0x17 0x1>;
1300                 };
1301                 gpu_leakage: gpu-leakage {
1302                         reg = <0x18 0x1>;
1303                 };
1304                 center_leakage: center-leakage {
1305                         reg = <0x19 0x1>;
1306                 };
1307                 logic_leakage: logic-leakage {
1308                         reg = <0x1b 0x1>;
1309                 };
1310                 wafer_info: wafer-info {
1311                         reg = <0x1c 0x1>;
1312                 };
1313         };
1314
1315         pmucru: pmu-clock-controller@ff750000 {
1316                 compatible = "rockchip,rk3399-pmucru";
1317                 reg = <0x0 0xff750000 0x0 0x1000>;
1318                 #clock-cells = <1>;
1319                 #reset-cells = <1>;
1320                 assigned-clocks = <&pmucru PLL_PPLL>;
1321                 assigned-clock-rates = <676000000>;
1322         };
1323
1324         cru: clock-controller@ff760000 {
1325                 compatible = "rockchip,rk3399-cru";
1326                 reg = <0x0 0xff760000 0x0 0x1000>;
1327                 #clock-cells = <1>;
1328                 #reset-cells = <1>;
1329                 assigned-clocks =
1330                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1331                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1332                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1333                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1334                         <&cru PLL_NPLL>,
1335                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1336                         <&cru PCLK_PERIHP>,
1337                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1338                         <&cru PCLK_PERILP0>,
1339                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1340                 assigned-clock-rates =
1341                          <400000000>,  <200000000>,
1342                          <400000000>,  <200000000>,
1343                          <816000000>, <816000000>,
1344                          <594000000>,  <800000000>,
1345                         <1000000000>,
1346                          <150000000>,   <75000000>,
1347                           <37500000>,
1348                          <100000000>,  <100000000>,
1349                           <50000000>,
1350                          <100000000>,   <50000000>;
1351         };
1352
1353         grf: syscon@ff770000 {
1354                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1355                 reg = <0x0 0xff770000 0x0 0x10000>;
1356                 #address-cells = <1>;
1357                 #size-cells = <1>;
1358
1359                 emmc_phy: phy@f780 {
1360                         compatible = "rockchip,rk3399-emmc-phy";
1361                         reg = <0xf780 0x24>;
1362                         clocks = <&sdhci>;
1363                         clock-names = "emmcclk";
1364                         #phy-cells = <0>;
1365                         status = "disabled";
1366                 };
1367
1368                 u2phy0: usb2-phy@e450 {
1369                         compatible = "rockchip,rk3399-usb2phy";
1370                         reg = <0xe450 0x10>;
1371                         clocks = <&cru SCLK_USB2PHY0_REF>;
1372                         clock-names = "phyclk";
1373                         #clock-cells = <0>;
1374                         clock-output-names = "clk_usbphy0_480m";
1375                         status = "disabled";
1376
1377                         u2phy0_otg: otg-port {
1378                                 #phy-cells = <0>;
1379                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1380                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1381                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1382                                 interrupt-names = "otg-bvalid", "otg-id",
1383                                                   "linestate";
1384                                 status = "disabled";
1385                         };
1386
1387                         u2phy0_host: host-port {
1388                                 #phy-cells = <0>;
1389                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1390                                 interrupt-names = "linestate";
1391                                 status = "disabled";
1392                         };
1393                 };
1394
1395                 u2phy1: usb2-phy@e460 {
1396                         compatible = "rockchip,rk3399-usb2phy";
1397                         reg = <0xe460 0x10>;
1398                         clocks = <&cru SCLK_USB2PHY1_REF>;
1399                         clock-names = "phyclk";
1400                         #clock-cells = <0>;
1401                         clock-output-names = "clk_usbphy1_480m";
1402                         status = "disabled";
1403
1404                         u2phy1_otg: otg-port {
1405                                 #phy-cells = <0>;
1406                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1407                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1408                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1409                                 interrupt-names = "otg-bvalid", "otg-id",
1410                                                   "linestate";
1411                                 status = "disabled";
1412                         };
1413
1414                         u2phy1_host: host-port {
1415                                 #phy-cells = <0>;
1416                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1417                                 interrupt-names = "linestate";
1418                                 status = "disabled";
1419                         };
1420                 };
1421         };
1422
1423         tcphy0: phy@ff7c0000 {
1424                 compatible = "rockchip,rk3399-typec-phy";
1425                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1426                 rockchip,grf = <&grf>;
1427                 #phy-cells = <1>;
1428                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1429                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1430                 clock-names = "tcpdcore", "tcpdphy-ref";
1431                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1432                 assigned-clock-rates = <50000000>;
1433                 resets = <&cru SRST_UPHY0>,
1434                          <&cru SRST_UPHY0_PIPE_L00>,
1435                          <&cru SRST_P_UPHY0_TCPHY>;
1436                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1437                 rockchip,typec-conn-dir = <0xe580 0 16>;
1438                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1439                 rockchip,usb3-host-disable = <0x2434 0 16>;
1440                 rockchip,usb3-host-port = <0x2434 12 28>;
1441                 rockchip,external-psm = <0xe588 14 30>;
1442                 rockchip,pipe-status = <0xe5c0 0 0>;
1443                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1444                 status = "disabled";
1445
1446                 tcphy0_dp: dp-port {
1447                         #phy-cells = <0>;
1448                 };
1449
1450                 tcphy0_usb3: usb3-port {
1451                         #phy-cells = <0>;
1452                 };
1453         };
1454
1455         tcphy1: phy@ff800000 {
1456                 compatible = "rockchip,rk3399-typec-phy";
1457                 reg = <0x0 0xff800000 0x0 0x40000>;
1458                 rockchip,grf = <&grf>;
1459                 #phy-cells = <1>;
1460                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1461                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1462                 clock-names = "tcpdcore", "tcpdphy-ref";
1463                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1464                 assigned-clock-rates = <50000000>;
1465                 resets = <&cru SRST_UPHY1>,
1466                          <&cru SRST_UPHY1_PIPE_L00>,
1467                          <&cru SRST_P_UPHY1_TCPHY>;
1468                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1469                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1470                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1471                 rockchip,usb3-host-disable = <0x2444 0 16>;
1472                 rockchip,usb3-host-port = <0x2444 12 28>;
1473                 rockchip,external-psm = <0xe594 14 30>;
1474                 rockchip,pipe-status = <0xe5c0 16 16>;
1475                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1476                 status = "disabled";
1477
1478                 tcphy1_dp: dp-port {
1479                         #phy-cells = <0>;
1480                 };
1481
1482                 tcphy1_usb3: usb3-port {
1483                         #phy-cells = <0>;
1484                 };
1485         };
1486
1487         watchdog@ff848000 {
1488                 compatible = "snps,dw-wdt";
1489                 reg = <0x0 0xff848000 0x0 0x100>;
1490                 clocks = <&cru PCLK_WDT>;
1491                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1492         };
1493
1494         rktimer: rktimer@ff850000 {
1495                 compatible = "rockchip,rk3399-timer";
1496                 reg = <0x0 0xff850000 0x0 0x1000>;
1497                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1498                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1499                 clock-names = "pclk", "timer";
1500         };
1501
1502         spdif: spdif@ff870000 {
1503                 compatible = "rockchip,rk3399-spdif";
1504                 reg = <0x0 0xff870000 0x0 0x1000>;
1505                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1506                 dmas = <&dmac_bus 7>;
1507                 dma-names = "tx";
1508                 clock-names = "mclk", "hclk";
1509                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1510                 pinctrl-names = "default";
1511                 pinctrl-0 = <&spdif_bus>;
1512                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1513                 status = "disabled";
1514         };
1515
1516         i2s0: i2s@ff880000 {
1517                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1518                 reg = <0x0 0xff880000 0x0 0x1000>;
1519                 rockchip,grf = <&grf>;
1520                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1521                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1522                 dma-names = "tx", "rx";
1523                 clock-names = "i2s_clk", "i2s_hclk";
1524                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1525                 pinctrl-names = "default";
1526                 pinctrl-0 = <&i2s0_8ch_bus>;
1527                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1528                 status = "disabled";
1529         };
1530
1531         i2s1: i2s@ff890000 {
1532                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1533                 reg = <0x0 0xff890000 0x0 0x1000>;
1534                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1535                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1536                 dma-names = "tx", "rx";
1537                 clock-names = "i2s_clk", "i2s_hclk";
1538                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1539                 pinctrl-names = "default";
1540                 pinctrl-0 = <&i2s1_2ch_bus>;
1541                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1542                 status = "disabled";
1543         };
1544
1545         i2s2: i2s@ff8a0000 {
1546                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1547                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1548                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1549                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1550                 dma-names = "tx", "rx";
1551                 clock-names = "i2s_clk", "i2s_hclk";
1552                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1553                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1554                 status = "disabled";
1555         };
1556
1557         gpu: gpu@ff9a0000 {
1558                 compatible = "arm,malit860",
1559                              "arm,malit86x",
1560                              "arm,malit8xx",
1561                              "arm,mali-midgard";
1562
1563                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1564
1565                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1566                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1567                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1568                 interrupt-names = "GPU", "JOB", "MMU";
1569
1570                 clocks = <&cru ACLK_GPU>;
1571                 clock-names = "clk_mali";
1572                 #cooling-cells = <2>; /* min followed by max */
1573                 operating-points-v2 = <&gpu_opp_table>;
1574                 power-domains = <&power RK3399_PD_GPU>;
1575                 power-off-delay-ms = <200>;
1576                 status = "disabled";
1577
1578                 gpu_power_model: power_model {
1579                         compatible = "arm,mali-simple-power-model";
1580                         voltage = <900>;
1581                         frequency = <500>;
1582                         static-power = <300>;
1583                         dynamic-power = <396>;
1584                         ts = <32000 4700 (-80) 2>;
1585                         thermal-zone = "gpu-thermal";
1586                 };
1587         };
1588
1589         gpu_opp_table: gpu_opp_table {
1590                 compatible = "operating-points-v2";
1591                 opp-shared;
1592
1593                 opp@200000000 {
1594                         opp-hz = /bits/ 64 <200000000>;
1595                         opp-microvolt = <900000>;
1596                 };
1597                 opp@300000000 {
1598                         opp-hz = /bits/ 64 <300000000>;
1599                         opp-microvolt = <900000>;
1600                 };
1601                 opp@400000000 {
1602                         opp-hz = /bits/ 64 <400000000>;
1603                         opp-microvolt = <900000>;
1604                 };
1605
1606         };
1607
1608         vopl: vop@ff8f0000 {
1609                 compatible = "rockchip,rk3399-vop-lit";
1610                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1611                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1612                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1613                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1614                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1615                 reset-names = "axi", "ahb", "dclk";
1616                 power-domains = <&power RK3399_PD_VOPL>;
1617                 iommus = <&vopl_mmu>;
1618                 status = "disabled";
1619
1620                 vopl_out: port {
1621                         #address-cells = <1>;
1622                         #size-cells = <0>;
1623
1624                         vopl_out_mipi: endpoint@0 {
1625                                 reg = <0>;
1626                                 remote-endpoint = <&mipi_in_vopl>;
1627                         };
1628
1629                         vopl_out_edp: endpoint@1 {
1630                                 reg = <1>;
1631                                 remote-endpoint = <&edp_in_vopl>;
1632                         };
1633
1634                         vopl_out_hdmi: endpoint@2 {
1635                                 reg = <2>;
1636                                 remote-endpoint = <&hdmi_in_vopl>;
1637                         };
1638                 };
1639         };
1640
1641         vop1_pwm: voppwm@ff8f01a0 {
1642                 compatible = "rockchip,vop-pwm";
1643                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1644                 #pwm-cells = <3>;
1645                 pinctrl-names = "default";
1646                 pinctrl-0 = <&vop1_pwm_pin>;
1647                 clocks = <&cru SCLK_VOP1_PWM>;
1648                 clock-names = "pwm";
1649                 status = "disabled";
1650         };
1651
1652         vopl_mmu: iommu@ff8f3f00 {
1653                 compatible = "rockchip,iommu";
1654                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1655                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1656                 interrupt-names = "vopl_mmu";
1657                 #iommu-cells = <0>;
1658                 status = "disabled";
1659         };
1660
1661         vopb: vop@ff900000 {
1662                 compatible = "rockchip,rk3399-vop-big";
1663                 reg = <0x0 0xff900000 0x0 0x3efc>;
1664                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1665                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1666                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1667                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1668                 reset-names = "axi", "ahb", "dclk";
1669                 power-domains = <&power RK3399_PD_VOPB>;
1670                 iommus = <&vopb_mmu>;
1671                 status = "disabled";
1672
1673                 vopb_out: port {
1674                         #address-cells = <1>;
1675                         #size-cells = <0>;
1676
1677                         vopb_out_edp: endpoint@0 {
1678                                 reg = <0>;
1679                                 remote-endpoint = <&edp_in_vopb>;
1680                         };
1681
1682                         vopb_out_mipi: endpoint@1 {
1683                                 reg = <1>;
1684                                 remote-endpoint = <&mipi_in_vopb>;
1685                         };
1686
1687                         vopb_out_hdmi: endpoint@2 {
1688                                 reg = <2>;
1689                                 remote-endpoint = <&hdmi_in_vopb>;
1690                         };
1691                 };
1692         };
1693
1694         vop0_pwm: voppwm@ff9001a0 {
1695                 compatible = "rockchip,vop-pwm";
1696                 reg = <0x0 0xff9001a0 0x0 0x10>;
1697                 #pwm-cells = <3>;
1698                 pinctrl-names = "default";
1699                 pinctrl-0 = <&vop0_pwm_pin>;
1700                 clocks = <&cru SCLK_VOP0_PWM>;
1701                 clock-names = "pwm";
1702                 status = "disabled";
1703         };
1704
1705         vopb_mmu: iommu@ff903f00 {
1706                 compatible = "rockchip,iommu";
1707                 reg = <0x0 0xff903f00 0x0 0x100>;
1708                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1709                 interrupt-names = "vopb_mmu";
1710                 #iommu-cells = <0>;
1711                 status = "disabled";
1712         };
1713
1714         hdmi: hdmi@ff940000 {
1715                 compatible = "rockchip,rk3399-dw-hdmi";
1716                 reg = <0x0 0xff940000 0x0 0x20000>;
1717                 reg-io-width = <4>;
1718                 rockchip,grf = <&grf>;
1719                 power-domains = <&power RK3399_PD_HDCP>;
1720                 pinctrl-names = "default";
1721                 pinctrl-0 = <&hdmi_i2c_xfer>;
1722                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1723                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1724                 clock-names = "iahb", "isfr", "vpll", "grf";
1725                 status = "disabled";
1726
1727                 ports {
1728                         hdmi_in: port {
1729                                 #address-cells = <1>;
1730                                 #size-cells = <0>;
1731                                 hdmi_in_vopb: endpoint@0 {
1732                                         reg = <0>;
1733                                         remote-endpoint = <&vopb_out_hdmi>;
1734                                 };
1735                                 hdmi_in_vopl: endpoint@1 {
1736                                         reg = <1>;
1737                                         remote-endpoint = <&vopl_out_hdmi>;
1738                                 };
1739                         };
1740                 };
1741         };
1742
1743         mipi_dsi: mipi@ff960000 {
1744                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1745                 reg = <0x0 0xff960000 0x0 0x8000>;
1746                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1747                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1748                          <&cru SCLK_DPHY_TX0_CFG>;
1749                 clock-names = "ref", "pclk", "phy_cfg";
1750                 power-domains = <&power RK3399_PD_VIO>;
1751                 rockchip,grf = <&grf>;
1752                 #address-cells = <1>;
1753                 #size-cells = <0>;
1754                 status = "disabled";
1755
1756                 ports {
1757                         #address-cells = <1>;
1758                         #size-cells = <0>;
1759                         reg = <1>;
1760
1761                         mipi_in: port {
1762                                 #address-cells = <1>;
1763                                 #size-cells = <0>;
1764
1765                                 mipi_in_vopb: endpoint@0 {
1766                                         reg = <0>;
1767                                         remote-endpoint = <&vopb_out_mipi>;
1768                                 };
1769                                 mipi_in_vopl: endpoint@1 {
1770                                         reg = <1>;
1771                                         remote-endpoint = <&vopl_out_mipi>;
1772                                 };
1773                         };
1774                 };
1775         };
1776
1777         edp: edp@ff970000 {
1778                 compatible = "rockchip,rk3399-edp";
1779                 reg = <0x0 0xff970000 0x0 0x8000>;
1780                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1781                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1782                 clock-names = "dp", "pclk";
1783                 power-domains = <&power RK3399_PD_EDP>;
1784                 resets = <&cru SRST_P_EDP_CTRL>;
1785                 reset-names = "dp";
1786                 rockchip,grf = <&grf>;
1787                 status = "disabled";
1788                 pinctrl-names = "default";
1789                 pinctrl-0 = <&edp_hpd>;
1790
1791                 ports {
1792                         #address-cells = <1>;
1793                         #size-cells = <0>;
1794
1795                         edp_in: port@0 {
1796                                 reg = <0>;
1797                                 #address-cells = <1>;
1798                                 #size-cells = <0>;
1799
1800                                 edp_in_vopb: endpoint@0 {
1801                                         reg = <0>;
1802                                         remote-endpoint = <&vopb_out_edp>;
1803                                 };
1804
1805                                 edp_in_vopl: endpoint@1 {
1806                                         reg = <1>;
1807                                         remote-endpoint = <&vopl_out_edp>;
1808                                 };
1809                         };
1810                 };
1811         };
1812
1813         display_subsystem: display-subsystem {
1814                 compatible = "rockchip,display-subsystem";
1815                 ports = <&vopl_out>, <&vopb_out>;
1816                 status = "disabled";
1817         };
1818
1819         pinctrl: pinctrl {
1820                 compatible = "rockchip,rk3399-pinctrl";
1821                 rockchip,grf = <&grf>;
1822                 rockchip,pmu = <&pmugrf>;
1823                 #address-cells = <0x2>;
1824                 #size-cells = <0x2>;
1825                 ranges;
1826
1827                 gpio0: gpio0@ff720000 {
1828                         compatible = "rockchip,gpio-bank";
1829                         reg = <0x0 0xff720000 0x0 0x100>;
1830                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1831                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1832
1833                         gpio-controller;
1834                         #gpio-cells = <0x2>;
1835
1836                         interrupt-controller;
1837                         #interrupt-cells = <0x2>;
1838                 };
1839
1840                 gpio1: gpio1@ff730000 {
1841                         compatible = "rockchip,gpio-bank";
1842                         reg = <0x0 0xff730000 0x0 0x100>;
1843                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1844                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1845
1846                         gpio-controller;
1847                         #gpio-cells = <0x2>;
1848
1849                         interrupt-controller;
1850                         #interrupt-cells = <0x2>;
1851                 };
1852
1853                 gpio2: gpio2@ff780000 {
1854                         compatible = "rockchip,gpio-bank";
1855                         reg = <0x0 0xff780000 0x0 0x100>;
1856                         clocks = <&cru PCLK_GPIO2>;
1857                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1858
1859                         gpio-controller;
1860                         #gpio-cells = <0x2>;
1861
1862                         interrupt-controller;
1863                         #interrupt-cells = <0x2>;
1864                 };
1865
1866                 gpio3: gpio3@ff788000 {
1867                         compatible = "rockchip,gpio-bank";
1868                         reg = <0x0 0xff788000 0x0 0x100>;
1869                         clocks = <&cru PCLK_GPIO3>;
1870                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1871
1872                         gpio-controller;
1873                         #gpio-cells = <0x2>;
1874
1875                         interrupt-controller;
1876                         #interrupt-cells = <0x2>;
1877                 };
1878
1879                 gpio4: gpio4@ff790000 {
1880                         compatible = "rockchip,gpio-bank";
1881                         reg = <0x0 0xff790000 0x0 0x100>;
1882                         clocks = <&cru PCLK_GPIO4>;
1883                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1884
1885                         gpio-controller;
1886                         #gpio-cells = <0x2>;
1887
1888                         interrupt-controller;
1889                         #interrupt-cells = <0x2>;
1890                 };
1891
1892                 pcfg_pull_up: pcfg-pull-up {
1893                         bias-pull-up;
1894                 };
1895
1896                 pcfg_pull_down: pcfg-pull-down {
1897                         bias-pull-down;
1898                 };
1899
1900                 pcfg_pull_none: pcfg-pull-none {
1901                         bias-disable;
1902                 };
1903
1904                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1905                         bias-pull-up;
1906                         drive-strength = <20>;
1907                 };
1908
1909                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1910                         bias-disable;
1911                         drive-strength = <20>;
1912                 };
1913
1914                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1915                         bias-disable;
1916                         drive-strength = <18>;
1917                 };
1918
1919                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1920                         bias-disable;
1921                         drive-strength = <12>;
1922                 };
1923
1924                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1925                         bias-pull-up;
1926                         drive-strength = <8>;
1927                 };
1928
1929                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1930                         bias-pull-down;
1931                         drive-strength = <4>;
1932                 };
1933
1934                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1935                         bias-pull-up;
1936                         drive-strength = <2>;
1937                 };
1938
1939                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1940                         bias-pull-down;
1941                         drive-strength = <12>;
1942                 };
1943
1944                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1945                         bias-disable;
1946                         drive-strength = <13>;
1947                 };
1948
1949                 pcfg_output_high: pcfg-output-high {
1950                         output-high;
1951                 };
1952
1953                 pcfg_output_low: pcfg-output-low {
1954                         output-low;
1955                 };
1956
1957                 pcfg_input: pcfg-input {
1958                         input-enable;
1959                 };
1960
1961                 emmc {
1962                         emmc_pwr: emmc-pwr {
1963                                 rockchip,pins =
1964                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1965                         };
1966                 };
1967
1968                 gmac {
1969                         rgmii_pins: rgmii-pins {
1970                                 rockchip,pins =
1971                                         /* mac_txclk */
1972                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1973                                         /* mac_rxclk */
1974                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1975                                         /* mac_mdio */
1976                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1977                                         /* mac_txen */
1978                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1979                                         /* mac_clk */
1980                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1981                                         /* mac_rxdv */
1982                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1983                                         /* mac_mdc */
1984                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1985                                         /* mac_rxd1 */
1986                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1987                                         /* mac_rxd0 */
1988                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1989                                         /* mac_txd1 */
1990                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1991                                         /* mac_txd0 */
1992                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1993                                         /* mac_rxd3 */
1994                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1995                                         /* mac_rxd2 */
1996                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1997                                         /* mac_txd3 */
1998                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1999                                         /* mac_txd2 */
2000                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2001                         };
2002
2003                         rmii_pins: rmii-pins {
2004                                 rockchip,pins =
2005                                         /* mac_mdio */
2006                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2007                                         /* mac_txen */
2008                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2009                                         /* mac_clk */
2010                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2011                                         /* mac_rxer */
2012                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2013                                         /* mac_rxdv */
2014                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2015                                         /* mac_mdc */
2016                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2017                                         /* mac_rxd1 */
2018                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2019                                         /* mac_rxd0 */
2020                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2021                                         /* mac_txd1 */
2022                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2023                                         /* mac_txd0 */
2024                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2025                         };
2026                 };
2027
2028                 i2c0 {
2029                         i2c0_xfer: i2c0-xfer {
2030                                 rockchip,pins =
2031                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2032                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2033                         };
2034                 };
2035
2036                 i2c1 {
2037                         i2c1_xfer: i2c1-xfer {
2038                                 rockchip,pins =
2039                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2040                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2041                         };
2042                 };
2043
2044                 i2c2 {
2045                         i2c2_xfer: i2c2-xfer {
2046                                 rockchip,pins =
2047                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2048                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2049                         };
2050                 };
2051
2052                 i2c3 {
2053                         i2c3_xfer: i2c3-xfer {
2054                                 rockchip,pins =
2055                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2056                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2057                         };
2058
2059                         i2c3_gpio: i2c3_gpio {
2060                                 rockchip,pins =
2061                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2062                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2063                         };
2064
2065                 };
2066
2067                 i2c4 {
2068                         i2c4_xfer: i2c4-xfer {
2069                                 rockchip,pins =
2070                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2071                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2072                         };
2073                 };
2074
2075                 i2c5 {
2076                         i2c5_xfer: i2c5-xfer {
2077                                 rockchip,pins =
2078                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2079                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2080                         };
2081                 };
2082
2083                 i2c6 {
2084                         i2c6_xfer: i2c6-xfer {
2085                                 rockchip,pins =
2086                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2087                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2088                         };
2089                 };
2090
2091                 i2c7 {
2092                         i2c7_xfer: i2c7-xfer {
2093                                 rockchip,pins =
2094                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2095                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2096                         };
2097                 };
2098
2099                 i2c8 {
2100                         i2c8_xfer: i2c8-xfer {
2101                                 rockchip,pins =
2102                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2103                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2104                         };
2105                 };
2106
2107                 i2s0 {
2108                         i2s0_8ch_bus: i2s0-8ch-bus {
2109                                 rockchip,pins =
2110                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2111                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2112                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2113                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2114                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2115                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2116                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2117                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2118                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2119                         };
2120                 };
2121
2122                 i2s1 {
2123                         i2s1_2ch_bus: i2s1-2ch-bus {
2124                                 rockchip,pins =
2125                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2126                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2127                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2128                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2129                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2130                         };
2131                 };
2132
2133                 sdio0 {
2134                         sdio0_bus1: sdio0-bus1 {
2135                                 rockchip,pins =
2136                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2137                         };
2138
2139                         sdio0_bus4: sdio0-bus4 {
2140                                 rockchip,pins =
2141                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2142                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2143                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2144                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2145                         };
2146
2147                         sdio0_cmd: sdio0-cmd {
2148                                 rockchip,pins =
2149                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2150                         };
2151
2152                         sdio0_clk: sdio0-clk {
2153                                 rockchip,pins =
2154                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2155                         };
2156
2157                         sdio0_cd: sdio0-cd {
2158                                 rockchip,pins =
2159                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2160                         };
2161
2162                         sdio0_pwr: sdio0-pwr {
2163                                 rockchip,pins =
2164                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2165                         };
2166
2167                         sdio0_bkpwr: sdio0-bkpwr {
2168                                 rockchip,pins =
2169                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2170                         };
2171
2172                         sdio0_wp: sdio0-wp {
2173                                 rockchip,pins =
2174                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2175                         };
2176
2177                         sdio0_int: sdio0-int {
2178                                 rockchip,pins =
2179                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2180                         };
2181                 };
2182
2183                 sdmmc {
2184                         sdmmc_bus1: sdmmc-bus1 {
2185                                 rockchip,pins =
2186                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2187                         };
2188
2189                         sdmmc_bus4: sdmmc-bus4 {
2190                                 rockchip,pins =
2191                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2192                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2193                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2194                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2195                         };
2196
2197                         sdmmc_clk: sdmmc-clk {
2198                                 rockchip,pins =
2199                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2200                         };
2201
2202                         sdmmc_cmd: sdmmc-cmd {
2203                                 rockchip,pins =
2204                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2205                         };
2206
2207                         sdmmc_cd: sdmcc-cd {
2208                                 rockchip,pins =
2209                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2210                         };
2211
2212                         sdmmc_wp: sdmmc-wp {
2213                                 rockchip,pins =
2214                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2215                         };
2216                 };
2217
2218                 spdif {
2219                         spdif_bus: spdif-bus {
2220                                 rockchip,pins =
2221                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2222                         };
2223
2224                         spdif_bus_1: spdif-bus-1 {
2225                                 rockchip,pins =
2226                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2227                         };
2228                 };
2229
2230                 spi0 {
2231                         spi0_clk: spi0-clk {
2232                                 rockchip,pins =
2233                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2234                         };
2235                         spi0_cs0: spi0-cs0 {
2236                                 rockchip,pins =
2237                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2238                         };
2239                         spi0_cs1: spi0-cs1 {
2240                                 rockchip,pins =
2241                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2242                         };
2243                         spi0_tx: spi0-tx {
2244                                 rockchip,pins =
2245                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2246                         };
2247                         spi0_rx: spi0-rx {
2248                                 rockchip,pins =
2249                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2250                         };
2251                 };
2252
2253                 spi1 {
2254                         spi1_clk: spi1-clk {
2255                                 rockchip,pins =
2256                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2257                         };
2258                         spi1_cs0: spi1-cs0 {
2259                                 rockchip,pins =
2260                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2261                         };
2262                         spi1_rx: spi1-rx {
2263                                 rockchip,pins =
2264                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2265                         };
2266                         spi1_tx: spi1-tx {
2267                                 rockchip,pins =
2268                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2269                         };
2270                 };
2271
2272                 spi2 {
2273                         spi2_clk: spi2-clk {
2274                                 rockchip,pins =
2275                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2276                         };
2277                         spi2_cs0: spi2-cs0 {
2278                                 rockchip,pins =
2279                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2280                         };
2281                         spi2_rx: spi2-rx {
2282                                 rockchip,pins =
2283                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2284                         };
2285                         spi2_tx: spi2-tx {
2286                                 rockchip,pins =
2287                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2288                         };
2289                 };
2290
2291                 spi3 {
2292                         spi3_clk: spi3-clk {
2293                                 rockchip,pins =
2294                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2295                         };
2296                         spi3_cs0: spi3-cs0 {
2297                                 rockchip,pins =
2298                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2299                         };
2300                         spi3_rx: spi3-rx {
2301                                 rockchip,pins =
2302                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2303                         };
2304                         spi3_tx: spi3-tx {
2305                                 rockchip,pins =
2306                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2307                         };
2308                 };
2309
2310                 spi4 {
2311                         spi4_clk: spi4-clk {
2312                                 rockchip,pins =
2313                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2314                         };
2315                         spi4_cs0: spi4-cs0 {
2316                                 rockchip,pins =
2317                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2318                         };
2319                         spi4_rx: spi4-rx {
2320                                 rockchip,pins =
2321                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2322                         };
2323                         spi4_tx: spi4-tx {
2324                                 rockchip,pins =
2325                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2326                         };
2327                 };
2328
2329                 spi5 {
2330                         spi5_clk: spi5-clk {
2331                                 rockchip,pins =
2332                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2333                         };
2334                         spi5_cs0: spi5-cs0 {
2335                                 rockchip,pins =
2336                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2337                         };
2338                         spi5_rx: spi5-rx {
2339                                 rockchip,pins =
2340                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2341                         };
2342                         spi5_tx: spi5-tx {
2343                                 rockchip,pins =
2344                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2345                         };
2346                 };
2347
2348                 tsadc {
2349                         otp_gpio: otp-gpio {
2350                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2351                         };
2352
2353                         otp_out: otp-out {
2354                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2355                         };
2356                 };
2357
2358                 uart0 {
2359                         uart0_xfer: uart0-xfer {
2360                                 rockchip,pins =
2361                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2362                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2363                         };
2364
2365                         uart0_cts: uart0-cts {
2366                                 rockchip,pins =
2367                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2368                         };
2369
2370                         uart0_rts: uart0-rts {
2371                                 rockchip,pins =
2372                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2373                         };
2374                 };
2375
2376                 uart1 {
2377                         uart1_xfer: uart1-xfer {
2378                                 rockchip,pins =
2379                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2380                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2381                         };
2382                 };
2383
2384                 uart2a {
2385                         uart2a_xfer: uart2a-xfer {
2386                                 rockchip,pins =
2387                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2388                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2389                         };
2390                 };
2391
2392                 uart2b {
2393                         uart2b_xfer: uart2b-xfer {
2394                                 rockchip,pins =
2395                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2396                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2397                         };
2398                 };
2399
2400                 uart2c {
2401                         uart2c_xfer: uart2c-xfer {
2402                                 rockchip,pins =
2403                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2404                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2405                         };
2406                 };
2407
2408                 uart3 {
2409                         uart3_xfer: uart3-xfer {
2410                                 rockchip,pins =
2411                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2412                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2413                         };
2414
2415                         uart3_cts: uart3-cts {
2416                                 rockchip,pins =
2417                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2418                         };
2419
2420                         uart3_rts: uart3-rts {
2421                                 rockchip,pins =
2422                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2423                         };
2424                 };
2425
2426                 uart4 {
2427                         uart4_xfer: uart4-xfer {
2428                                 rockchip,pins =
2429                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2430                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2431                         };
2432                 };
2433
2434                 uarthdcp {
2435                         uarthdcp_xfer: uarthdcp-xfer {
2436                                 rockchip,pins =
2437                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2438                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2439                         };
2440                 };
2441
2442                 pwm0 {
2443                         pwm0_pin: pwm0-pin {
2444                                 rockchip,pins =
2445                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2446                         };
2447
2448                         vop0_pwm_pin: vop0-pwm-pin {
2449                                 rockchip,pins =
2450                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2451                         };
2452                 };
2453
2454                 pwm1 {
2455                         pwm1_pin: pwm1-pin {
2456                                 rockchip,pins =
2457                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2458                         };
2459
2460                         vop1_pwm_pin: vop1-pwm-pin {
2461                                 rockchip,pins =
2462                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2463                         };
2464                 };
2465
2466                 pwm2 {
2467                         pwm2_pin: pwm2-pin {
2468                                 rockchip,pins =
2469                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2470                         };
2471                 };
2472
2473                 pwm3a {
2474                         pwm3a_pin: pwm3a-pin {
2475                                 rockchip,pins =
2476                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2477                         };
2478                 };
2479
2480                 pwm3b {
2481                         pwm3b_pin: pwm3b-pin {
2482                                 rockchip,pins =
2483                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2484                         };
2485                 };
2486
2487                 edp {
2488                         edp_hpd: edp-hpd {
2489                                 rockchip,pins =
2490                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2491                         };
2492                 };
2493
2494                 hdmi {
2495                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2496                                 rockchip,pins =
2497                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2498                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2499                         };
2500
2501                         hdmi_cec: hdmi-cec {
2502                                 rockchip,pins =
2503                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2504                         };
2505                 };
2506
2507                 pcie {
2508                         pcie_clkreqn: pci-clkreqn {
2509                                 rockchip,pins =
2510                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2511                         };
2512
2513                         pcie_clkreqnb: pci-clkreqnb {
2514                                 rockchip,pins =
2515                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2516                         };
2517                 };
2518         };
2519 };