2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
52 #include "rk3399-dram-default-timing.dtsi"
55 compatible = "rockchip,rk3399";
57 interrupt-parent = <&gic>;
79 compatible = "arm,psci-1.0";
115 compatible = "arm,cortex-a53", "arm,armv8";
117 enable-method = "psci";
118 #cooling-cells = <2>; /* min followed by max */
119 dynamic-power-coefficient = <100>;
120 clocks = <&cru ARMCLKL>;
121 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
122 operating-points-v2 = <&cluster0_opp>;
123 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
128 compatible = "arm,cortex-a53", "arm,armv8";
130 enable-method = "psci";
131 clocks = <&cru ARMCLKL>;
132 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
133 operating-points-v2 = <&cluster0_opp>;
134 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
139 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 operating-points-v2 = <&cluster0_opp>;
145 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
150 compatible = "arm,cortex-a53", "arm,armv8";
152 enable-method = "psci";
153 clocks = <&cru ARMCLKL>;
154 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
155 operating-points-v2 = <&cluster0_opp>;
156 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
161 compatible = "arm,cortex-a72", "arm,armv8";
163 enable-method = "psci";
164 #cooling-cells = <2>; /* min followed by max */
165 dynamic-power-coefficient = <436>;
166 clocks = <&cru ARMCLKB>;
167 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
168 operating-points-v2 = <&cluster1_opp>;
169 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
174 compatible = "arm,cortex-a72", "arm,armv8";
176 enable-method = "psci";
177 clocks = <&cru ARMCLKB>;
178 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
179 operating-points-v2 = <&cluster1_opp>;
180 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
184 entry-method = "psci";
186 CPU_SLEEP: cpu-sleep {
187 compatible = "arm,idle-state";
189 arm,psci-suspend-param = <0x0010000>;
190 entry-latency-us = <120>;
191 exit-latency-us = <250>;
192 min-residency-us = <900>;
195 CLUSTER_SLEEP: cluster-sleep {
196 compatible = "arm,idle-state";
198 arm,psci-suspend-param = <0x1010000>;
199 entry-latency-us = <400>;
200 exit-latency-us = <500>;
201 min-residency-us = <2000>;
205 /include/ "rk3399-sched-energy.dtsi"
209 cluster0_opp: opp_table0 {
210 compatible = "operating-points-v2";
214 opp-hz = /bits/ 64 <408000000>;
215 opp-microvolt = <800000>;
216 clock-latency-ns = <40000>;
219 opp-hz = /bits/ 64 <600000000>;
220 opp-microvolt = <800000>;
221 clock-latency-ns = <40000>;
224 opp-hz = /bits/ 64 <816000000>;
225 opp-microvolt = <800000>;
226 clock-latency-ns = <40000>;
229 opp-hz = /bits/ 64 <1008000000>;
230 opp-microvolt = <875000>;
231 clock-latency-ns = <40000>;
234 opp-hz = /bits/ 64 <1200000000>;
235 opp-microvolt = <925000>;
236 clock-latency-ns = <40000>;
239 opp-hz = /bits/ 64 <1416000000>;
240 opp-microvolt = <1025000>;
241 clock-latency-ns = <40000>;
245 cluster1_opp: opp_table1 {
246 compatible = "operating-points-v2";
250 opp-hz = /bits/ 64 <408000000>;
251 opp-microvolt = <800000>;
252 clock-latency-ns = <40000>;
255 opp-hz = /bits/ 64 <600000000>;
256 opp-microvolt = <800000>;
257 clock-latency-ns = <40000>;
260 opp-hz = /bits/ 64 <816000000>;
261 opp-microvolt = <800000>;
262 clock-latency-ns = <40000>;
265 opp-hz = /bits/ 64 <1008000000>;
266 opp-microvolt = <850000>;
267 clock-latency-ns = <40000>;
270 opp-hz = /bits/ 64 <1200000000>;
271 opp-microvolt = <925000>;
272 clock-latency-ns = <40000>;
279 min-volt = <800000>; /* uV */
280 min-freq = <408000>; /* KHz */
281 leakage-adjust-volt = <
285 nvmem-cells = <&cpul_leakage>;
286 nvmem-cell-names = "cpu_leakage";
290 min-volt = <800000>; /* uV */
291 min-freq = <408000>; /* KHz */
292 leakage-adjust-volt = <
296 nvmem-cells = <&cpub_leakage>;
297 nvmem-cell-names = "cpu_leakage";
302 compatible = "arm,armv8-timer";
303 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
304 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
305 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
306 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
310 compatible = "arm,cortex-a53-pmu";
311 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
315 compatible = "arm,cortex-a72-pmu";
316 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
320 compatible = "fixed-clock";
322 clock-frequency = <24000000>;
323 clock-output-names = "xin24m";
327 compatible = "arm,amba-bus";
328 #address-cells = <2>;
332 dmac_bus: dma-controller@ff6d0000 {
333 compatible = "arm,pl330", "arm,primecell";
334 reg = <0x0 0xff6d0000 0x0 0x4000>;
335 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
336 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
338 clocks = <&cru ACLK_DMAC0_PERILP>;
339 clock-names = "apb_pclk";
340 peripherals-req-type-burst;
343 dmac_peri: dma-controller@ff6e0000 {
344 compatible = "arm,pl330", "arm,primecell";
345 reg = <0x0 0xff6e0000 0x0 0x4000>;
346 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
347 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
349 clocks = <&cru ACLK_DMAC1_PERILP>;
350 clock-names = "apb_pclk";
351 peripherals-req-type-burst;
356 compatible = "rockchip,rk3399-gmac";
357 reg = <0x0 0xfe300000 0x0 0x10000>;
358 rockchip,grf = <&grf>;
359 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
360 interrupt-names = "macirq";
361 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
362 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
363 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
365 clock-names = "stmmaceth", "mac_clk_rx",
366 "mac_clk_tx", "clk_mac_ref",
367 "clk_mac_refout", "aclk_mac",
369 resets = <&cru SRST_A_GMAC>;
370 reset-names = "stmmaceth";
371 power-domains = <&power RK3399_PD_GMAC>;
375 sdio0: dwmmc@fe310000 {
376 compatible = "rockchip,rk3399-dw-mshc",
377 "rockchip,rk3288-dw-mshc";
378 reg = <0x0 0xfe310000 0x0 0x4000>;
379 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
380 clock-freq-min-max = <400000 150000000>;
381 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
382 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
383 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
384 fifo-depth = <0x100>;
385 power-domains = <&power RK3399_PD_SDIOAUDIO>;
389 sdmmc: dwmmc@fe320000 {
390 compatible = "rockchip,rk3399-dw-mshc",
391 "rockchip,rk3288-dw-mshc";
392 reg = <0x0 0xfe320000 0x0 0x4000>;
393 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
394 clock-freq-min-max = <400000 150000000>;
395 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
396 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
397 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
398 fifo-depth = <0x100>;
399 power-domains = <&power RK3399_PD_SD>;
403 sdhci: sdhci@fe330000 {
404 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
405 reg = <0x0 0xfe330000 0x0 0x10000>;
406 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
407 arasan,soc-ctl-syscon = <&grf>;
408 assigned-clocks = <&cru SCLK_EMMC>;
409 assigned-clock-rates = <200000000>;
410 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
411 clock-names = "clk_xin", "clk_ahb";
412 clock-output-names = "emmc_cardclock";
415 phy-names = "phy_arasan";
416 power-domains = <&power RK3399_PD_EMMC>;
420 usb_host0_ehci: usb@fe380000 {
421 compatible = "generic-ehci";
422 reg = <0x0 0xfe380000 0x0 0x20000>;
423 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
424 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
425 <&cru SCLK_USBPHY0_480M_SRC>;
426 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
427 phys = <&u2phy0_host>;
429 power-domains = <&power RK3399_PD_PERIHP>;
433 usb_host0_ohci: usb@fe3a0000 {
434 compatible = "generic-ohci";
435 reg = <0x0 0xfe3a0000 0x0 0x20000>;
436 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
437 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
438 <&cru SCLK_USBPHY0_480M_SRC>;
439 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
440 phys = <&u2phy0_host>;
442 power-domains = <&power RK3399_PD_PERIHP>;
446 usb_host1_ehci: usb@fe3c0000 {
447 compatible = "generic-ehci";
448 reg = <0x0 0xfe3c0000 0x0 0x20000>;
449 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
450 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
451 <&cru SCLK_USBPHY1_480M_SRC>;
452 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
453 phys = <&u2phy1_host>;
455 power-domains = <&power RK3399_PD_PERIHP>;
459 usb_host1_ohci: usb@fe3e0000 {
460 compatible = "generic-ohci";
461 reg = <0x0 0xfe3e0000 0x0 0x20000>;
462 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
463 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
464 <&cru SCLK_USBPHY1_480M_SRC>;
465 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
466 phys = <&u2phy1_host>;
468 power-domains = <&power RK3399_PD_PERIHP>;
472 usbdrd3_0: usb@fe800000 {
473 compatible = "rockchip,rk3399-dwc3";
474 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
475 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
476 clock-names = "ref_clk", "suspend_clk",
477 "bus_clk", "grf_clk";
478 power-domains = <&power RK3399_PD_USB3>;
479 resets = <&cru SRST_A_USB3_OTG0>;
480 reset-names = "usb3-otg";
481 #address-cells = <2>;
485 usbdrd_dwc3_0: dwc3@fe800000 {
486 compatible = "snps,dwc3";
487 reg = <0x0 0xfe800000 0x0 0x100000>;
488 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
490 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
491 phy-names = "usb2-phy", "usb3-phy";
492 phy_type = "utmi_wide";
493 snps,dis_enblslpm_quirk;
494 snps,dis-u2-freeclk-exists-quirk;
495 snps,dis_u2_susphy_quirk;
496 snps,dis-del-phy-power-chg-quirk;
497 snps,xhci-slow-suspend-quirk;
502 usbdrd3_1: usb@fe900000 {
503 compatible = "rockchip,rk3399-dwc3";
504 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
505 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
506 clock-names = "ref_clk", "suspend_clk",
507 "bus_clk", "grf_clk";
508 power-domains = <&power RK3399_PD_USB3>;
509 resets = <&cru SRST_A_USB3_OTG1>;
510 reset-names = "usb3-otg";
511 #address-cells = <2>;
515 usbdrd_dwc3_1: dwc3@fe900000 {
516 compatible = "snps,dwc3";
517 reg = <0x0 0xfe900000 0x0 0x100000>;
518 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
520 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
521 phy-names = "usb2-phy", "usb3-phy";
522 phy_type = "utmi_wide";
523 snps,dis_enblslpm_quirk;
524 snps,dis-u2-freeclk-exists-quirk;
525 snps,dis_u2_susphy_quirk;
526 snps,dis-del-phy-power-chg-quirk;
527 snps,xhci-slow-suspend-quirk;
532 gic: interrupt-controller@fee00000 {
533 compatible = "arm,gic-v3";
534 #interrupt-cells = <4>;
535 #address-cells = <2>;
538 interrupt-controller;
540 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
541 <0x0 0xfef00000 0 0xc0000>, /* GICR */
542 <0x0 0xfff00000 0 0x10000>, /* GICC */
543 <0x0 0xfff10000 0 0x10000>, /* GICH */
544 <0x0 0xfff20000 0 0x10000>; /* GICV */
545 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
546 its: interrupt-controller@fee20000 {
547 compatible = "arm,gic-v3-its";
549 reg = <0x0 0xfee20000 0x0 0x20000>;
553 part0: interrupt-partition-0 {
554 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
557 part1: interrupt-partition-1 {
558 affinity = <&cpu_b0 &cpu_b1>;
563 saradc: saradc@ff100000 {
564 compatible = "rockchip,rk3399-saradc";
565 reg = <0x0 0xff100000 0x0 0x100>;
566 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
567 #io-channel-cells = <1>;
568 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
569 clock-names = "saradc", "apb_pclk";
570 resets = <&cru SRST_P_SARADC>;
571 reset-names = "saradc-apb";
576 compatible = "rockchip,rk3399-i2c";
577 reg = <0x0 0xff3c0000 0x0 0x1000>;
578 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
579 clock-names = "i2c", "pclk";
580 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&i2c0_xfer>;
583 #address-cells = <1>;
589 compatible = "rockchip,rk3399-i2c";
590 reg = <0x0 0xff110000 0x0 0x1000>;
591 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
592 clock-names = "i2c", "pclk";
593 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&i2c1_xfer>;
596 #address-cells = <1>;
602 compatible = "rockchip,rk3399-i2c";
603 reg = <0x0 0xff120000 0x0 0x1000>;
604 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
605 clock-names = "i2c", "pclk";
606 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
607 pinctrl-names = "default";
608 pinctrl-0 = <&i2c2_xfer>;
609 #address-cells = <1>;
615 compatible = "rockchip,rk3399-i2c";
616 reg = <0x0 0xff130000 0x0 0x1000>;
617 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
618 clock-names = "i2c", "pclk";
619 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&i2c3_xfer>;
622 #address-cells = <1>;
628 compatible = "rockchip,rk3399-i2c";
629 reg = <0x0 0xff140000 0x0 0x1000>;
630 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
631 clock-names = "i2c", "pclk";
632 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
633 pinctrl-names = "default";
634 pinctrl-0 = <&i2c5_xfer>;
635 #address-cells = <1>;
641 compatible = "rockchip,rk3399-i2c";
642 reg = <0x0 0xff150000 0x0 0x1000>;
643 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
644 clock-names = "i2c", "pclk";
645 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&i2c6_xfer>;
648 #address-cells = <1>;
654 compatible = "rockchip,rk3399-i2c";
655 reg = <0x0 0xff160000 0x0 0x1000>;
656 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
657 clock-names = "i2c", "pclk";
658 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&i2c7_xfer>;
661 #address-cells = <1>;
666 uart0: serial@ff180000 {
667 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
668 reg = <0x0 0xff180000 0x0 0x100>;
669 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
670 clock-names = "baudclk", "apb_pclk";
671 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
674 pinctrl-names = "default";
675 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
679 uart1: serial@ff190000 {
680 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
681 reg = <0x0 0xff190000 0x0 0x100>;
682 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
683 clock-names = "baudclk", "apb_pclk";
684 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
687 pinctrl-names = "default";
688 pinctrl-0 = <&uart1_xfer>;
692 uart2: serial@ff1a0000 {
693 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
694 reg = <0x0 0xff1a0000 0x0 0x100>;
695 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
696 clock-names = "baudclk", "apb_pclk";
697 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
700 pinctrl-names = "default";
701 pinctrl-0 = <&uart2c_xfer>;
705 uart3: serial@ff1b0000 {
706 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
707 reg = <0x0 0xff1b0000 0x0 0x100>;
708 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
709 clock-names = "baudclk", "apb_pclk";
710 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
713 pinctrl-names = "default";
714 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
719 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
720 reg = <0x0 0xff1c0000 0x0 0x1000>;
721 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
722 clock-names = "spiclk", "apb_pclk";
723 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
724 pinctrl-names = "default";
725 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
726 #address-cells = <1>;
732 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
733 reg = <0x0 0xff1d0000 0x0 0x1000>;
734 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
735 clock-names = "spiclk", "apb_pclk";
736 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
737 pinctrl-names = "default";
738 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
739 #address-cells = <1>;
745 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
746 reg = <0x0 0xff1e0000 0x0 0x1000>;
747 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
748 clock-names = "spiclk", "apb_pclk";
749 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
750 pinctrl-names = "default";
751 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
752 #address-cells = <1>;
758 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
759 reg = <0x0 0xff1f0000 0x0 0x1000>;
760 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
761 clock-names = "spiclk", "apb_pclk";
762 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
763 pinctrl-names = "default";
764 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
765 #address-cells = <1>;
771 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
772 reg = <0x0 0xff200000 0x0 0x1000>;
773 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
774 clock-names = "spiclk", "apb_pclk";
775 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
776 pinctrl-names = "default";
777 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
778 #address-cells = <1>;
784 soc_thermal: soc-thermal {
785 polling-delay-passive = <20>; /* milliseconds */
786 polling-delay = <1000>; /* milliseconds */
787 sustainable-power = <1000>; /* milliwatts */
789 thermal-sensors = <&tsadc 0>;
792 threshold: trip-point@0 {
793 temperature = <70000>; /* millicelsius */
794 hysteresis = <2000>; /* millicelsius */
797 target: trip-point@1 {
798 temperature = <85000>; /* millicelsius */
799 hysteresis = <2000>; /* millicelsius */
803 temperature = <95000>; /* millicelsius */
804 hysteresis = <2000>; /* millicelsius */
813 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
814 contribution = <4096>;
819 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
820 contribution = <1024>;
825 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
826 contribution = <4096>;
831 gpu_thermal: gpu-thermal {
832 polling-delay-passive = <100>; /* milliseconds */
833 polling-delay = <1000>; /* milliseconds */
835 thermal-sensors = <&tsadc 1>;
839 tsadc: tsadc@ff260000 {
840 compatible = "rockchip,rk3399-tsadc";
841 reg = <0x0 0xff260000 0x0 0x100>;
842 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
843 rockchip,grf = <&grf>;
844 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
845 clock-names = "tsadc", "apb_pclk";
846 assigned-clocks = <&cru SCLK_TSADC>;
847 assigned-clock-rates = <750000>;
848 resets = <&cru SRST_TSADC>;
849 reset-names = "tsadc-apb";
850 pinctrl-names = "init", "default", "sleep";
851 pinctrl-0 = <&otp_gpio>;
852 pinctrl-1 = <&otp_out>;
853 pinctrl-2 = <&otp_gpio>;
854 #thermal-sensor-cells = <1>;
855 rockchip,hw-tshut-temp = <95000>;
859 qos_emmc: qos@ffa58000 {
860 compatible = "syscon";
861 reg = <0x0 0xffa58000 0x0 0x20>;
864 qos_gmac: qos@ffa5c000 {
865 compatible = "syscon";
866 reg = <0x0 0xffa5c000 0x0 0x20>;
869 qos_pcie: qos@ffa60080 {
870 compatible = "syscon";
871 reg = <0x0 0xffa60080 0x0 0x20>;
874 qos_usb_host0: qos@ffa60100 {
875 compatible = "syscon";
876 reg = <0x0 0xffa60100 0x0 0x20>;
879 qos_usb_host1: qos@ffa60180 {
880 compatible = "syscon";
881 reg = <0x0 0xffa60180 0x0 0x20>;
884 qos_usb_otg0: qos@ffa70000 {
885 compatible = "syscon";
886 reg = <0x0 0xffa70000 0x0 0x20>;
889 qos_usb_otg1: qos@ffa70080 {
890 compatible = "syscon";
891 reg = <0x0 0xffa70080 0x0 0x20>;
894 qos_sd: qos@ffa74000 {
895 compatible = "syscon";
896 reg = <0x0 0xffa74000 0x0 0x20>;
899 qos_sdioaudio: qos@ffa76000 {
900 compatible = "syscon";
901 reg = <0x0 0xffa76000 0x0 0x20>;
904 qos_hdcp: qos@ffa90000 {
905 compatible = "syscon";
906 reg = <0x0 0xffa90000 0x0 0x20>;
909 qos_iep: qos@ffa98000 {
910 compatible = "syscon";
911 reg = <0x0 0xffa98000 0x0 0x20>;
914 qos_isp0_m0: qos@ffaa0000 {
915 compatible = "syscon";
916 reg = <0x0 0xffaa0000 0x0 0x20>;
919 qos_isp0_m1: qos@ffaa0080 {
920 compatible = "syscon";
921 reg = <0x0 0xffaa0080 0x0 0x20>;
924 qos_isp1_m0: qos@ffaa8000 {
925 compatible = "syscon";
926 reg = <0x0 0xffaa8000 0x0 0x20>;
929 qos_isp1_m1: qos@ffaa8080 {
930 compatible = "syscon";
931 reg = <0x0 0xffaa8080 0x0 0x20>;
934 qos_rga_r: qos@ffab0000 {
935 compatible = "syscon";
936 reg = <0x0 0xffab0000 0x0 0x20>;
939 qos_rga_w: qos@ffab0080 {
940 compatible = "syscon";
941 reg = <0x0 0xffab0080 0x0 0x20>;
944 qos_video_m0: qos@ffab8000 {
945 compatible = "syscon";
946 reg = <0x0 0xffab8000 0x0 0x20>;
949 qos_video_m1_r: qos@ffac0000 {
950 compatible = "syscon";
951 reg = <0x0 0xffac0000 0x0 0x20>;
954 qos_video_m1_w: qos@ffac0080 {
955 compatible = "syscon";
956 reg = <0x0 0xffac0080 0x0 0x20>;
959 qos_vop_big_r: qos@ffac8000 {
960 compatible = "syscon";
961 reg = <0x0 0xffac8000 0x0 0x20>;
964 qos_vop_big_w: qos@ffac8080 {
965 compatible = "syscon";
966 reg = <0x0 0xffac8080 0x0 0x20>;
969 qos_vop_little: qos@ffad0000 {
970 compatible = "syscon";
971 reg = <0x0 0xffad0000 0x0 0x20>;
974 qos_perihp: qos@ffad8080 {
975 compatible = "syscon";
976 reg = <0x0 0xffad8080 0x0 0x20>;
979 qos_gpu: qos@ffae0000 {
980 compatible = "syscon";
981 reg = <0x0 0xffae0000 0x0 0x20>;
984 pmu: power-management@ff310000 {
985 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
986 reg = <0x0 0xff310000 0x0 0x1000>;
989 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
990 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
991 * Some of the power domains are grouped together for every
993 * The detail contents as below.
995 power: power-controller {
996 compatible = "rockchip,rk3399-power-controller";
997 #power-domain-cells = <1>;
998 #address-cells = <1>;
1001 /* These power domains are grouped by VD_CENTER */
1002 pd_iep@RK3399_PD_IEP {
1003 reg = <RK3399_PD_IEP>;
1004 clocks = <&cru ACLK_IEP>,
1006 pm_qos = <&qos_iep>;
1008 pd_rga@RK3399_PD_RGA {
1009 reg = <RK3399_PD_RGA>;
1010 clocks = <&cru ACLK_RGA>,
1012 pm_qos = <&qos_rga_r>,
1015 pd_vcodec@RK3399_PD_VCODEC {
1016 reg = <RK3399_PD_VCODEC>;
1017 clocks = <&cru ACLK_VCODEC>,
1019 pm_qos = <&qos_video_m0>;
1021 pd_vdu@RK3399_PD_VDU {
1022 reg = <RK3399_PD_VDU>;
1023 clocks = <&cru ACLK_VDU>,
1025 pm_qos = <&qos_video_m1_r>,
1029 /* These power domains are grouped by VD_GPU */
1030 pd_gpu@RK3399_PD_GPU {
1031 reg = <RK3399_PD_GPU>;
1032 clocks = <&cru ACLK_GPU>;
1033 pm_qos = <&qos_gpu>;
1036 /* These power domains are grouped by VD_LOGIC */
1037 pd_edp@RK3399_PD_EDP {
1038 reg = <RK3399_PD_EDP>;
1039 clocks = <&cru PCLK_EDP_CTRL>;
1041 pd_emmc@RK3399_PD_EMMC {
1042 reg = <RK3399_PD_EMMC>;
1043 clocks = <&cru ACLK_EMMC>;
1044 pm_qos = <&qos_emmc>;
1046 pd_gmac@RK3399_PD_GMAC {
1047 reg = <RK3399_PD_GMAC>;
1048 clocks = <&cru ACLK_GMAC>;
1049 pm_qos = <&qos_gmac>;
1051 pd_perihp@RK3399_PD_PERIHP {
1052 reg = <RK3399_PD_PERIHP>;
1053 #address-cells = <1>;
1055 clocks = <&cru ACLK_PERIHP>;
1056 pm_qos = <&qos_perihp>,
1061 pd_sd@RK3399_PD_SD {
1062 reg = <RK3399_PD_SD>;
1063 clocks = <&cru HCLK_SDMMC>,
1068 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1069 reg = <RK3399_PD_SDIOAUDIO>;
1070 clocks = <&cru HCLK_SDIO>;
1071 pm_qos = <&qos_sdioaudio>;
1073 pd_usb3@RK3399_PD_USB3 {
1074 reg = <RK3399_PD_USB3>;
1075 clocks = <&cru ACLK_USB3>;
1076 pm_qos = <&qos_usb_otg0>,
1079 pd_vio@RK3399_PD_VIO {
1080 reg = <RK3399_PD_VIO>;
1081 #address-cells = <1>;
1084 pd_hdcp@RK3399_PD_HDCP {
1085 reg = <RK3399_PD_HDCP>;
1086 clocks = <&cru ACLK_HDCP>,
1089 pm_qos = <&qos_hdcp>;
1091 pd_isp0@RK3399_PD_ISP0 {
1092 reg = <RK3399_PD_ISP0>;
1093 clocks = <&cru ACLK_ISP0>,
1095 pm_qos = <&qos_isp0_m0>,
1098 pd_isp1@RK3399_PD_ISP1 {
1099 reg = <RK3399_PD_ISP1>;
1100 clocks = <&cru ACLK_ISP1>,
1102 pm_qos = <&qos_isp1_m0>,
1105 pd_tcpc0@RK3399_PD_TCPC0 {
1106 reg = <RK3399_PD_TCPD0>;
1107 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1108 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1110 pd_tcpc1@RK3399_PD_TCPC1 {
1111 reg = <RK3399_PD_TCPD1>;
1112 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1113 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1115 pd_vo@RK3399_PD_VO {
1116 reg = <RK3399_PD_VO>;
1117 #address-cells = <1>;
1120 pd_vopb@RK3399_PD_VOPB {
1121 reg = <RK3399_PD_VOPB>;
1122 clocks = <&cru ACLK_VOP0>,
1124 pm_qos = <&qos_vop_big_r>,
1127 pd_vopl@RK3399_PD_VOPL {
1128 reg = <RK3399_PD_VOPL>;
1129 clocks = <&cru ACLK_VOP1>,
1131 pm_qos = <&qos_vop_little>;
1138 pmugrf: syscon@ff320000 {
1139 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1140 reg = <0x0 0xff320000 0x0 0x1000>;
1143 compatible = "syscon-reboot-mode";
1145 mode-bootloader = <BOOT_LOADER>;
1146 mode-charge = <BOOT_CHARGING>;
1147 mode-fastboot = <BOOT_FASTBOOT>;
1148 mode-loader = <BOOT_LOADER>;
1149 mode-normal = <BOOT_NORMAL>;
1150 mode-recovery = <BOOT_RECOVERY>;
1151 mode-ums = <BOOT_UMS>;
1154 pmu_pvtm: pmu-pvtm {
1155 compatible = "rockchip,rk3399-pmu-pvtm";
1156 clocks = <&pmucru SCLK_PVTM_PMU>;
1157 clock-names = "pmu";
1158 status = "disabled";
1162 spi3: spi@ff350000 {
1163 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1164 reg = <0x0 0xff350000 0x0 0x1000>;
1165 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1166 clock-names = "spiclk", "apb_pclk";
1167 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1170 #address-cells = <1>;
1172 status = "disabled";
1175 uart4: serial@ff370000 {
1176 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1177 reg = <0x0 0xff370000 0x0 0x100>;
1178 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1179 clock-names = "baudclk", "apb_pclk";
1180 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1183 pinctrl-names = "default";
1184 pinctrl-0 = <&uart4_xfer>;
1185 status = "disabled";
1188 i2c4: i2c@ff3d0000 {
1189 compatible = "rockchip,rk3399-i2c";
1190 reg = <0x0 0xff3d0000 0x0 0x1000>;
1191 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1192 clock-names = "i2c", "pclk";
1193 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1194 pinctrl-names = "default";
1195 pinctrl-0 = <&i2c4_xfer>;
1196 #address-cells = <1>;
1198 status = "disabled";
1201 i2c8: i2c@ff3e0000 {
1202 compatible = "rockchip,rk3399-i2c";
1203 reg = <0x0 0xff3e0000 0x0 0x1000>;
1204 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1205 clock-names = "i2c", "pclk";
1206 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1207 pinctrl-names = "default";
1208 pinctrl-0 = <&i2c8_xfer>;
1209 #address-cells = <1>;
1211 status = "disabled";
1214 pcie_phy: phy@e220 {
1215 compatible = "rockchip,rk3399-pcie-phy";
1217 rockchip,grf = <&grf>;
1218 clocks = <&cru SCLK_PCIEPHY_REF>;
1219 clock-names = "refclk";
1220 resets = <&cru SRST_PCIEPHY>;
1221 reset-names = "phy";
1222 status = "disabled";
1225 pcie0: pcie@f8000000 {
1226 compatible = "rockchip,rk3399-pcie";
1227 #address-cells = <3>;
1229 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1230 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1231 clock-names = "aclk", "aclk-perf",
1233 bus-range = <0x0 0x1>;
1234 msi-map = <0x0 &its 0x0 0x1000>;
1235 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1236 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1237 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1238 interrupt-names = "sys", "legacy", "client";
1239 #interrupt-cells = <1>;
1240 interrupt-map-mask = <0 0 0 7>;
1241 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1242 <0 0 0 2 &pcie0_intc 1>,
1243 <0 0 0 3 &pcie0_intc 2>,
1244 <0 0 0 4 &pcie0_intc 3>;
1246 phy-names = "pcie-phy";
1247 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1248 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1249 reg = <0x0 0xf8000000 0x0 0x2000000>,
1250 <0x0 0xfd000000 0x0 0x1000000>;
1251 reg-names = "axi-base", "apb-base";
1252 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1253 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1254 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1256 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1257 "pm", "pclk", "aclk";
1258 status = "disabled";
1259 pcie0_intc: interrupt-controller {
1260 interrupt-controller;
1261 #address-cells = <0>;
1262 #interrupt-cells = <1>;
1266 pwm0: pwm@ff420000 {
1267 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1268 reg = <0x0 0xff420000 0x0 0x10>;
1270 pinctrl-names = "default";
1271 pinctrl-0 = <&pwm0_pin>;
1272 clocks = <&pmucru PCLK_RKPWM_PMU>;
1273 clock-names = "pwm";
1274 status = "disabled";
1277 pwm1: pwm@ff420010 {
1278 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1279 reg = <0x0 0xff420010 0x0 0x10>;
1281 pinctrl-names = "default";
1282 pinctrl-0 = <&pwm1_pin>;
1283 clocks = <&pmucru PCLK_RKPWM_PMU>;
1284 clock-names = "pwm";
1285 status = "disabled";
1288 pwm2: pwm@ff420020 {
1289 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1290 reg = <0x0 0xff420020 0x0 0x10>;
1292 pinctrl-names = "default";
1293 pinctrl-0 = <&pwm2_pin>;
1294 clocks = <&pmucru PCLK_RKPWM_PMU>;
1295 clock-names = "pwm";
1296 status = "disabled";
1299 pwm3: pwm@ff420030 {
1300 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1301 reg = <0x0 0xff420030 0x0 0x10>;
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&pwm3a_pin>;
1305 clocks = <&pmucru PCLK_RKPWM_PMU>;
1306 clock-names = "pwm";
1307 status = "disabled";
1311 reg = <0x00 0xff630000 0x00 0x4000>;
1312 compatible = "rockchip,rk3399-dfi";
1313 rockchip,pmu = <&pmugrf>;
1314 clocks = <&cru PCLK_DDR_MON>;
1315 clock-names = "pclk_ddr_mon";
1316 status = "disabled";
1320 compatible = "rockchip,rk3399-dmc";
1321 devfreq-events = <&dfi>;
1322 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1323 clocks = <&cru SCLK_DDRCLK>;
1324 clock-names = "dmc_clk";
1325 ddr_timing = <&ddr_timing>;
1326 operating-points-v2 = <&dmc_opp_table>;
1327 status = "disabled";
1330 dmc_opp_table: dmc_opp_table {
1331 compatible = "operating-points-v2";
1334 opp-hz = /bits/ 64 <666000000>;
1335 opp-microvolt = <900000>;
1340 compatible = "rockchip,rk3399-rga";
1341 reg = <0x0 0xff680000 0x0 0x10000>;
1342 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1343 interrupt-names = "rga";
1344 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1345 clock-names = "aclk", "hclk", "sclk";
1346 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1347 reset-names = "core", "axi", "ahb";
1348 power-domains = <&power RK3399_PD_RGA>;
1349 status = "disabled";
1352 efuse0: efuse@ff690000 {
1353 compatible = "rockchip,rk3399-efuse";
1354 reg = <0x0 0xff690000 0x0 0x80>;
1355 #address-cells = <1>;
1357 clocks = <&cru PCLK_EFUSE1024NS>;
1358 clock-names = "pclk_efuse";
1361 cpul_leakage: cpul-leakage {
1364 cpub_leakage: cpub-leakage {
1367 gpu_leakage: gpu-leakage {
1370 center_leakage: center-leakage {
1373 logic_leakage: logic-leakage {
1376 wafer_info: wafer-info {
1381 pmucru: pmu-clock-controller@ff750000 {
1382 compatible = "rockchip,rk3399-pmucru";
1383 reg = <0x0 0xff750000 0x0 0x1000>;
1386 assigned-clocks = <&pmucru PLL_PPLL>;
1387 assigned-clock-rates = <676000000>;
1390 cru: clock-controller@ff760000 {
1391 compatible = "rockchip,rk3399-cru";
1392 reg = <0x0 0xff760000 0x0 0x1000>;
1396 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1397 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1398 <&cru ARMCLKL>, <&cru ARMCLKB>,
1399 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1400 <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1401 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1403 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1404 <&cru PCLK_PERILP0>,
1405 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1406 assigned-clock-rates =
1407 <400000000>, <200000000>,
1408 <400000000>, <200000000>,
1409 <816000000>, <816000000>,
1410 <594000000>, <800000000>,
1411 <200000000>, <1000000000>,
1412 <150000000>, <75000000>,
1414 <100000000>, <100000000>,
1416 <100000000>, <50000000>;
1419 grf: syscon@ff770000 {
1420 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1421 reg = <0x0 0xff770000 0x0 0x10000>;
1422 #address-cells = <1>;
1425 emmc_phy: phy@f780 {
1426 compatible = "rockchip,rk3399-emmc-phy";
1427 reg = <0xf780 0x24>;
1429 clock-names = "emmcclk";
1431 status = "disabled";
1434 u2phy0: usb2-phy@e450 {
1435 compatible = "rockchip,rk3399-usb2phy";
1436 reg = <0xe450 0x10>;
1437 clocks = <&cru SCLK_USB2PHY0_REF>;
1438 clock-names = "phyclk";
1440 clock-output-names = "clk_usbphy0_480m";
1441 status = "disabled";
1443 u2phy0_otg: otg-port {
1445 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1446 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1447 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1448 interrupt-names = "otg-bvalid", "otg-id",
1450 status = "disabled";
1453 u2phy0_host: host-port {
1455 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1456 interrupt-names = "linestate";
1457 status = "disabled";
1461 u2phy1: usb2-phy@e460 {
1462 compatible = "rockchip,rk3399-usb2phy";
1463 reg = <0xe460 0x10>;
1464 clocks = <&cru SCLK_USB2PHY1_REF>;
1465 clock-names = "phyclk";
1467 clock-output-names = "clk_usbphy1_480m";
1468 status = "disabled";
1470 u2phy1_otg: otg-port {
1472 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1473 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1474 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1475 interrupt-names = "otg-bvalid", "otg-id",
1477 status = "disabled";
1480 u2phy1_host: host-port {
1482 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1483 interrupt-names = "linestate";
1484 status = "disabled";
1489 compatible = "rockchip,rk3399-pvtm";
1490 clocks = <&cru SCLK_PVTM_CORE_L>,
1491 <&cru SCLK_PVTM_CORE_B>,
1492 <&cru SCLK_PVTM_GPU>,
1493 <&cru SCLK_PVTM_DDR>;
1494 clock-names = "core_l", "core_b", "gpu", "ddr";
1495 status = "disabled";
1499 tcphy0: phy@ff7c0000 {
1500 compatible = "rockchip,rk3399-typec-phy";
1501 reg = <0x0 0xff7c0000 0x0 0x40000>;
1502 rockchip,grf = <&grf>;
1504 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1505 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1506 clock-names = "tcpdcore", "tcpdphy-ref";
1507 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1508 assigned-clock-rates = <50000000>;
1509 power-domains = <&power RK3399_PD_TCPD0>;
1510 resets = <&cru SRST_UPHY0>,
1511 <&cru SRST_UPHY0_PIPE_L00>,
1512 <&cru SRST_P_UPHY0_TCPHY>;
1513 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1514 rockchip,typec-conn-dir = <0xe580 0 16>;
1515 rockchip,usb3tousb2-en = <0xe580 3 19>;
1516 rockchip,usb3-host-disable = <0x2434 0 16>;
1517 rockchip,usb3-host-port = <0x2434 12 28>;
1518 rockchip,external-psm = <0xe588 14 30>;
1519 rockchip,pipe-status = <0xe5c0 0 0>;
1520 rockchip,uphy-dp-sel = <0x6268 19 19>;
1521 status = "disabled";
1523 tcphy0_dp: dp-port {
1527 tcphy0_usb3: usb3-port {
1532 tcphy1: phy@ff800000 {
1533 compatible = "rockchip,rk3399-typec-phy";
1534 reg = <0x0 0xff800000 0x0 0x40000>;
1535 rockchip,grf = <&grf>;
1537 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1538 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1539 clock-names = "tcpdcore", "tcpdphy-ref";
1540 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1541 assigned-clock-rates = <50000000>;
1542 power-domains = <&power RK3399_PD_TCPD1>;
1543 resets = <&cru SRST_UPHY1>,
1544 <&cru SRST_UPHY1_PIPE_L00>,
1545 <&cru SRST_P_UPHY1_TCPHY>;
1546 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1547 rockchip,typec-conn-dir = <0xe58c 0 16>;
1548 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1549 rockchip,usb3-host-disable = <0x2444 0 16>;
1550 rockchip,usb3-host-port = <0x2444 12 28>;
1551 rockchip,external-psm = <0xe594 14 30>;
1552 rockchip,pipe-status = <0xe5c0 16 16>;
1553 rockchip,uphy-dp-sel = <0x6268 3 19>;
1554 status = "disabled";
1556 tcphy1_dp: dp-port {
1560 tcphy1_usb3: usb3-port {
1566 compatible = "snps,dw-wdt";
1567 reg = <0x0 0xff848000 0x0 0x100>;
1568 clocks = <&cru PCLK_WDT>;
1569 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1572 rktimer: rktimer@ff850000 {
1573 compatible = "rockchip,rk3399-timer";
1574 reg = <0x0 0xff850000 0x0 0x1000>;
1575 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1576 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1577 clock-names = "pclk", "timer";
1580 spdif: spdif@ff870000 {
1581 compatible = "rockchip,rk3399-spdif";
1582 reg = <0x0 0xff870000 0x0 0x1000>;
1583 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1584 dmas = <&dmac_bus 7>;
1586 clock-names = "mclk", "hclk";
1587 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1588 pinctrl-names = "default";
1589 pinctrl-0 = <&spdif_bus>;
1590 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1591 status = "disabled";
1594 i2s0: i2s@ff880000 {
1595 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1596 reg = <0x0 0xff880000 0x0 0x1000>;
1597 rockchip,grf = <&grf>;
1598 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1599 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1600 dma-names = "tx", "rx";
1601 clock-names = "i2s_clk", "i2s_hclk";
1602 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1603 pinctrl-names = "default";
1604 pinctrl-0 = <&i2s0_8ch_bus>;
1605 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1606 status = "disabled";
1609 i2s1: i2s@ff890000 {
1610 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1611 reg = <0x0 0xff890000 0x0 0x1000>;
1612 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1613 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1614 dma-names = "tx", "rx";
1615 clock-names = "i2s_clk", "i2s_hclk";
1616 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1617 pinctrl-names = "default";
1618 pinctrl-0 = <&i2s1_2ch_bus>;
1619 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1620 status = "disabled";
1623 i2s2: i2s@ff8a0000 {
1624 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1625 reg = <0x0 0xff8a0000 0x0 0x1000>;
1626 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1627 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1628 dma-names = "tx", "rx";
1629 clock-names = "i2s_clk", "i2s_hclk";
1630 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1631 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1632 status = "disabled";
1636 compatible = "arm,malit860",
1641 reg = <0x0 0xff9a0000 0x0 0x10000>;
1643 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1644 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1645 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1646 interrupt-names = "GPU", "JOB", "MMU";
1648 clocks = <&cru ACLK_GPU>;
1649 clock-names = "clk_mali";
1650 #cooling-cells = <2>; /* min followed by max */
1651 operating-points-v2 = <&gpu_opp_table>;
1652 power-domains = <&power RK3399_PD_GPU>;
1653 power-off-delay-ms = <200>;
1654 status = "disabled";
1656 gpu_power_model: power_model {
1657 compatible = "arm,mali-simple-power-model";
1660 static-power = <300>;
1661 dynamic-power = <396>;
1662 ts = <32000 4700 (-80) 2>;
1663 thermal-zone = "gpu-thermal";
1667 gpu_opp_table: gpu_opp_table {
1668 compatible = "operating-points-v2";
1672 opp-hz = /bits/ 64 <200000000>;
1673 opp-microvolt = <900000>;
1676 opp-hz = /bits/ 64 <300000000>;
1677 opp-microvolt = <900000>;
1680 opp-hz = /bits/ 64 <400000000>;
1681 opp-microvolt = <900000>;
1686 vopl: vop@ff8f0000 {
1687 compatible = "rockchip,rk3399-vop-lit";
1688 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1689 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1690 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1691 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1692 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1693 reset-names = "axi", "ahb", "dclk";
1694 power-domains = <&power RK3399_PD_VOPL>;
1695 iommus = <&vopl_mmu>;
1696 status = "disabled";
1699 #address-cells = <1>;
1702 vopl_out_mipi: endpoint@0 {
1704 remote-endpoint = <&mipi_in_vopl>;
1707 vopl_out_edp: endpoint@1 {
1709 remote-endpoint = <&edp_in_vopl>;
1712 vopl_out_hdmi: endpoint@2 {
1714 remote-endpoint = <&hdmi_in_vopl>;
1719 vop1_pwm: voppwm@ff8f01a0 {
1720 compatible = "rockchip,vop-pwm";
1721 reg = <0x0 0xff8f01a0 0x0 0x10>;
1723 pinctrl-names = "default";
1724 pinctrl-0 = <&vop1_pwm_pin>;
1725 clocks = <&cru SCLK_VOP1_PWM>;
1726 clock-names = "pwm";
1727 status = "disabled";
1730 vopl_mmu: iommu@ff8f3f00 {
1731 compatible = "rockchip,iommu";
1732 reg = <0x0 0xff8f3f00 0x0 0x100>;
1733 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1734 interrupt-names = "vopl_mmu";
1736 status = "disabled";
1739 vopb: vop@ff900000 {
1740 compatible = "rockchip,rk3399-vop-big";
1741 reg = <0x0 0xff900000 0x0 0x3efc>;
1742 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1743 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1744 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1745 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1746 reset-names = "axi", "ahb", "dclk";
1747 power-domains = <&power RK3399_PD_VOPB>;
1748 iommus = <&vopb_mmu>;
1749 status = "disabled";
1752 #address-cells = <1>;
1755 vopb_out_edp: endpoint@0 {
1757 remote-endpoint = <&edp_in_vopb>;
1760 vopb_out_mipi: endpoint@1 {
1762 remote-endpoint = <&mipi_in_vopb>;
1765 vopb_out_hdmi: endpoint@2 {
1767 remote-endpoint = <&hdmi_in_vopb>;
1772 vop0_pwm: voppwm@ff9001a0 {
1773 compatible = "rockchip,vop-pwm";
1774 reg = <0x0 0xff9001a0 0x0 0x10>;
1776 pinctrl-names = "default";
1777 pinctrl-0 = <&vop0_pwm_pin>;
1778 clocks = <&cru SCLK_VOP0_PWM>;
1779 clock-names = "pwm";
1780 status = "disabled";
1783 vopb_mmu: iommu@ff903f00 {
1784 compatible = "rockchip,iommu";
1785 reg = <0x0 0xff903f00 0x0 0x100>;
1786 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1787 interrupt-names = "vopb_mmu";
1789 status = "disabled";
1792 hdmi: hdmi@ff940000 {
1793 compatible = "rockchip,rk3399-dw-hdmi";
1794 reg = <0x0 0xff940000 0x0 0x20000>;
1796 rockchip,grf = <&grf>;
1797 power-domains = <&power RK3399_PD_HDCP>;
1798 pinctrl-names = "default";
1799 pinctrl-0 = <&hdmi_i2c_xfer>;
1800 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1801 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1802 clock-names = "iahb", "isfr", "vpll", "grf";
1803 status = "disabled";
1807 #address-cells = <1>;
1809 hdmi_in_vopb: endpoint@0 {
1811 remote-endpoint = <&vopb_out_hdmi>;
1813 hdmi_in_vopl: endpoint@1 {
1815 remote-endpoint = <&vopl_out_hdmi>;
1821 mipi_dsi: mipi@ff960000 {
1822 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1823 reg = <0x0 0xff960000 0x0 0x8000>;
1824 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1825 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1826 <&cru SCLK_DPHY_TX0_CFG>;
1827 clock-names = "ref", "pclk", "phy_cfg";
1828 power-domains = <&power RK3399_PD_VIO>;
1829 rockchip,grf = <&grf>;
1830 #address-cells = <1>;
1832 status = "disabled";
1835 #address-cells = <1>;
1840 #address-cells = <1>;
1843 mipi_in_vopb: endpoint@0 {
1845 remote-endpoint = <&vopb_out_mipi>;
1847 mipi_in_vopl: endpoint@1 {
1849 remote-endpoint = <&vopl_out_mipi>;
1856 compatible = "rockchip,rk3399-edp";
1857 reg = <0x0 0xff970000 0x0 0x8000>;
1858 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1859 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1860 clock-names = "dp", "pclk";
1861 power-domains = <&power RK3399_PD_EDP>;
1862 resets = <&cru SRST_P_EDP_CTRL>;
1864 rockchip,grf = <&grf>;
1865 status = "disabled";
1866 pinctrl-names = "default";
1867 pinctrl-0 = <&edp_hpd>;
1870 #address-cells = <1>;
1875 #address-cells = <1>;
1878 edp_in_vopb: endpoint@0 {
1880 remote-endpoint = <&vopb_out_edp>;
1883 edp_in_vopl: endpoint@1 {
1885 remote-endpoint = <&vopl_out_edp>;
1891 display_subsystem: display-subsystem {
1892 compatible = "rockchip,display-subsystem";
1893 ports = <&vopl_out>, <&vopb_out>;
1894 status = "disabled";
1898 compatible = "rockchip,rk3399-pinctrl";
1899 rockchip,grf = <&grf>;
1900 rockchip,pmu = <&pmugrf>;
1901 #address-cells = <0x2>;
1902 #size-cells = <0x2>;
1905 gpio0: gpio0@ff720000 {
1906 compatible = "rockchip,gpio-bank";
1907 reg = <0x0 0xff720000 0x0 0x100>;
1908 clocks = <&pmucru PCLK_GPIO0_PMU>;
1909 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1912 #gpio-cells = <0x2>;
1914 interrupt-controller;
1915 #interrupt-cells = <0x2>;
1918 gpio1: gpio1@ff730000 {
1919 compatible = "rockchip,gpio-bank";
1920 reg = <0x0 0xff730000 0x0 0x100>;
1921 clocks = <&pmucru PCLK_GPIO1_PMU>;
1922 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1925 #gpio-cells = <0x2>;
1927 interrupt-controller;
1928 #interrupt-cells = <0x2>;
1931 gpio2: gpio2@ff780000 {
1932 compatible = "rockchip,gpio-bank";
1933 reg = <0x0 0xff780000 0x0 0x100>;
1934 clocks = <&cru PCLK_GPIO2>;
1935 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1938 #gpio-cells = <0x2>;
1940 interrupt-controller;
1941 #interrupt-cells = <0x2>;
1944 gpio3: gpio3@ff788000 {
1945 compatible = "rockchip,gpio-bank";
1946 reg = <0x0 0xff788000 0x0 0x100>;
1947 clocks = <&cru PCLK_GPIO3>;
1948 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1951 #gpio-cells = <0x2>;
1953 interrupt-controller;
1954 #interrupt-cells = <0x2>;
1957 gpio4: gpio4@ff790000 {
1958 compatible = "rockchip,gpio-bank";
1959 reg = <0x0 0xff790000 0x0 0x100>;
1960 clocks = <&cru PCLK_GPIO4>;
1961 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1964 #gpio-cells = <0x2>;
1966 interrupt-controller;
1967 #interrupt-cells = <0x2>;
1970 pcfg_pull_up: pcfg-pull-up {
1974 pcfg_pull_down: pcfg-pull-down {
1978 pcfg_pull_none: pcfg-pull-none {
1982 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1984 drive-strength = <20>;
1987 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1989 drive-strength = <20>;
1992 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1994 drive-strength = <18>;
1997 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1999 drive-strength = <12>;
2002 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2004 drive-strength = <8>;
2007 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2009 drive-strength = <4>;
2012 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2014 drive-strength = <2>;
2017 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2019 drive-strength = <12>;
2022 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2024 drive-strength = <13>;
2027 pcfg_output_high: pcfg-output-high {
2031 pcfg_output_low: pcfg-output-low {
2035 pcfg_input: pcfg-input {
2040 emmc_pwr: emmc-pwr {
2042 <0 5 RK_FUNC_1 &pcfg_pull_up>;
2047 rgmii_pins: rgmii-pins {
2050 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2052 <3 14 RK_FUNC_1 &pcfg_pull_none>,
2054 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2056 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2058 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2060 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2062 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2064 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2066 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2068 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2070 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2072 <3 3 RK_FUNC_1 &pcfg_pull_none>,
2074 <3 2 RK_FUNC_1 &pcfg_pull_none>,
2076 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2078 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2081 rmii_pins: rmii-pins {
2084 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2086 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2088 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2090 <3 10 RK_FUNC_1 &pcfg_pull_none>,
2092 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2094 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2096 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2098 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2100 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2102 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2107 i2c0_xfer: i2c0-xfer {
2109 <1 15 RK_FUNC_2 &pcfg_pull_none>,
2110 <1 16 RK_FUNC_2 &pcfg_pull_none>;
2115 i2c1_xfer: i2c1-xfer {
2117 <4 2 RK_FUNC_1 &pcfg_pull_none>,
2118 <4 1 RK_FUNC_1 &pcfg_pull_none>;
2123 i2c2_xfer: i2c2-xfer {
2125 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2126 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2131 i2c3_xfer: i2c3-xfer {
2133 <4 17 RK_FUNC_1 &pcfg_pull_none>,
2134 <4 16 RK_FUNC_1 &pcfg_pull_none>;
2137 i2c3_gpio: i2c3_gpio {
2139 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2140 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2146 i2c4_xfer: i2c4-xfer {
2148 <1 12 RK_FUNC_1 &pcfg_pull_none>,
2149 <1 11 RK_FUNC_1 &pcfg_pull_none>;
2154 i2c5_xfer: i2c5-xfer {
2156 <3 11 RK_FUNC_2 &pcfg_pull_none>,
2157 <3 10 RK_FUNC_2 &pcfg_pull_none>;
2162 i2c6_xfer: i2c6-xfer {
2164 <2 10 RK_FUNC_2 &pcfg_pull_none>,
2165 <2 9 RK_FUNC_2 &pcfg_pull_none>;
2170 i2c7_xfer: i2c7-xfer {
2172 <2 8 RK_FUNC_2 &pcfg_pull_none>,
2173 <2 7 RK_FUNC_2 &pcfg_pull_none>;
2178 i2c8_xfer: i2c8-xfer {
2180 <1 21 RK_FUNC_1 &pcfg_pull_none>,
2181 <1 20 RK_FUNC_1 &pcfg_pull_none>;
2186 i2s0_8ch_bus: i2s0-8ch-bus {
2188 <3 24 RK_FUNC_1 &pcfg_pull_none>,
2189 <3 25 RK_FUNC_1 &pcfg_pull_none>,
2190 <3 26 RK_FUNC_1 &pcfg_pull_none>,
2191 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2192 <3 28 RK_FUNC_1 &pcfg_pull_none>,
2193 <3 29 RK_FUNC_1 &pcfg_pull_none>,
2194 <3 30 RK_FUNC_1 &pcfg_pull_none>,
2195 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2196 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2201 i2s1_2ch_bus: i2s1-2ch-bus {
2203 <4 3 RK_FUNC_1 &pcfg_pull_none>,
2204 <4 4 RK_FUNC_1 &pcfg_pull_none>,
2205 <4 5 RK_FUNC_1 &pcfg_pull_none>,
2206 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2207 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2212 sdio0_bus1: sdio0-bus1 {
2214 <2 20 RK_FUNC_1 &pcfg_pull_up>;
2217 sdio0_bus4: sdio0-bus4 {
2219 <2 20 RK_FUNC_1 &pcfg_pull_up>,
2220 <2 21 RK_FUNC_1 &pcfg_pull_up>,
2221 <2 22 RK_FUNC_1 &pcfg_pull_up>,
2222 <2 23 RK_FUNC_1 &pcfg_pull_up>;
2225 sdio0_cmd: sdio0-cmd {
2227 <2 24 RK_FUNC_1 &pcfg_pull_up>;
2230 sdio0_clk: sdio0-clk {
2232 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2235 sdio0_cd: sdio0-cd {
2237 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2240 sdio0_pwr: sdio0-pwr {
2242 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2245 sdio0_bkpwr: sdio0-bkpwr {
2247 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2250 sdio0_wp: sdio0-wp {
2252 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2255 sdio0_int: sdio0-int {
2257 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2262 sdmmc_bus1: sdmmc-bus1 {
2264 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2267 sdmmc_bus4: sdmmc-bus4 {
2269 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2270 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2271 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2272 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2275 sdmmc_clk: sdmmc-clk {
2277 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2280 sdmmc_cmd: sdmmc-cmd {
2282 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2285 sdmmc_cd: sdmcc-cd {
2287 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2290 sdmmc_wp: sdmmc-wp {
2292 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2297 spdif_bus: spdif-bus {
2299 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2302 spdif_bus_1: spdif-bus-1 {
2304 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2309 spi0_clk: spi0-clk {
2311 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2313 spi0_cs0: spi0-cs0 {
2315 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2317 spi0_cs1: spi0-cs1 {
2319 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2323 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2327 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2332 spi1_clk: spi1-clk {
2334 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2336 spi1_cs0: spi1-cs0 {
2338 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2342 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2346 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2351 spi2_clk: spi2-clk {
2353 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2355 spi2_cs0: spi2-cs0 {
2357 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2361 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2365 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2370 spi3_clk: spi3-clk {
2372 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2374 spi3_cs0: spi3-cs0 {
2376 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2380 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2384 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2389 spi4_clk: spi4-clk {
2391 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2393 spi4_cs0: spi4-cs0 {
2395 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2399 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2403 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2408 spi5_clk: spi5-clk {
2410 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2412 spi5_cs0: spi5-cs0 {
2414 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2418 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2422 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2427 otp_gpio: otp-gpio {
2428 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2432 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2437 uart0_xfer: uart0-xfer {
2439 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2440 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2443 uart0_cts: uart0-cts {
2445 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2448 uart0_rts: uart0-rts {
2450 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2455 uart1_xfer: uart1-xfer {
2457 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2458 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2463 uart2a_xfer: uart2a-xfer {
2465 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2466 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2471 uart2b_xfer: uart2b-xfer {
2473 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2474 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2479 uart2c_xfer: uart2c-xfer {
2481 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2482 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2487 uart3_xfer: uart3-xfer {
2489 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2490 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2493 uart3_cts: uart3-cts {
2495 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2498 uart3_rts: uart3-rts {
2500 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2505 uart4_xfer: uart4-xfer {
2507 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2508 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2513 uarthdcp_xfer: uarthdcp-xfer {
2515 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2516 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2521 pwm0_pin: pwm0-pin {
2523 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2526 vop0_pwm_pin: vop0-pwm-pin {
2528 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2533 pwm1_pin: pwm1-pin {
2535 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2538 vop1_pwm_pin: vop1-pwm-pin {
2540 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2545 pwm2_pin: pwm2-pin {
2547 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2552 pwm3a_pin: pwm3a-pin {
2554 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2559 pwm3b_pin: pwm3b-pin {
2561 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2568 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2573 hdmi_i2c_xfer: hdmi-i2c-xfer {
2575 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2576 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2579 hdmi_cec: hdmi-cec {
2581 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2586 pcie_clkreqn: pci-clkreqn {
2588 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2591 pcie_clkreqnb: pci-clkreqnb {
2593 <4 24 RK_FUNC_1 &pcfg_pull_none>;