2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
52 #include "rk3399-dram-default-timing.dtsi"
55 compatible = "rockchip,rk3399";
57 interrupt-parent = <&gic>;
79 compatible = "arm,psci-1.0";
115 compatible = "arm,cortex-a53", "arm,armv8";
117 enable-method = "psci";
118 #cooling-cells = <2>; /* min followed by max */
119 dynamic-power-coefficient = <100>;
120 clocks = <&cru ARMCLKL>;
121 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
126 compatible = "arm,cortex-a53", "arm,armv8";
128 enable-method = "psci";
129 clocks = <&cru ARMCLKL>;
130 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
135 compatible = "arm,cortex-a53", "arm,armv8";
137 enable-method = "psci";
138 clocks = <&cru ARMCLKL>;
139 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 compatible = "arm,cortex-a53", "arm,armv8";
146 enable-method = "psci";
147 clocks = <&cru ARMCLKL>;
148 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
153 compatible = "arm,cortex-a72", "arm,armv8";
155 enable-method = "psci";
156 #cooling-cells = <2>; /* min followed by max */
157 dynamic-power-coefficient = <436>;
158 clocks = <&cru ARMCLKB>;
159 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
164 compatible = "arm,cortex-a72", "arm,armv8";
166 enable-method = "psci";
167 clocks = <&cru ARMCLKB>;
168 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
172 entry-method = "psci";
174 CPU_SLEEP: cpu-sleep {
175 compatible = "arm,idle-state";
177 arm,psci-suspend-param = <0x0010000>;
178 entry-latency-us = <120>;
179 exit-latency-us = <250>;
180 min-residency-us = <900>;
183 CLUSTER_SLEEP: cluster-sleep {
184 compatible = "arm,idle-state";
186 arm,psci-suspend-param = <0x1010000>;
187 entry-latency-us = <400>;
188 exit-latency-us = <500>;
189 min-residency-us = <2000>;
197 min-volt = <800000>; /* uV */
198 min-freq = <408000>; /* KHz */
199 leakage-adjust-volt = <
203 nvmem-cells = <&cpul_leakage>;
204 nvmem-cell-names = "cpu_leakage";
208 min-volt = <800000>; /* uV */
209 min-freq = <408000>; /* KHz */
210 leakage-adjust-volt = <
214 nvmem-cells = <&cpub_leakage>;
215 nvmem-cell-names = "cpu_leakage";
220 compatible = "arm,armv8-timer";
221 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
222 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
223 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
224 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
228 compatible = "arm,cortex-a53-pmu";
229 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
233 compatible = "arm,cortex-a72-pmu";
234 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
238 compatible = "fixed-clock";
240 clock-frequency = <24000000>;
241 clock-output-names = "xin24m";
245 compatible = "arm,amba-bus";
246 #address-cells = <2>;
250 dmac_bus: dma-controller@ff6d0000 {
251 compatible = "arm,pl330", "arm,primecell";
252 reg = <0x0 0xff6d0000 0x0 0x4000>;
253 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
254 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
256 clocks = <&cru ACLK_DMAC0_PERILP>;
257 clock-names = "apb_pclk";
258 peripherals-req-type-burst;
261 dmac_peri: dma-controller@ff6e0000 {
262 compatible = "arm,pl330", "arm,primecell";
263 reg = <0x0 0xff6e0000 0x0 0x4000>;
264 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
265 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
267 clocks = <&cru ACLK_DMAC1_PERILP>;
268 clock-names = "apb_pclk";
269 peripherals-req-type-burst;
274 compatible = "rockchip,rk3399-gmac";
275 reg = <0x0 0xfe300000 0x0 0x10000>;
276 rockchip,grf = <&grf>;
277 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
278 interrupt-names = "macirq";
279 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
280 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
281 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
283 clock-names = "stmmaceth", "mac_clk_rx",
284 "mac_clk_tx", "clk_mac_ref",
285 "clk_mac_refout", "aclk_mac",
287 resets = <&cru SRST_A_GMAC>;
288 reset-names = "stmmaceth";
289 power-domains = <&power RK3399_PD_GMAC>;
293 sdio0: dwmmc@fe310000 {
294 compatible = "rockchip,rk3399-dw-mshc",
295 "rockchip,rk3288-dw-mshc";
296 reg = <0x0 0xfe310000 0x0 0x4000>;
297 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
298 clock-freq-min-max = <400000 150000000>;
299 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
300 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
301 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
302 fifo-depth = <0x100>;
303 power-domains = <&power RK3399_PD_SDIOAUDIO>;
307 sdmmc: dwmmc@fe320000 {
308 compatible = "rockchip,rk3399-dw-mshc",
309 "rockchip,rk3288-dw-mshc";
310 reg = <0x0 0xfe320000 0x0 0x4000>;
311 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
312 clock-freq-min-max = <400000 150000000>;
313 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
314 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
315 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
316 fifo-depth = <0x100>;
317 power-domains = <&power RK3399_PD_SD>;
321 sdhci: sdhci@fe330000 {
322 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
323 reg = <0x0 0xfe330000 0x0 0x10000>;
324 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
325 arasan,soc-ctl-syscon = <&grf>;
326 assigned-clocks = <&cru SCLK_EMMC>;
327 assigned-clock-rates = <200000000>;
328 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
329 clock-names = "clk_xin", "clk_ahb";
330 clock-output-names = "emmc_cardclock";
333 phy-names = "phy_arasan";
334 power-domains = <&power RK3399_PD_EMMC>;
338 usb_host0_ehci: usb@fe380000 {
339 compatible = "generic-ehci";
340 reg = <0x0 0xfe380000 0x0 0x20000>;
341 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
342 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
343 <&cru SCLK_USBPHY0_480M_SRC>;
344 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
345 phys = <&u2phy0_host>;
347 power-domains = <&power RK3399_PD_PERIHP>;
351 usb_host0_ohci: usb@fe3a0000 {
352 compatible = "generic-ohci";
353 reg = <0x0 0xfe3a0000 0x0 0x20000>;
354 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
355 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
356 <&cru SCLK_USBPHY0_480M_SRC>;
357 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
358 phys = <&u2phy0_host>;
360 power-domains = <&power RK3399_PD_PERIHP>;
364 usb_host1_ehci: usb@fe3c0000 {
365 compatible = "generic-ehci";
366 reg = <0x0 0xfe3c0000 0x0 0x20000>;
367 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
368 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
369 <&cru SCLK_USBPHY1_480M_SRC>;
370 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
371 phys = <&u2phy1_host>;
373 power-domains = <&power RK3399_PD_PERIHP>;
377 usb_host1_ohci: usb@fe3e0000 {
378 compatible = "generic-ohci";
379 reg = <0x0 0xfe3e0000 0x0 0x20000>;
380 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
381 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
382 <&cru SCLK_USBPHY1_480M_SRC>;
383 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
384 phys = <&u2phy1_host>;
386 power-domains = <&power RK3399_PD_PERIHP>;
390 usbdrd3_0: usb@fe800000 {
391 compatible = "rockchip,rk3399-dwc3";
392 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
393 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
394 clock-names = "ref_clk", "suspend_clk",
395 "bus_clk", "grf_clk";
396 power-domains = <&power RK3399_PD_USB3>;
397 resets = <&cru SRST_A_USB3_OTG0>;
398 reset-names = "usb3-otg";
399 #address-cells = <2>;
403 usbdrd_dwc3_0: dwc3@fe800000 {
404 compatible = "snps,dwc3";
405 reg = <0x0 0xfe800000 0x0 0x100000>;
406 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
408 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
409 phy-names = "usb2-phy", "usb3-phy";
410 phy_type = "utmi_wide";
411 snps,dis_enblslpm_quirk;
412 snps,dis-u2-freeclk-exists-quirk;
413 snps,dis_u2_susphy_quirk;
414 snps,dis-del-phy-power-chg-quirk;
415 snps,xhci-slow-suspend-quirk;
420 usbdrd3_1: usb@fe900000 {
421 compatible = "rockchip,rk3399-dwc3";
422 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
423 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
424 clock-names = "ref_clk", "suspend_clk",
425 "bus_clk", "grf_clk";
426 power-domains = <&power RK3399_PD_USB3>;
427 resets = <&cru SRST_A_USB3_OTG1>;
428 reset-names = "usb3-otg";
429 #address-cells = <2>;
433 usbdrd_dwc3_1: dwc3@fe900000 {
434 compatible = "snps,dwc3";
435 reg = <0x0 0xfe900000 0x0 0x100000>;
436 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
438 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
439 phy-names = "usb2-phy", "usb3-phy";
440 phy_type = "utmi_wide";
441 snps,dis_enblslpm_quirk;
442 snps,dis-u2-freeclk-exists-quirk;
443 snps,dis_u2_susphy_quirk;
444 snps,dis-del-phy-power-chg-quirk;
445 snps,xhci-slow-suspend-quirk;
450 cdn_dp: dp@fec00000 {
451 compatible = "rockchip,rk3399-cdn-dp";
452 reg = <0x0 0xfec00000 0x0 0x100000>;
453 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
455 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
456 clock-names = "core-clk", "pclk", "spdif", "grf";
457 assigned-clocks = <&cru SCLK_DP_CORE>;
458 assigned-clock-rates = <100000000>;
459 power-domains = <&power RK3399_PD_HDCP>;
460 phys = <&tcphy0_dp>, <&tcphy1_dp>;
461 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
462 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
463 reset-names = "spdif", "dptx", "apb", "core";
464 rockchip,grf = <&grf>;
465 #address-cells = <1>;
467 #sound-dai-cells = <1>;
471 #address-cells = <1>;
475 #address-cells = <1>;
477 dp_in_vopb: endpoint@0 {
479 remote-endpoint = <&vopb_out_dp>;
482 dp_in_vopl: endpoint@1 {
484 remote-endpoint = <&vopl_out_dp>;
490 gic: interrupt-controller@fee00000 {
491 compatible = "arm,gic-v3";
492 #interrupt-cells = <4>;
493 #address-cells = <2>;
496 interrupt-controller;
498 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
499 <0x0 0xfef00000 0 0xc0000>, /* GICR */
500 <0x0 0xfff00000 0 0x10000>, /* GICC */
501 <0x0 0xfff10000 0 0x10000>, /* GICH */
502 <0x0 0xfff20000 0 0x10000>; /* GICV */
503 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
504 its: interrupt-controller@fee20000 {
505 compatible = "arm,gic-v3-its";
507 reg = <0x0 0xfee20000 0x0 0x20000>;
511 part0: interrupt-partition-0 {
512 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
515 part1: interrupt-partition-1 {
516 affinity = <&cpu_b0 &cpu_b1>;
521 saradc: saradc@ff100000 {
522 compatible = "rockchip,rk3399-saradc";
523 reg = <0x0 0xff100000 0x0 0x100>;
524 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
525 #io-channel-cells = <1>;
526 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
527 clock-names = "saradc", "apb_pclk";
528 resets = <&cru SRST_P_SARADC>;
529 reset-names = "saradc-apb";
534 compatible = "rockchip,rk3399-i2c";
535 reg = <0x0 0xff3c0000 0x0 0x1000>;
536 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
537 clock-names = "i2c", "pclk";
538 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&i2c0_xfer>;
541 #address-cells = <1>;
547 compatible = "rockchip,rk3399-i2c";
548 reg = <0x0 0xff110000 0x0 0x1000>;
549 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
550 clock-names = "i2c", "pclk";
551 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&i2c1_xfer>;
554 #address-cells = <1>;
560 compatible = "rockchip,rk3399-i2c";
561 reg = <0x0 0xff120000 0x0 0x1000>;
562 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
563 clock-names = "i2c", "pclk";
564 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&i2c2_xfer>;
567 #address-cells = <1>;
573 compatible = "rockchip,rk3399-i2c";
574 reg = <0x0 0xff130000 0x0 0x1000>;
575 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
576 clock-names = "i2c", "pclk";
577 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
578 pinctrl-names = "default";
579 pinctrl-0 = <&i2c3_xfer>;
580 #address-cells = <1>;
586 compatible = "rockchip,rk3399-i2c";
587 reg = <0x0 0xff140000 0x0 0x1000>;
588 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
589 clock-names = "i2c", "pclk";
590 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
591 pinctrl-names = "default";
592 pinctrl-0 = <&i2c5_xfer>;
593 #address-cells = <1>;
599 compatible = "rockchip,rk3399-i2c";
600 reg = <0x0 0xff150000 0x0 0x1000>;
601 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
602 clock-names = "i2c", "pclk";
603 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&i2c6_xfer>;
606 #address-cells = <1>;
612 compatible = "rockchip,rk3399-i2c";
613 reg = <0x0 0xff160000 0x0 0x1000>;
614 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
615 clock-names = "i2c", "pclk";
616 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&i2c7_xfer>;
619 #address-cells = <1>;
624 uart0: serial@ff180000 {
625 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
626 reg = <0x0 0xff180000 0x0 0x100>;
627 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
628 clock-names = "baudclk", "apb_pclk";
629 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
632 pinctrl-names = "default";
633 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
637 uart1: serial@ff190000 {
638 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
639 reg = <0x0 0xff190000 0x0 0x100>;
640 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
641 clock-names = "baudclk", "apb_pclk";
642 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
645 pinctrl-names = "default";
646 pinctrl-0 = <&uart1_xfer>;
650 uart2: serial@ff1a0000 {
651 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
652 reg = <0x0 0xff1a0000 0x0 0x100>;
653 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
654 clock-names = "baudclk", "apb_pclk";
655 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
658 pinctrl-names = "default";
659 pinctrl-0 = <&uart2c_xfer>;
663 uart3: serial@ff1b0000 {
664 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
665 reg = <0x0 0xff1b0000 0x0 0x100>;
666 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
667 clock-names = "baudclk", "apb_pclk";
668 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
677 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
678 reg = <0x0 0xff1c0000 0x0 0x1000>;
679 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
680 clock-names = "spiclk", "apb_pclk";
681 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
682 pinctrl-names = "default";
683 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
684 #address-cells = <1>;
690 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
691 reg = <0x0 0xff1d0000 0x0 0x1000>;
692 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
693 clock-names = "spiclk", "apb_pclk";
694 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
695 pinctrl-names = "default";
696 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
697 #address-cells = <1>;
703 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
704 reg = <0x0 0xff1e0000 0x0 0x1000>;
705 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
706 clock-names = "spiclk", "apb_pclk";
707 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
708 pinctrl-names = "default";
709 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
710 #address-cells = <1>;
716 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
717 reg = <0x0 0xff1f0000 0x0 0x1000>;
718 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
719 clock-names = "spiclk", "apb_pclk";
720 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
721 pinctrl-names = "default";
722 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
723 #address-cells = <1>;
729 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
730 reg = <0x0 0xff200000 0x0 0x1000>;
731 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
732 clock-names = "spiclk", "apb_pclk";
733 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
734 pinctrl-names = "default";
735 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
736 #address-cells = <1>;
742 soc_thermal: soc-thermal {
743 polling-delay-passive = <20>; /* milliseconds */
744 polling-delay = <1000>; /* milliseconds */
745 sustainable-power = <1000>; /* milliwatts */
747 thermal-sensors = <&tsadc 0>;
750 threshold: trip-point@0 {
751 temperature = <70000>; /* millicelsius */
752 hysteresis = <2000>; /* millicelsius */
755 target: trip-point@1 {
756 temperature = <85000>; /* millicelsius */
757 hysteresis = <2000>; /* millicelsius */
761 temperature = <95000>; /* millicelsius */
762 hysteresis = <2000>; /* millicelsius */
771 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
772 contribution = <4096>;
777 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
778 contribution = <1024>;
783 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
784 contribution = <4096>;
789 gpu_thermal: gpu-thermal {
790 polling-delay-passive = <100>; /* milliseconds */
791 polling-delay = <1000>; /* milliseconds */
793 thermal-sensors = <&tsadc 1>;
797 tsadc: tsadc@ff260000 {
798 compatible = "rockchip,rk3399-tsadc";
799 reg = <0x0 0xff260000 0x0 0x100>;
800 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
801 rockchip,grf = <&grf>;
802 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
803 clock-names = "tsadc", "apb_pclk";
804 assigned-clocks = <&cru SCLK_TSADC>;
805 assigned-clock-rates = <750000>;
806 resets = <&cru SRST_TSADC>;
807 reset-names = "tsadc-apb";
808 pinctrl-names = "init", "default", "sleep";
809 pinctrl-0 = <&otp_gpio>;
810 pinctrl-1 = <&otp_out>;
811 pinctrl-2 = <&otp_gpio>;
812 #thermal-sensor-cells = <1>;
813 rockchip,hw-tshut-temp = <95000>;
817 qos_emmc: qos@ffa58000 {
818 compatible = "syscon";
819 reg = <0x0 0xffa58000 0x0 0x20>;
822 qos_gmac: qos@ffa5c000 {
823 compatible = "syscon";
824 reg = <0x0 0xffa5c000 0x0 0x20>;
827 qos_pcie: qos@ffa60080 {
828 compatible = "syscon";
829 reg = <0x0 0xffa60080 0x0 0x20>;
832 qos_usb_host0: qos@ffa60100 {
833 compatible = "syscon";
834 reg = <0x0 0xffa60100 0x0 0x20>;
837 qos_usb_host1: qos@ffa60180 {
838 compatible = "syscon";
839 reg = <0x0 0xffa60180 0x0 0x20>;
842 qos_usb_otg0: qos@ffa70000 {
843 compatible = "syscon";
844 reg = <0x0 0xffa70000 0x0 0x20>;
847 qos_usb_otg1: qos@ffa70080 {
848 compatible = "syscon";
849 reg = <0x0 0xffa70080 0x0 0x20>;
852 qos_sd: qos@ffa74000 {
853 compatible = "syscon";
854 reg = <0x0 0xffa74000 0x0 0x20>;
857 qos_sdioaudio: qos@ffa76000 {
858 compatible = "syscon";
859 reg = <0x0 0xffa76000 0x0 0x20>;
862 qos_hdcp: qos@ffa90000 {
863 compatible = "syscon";
864 reg = <0x0 0xffa90000 0x0 0x20>;
867 qos_iep: qos@ffa98000 {
868 compatible = "syscon";
869 reg = <0x0 0xffa98000 0x0 0x20>;
872 qos_isp0_m0: qos@ffaa0000 {
873 compatible = "syscon";
874 reg = <0x0 0xffaa0000 0x0 0x20>;
877 qos_isp0_m1: qos@ffaa0080 {
878 compatible = "syscon";
879 reg = <0x0 0xffaa0080 0x0 0x20>;
882 qos_isp1_m0: qos@ffaa8000 {
883 compatible = "syscon";
884 reg = <0x0 0xffaa8000 0x0 0x20>;
887 qos_isp1_m1: qos@ffaa8080 {
888 compatible = "syscon";
889 reg = <0x0 0xffaa8080 0x0 0x20>;
892 qos_rga_r: qos@ffab0000 {
893 compatible = "syscon";
894 reg = <0x0 0xffab0000 0x0 0x20>;
897 qos_rga_w: qos@ffab0080 {
898 compatible = "syscon";
899 reg = <0x0 0xffab0080 0x0 0x20>;
902 qos_video_m0: qos@ffab8000 {
903 compatible = "syscon";
904 reg = <0x0 0xffab8000 0x0 0x20>;
907 qos_video_m1_r: qos@ffac0000 {
908 compatible = "syscon";
909 reg = <0x0 0xffac0000 0x0 0x20>;
912 qos_video_m1_w: qos@ffac0080 {
913 compatible = "syscon";
914 reg = <0x0 0xffac0080 0x0 0x20>;
917 qos_vop_big_r: qos@ffac8000 {
918 compatible = "syscon";
919 reg = <0x0 0xffac8000 0x0 0x20>;
922 qos_vop_big_w: qos@ffac8080 {
923 compatible = "syscon";
924 reg = <0x0 0xffac8080 0x0 0x20>;
927 qos_vop_little: qos@ffad0000 {
928 compatible = "syscon";
929 reg = <0x0 0xffad0000 0x0 0x20>;
932 qos_perihp: qos@ffad8080 {
933 compatible = "syscon";
934 reg = <0x0 0xffad8080 0x0 0x20>;
937 qos_gpu: qos@ffae0000 {
938 compatible = "syscon";
939 reg = <0x0 0xffae0000 0x0 0x20>;
942 pmu: power-management@ff310000 {
943 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
944 reg = <0x0 0xff310000 0x0 0x1000>;
947 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
948 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
949 * Some of the power domains are grouped together for every
951 * The detail contents as below.
953 power: power-controller {
954 compatible = "rockchip,rk3399-power-controller";
955 #power-domain-cells = <1>;
956 #address-cells = <1>;
959 /* These power domains are grouped by VD_CENTER */
960 pd_iep@RK3399_PD_IEP {
961 reg = <RK3399_PD_IEP>;
962 clocks = <&cru ACLK_IEP>,
966 pd_rga@RK3399_PD_RGA {
967 reg = <RK3399_PD_RGA>;
968 clocks = <&cru ACLK_RGA>,
970 pm_qos = <&qos_rga_r>,
973 pd_vcodec@RK3399_PD_VCODEC {
974 reg = <RK3399_PD_VCODEC>;
975 clocks = <&cru ACLK_VCODEC>,
977 pm_qos = <&qos_video_m0>;
979 pd_vdu@RK3399_PD_VDU {
980 reg = <RK3399_PD_VDU>;
981 clocks = <&cru ACLK_VDU>,
983 pm_qos = <&qos_video_m1_r>,
987 /* These power domains are grouped by VD_GPU */
988 pd_gpu@RK3399_PD_GPU {
989 reg = <RK3399_PD_GPU>;
990 clocks = <&cru ACLK_GPU>;
994 /* These power domains are grouped by VD_LOGIC */
995 pd_edp@RK3399_PD_EDP {
996 reg = <RK3399_PD_EDP>;
997 clocks = <&cru PCLK_EDP_CTRL>;
999 pd_emmc@RK3399_PD_EMMC {
1000 reg = <RK3399_PD_EMMC>;
1001 clocks = <&cru ACLK_EMMC>;
1002 pm_qos = <&qos_emmc>;
1004 pd_gmac@RK3399_PD_GMAC {
1005 reg = <RK3399_PD_GMAC>;
1006 clocks = <&cru ACLK_GMAC>,
1008 pm_qos = <&qos_gmac>;
1010 pd_perihp@RK3399_PD_PERIHP {
1011 reg = <RK3399_PD_PERIHP>;
1012 #address-cells = <1>;
1014 clocks = <&cru ACLK_PERIHP>;
1015 pm_qos = <&qos_perihp>,
1020 pd_sd@RK3399_PD_SD {
1021 reg = <RK3399_PD_SD>;
1022 clocks = <&cru HCLK_SDMMC>,
1027 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1028 reg = <RK3399_PD_SDIOAUDIO>;
1029 clocks = <&cru HCLK_SDIO>;
1030 pm_qos = <&qos_sdioaudio>;
1032 pd_usb3@RK3399_PD_USB3 {
1033 reg = <RK3399_PD_USB3>;
1034 clocks = <&cru ACLK_USB3>;
1035 pm_qos = <&qos_usb_otg0>,
1038 pd_vio@RK3399_PD_VIO {
1039 reg = <RK3399_PD_VIO>;
1040 #address-cells = <1>;
1043 pd_hdcp@RK3399_PD_HDCP {
1044 reg = <RK3399_PD_HDCP>;
1045 clocks = <&cru ACLK_HDCP>,
1048 pm_qos = <&qos_hdcp>;
1050 pd_isp0@RK3399_PD_ISP0 {
1051 reg = <RK3399_PD_ISP0>;
1052 clocks = <&cru ACLK_ISP0>,
1054 pm_qos = <&qos_isp0_m0>,
1057 pd_isp1@RK3399_PD_ISP1 {
1058 reg = <RK3399_PD_ISP1>;
1059 clocks = <&cru ACLK_ISP1>,
1061 pm_qos = <&qos_isp1_m0>,
1064 pd_tcpc0@RK3399_PD_TCPC0 {
1065 reg = <RK3399_PD_TCPD0>;
1066 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1067 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1069 pd_tcpc1@RK3399_PD_TCPC1 {
1070 reg = <RK3399_PD_TCPD1>;
1071 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1072 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1074 pd_vo@RK3399_PD_VO {
1075 reg = <RK3399_PD_VO>;
1076 #address-cells = <1>;
1079 pd_vopb@RK3399_PD_VOPB {
1080 reg = <RK3399_PD_VOPB>;
1081 clocks = <&cru ACLK_VOP0>,
1083 pm_qos = <&qos_vop_big_r>,
1086 pd_vopl@RK3399_PD_VOPL {
1087 reg = <RK3399_PD_VOPL>;
1088 clocks = <&cru ACLK_VOP1>,
1090 pm_qos = <&qos_vop_little>;
1097 pmugrf: syscon@ff320000 {
1098 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1099 reg = <0x0 0xff320000 0x0 0x1000>;
1101 pmu_io_domains: pmu-io-domains {
1102 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1103 status = "disabled";
1107 compatible = "syscon-reboot-mode";
1109 mode-bootloader = <BOOT_LOADER>;
1110 mode-charge = <BOOT_CHARGING>;
1111 mode-fastboot = <BOOT_FASTBOOT>;
1112 mode-loader = <BOOT_LOADER>;
1113 mode-normal = <BOOT_NORMAL>;
1114 mode-recovery = <BOOT_RECOVERY>;
1115 mode-ums = <BOOT_UMS>;
1118 pmu_pvtm: pmu-pvtm {
1119 compatible = "rockchip,rk3399-pmu-pvtm";
1120 clocks = <&pmucru SCLK_PVTM_PMU>;
1121 clock-names = "pmu";
1122 status = "disabled";
1126 spi3: spi@ff350000 {
1127 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1128 reg = <0x0 0xff350000 0x0 0x1000>;
1129 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1130 clock-names = "spiclk", "apb_pclk";
1131 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1132 pinctrl-names = "default";
1133 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1134 #address-cells = <1>;
1136 status = "disabled";
1139 uart4: serial@ff370000 {
1140 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1141 reg = <0x0 0xff370000 0x0 0x100>;
1142 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1143 clock-names = "baudclk", "apb_pclk";
1144 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1147 pinctrl-names = "default";
1148 pinctrl-0 = <&uart4_xfer>;
1149 status = "disabled";
1152 i2c4: i2c@ff3d0000 {
1153 compatible = "rockchip,rk3399-i2c";
1154 reg = <0x0 0xff3d0000 0x0 0x1000>;
1155 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1156 clock-names = "i2c", "pclk";
1157 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1158 pinctrl-names = "default";
1159 pinctrl-0 = <&i2c4_xfer>;
1160 #address-cells = <1>;
1162 status = "disabled";
1165 i2c8: i2c@ff3e0000 {
1166 compatible = "rockchip,rk3399-i2c";
1167 reg = <0x0 0xff3e0000 0x0 0x1000>;
1168 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1169 clock-names = "i2c", "pclk";
1170 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1171 pinctrl-names = "default";
1172 pinctrl-0 = <&i2c8_xfer>;
1173 #address-cells = <1>;
1175 status = "disabled";
1178 pcie_phy: phy@e220 {
1179 compatible = "rockchip,rk3399-pcie-phy";
1181 rockchip,grf = <&grf>;
1182 clocks = <&cru SCLK_PCIEPHY_REF>;
1183 clock-names = "refclk";
1184 resets = <&cru SRST_PCIEPHY>;
1185 reset-names = "phy";
1186 status = "disabled";
1189 pcie0: pcie@f8000000 {
1190 compatible = "rockchip,rk3399-pcie";
1191 #address-cells = <3>;
1193 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1194 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1195 clock-names = "aclk", "aclk-perf",
1197 bus-range = <0x0 0x1>;
1198 max-link-speed = <1>;
1199 msi-map = <0x0 &its 0x0 0x1000>;
1200 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1201 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1202 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1203 interrupt-names = "sys", "legacy", "client";
1204 #interrupt-cells = <1>;
1205 interrupt-map-mask = <0 0 0 7>;
1206 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1207 <0 0 0 2 &pcie0_intc 1>,
1208 <0 0 0 3 &pcie0_intc 2>,
1209 <0 0 0 4 &pcie0_intc 3>;
1211 phy-names = "pcie-phy";
1212 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1213 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1214 reg = <0x0 0xf8000000 0x0 0x2000000>,
1215 <0x0 0xfd000000 0x0 0x1000000>;
1216 reg-names = "axi-base", "apb-base";
1217 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1218 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1219 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1221 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1222 "pm", "pclk", "aclk";
1223 status = "disabled";
1224 pcie0_intc: interrupt-controller {
1225 interrupt-controller;
1226 #address-cells = <0>;
1227 #interrupt-cells = <1>;
1231 pwm0: pwm@ff420000 {
1232 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1233 reg = <0x0 0xff420000 0x0 0x10>;
1235 pinctrl-names = "default";
1236 pinctrl-0 = <&pwm0_pin>;
1237 clocks = <&pmucru PCLK_RKPWM_PMU>;
1238 clock-names = "pwm";
1239 status = "disabled";
1242 pwm1: pwm@ff420010 {
1243 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1244 reg = <0x0 0xff420010 0x0 0x10>;
1246 pinctrl-names = "default";
1247 pinctrl-0 = <&pwm1_pin>;
1248 clocks = <&pmucru PCLK_RKPWM_PMU>;
1249 clock-names = "pwm";
1250 status = "disabled";
1253 pwm2: pwm@ff420020 {
1254 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1255 reg = <0x0 0xff420020 0x0 0x10>;
1257 pinctrl-names = "default";
1258 pinctrl-0 = <&pwm2_pin>;
1259 clocks = <&pmucru PCLK_RKPWM_PMU>;
1260 clock-names = "pwm";
1261 status = "disabled";
1264 pwm3: pwm@ff420030 {
1265 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1266 reg = <0x0 0xff420030 0x0 0x10>;
1268 pinctrl-names = "default";
1269 pinctrl-0 = <&pwm3a_pin>;
1270 clocks = <&pmucru PCLK_RKPWM_PMU>;
1271 clock-names = "pwm";
1272 status = "disabled";
1276 reg = <0x00 0xff630000 0x00 0x4000>;
1277 compatible = "rockchip,rk3399-dfi";
1278 rockchip,pmu = <&pmugrf>;
1279 clocks = <&cru PCLK_DDR_MON>;
1280 clock-names = "pclk_ddr_mon";
1281 status = "disabled";
1285 compatible = "rockchip,rk3399-dmc";
1286 devfreq-events = <&dfi>;
1287 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1288 clocks = <&cru SCLK_DDRCLK>;
1289 clock-names = "dmc_clk";
1290 ddr_timing = <&ddr_timing>;
1291 status = "disabled";
1295 compatible = "rockchip,rk3399-rga";
1296 reg = <0x0 0xff680000 0x0 0x10000>;
1297 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1298 interrupt-names = "rga";
1299 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1300 clock-names = "aclk", "hclk", "sclk";
1301 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1302 reset-names = "core", "axi", "ahb";
1303 power-domains = <&power RK3399_PD_RGA>;
1304 status = "disabled";
1307 efuse0: efuse@ff690000 {
1308 compatible = "rockchip,rk3399-efuse";
1309 reg = <0x0 0xff690000 0x0 0x80>;
1310 #address-cells = <1>;
1312 clocks = <&cru PCLK_EFUSE1024NS>;
1313 clock-names = "pclk_efuse";
1316 cpul_leakage: cpul-leakage {
1319 cpub_leakage: cpub-leakage {
1322 gpu_leakage: gpu-leakage {
1325 center_leakage: center-leakage {
1328 logic_leakage: logic-leakage {
1331 wafer_info: wafer-info {
1336 pmucru: pmu-clock-controller@ff750000 {
1337 compatible = "rockchip,rk3399-pmucru";
1338 reg = <0x0 0xff750000 0x0 0x1000>;
1341 assigned-clocks = <&pmucru PLL_PPLL>;
1342 assigned-clock-rates = <676000000>;
1345 cru: clock-controller@ff760000 {
1346 compatible = "rockchip,rk3399-cru";
1347 reg = <0x0 0xff760000 0x0 0x1000>;
1351 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1352 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1353 <&cru ARMCLKL>, <&cru ARMCLKB>,
1354 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1355 <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1356 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1358 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1359 <&cru PCLK_PERILP0>,
1360 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1361 assigned-clock-rates =
1362 <400000000>, <200000000>,
1363 <400000000>, <200000000>,
1364 <816000000>, <816000000>,
1365 <594000000>, <800000000>,
1366 <200000000>, <1000000000>,
1367 <150000000>, <75000000>,
1369 <100000000>, <100000000>,
1371 <100000000>, <50000000>;
1374 grf: syscon@ff770000 {
1375 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1376 reg = <0x0 0xff770000 0x0 0x10000>;
1377 #address-cells = <1>;
1380 io_domains: io-domains {
1381 compatible = "rockchip,rk3399-io-voltage-domain";
1382 status = "disabled";
1385 emmc_phy: phy@f780 {
1386 compatible = "rockchip,rk3399-emmc-phy";
1387 reg = <0xf780 0x24>;
1389 clock-names = "emmcclk";
1391 status = "disabled";
1394 u2phy0: usb2-phy@e450 {
1395 compatible = "rockchip,rk3399-usb2phy";
1396 reg = <0xe450 0x10>;
1397 clocks = <&cru SCLK_USB2PHY0_REF>;
1398 clock-names = "phyclk";
1400 clock-output-names = "clk_usbphy0_480m";
1401 status = "disabled";
1403 u2phy0_otg: otg-port {
1405 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1406 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1407 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1408 interrupt-names = "otg-bvalid", "otg-id",
1410 status = "disabled";
1413 u2phy0_host: host-port {
1415 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1416 interrupt-names = "linestate";
1417 status = "disabled";
1421 u2phy1: usb2-phy@e460 {
1422 compatible = "rockchip,rk3399-usb2phy";
1423 reg = <0xe460 0x10>;
1424 clocks = <&cru SCLK_USB2PHY1_REF>;
1425 clock-names = "phyclk";
1427 clock-output-names = "clk_usbphy1_480m";
1428 status = "disabled";
1430 u2phy1_otg: otg-port {
1432 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1433 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1434 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1435 interrupt-names = "otg-bvalid", "otg-id",
1437 status = "disabled";
1440 u2phy1_host: host-port {
1442 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1443 interrupt-names = "linestate";
1444 status = "disabled";
1449 compatible = "rockchip,rk3399-pvtm";
1450 clocks = <&cru SCLK_PVTM_CORE_L>,
1451 <&cru SCLK_PVTM_CORE_B>,
1452 <&cru SCLK_PVTM_GPU>,
1453 <&cru SCLK_PVTM_DDR>;
1454 clock-names = "core_l", "core_b", "gpu", "ddr";
1455 status = "disabled";
1459 tcphy0: phy@ff7c0000 {
1460 compatible = "rockchip,rk3399-typec-phy";
1461 reg = <0x0 0xff7c0000 0x0 0x40000>;
1462 rockchip,grf = <&grf>;
1464 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1465 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1466 clock-names = "tcpdcore", "tcpdphy-ref";
1467 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1468 assigned-clock-rates = <50000000>;
1469 power-domains = <&power RK3399_PD_TCPD0>;
1470 resets = <&cru SRST_UPHY0>,
1471 <&cru SRST_UPHY0_PIPE_L00>,
1472 <&cru SRST_P_UPHY0_TCPHY>;
1473 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1474 rockchip,typec-conn-dir = <0xe580 0 16>;
1475 rockchip,usb3tousb2-en = <0xe580 3 19>;
1476 rockchip,usb3-host-disable = <0x2434 0 16>;
1477 rockchip,usb3-host-port = <0x2434 12 28>;
1478 rockchip,external-psm = <0xe588 14 30>;
1479 rockchip,pipe-status = <0xe5c0 0 0>;
1480 rockchip,uphy-dp-sel = <0x6268 19 19>;
1481 status = "disabled";
1483 tcphy0_dp: dp-port {
1487 tcphy0_usb3: usb3-port {
1492 tcphy1: phy@ff800000 {
1493 compatible = "rockchip,rk3399-typec-phy";
1494 reg = <0x0 0xff800000 0x0 0x40000>;
1495 rockchip,grf = <&grf>;
1497 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1498 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1499 clock-names = "tcpdcore", "tcpdphy-ref";
1500 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1501 assigned-clock-rates = <50000000>;
1502 power-domains = <&power RK3399_PD_TCPD1>;
1503 resets = <&cru SRST_UPHY1>,
1504 <&cru SRST_UPHY1_PIPE_L00>,
1505 <&cru SRST_P_UPHY1_TCPHY>;
1506 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1507 rockchip,typec-conn-dir = <0xe58c 0 16>;
1508 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1509 rockchip,usb3-host-disable = <0x2444 0 16>;
1510 rockchip,usb3-host-port = <0x2444 12 28>;
1511 rockchip,external-psm = <0xe594 14 30>;
1512 rockchip,pipe-status = <0xe5c0 16 16>;
1513 rockchip,uphy-dp-sel = <0x6268 3 19>;
1514 status = "disabled";
1516 tcphy1_dp: dp-port {
1520 tcphy1_usb3: usb3-port {
1526 compatible = "snps,dw-wdt";
1527 reg = <0x0 0xff848000 0x0 0x100>;
1528 clocks = <&cru PCLK_WDT>;
1529 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1532 rktimer: rktimer@ff850000 {
1533 compatible = "rockchip,rk3399-timer";
1534 reg = <0x0 0xff850000 0x0 0x1000>;
1535 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1536 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1537 clock-names = "pclk", "timer";
1540 spdif: spdif@ff870000 {
1541 compatible = "rockchip,rk3399-spdif";
1542 reg = <0x0 0xff870000 0x0 0x1000>;
1543 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1544 dmas = <&dmac_bus 7>;
1546 clock-names = "mclk", "hclk";
1547 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1548 pinctrl-names = "default";
1549 pinctrl-0 = <&spdif_bus>;
1550 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1551 status = "disabled";
1554 i2s0: i2s@ff880000 {
1555 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1556 reg = <0x0 0xff880000 0x0 0x1000>;
1557 rockchip,grf = <&grf>;
1558 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1559 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1560 dma-names = "tx", "rx";
1561 clock-names = "i2s_clk", "i2s_hclk";
1562 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1563 pinctrl-names = "default";
1564 pinctrl-0 = <&i2s0_8ch_bus>;
1565 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1566 status = "disabled";
1569 i2s1: i2s@ff890000 {
1570 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1571 reg = <0x0 0xff890000 0x0 0x1000>;
1572 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1573 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1574 dma-names = "tx", "rx";
1575 clock-names = "i2s_clk", "i2s_hclk";
1576 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1577 pinctrl-names = "default";
1578 pinctrl-0 = <&i2s1_2ch_bus>;
1579 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1580 status = "disabled";
1583 i2s2: i2s@ff8a0000 {
1584 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1585 reg = <0x0 0xff8a0000 0x0 0x1000>;
1586 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1587 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1588 dma-names = "tx", "rx";
1589 clock-names = "i2s_clk", "i2s_hclk";
1590 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1591 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1592 status = "disabled";
1596 compatible = "arm,malit860",
1601 reg = <0x0 0xff9a0000 0x0 0x10000>;
1603 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1604 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1605 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1606 interrupt-names = "GPU", "JOB", "MMU";
1608 clocks = <&cru ACLK_GPU>;
1609 clock-names = "clk_mali";
1610 #cooling-cells = <2>; /* min followed by max */
1611 power-domains = <&power RK3399_PD_GPU>;
1612 power-off-delay-ms = <200>;
1613 status = "disabled";
1615 gpu_power_model: power_model {
1616 compatible = "arm,mali-simple-power-model";
1619 static-power = <300>;
1620 dynamic-power = <396>;
1621 ts = <32000 4700 (-80) 2>;
1622 thermal-zone = "gpu-thermal";
1626 vopl: vop@ff8f0000 {
1627 compatible = "rockchip,rk3399-vop-lit";
1628 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1629 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1630 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1631 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1632 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1633 reset-names = "axi", "ahb", "dclk";
1634 power-domains = <&power RK3399_PD_VOPL>;
1635 iommus = <&vopl_mmu>;
1636 status = "disabled";
1639 #address-cells = <1>;
1642 vopl_out_mipi: endpoint@0 {
1644 remote-endpoint = <&mipi_in_vopl>;
1647 vopl_out_edp: endpoint@1 {
1649 remote-endpoint = <&edp_in_vopl>;
1652 vopl_out_hdmi: endpoint@2 {
1654 remote-endpoint = <&hdmi_in_vopl>;
1657 vopl_out_dp: endpoint@3 {
1659 remote-endpoint = <&dp_in_vopl>;
1664 vop1_pwm: voppwm@ff8f01a0 {
1665 compatible = "rockchip,vop-pwm";
1666 reg = <0x0 0xff8f01a0 0x0 0x10>;
1668 pinctrl-names = "default";
1669 pinctrl-0 = <&vop1_pwm_pin>;
1670 clocks = <&cru SCLK_VOP1_PWM>;
1671 clock-names = "pwm";
1672 status = "disabled";
1675 vopl_mmu: iommu@ff8f3f00 {
1676 compatible = "rockchip,iommu";
1677 reg = <0x0 0xff8f3f00 0x0 0x100>;
1678 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1679 interrupt-names = "vopl_mmu";
1681 status = "disabled";
1684 vopb: vop@ff900000 {
1685 compatible = "rockchip,rk3399-vop-big";
1686 reg = <0x0 0xff900000 0x0 0x3efc>;
1687 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1688 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1689 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1690 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1691 reset-names = "axi", "ahb", "dclk";
1692 power-domains = <&power RK3399_PD_VOPB>;
1693 iommus = <&vopb_mmu>;
1694 status = "disabled";
1697 #address-cells = <1>;
1700 vopb_out_edp: endpoint@0 {
1702 remote-endpoint = <&edp_in_vopb>;
1705 vopb_out_mipi: endpoint@1 {
1707 remote-endpoint = <&mipi_in_vopb>;
1710 vopb_out_hdmi: endpoint@2 {
1712 remote-endpoint = <&hdmi_in_vopb>;
1715 vopb_out_dp: endpoint@3 {
1717 remote-endpoint = <&dp_in_vopb>;
1722 vop0_pwm: voppwm@ff9001a0 {
1723 compatible = "rockchip,vop-pwm";
1724 reg = <0x0 0xff9001a0 0x0 0x10>;
1726 pinctrl-names = "default";
1727 pinctrl-0 = <&vop0_pwm_pin>;
1728 clocks = <&cru SCLK_VOP0_PWM>;
1729 clock-names = "pwm";
1730 status = "disabled";
1733 vopb_mmu: iommu@ff903f00 {
1734 compatible = "rockchip,iommu";
1735 reg = <0x0 0xff903f00 0x0 0x100>;
1736 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1737 interrupt-names = "vopb_mmu";
1739 status = "disabled";
1742 isp0_mmu: iommu@ff914000 {
1743 compatible = "rockchip,iommu";
1744 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1745 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1746 interrupt-names = "isp0_mmu";
1748 rk_iommu,disable_reset_quirk;
1749 status = "disabled";
1752 isp1_mmu: iommu@ff924000 {
1753 compatible = "rockchip,iommu";
1754 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1755 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1756 interrupt-names = "isp1_mmu";
1758 rk_iommu,disable_reset_quirk;
1759 status = "disabled";
1762 hdmi: hdmi@ff940000 {
1763 compatible = "rockchip,rk3399-dw-hdmi";
1764 reg = <0x0 0xff940000 0x0 0x20000>;
1766 rockchip,grf = <&grf>;
1767 power-domains = <&power RK3399_PD_HDCP>;
1768 pinctrl-names = "default";
1769 pinctrl-0 = <&hdmi_i2c_xfer>;
1770 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1771 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1772 clock-names = "iahb", "isfr", "vpll", "grf";
1773 status = "disabled";
1777 #address-cells = <1>;
1779 hdmi_in_vopb: endpoint@0 {
1781 remote-endpoint = <&vopb_out_hdmi>;
1783 hdmi_in_vopl: endpoint@1 {
1785 remote-endpoint = <&vopl_out_hdmi>;
1791 mipi_dsi: mipi@ff960000 {
1792 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1793 reg = <0x0 0xff960000 0x0 0x8000>;
1794 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1795 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1796 <&cru SCLK_DPHY_TX0_CFG>;
1797 clock-names = "ref", "pclk", "phy_cfg";
1798 power-domains = <&power RK3399_PD_VIO>;
1799 rockchip,grf = <&grf>;
1800 #address-cells = <1>;
1802 status = "disabled";
1805 #address-cells = <1>;
1810 #address-cells = <1>;
1813 mipi_in_vopb: endpoint@0 {
1815 remote-endpoint = <&vopb_out_mipi>;
1817 mipi_in_vopl: endpoint@1 {
1819 remote-endpoint = <&vopl_out_mipi>;
1826 compatible = "rockchip,rk3399-edp";
1827 reg = <0x0 0xff970000 0x0 0x8000>;
1828 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1829 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1830 clock-names = "dp", "pclk";
1831 power-domains = <&power RK3399_PD_EDP>;
1832 resets = <&cru SRST_P_EDP_CTRL>;
1834 rockchip,grf = <&grf>;
1835 status = "disabled";
1836 pinctrl-names = "default";
1837 pinctrl-0 = <&edp_hpd>;
1840 #address-cells = <1>;
1845 #address-cells = <1>;
1848 edp_in_vopb: endpoint@0 {
1850 remote-endpoint = <&vopb_out_edp>;
1853 edp_in_vopl: endpoint@1 {
1855 remote-endpoint = <&vopl_out_edp>;
1861 display_subsystem: display-subsystem {
1862 compatible = "rockchip,display-subsystem";
1863 ports = <&vopl_out>, <&vopb_out>;
1864 status = "disabled";
1868 compatible = "rockchip,rk3399-pinctrl";
1869 rockchip,grf = <&grf>;
1870 rockchip,pmu = <&pmugrf>;
1871 #address-cells = <0x2>;
1872 #size-cells = <0x2>;
1875 gpio0: gpio0@ff720000 {
1876 compatible = "rockchip,gpio-bank";
1877 reg = <0x0 0xff720000 0x0 0x100>;
1878 clocks = <&pmucru PCLK_GPIO0_PMU>;
1879 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1882 #gpio-cells = <0x2>;
1884 interrupt-controller;
1885 #interrupt-cells = <0x2>;
1888 gpio1: gpio1@ff730000 {
1889 compatible = "rockchip,gpio-bank";
1890 reg = <0x0 0xff730000 0x0 0x100>;
1891 clocks = <&pmucru PCLK_GPIO1_PMU>;
1892 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1895 #gpio-cells = <0x2>;
1897 interrupt-controller;
1898 #interrupt-cells = <0x2>;
1901 gpio2: gpio2@ff780000 {
1902 compatible = "rockchip,gpio-bank";
1903 reg = <0x0 0xff780000 0x0 0x100>;
1904 clocks = <&cru PCLK_GPIO2>;
1905 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1908 #gpio-cells = <0x2>;
1910 interrupt-controller;
1911 #interrupt-cells = <0x2>;
1914 gpio3: gpio3@ff788000 {
1915 compatible = "rockchip,gpio-bank";
1916 reg = <0x0 0xff788000 0x0 0x100>;
1917 clocks = <&cru PCLK_GPIO3>;
1918 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1921 #gpio-cells = <0x2>;
1923 interrupt-controller;
1924 #interrupt-cells = <0x2>;
1927 gpio4: gpio4@ff790000 {
1928 compatible = "rockchip,gpio-bank";
1929 reg = <0x0 0xff790000 0x0 0x100>;
1930 clocks = <&cru PCLK_GPIO4>;
1931 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1934 #gpio-cells = <0x2>;
1936 interrupt-controller;
1937 #interrupt-cells = <0x2>;
1940 pcfg_pull_up: pcfg-pull-up {
1944 pcfg_pull_down: pcfg-pull-down {
1948 pcfg_pull_none: pcfg-pull-none {
1952 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1954 drive-strength = <20>;
1957 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1959 drive-strength = <20>;
1962 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1964 drive-strength = <18>;
1967 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1969 drive-strength = <12>;
1972 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1974 drive-strength = <8>;
1977 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1979 drive-strength = <4>;
1982 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1984 drive-strength = <2>;
1987 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1989 drive-strength = <12>;
1992 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1994 drive-strength = <13>;
1997 pcfg_output_high: pcfg-output-high {
2001 pcfg_output_low: pcfg-output-low {
2005 pcfg_input: pcfg-input {
2010 emmc_pwr: emmc-pwr {
2012 <0 5 RK_FUNC_1 &pcfg_pull_up>;
2017 rgmii_pins: rgmii-pins {
2020 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2022 <3 14 RK_FUNC_1 &pcfg_pull_none>,
2024 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2026 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2028 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2030 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2032 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2034 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2036 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2038 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2040 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2042 <3 3 RK_FUNC_1 &pcfg_pull_none>,
2044 <3 2 RK_FUNC_1 &pcfg_pull_none>,
2046 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2048 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2051 rmii_pins: rmii-pins {
2054 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2056 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2058 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2060 <3 10 RK_FUNC_1 &pcfg_pull_none>,
2062 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2064 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2066 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2068 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2070 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2072 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2077 i2c0_xfer: i2c0-xfer {
2079 <1 15 RK_FUNC_2 &pcfg_pull_none>,
2080 <1 16 RK_FUNC_2 &pcfg_pull_none>;
2085 i2c1_xfer: i2c1-xfer {
2087 <4 2 RK_FUNC_1 &pcfg_pull_none>,
2088 <4 1 RK_FUNC_1 &pcfg_pull_none>;
2093 i2c2_xfer: i2c2-xfer {
2095 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2096 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2101 i2c3_xfer: i2c3-xfer {
2103 <4 17 RK_FUNC_1 &pcfg_pull_none>,
2104 <4 16 RK_FUNC_1 &pcfg_pull_none>;
2107 i2c3_gpio: i2c3_gpio {
2109 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2110 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2116 i2c4_xfer: i2c4-xfer {
2118 <1 12 RK_FUNC_1 &pcfg_pull_none>,
2119 <1 11 RK_FUNC_1 &pcfg_pull_none>;
2124 i2c5_xfer: i2c5-xfer {
2126 <3 11 RK_FUNC_2 &pcfg_pull_none>,
2127 <3 10 RK_FUNC_2 &pcfg_pull_none>;
2132 i2c6_xfer: i2c6-xfer {
2134 <2 10 RK_FUNC_2 &pcfg_pull_none>,
2135 <2 9 RK_FUNC_2 &pcfg_pull_none>;
2140 i2c7_xfer: i2c7-xfer {
2142 <2 8 RK_FUNC_2 &pcfg_pull_none>,
2143 <2 7 RK_FUNC_2 &pcfg_pull_none>;
2148 i2c8_xfer: i2c8-xfer {
2150 <1 21 RK_FUNC_1 &pcfg_pull_none>,
2151 <1 20 RK_FUNC_1 &pcfg_pull_none>;
2156 i2s0_8ch_bus: i2s0-8ch-bus {
2158 <3 24 RK_FUNC_1 &pcfg_pull_none>,
2159 <3 25 RK_FUNC_1 &pcfg_pull_none>,
2160 <3 26 RK_FUNC_1 &pcfg_pull_none>,
2161 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2162 <3 28 RK_FUNC_1 &pcfg_pull_none>,
2163 <3 29 RK_FUNC_1 &pcfg_pull_none>,
2164 <3 30 RK_FUNC_1 &pcfg_pull_none>,
2165 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2166 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2171 i2s1_2ch_bus: i2s1-2ch-bus {
2173 <4 3 RK_FUNC_1 &pcfg_pull_none>,
2174 <4 4 RK_FUNC_1 &pcfg_pull_none>,
2175 <4 5 RK_FUNC_1 &pcfg_pull_none>,
2176 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2177 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2182 sdio0_bus1: sdio0-bus1 {
2184 <2 20 RK_FUNC_1 &pcfg_pull_up>;
2187 sdio0_bus4: sdio0-bus4 {
2189 <2 20 RK_FUNC_1 &pcfg_pull_up>,
2190 <2 21 RK_FUNC_1 &pcfg_pull_up>,
2191 <2 22 RK_FUNC_1 &pcfg_pull_up>,
2192 <2 23 RK_FUNC_1 &pcfg_pull_up>;
2195 sdio0_cmd: sdio0-cmd {
2197 <2 24 RK_FUNC_1 &pcfg_pull_up>;
2200 sdio0_clk: sdio0-clk {
2202 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2205 sdio0_cd: sdio0-cd {
2207 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2210 sdio0_pwr: sdio0-pwr {
2212 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2215 sdio0_bkpwr: sdio0-bkpwr {
2217 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2220 sdio0_wp: sdio0-wp {
2222 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2225 sdio0_int: sdio0-int {
2227 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2232 sdmmc_bus1: sdmmc-bus1 {
2234 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2237 sdmmc_bus4: sdmmc-bus4 {
2239 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2240 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2241 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2242 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2245 sdmmc_clk: sdmmc-clk {
2247 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2250 sdmmc_cmd: sdmmc-cmd {
2252 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2255 sdmmc_cd: sdmcc-cd {
2257 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2260 sdmmc_wp: sdmmc-wp {
2262 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2267 spdif_bus: spdif-bus {
2269 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2272 spdif_bus_1: spdif-bus-1 {
2274 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2279 spi0_clk: spi0-clk {
2281 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2283 spi0_cs0: spi0-cs0 {
2285 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2287 spi0_cs1: spi0-cs1 {
2289 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2293 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2297 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2302 spi1_clk: spi1-clk {
2304 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2306 spi1_cs0: spi1-cs0 {
2308 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2312 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2316 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2321 spi2_clk: spi2-clk {
2323 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2325 spi2_cs0: spi2-cs0 {
2327 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2331 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2335 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2340 spi3_clk: spi3-clk {
2342 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2344 spi3_cs0: spi3-cs0 {
2346 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2350 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2354 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2359 spi4_clk: spi4-clk {
2361 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2363 spi4_cs0: spi4-cs0 {
2365 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2369 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2373 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2378 spi5_clk: spi5-clk {
2380 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2382 spi5_cs0: spi5-cs0 {
2384 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2388 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2392 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2397 otp_gpio: otp-gpio {
2398 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2402 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2407 uart0_xfer: uart0-xfer {
2409 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2410 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2413 uart0_cts: uart0-cts {
2415 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2418 uart0_rts: uart0-rts {
2420 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2425 uart1_xfer: uart1-xfer {
2427 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2428 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2433 uart2a_xfer: uart2a-xfer {
2435 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2436 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2441 uart2b_xfer: uart2b-xfer {
2443 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2444 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2449 uart2c_xfer: uart2c-xfer {
2451 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2452 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2457 uart3_xfer: uart3-xfer {
2459 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2460 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2463 uart3_cts: uart3-cts {
2465 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2468 uart3_rts: uart3-rts {
2470 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2475 uart4_xfer: uart4-xfer {
2477 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2478 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2483 uarthdcp_xfer: uarthdcp-xfer {
2485 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2486 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2491 pwm0_pin: pwm0-pin {
2493 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2496 vop0_pwm_pin: vop0-pwm-pin {
2498 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2503 pwm1_pin: pwm1-pin {
2505 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2508 vop1_pwm_pin: vop1-pwm-pin {
2510 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2515 pwm2_pin: pwm2-pin {
2517 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2522 pwm3a_pin: pwm3a-pin {
2524 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2529 pwm3b_pin: pwm3b-pin {
2531 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2538 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2543 hdmi_i2c_xfer: hdmi-i2c-xfer {
2545 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2546 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2549 hdmi_cec: hdmi-cec {
2551 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2556 pcie_clkreqn: pci-clkreqn {
2558 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2561 pcie_clkreqnb: pci-clkreqnb {
2563 <4 24 RK_FUNC_1 &pcfg_pull_none>;