arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42 #include <dt-bindings/clock/rk3399-cru.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/pinctrl/rockchip.h>
  46
  47 / {
  48         compatible = "rockchip,rk3399";
  49         interrupt-parent = <&gic>;
  50         #address-cells = <2>;
  51         #size-cells = <2>;
  52
  53         aliases {
  54                 serial0 = &uart0;
  55                 serial1 = &uart1;
  56                 serial2 = &uart2;
  57                 serial3 = &uart3;
  58         };
  59
  60         psci {
  61                 compatible = "arm,psci";
  62                 method = "smc";
  63         };
  64
  65         cpus {
  66                 #address-cells = <2>;
  67                 #size-cells = <0>;
  68
  69                 cpu-map {
  70                         cluster0 {
  71                                 core0 {
  72                                         cpu = <&cpu_l0>;
  73                                 };
  74                                 core1 {
  75                                         cpu = <&cpu_l1>;
  76                                 };
  77                                 core2 {
  78                                         cpu = <&cpu_l2>;
  79                                 };
  80                                 core3 {
  81                                         cpu = <&cpu_l3>;
  82                                 };
  83                         };
  84
  85                         cluster1 {
  86                                 core0 {
  87                                         cpu = <&cpu_b0>;
  88                                 };
  89                                 core1 {
  90                                         cpu = <&cpu_b1>;
  91                                 };
  92                         };
  93                 };
  94
  95                 idle-states {
  96                         entry-method = "psci";
  97
  98                         cpu_sleep: cpu-sleep-0 {
  99                                 compatible = "arm,idle-state";
 100                         };
 101                 };
 102
 103                 cpu_l0: cpu@0 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a53", "arm,armv8";
 106                         reg = <0x0 0x0>;
 107                         cpu-idle-states = <&cpu_sleep>;
 108                         enable-method = "psci";
 109                 };
 110
 111                 cpu_l1: cpu@1 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x1>;
 115                         cpu-idle-states = <&cpu_sleep>;
 116                         enable-method = "psci";
 117                 };
 118
 119                 cpu_l2: cpu@2 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         reg = <0x0 0x2>;
 123                         cpu-idle-states = <&cpu_sleep>;
 124                         enable-method = "psci";
 125                 };
 126
 127                 cpu_l3: cpu@3 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x0 0x3>;
 131                         cpu-idle-states = <&cpu_sleep>;
 132                         enable-method = "psci";
 133                 };
 134
 135                 cpu_b0: cpu@100 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a72", "arm,armv8";
 138                         reg = <0x0 0x100>;
 139                         cpu-idle-states = <&cpu_sleep>;
 140                         enable-method = "psci";
 141                 };
 142
 143                 cpu_b1: cpu@101 {
 144                         device_type = "cpu";
 145                         compatible = "arm,cortex-a72", "arm,armv8";
 146                         reg = <0x0 0x101>;
 147                         cpu-idle-states = <&cpu_sleep>;
 148                         enable-method = "psci";
 149                 };
 150         };
 151
 152         pmu {
 153                 compatible = "arm,armv8-pmuv3";
 154                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 155                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 156                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>;
 157         };
 158
 159         timer {
 160                 compatible = "arm,armv8-timer";
 161                 interrupts =
 162                         <GIC_PPI 13
 163                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 164                         <GIC_PPI 14
 165                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 166                         <GIC_PPI 11
 167                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 168                         <GIC_PPI 10
 169                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 170                 clock-frequency = <24000000>;
 171         };
 172
 173         xin24m: xin24m {
 174                 compatible = "fixed-clock";
 175                 #clock-cells = <0>;
 176                 clock-frequency = <24000000>;
 177                 clock-output-names = "xin24m";
 178         };
 179
 180         gic: interrupt-controller@fee00000 {
 181                 compatible = "arm,gic-v3";
 182                 #interrupt-cells = <3>;
 183                 #address-cells = <2>;
 184                 #size-cells = <2>;
 185                 ranges;
 186                 interrupt-controller;
 187
 188                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 189                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 190                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 191                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 192                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 193                 interrupts =
 194                         <GIC_PPI 9
 195                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 196                 its: interrupt-controller@fee20000 {
 197                         compatible = "arm,gic-v3-its";
 198                         msi-controller;
 199                         reg = <0x0 0xfee20000 0x0 0x20000>;
 200                 };
 201         };
 202
 203         amba {
 204                 compatible = "arm,amba-bus";
 205                 #address-cells = <2>;
 206                 #size-cells = <2>;
 207                 ranges;
 208
 209                 dmac_bus: dma-controller@ff6d0000 {
 210                         compatible = "arm,pl330", "arm,primecell";
 211                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 212                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 213                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 214                         #dma-cells = <1>;
 215                         clocks = <&cru ACLK_DMAC_BUS>;
 216                         clock-names = "apb_pclk";
 217                 };
 218
 219                 dmac_peri: dma-controller@ff6e0000 {
 220                         compatible = "arm,pl330", "arm,primecell";
 221                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 222                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 223                                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 224                         #dma-cells = <1>;
 225                         clocks = <&cru ACLK_DMAC_PERI>;
 226                         clock-names = "apb_pclk";
 227                 };
 228         };
 229
 230         uart0: serial@ff180000 {
 231                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 232                 reg = <0x0 0xff180000 0x0 0x100>;
 233                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 234                 clock-names = "baudclk", "apb_pclk";
 235                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 236                 reg-shift = <2>;
 237                 reg-io-width = <4>;
 238                 status = "disabled";
 239         };
 240
 241         uart1: serial@ff190000 {
 242                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 243                 reg = <0x0 0xff190000 0x0 0x100>;
 244                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 245                 clock-names = "baudclk", "apb_pclk";
 246                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 247                 reg-shift = <2>;
 248                 reg-io-width = <4>;
 249                 status = "disabled";
 250         };
 251
 252         uart2: serial@ff1a0000 {
 253                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 254                 reg = <0x0 0xff1a0000 0x0 0x100>;
 255                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 256                 clock-names = "baudclk", "apb_pclk";
 257                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 258                 reg-shift = <2>;
 259                 reg-io-width = <4>;
 260                 status = "disabled";
 261         };
 262
 263         uart3: serial@ff1b0000 {
 264                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 265                 reg = <0x0 0xff1b0000 0x0 0x100>;
 266                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 267                 clock-names = "baudclk", "apb_pclk";
 268                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 269                 reg-shift = <2>;
 270                 reg-io-width = <4>;
 271                 status = "disabled";
 272         };
 273
 274         pmugrf: syscon@ff320000 {
 275                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 276                 reg = <0x0 0xff320000 0x0 0x1000>;
 277         };
 278
 279         uart4: serial@ff370000 {
 280                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 281                 reg = <0x0 0xff370000 0x0 0x100>;
 282                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 283                 clock-names = "baudclk", "apb_pclk";
 284                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 285                 reg-shift = <2>;
 286                 reg-io-width = <4>;
 287                 status = "disabled";
 288         };
 289
 290         cru_pmu: pmu-clock-controller@ff750000 {
 291                 compatible = "rockchip,rk3399-pmu-cru";
 292                 reg = <0x0 0xff750000 0x0 0x1000>;
 293                 #clock-cells = <1>;
 294                 #reset-cells = <1>;
 295         };
 296
 297         cru: clock-controller@ff760000 {
 298                 compatible = "rockchip,rk3399-cru";
 299                 reg = <0x0 0xff760000 0x0 0x1000>;
 300                 rockchip,grf = <&grf>;
 301                 #clock-cells = <1>;
 302                 #reset-cells = <1>;
 303         };
 304
 305         grf: syscon@ff770000 {
 306                 compatible = "rockchip,rk3399-grf", "syscon";
 307                 reg = <0x0 0xff770000 0x0 0x10000>;
 308         };
 309
 310         i2s0: i2s@ff880000 {
 311                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 312                 reg = <0x0 0xff880000 0x0 0x1000>;
 313                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 317                 dma-names = "tx", "rx";
 318                 clock-names = "i2s_hclk", "i2s_clk";
 319                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 320                 status = "disabled";
 321         };
 322
 323         i2s1: i2s@ff890000 {
 324                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 325                 reg = <0x0 0xff890000 0x0 0x1000>;
 326                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 330                 dma-names = "tx", "rx";
 331                 clock-names = "i2s_hclk", "i2s_clk";
 332                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 333                 status = "disabled";
 334         };
 335
 336         i2s2: i2s@ff8a0000 {
 337                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 338                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 339                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 343                 dma-names = "tx", "rx";
 344                 clock-names = "i2s_hclk", "i2s_clk";
 345                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 346                 status = "disabled";
 347         };
 348
 349         pinctrl: pinctrl {
 350                 compatible = "rockchip,rk3399-pinctrl";
 351                 rockchip,grf = <&grf>;
 352                 rockchip,pmu = <&pmugrf>;
 353                 #address-cells = <0x2>;
 354                 #size-cells = <0x2>;
 355                 ranges;
 356
 357                 gpio0: gpio0@ff720000 {
 358                         compatible = "rockchip,gpio-bank";
 359                         reg = <0x0 0xff720000 0x0 0x100>;
 360                         clocks = <&xin24m>;
 361                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 362
 363                         gpio-controller;
 364                         #gpio-cells = <0x2>;
 365
 366                         interrupt-controller;
 367                         #interrupt-cells = <0x2>;
 368                 };
 369
 370                 gpio1: gpio1@ff730000 {
 371                         compatible = "rockchip,gpio-bank";
 372                         reg = <0x0 0xff730000 0x0 0x100>;
 373                         clocks = <&xin24m>;
 374                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 375
 376                         gpio-controller;
 377                         #gpio-cells = <0x2>;
 378
 379                         interrupt-controller;
 380                         #interrupt-cells = <0x2>;
 381                 };
 382
 383                 gpio2: gpio2@ff780000 {
 384                         compatible = "rockchip,gpio-bank";
 385                         reg = <0x0 0xff780000 0x0 0x100>;
 386                         clocks = <&xin24m>;
 387                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 388
 389                         gpio-controller;
 390                         #gpio-cells = <0x2>;
 391
 392                         interrupt-controller;
 393                         #interrupt-cells = <0x2>;
 394                 };
 395
 396                 gpio3: gpio3@ff788000 {
 397                         compatible = "rockchip,gpio-bank";
 398                         reg = <0x0 0xff788000 0x0 0x100>;
 399                         clocks = <&xin24m>;
 400                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 401
 402                         gpio-controller;
 403                         #gpio-cells = <0x2>;
 404
 405                         interrupt-controller;
 406                         #interrupt-cells = <0x2>;
 407                 };
 408
 409                 gpio4: gpio4@ff790000 {
 410                         compatible = "rockchip,gpio-bank";
 411                         reg = <0x0 0xff790000 0x0 0x100>;
 412                         clocks = <&xin24m>;
 413                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 414
 415                         gpio-controller;
 416                         #gpio-cells = <0x2>;
 417
 418                         interrupt-controller;
 419                         #interrupt-cells = <0x2>;
 420                 };
 421
 422                 pcfg_pull_up: pcfg-pull-up {
 423                         bias-pull-up;
 424                 };
 425
 426                 pcfg_pull_down: pcfg-pull-down {
 427                         bias-pull-down;
 428                 };
 429
 430                 pcfg_pull_none: pcfg-pull-none {
 431                         bias-disable;
 432                 };
 433
 434                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 435                         bias-disable;
 436                         drive-strength = <12>;
 437                 };
 438
 439                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 440                         bias-pull-up;
 441                         drive-strength = <8>;
 442                 };
 443
 444                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 445                         bias-pull-down;
 446                         drive-strength = <4>;
 447                 };
 448
 449                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 450                         bias-pull-up;
 451                         drive-strength = <2>;
 452                 };
 453
 454                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 455                         bias-pull-down;
 456                         drive-strength = <12>;
 457                 };
 458
 459                 emmc {
 460                         emmc_pwr: emmc-pwr {
 461                                 rockchip,pins =
 462                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
 463                         };
 464                 };
 465
 466                 gmac {
 467                         rgmii_pins: rgmii-pins {
 468                                 rockchip,pins =
 469                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 470                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 471                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 472                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 473                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 474                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
 475                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
 476                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
 477                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 478                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 479                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 480                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
 481                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
 482                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
 483                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
 484                         };
 485
 486                         rmii_pins: rmii-pins {
 487                                 rockchip,pins =
 488                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 489                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 490                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 491                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 492                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 493                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 494                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 495                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 496                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
 497                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
 498                         };
 499                 };
 500
 501                 i2c0 {
 502                         i2c0_xfer: i2c0-xfer {
 503                                 rockchip,pins =
 504                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
 505                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
 506                         };
 507                 };
 508
 509                 i2c1 {
 510                         i2c1_xfer: i2c1-xfer {
 511                                 rockchip,pins =
 512                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
 513                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
 514                         };
 515                 };
 516
 517                 i2c2 {
 518                         i2c2_xfer: i2c2-xfer {
 519                                 rockchip,pins =
 520                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
 521                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
 522                         };
 523                 };
 524
 525                 i2c3 {
 526                         i2c3_xfer: i2c3-xfer {
 527                                 rockchip,pins =
 528                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 529                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
 530                         };
 531                 };
 532
 533                 i2c4 {
 534                         i2c4_xfer: i2c4-xfer {
 535                                 rockchip,pins =
 536                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
 537                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 538                         };
 539                 };
 540
 541                 i2c5 {
 542                         i2c5_xfer: i2c5-xfer {
 543                                 rockchip,pins =
 544                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
 545                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
 546                         };
 547                 };
 548
 549                 i2c6 {
 550                         i2c6_xfer: i2c6-xfer {
 551                                 rockchip,pins =
 552                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
 553                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
 554                         };
 555                 };
 556
 557                 i2c7 {
 558                         i2c7_xfer: i2c7-xfer {
 559                                 rockchip,pins =
 560                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
 561                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
 562                         };
 563                 };
 564
 565                 i2c8 {
 566                         i2c8_xfer: i2c8-xfer {
 567                                 rockchip,pins =
 568                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
 569                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
 570                         };
 571                 };
 572
 573                 i2s0 {
 574                         i2s0_8ch_bus: i2s0-8ch-bus {
 575                                 rockchip,pins =
 576                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
 577                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
 578                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
 579                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
 580                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
 581                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
 582                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
 583                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
 584                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
 585                         };
 586                 };
 587
 588                 i2s1 {
 589                         i2s1_2ch_bus: i2s1-2ch-bus {
 590                                 rockchip,pins =
 591                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
 592                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
 593                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
 594                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
 595                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
 596                         };
 597                 };
 598
 599                 sdio0 {
 600                         sdio0_bus1: sdio0-bus1 {
 601                                 rockchip,pins =
 602                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
 603                         };
 604
 605                         sdio0_bus4: sdio0-bus4 {
 606                                 rockchip,pins =
 607                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
 608                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
 609                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
 610                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
 611                         };
 612
 613                         sdio0_cmd: sdio0-cmd {
 614                                 rockchip,pins =
 615                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
 616                         };
 617
 618                         sdio0_clk: sdio0-clk {
 619                                 rockchip,pins =
 620                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 621                         };
 622
 623                         sdio0_cd: sdio0-cd {
 624                                 rockchip,pins =
 625                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
 626                         };
 627
 628                         sdio0_pwr: sdio0-pwr {
 629                                 rockchip,pins =
 630                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
 631                         };
 632
 633                         sdio0_bkpwr: sdio0-bkpwr {
 634                                 rockchip,pins =
 635                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
 636                         };
 637
 638                         sdio0_wp: sdio0-wp {
 639                                 rockchip,pins =
 640                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
 641                         };
 642
 643                         sdio0_int: sdio0-int {
 644                                 rockchip,pins =
 645                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
 646                         };
 647                 };
 648
 649                 sdmmc {
 650                         sdmmc_bus1: sdmmc-bus1 {
 651                                 rockchip,pins =
 652                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
 653                         };
 654
 655                         sdmmc_bus4: sdmmc-bus4 {
 656                                 rockchip,pins =
 657                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
 658                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
 659                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
 660                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
 661                         };
 662
 663                         sdmmc_clk: sdmmc-clk {
 664                                 rockchip,pins =
 665                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
 666                         };
 667
 668                         sdmmc_cmd: sdmmc-cmd {
 669                                 rockchip,pins =
 670                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
 671                         };
 672
 673                         sdmmc_cd: sdmcc-cd {
 674                                 rockchip,pins =
 675                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
 676                         };
 677
 678                         sdmmc_wp: sdmmc-wp {
 679                                 rockchip,pins =
 680                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
 681                         };
 682                 };
 683
 684                 spi0 {
 685                         spi0_clk: spi0-clk {
 686                                 rockchip,pins =
 687                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
 688                         };
 689                         spi0_cs0: spi0-cs0 {
 690                                 rockchip,pins =
 691                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
 692                         };
 693                         spi0_cs1: spi0-cs1 {
 694                                 rockchip,pins =
 695                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
 696                         };
 697                         spi0_tx: spi0-tx {
 698                                 rockchip,pins =
 699                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
 700                         };
 701                         spi0_rx: spi0-rx {
 702                                 rockchip,pins =
 703                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
 704                         };
 705                 };
 706
 707                 spi1 {
 708                         spi1_clk: spi1-clk {
 709                                 rockchip,pins =
 710                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
 711                         };
 712                         spi1_cs0: spi1-cs0 {
 713                                 rockchip,pins =
 714                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
 715                         };
 716                         spi1_rx: spi1-rx {
 717                                 rockchip,pins =
 718                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
 719                         };
 720                         spi1_tx: spi1-tx {
 721                                 rockchip,pins =
 722                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
 723                         };
 724                 };
 725
 726                 spi2 {
 727                         spi2_clk: spi2-clk {
 728                                 rockchip,pins =
 729                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 730                         };
 731                         spi2_cs0: spi2-cs0 {
 732                                 rockchip,pins =
 733                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 734                         };
 735                         spi2_rx: spi2-rx {
 736                                 rockchip,pins =
 737                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 738                         };
 739                         spi2_tx: spi2-tx {
 740                                 rockchip,pins =
 741                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 742                         };
 743                 };
 744
 745                 spi3 {
 746                         spi3_clk: spi3-clk {
 747                                 rockchip,pins =
 748                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
 749                         };
 750                         spi3_cs0: spi3-cs0 {
 751                                 rockchip,pins =
 752                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
 753                         };
 754                         spi3_rx: spi3-rx {
 755                                 rockchip,pins =
 756                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
 757                         };
 758                         spi3_tx: spi3-tx {
 759                                 rockchip,pins =
 760                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
 761                         };
 762                 };
 763
 764                 spi4 {
 765                         spi4_clk: spi4-clk {
 766                                 rockchip,pins =
 767                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
 768                         };
 769                         spi4_cs0: spi4-cs0 {
 770                                 rockchip,pins =
 771                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
 772                         };
 773                         spi4_rx: spi4-rx {
 774                                 rockchip,pins =
 775                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
 776                         };
 777                         spi4_tx: spi4-tx {
 778                                 rockchip,pins =
 779                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
 780                         };
 781                 };
 782
 783                 spi5 {
 784                         spi5_clk: spi5-clk {
 785                                 rockchip,pins =
 786                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
 787                         };
 788                         spi5_cs0: spi5-cs0 {
 789                                 rockchip,pins =
 790                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
 791                         };
 792                         spi5_rx: spi5-rx {
 793                                 rockchip,pins =
 794                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
 795                         };
 796                         spi5_tx: spi5-tx {
 797                                 rockchip,pins =
 798                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
 799                         };
 800                 };
 801
 802                 uart0 {
 803                         uart0_xfer: uart0-xfer {
 804                                 rockchip,pins =
 805                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
 806                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
 807                         };
 808
 809                         uart0_cts: uart0-cts {
 810                                 rockchip,pins =
 811                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
 812                         };
 813
 814                         uart0_rts: uart0-rts {
 815                                 rockchip,pins =
 816                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
 817                         };
 818                 };
 819
 820                 uart1 {
 821                         uart1_xfer: uart1-xfer {
 822                                 rockchip,pins =
 823                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
 824                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
 825                         };
 826                 };
 827
 828                 uart2a {
 829                         uart2a_xfer: uart2a-xfer {
 830                                 rockchip,pins =
 831                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
 832                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
 833                         };
 834                 };
 835
 836                 uart2b {
 837                         uart2b_xfer: uart2b-xfer {
 838                                 rockchip,pins =
 839                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
 840                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
 841                         };
 842                 };
 843
 844                 uart2c {
 845                         uart2c_xfer: uart2c-xfer {
 846                                 rockchip,pins =
 847                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
 848                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
 849                         };
 850                 };
 851
 852                 uart3 {
 853                         uart3_xfer: uart3-xfer {
 854                                 rockchip,pins =
 855                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
 856                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
 857                         };
 858
 859                         uart3_cts: uart3-cts {
 860                                 rockchip,pins =
 861                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
 862                         };
 863
 864                         uart3_rts: uart3-rts {
 865                                 rockchip,pins =
 866                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
 867                         };
 868                 };
 869
 870                 uart4 {
 871                         uart4_xfer: uart4-xfer {
 872                                 rockchip,pins =
 873                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
 874                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 875                         };
 876                 };
 877
 878                 uarthdcp {
 879                         uarthdcp_xfer: uarthdcp-xfer {
 880                                 rockchip,pins =
 881                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
 882                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
 883                         };
 884                 };
 885
 886                 pwm0 {
 887                         pwm0_pin: pwm0-pin {
 888                                 rockchip,pins =
 889                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
 890                         };
 891
 892                         vop0_pwm_pin: vop0-pwm-pin {
 893                                 rockchip,pins =
 894                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
 895                         };
 896                 };
 897
 898                 pwm1 {
 899                         pwm1_pin: pwm1-pin {
 900                                 rockchip,pins =
 901                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
 902                         };
 903
 904                         vop1_pwm_pin: vop1-pwm-pin {
 905                                 rockchip,pins =
 906                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
 907                         };
 908                 };
 909         };
 910 };