2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
52 compatible = "rockchip,rk3399";
54 interrupt-parent = <&gic>;
76 compatible = "arm,psci-1.0";
112 compatible = "arm,cortex-a53", "arm,armv8";
114 enable-method = "psci";
115 #cooling-cells = <2>; /* min followed by max */
116 clocks = <&cru ARMCLKL>;
117 cpu-idle-states = <&cpu_sleep>;
118 operating-points-v2 = <&cluster0_opp>;
123 compatible = "arm,cortex-a53", "arm,armv8";
125 enable-method = "psci";
126 clocks = <&cru ARMCLKL>;
127 cpu-idle-states = <&cpu_sleep>;
128 operating-points-v2 = <&cluster0_opp>;
133 compatible = "arm,cortex-a53", "arm,armv8";
135 enable-method = "psci";
136 clocks = <&cru ARMCLKL>;
137 cpu-idle-states = <&cpu_sleep>;
138 operating-points-v2 = <&cluster0_opp>;
143 compatible = "arm,cortex-a53", "arm,armv8";
145 enable-method = "psci";
146 clocks = <&cru ARMCLKL>;
147 cpu-idle-states = <&cpu_sleep>;
148 operating-points-v2 = <&cluster0_opp>;
153 compatible = "arm,cortex-a72", "arm,armv8";
155 enable-method = "psci";
156 #cooling-cells = <2>; /* min followed by max */
157 clocks = <&cru ARMCLKB>;
158 cpu-idle-states = <&cpu_sleep>;
159 operating-points-v2 = <&cluster1_opp>;
164 compatible = "arm,cortex-a72", "arm,armv8";
166 enable-method = "psci";
167 clocks = <&cru ARMCLKB>;
168 cpu-idle-states = <&cpu_sleep>;
169 operating-points-v2 = <&cluster1_opp>;
173 entry-method = "psci";
174 cpu_sleep: cpu-sleep-0 {
175 compatible = "arm,idle-state";
177 arm,psci-suspend-param = <0x0010000>;
178 entry-latency-us = <350>;
179 exit-latency-us = <600>;
180 min-residency-us = <1150>;
185 cluster0_opp: opp_table0 {
186 compatible = "operating-points-v2";
190 opp-hz = /bits/ 64 <408000000>;
191 opp-microvolt = <800000>;
192 clock-latency-ns = <40000>;
195 opp-hz = /bits/ 64 <600000000>;
196 opp-microvolt = <800000>;
199 opp-hz = /bits/ 64 <816000000>;
200 opp-microvolt = <800000>;
203 opp-hz = /bits/ 64 <1008000000>;
204 opp-microvolt = <875000>;
207 opp-hz = /bits/ 64 <1200000000>;
208 opp-microvolt = <925000>;
211 opp-hz = /bits/ 64 <1416000000>;
212 opp-microvolt = <1025000>;
216 cluster1_opp: opp_table1 {
217 compatible = "operating-points-v2";
221 opp-hz = /bits/ 64 <408000000>;
222 opp-microvolt = <800000>;
223 clock-latency-ns = <40000>;
226 opp-hz = /bits/ 64 <600000000>;
227 opp-microvolt = <800000>;
230 opp-hz = /bits/ 64 <816000000>;
231 opp-microvolt = <800000>;
234 opp-hz = /bits/ 64 <1008000000>;
235 opp-microvolt = <850000>;
238 opp-hz = /bits/ 64 <1200000000>;
239 opp-microvolt = <925000>;
244 compatible = "arm,armv8-timer";
245 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
246 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
247 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
248 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
252 compatible = "arm,armv8-pmuv3";
253 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
257 compatible = "fixed-clock";
259 clock-frequency = <24000000>;
260 clock-output-names = "xin24m";
264 compatible = "arm,amba-bus";
265 #address-cells = <2>;
269 dmac_bus: dma-controller@ff6d0000 {
270 compatible = "arm,pl330", "arm,primecell";
271 reg = <0x0 0xff6d0000 0x0 0x4000>;
272 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&cru ACLK_DMAC0_PERILP>;
276 clock-names = "apb_pclk";
279 dmac_peri: dma-controller@ff6e0000 {
280 compatible = "arm,pl330", "arm,primecell";
281 reg = <0x0 0xff6e0000 0x0 0x4000>;
282 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cru ACLK_DMAC1_PERILP>;
286 clock-names = "apb_pclk";
291 compatible = "rockchip,rk3399-gmac";
292 reg = <0x0 0xfe300000 0x0 0x10000>;
293 rockchip,grf = <&grf>;
294 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
295 interrupt-names = "macirq";
296 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
297 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
298 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
300 clock-names = "stmmaceth", "mac_clk_rx",
301 "mac_clk_tx", "clk_mac_ref",
302 "clk_mac_refout", "aclk_mac",
304 resets = <&cru SRST_A_GMAC>;
305 reset-names = "stmmaceth";
310 compatible = "rockchip,rk3399-emmc-phy";
311 reg-offset = <0xf780>;
313 rockchip,grf = <&grf>;
314 ctrl-base = <0xfe330000>;
318 sdio0: dwmmc@fe310000 {
319 compatible = "rockchip,rk3399-dw-mshc",
320 "rockchip,rk3288-dw-mshc";
321 reg = <0x0 0xfe310000 0x0 0x4000>;
322 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
323 clock-freq-min-max = <400000 150000000>;
324 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
325 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
326 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
327 fifo-depth = <0x100>;
331 sdmmc: dwmmc@fe320000 {
332 compatible = "rockchip,rk3399-dw-mshc",
333 "rockchip,rk3288-dw-mshc";
334 reg = <0x0 0xfe320000 0x0 0x4000>;
335 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
336 clock-freq-min-max = <400000 150000000>;
337 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
338 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
339 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
340 fifo-depth = <0x100>;
344 sdhci: sdhci@fe330000 {
345 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
346 reg = <0x0 0xfe330000 0x0 0x10000>;
347 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
349 clock-names = "clk_xin", "clk_ahb";
350 assigned-clocks = <&cru SCLK_EMMC>;
351 assigned-clock-parents = <&cru PLL_CPLL>;
352 assigned-clock-rates = <200000000>;
354 phy-names = "phy_arasan";
359 compatible = "rockchip,rk3399-usb-phy";
360 rockchip,grf = <&grf>;
361 #address-cells = <1>;
364 usb2phy0: usb2-phy0 {
370 usb2phy1: usb2-phy1 {
377 usb_host0_ehci: usb@fe380000 {
378 compatible = "generic-ehci";
379 reg = <0x0 0xfe380000 0x0 0x20000>;
380 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
382 clock-names = "hclk_host0", "hclk_host0_arb";
384 phy-names = "usb2_phy0";
388 usb_host0_ohci: usb@fe3a0000 {
389 compatible = "generic-ohci";
390 reg = <0x0 0xfe3a0000 0x0 0x20000>;
391 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
393 clock-names = "hclk_host0", "hclk_host0_arb";
397 usb_host1_ehci: usb@fe3c0000 {
398 compatible = "generic-ehci";
399 reg = <0x0 0xfe3c0000 0x0 0x20000>;
400 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
402 clock-names = "hclk_host1", "hclk_host1_arb";
404 phy-names = "usb2_phy1";
408 usb_host1_ohci: usb@fe3e0000 {
409 compatible = "generic-ohci";
410 reg = <0x0 0xfe3e0000 0x0 0x20000>;
411 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
413 clock-names = "hclk_host1", "hclk_host1_arb";
417 usbdrd3_0: usb@fe800000 {
418 compatible = "rockchip,dwc3";
419 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
420 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
421 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
422 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
423 "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
424 "aclk_usb3", "aclk_usb3_grf";
425 #address-cells = <2>;
429 usbdrd_dwc3_0: dwc3 {
430 compatible = "snps,dwc3";
431 reg = <0x0 0xfe800000 0x0 0x100000>;
432 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
435 snps,dis_enblslpm_quirk;
436 snps,phyif_utmi_16_bits;
437 snps,dis_u2_freeclk_exists_quirk;
438 snps,dis_del_phy_power_chg_quirk;
439 snps,xhci_slow_suspend_quirk;
444 usbdrd3_1: usb@fe900000 {
445 compatible = "rockchip,dwc3";
446 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
447 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
448 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
449 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
450 "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
451 "aclk_usb3", "aclk_usb3_grf";
452 #address-cells = <2>;
456 usbdrd_dwc3_1: dwc3 {
457 compatible = "snps,dwc3";
458 reg = <0x0 0xfe900000 0x0 0x100000>;
459 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
462 snps,dis_enblslpm_quirk;
463 snps,phyif_utmi_16_bits;
464 snps,dis_u2_freeclk_exists_quirk;
465 snps,dis_del_phy_power_chg_quirk;
466 snps,xhci_slow_suspend_quirk;
471 gic: interrupt-controller@fee00000 {
472 compatible = "arm,gic-v3";
473 #interrupt-cells = <3>;
474 #address-cells = <2>;
477 interrupt-controller;
479 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
480 <0x0 0xfef00000 0 0xc0000>, /* GICR */
481 <0x0 0xfff00000 0 0x10000>, /* GICC */
482 <0x0 0xfff10000 0 0x10000>, /* GICH */
483 <0x0 0xfff20000 0 0x10000>; /* GICV */
484 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
485 its: interrupt-controller@fee20000 {
486 compatible = "arm,gic-v3-its";
488 reg = <0x0 0xfee20000 0x0 0x20000>;
492 saradc: saradc@ff100000 {
493 compatible = "rockchip,rk3399-saradc";
494 reg = <0x0 0xff100000 0x0 0x100>;
495 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
496 #io-channel-cells = <1>;
497 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
498 clock-names = "saradc", "apb_pclk";
503 compatible = "rockchip,rk3399-i2c";
504 reg = <0x0 0xff3c0000 0x0 0x1000>;
505 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
506 clock-names = "i2c", "pclk";
507 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
508 pinctrl-names = "default";
509 pinctrl-0 = <&i2c0_xfer>;
510 #address-cells = <1>;
516 compatible = "rockchip,rk3399-i2c";
517 reg = <0x0 0xff110000 0x0 0x1000>;
518 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
519 clock-names = "i2c", "pclk";
520 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&i2c1_xfer>;
523 #address-cells = <1>;
529 compatible = "rockchip,rk3399-i2c";
530 reg = <0x0 0xff120000 0x0 0x1000>;
531 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
532 clock-names = "i2c", "pclk";
533 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
534 pinctrl-names = "default";
535 pinctrl-0 = <&i2c2_xfer>;
536 #address-cells = <1>;
542 compatible = "rockchip,rk3399-i2c";
543 reg = <0x0 0xff130000 0x0 0x1000>;
544 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
545 clock-names = "i2c", "pclk";
546 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
547 pinctrl-names = "default";
548 pinctrl-0 = <&i2c3_xfer>;
549 #address-cells = <1>;
555 compatible = "rockchip,rk3399-i2c";
556 reg = <0x0 0xff140000 0x0 0x1000>;
557 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
558 clock-names = "i2c", "pclk";
559 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&i2c5_xfer>;
562 #address-cells = <1>;
568 compatible = "rockchip,rk3399-i2c";
569 reg = <0x0 0xff150000 0x0 0x1000>;
570 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
571 clock-names = "i2c", "pclk";
572 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
573 pinctrl-names = "default";
574 pinctrl-0 = <&i2c6_xfer>;
575 #address-cells = <1>;
581 compatible = "rockchip,rk3399-i2c";
582 reg = <0x0 0xff160000 0x0 0x1000>;
583 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
584 clock-names = "i2c", "pclk";
585 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&i2c7_xfer>;
588 #address-cells = <1>;
593 uart0: serial@ff180000 {
594 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
595 reg = <0x0 0xff180000 0x0 0x100>;
596 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
597 clock-names = "baudclk", "apb_pclk";
598 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
601 pinctrl-names = "default";
602 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
606 uart1: serial@ff190000 {
607 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
608 reg = <0x0 0xff190000 0x0 0x100>;
609 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
610 clock-names = "baudclk", "apb_pclk";
611 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
614 pinctrl-names = "default";
615 pinctrl-0 = <&uart1_xfer>;
619 uart2: serial@ff1a0000 {
620 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
621 reg = <0x0 0xff1a0000 0x0 0x100>;
622 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
623 clock-names = "baudclk", "apb_pclk";
624 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&uart2c_xfer>;
632 uart3: serial@ff1b0000 {
633 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
634 reg = <0x0 0xff1b0000 0x0 0x100>;
635 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
636 clock-names = "baudclk", "apb_pclk";
637 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
640 pinctrl-names = "default";
641 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
646 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
647 reg = <0x0 0xff1c0000 0x0 0x1000>;
648 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
649 clock-names = "spiclk", "apb_pclk";
650 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
651 pinctrl-names = "default";
652 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
653 #address-cells = <1>;
659 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
660 reg = <0x0 0xff1d0000 0x0 0x1000>;
661 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
662 clock-names = "spiclk", "apb_pclk";
663 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
664 pinctrl-names = "default";
665 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
666 #address-cells = <1>;
672 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
673 reg = <0x0 0xff1e0000 0x0 0x1000>;
674 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
675 clock-names = "spiclk", "apb_pclk";
676 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
677 pinctrl-names = "default";
678 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
679 #address-cells = <1>;
685 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
686 reg = <0x0 0xff1f0000 0x0 0x1000>;
687 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
688 clock-names = "spiclk", "apb_pclk";
689 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
690 pinctrl-names = "default";
691 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
692 #address-cells = <1>;
698 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
699 reg = <0x0 0xff200000 0x0 0x1000>;
700 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
701 clock-names = "spiclk", "apb_pclk";
702 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
703 pinctrl-names = "default";
704 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
705 #address-cells = <1>;
712 polling-delay-passive = <100>; /* milliseconds */
713 polling-delay = <1000>; /* milliseconds */
715 thermal-sensors = <&tsadc 0>;
718 cpu_alert0: cpu_alert0 {
719 temperature = <70000>; /* millicelsius */
720 hysteresis = <2000>; /* millicelsius */
723 cpu_alert1: cpu_alert1 {
724 temperature = <75000>; /* millicelsius */
725 hysteresis = <2000>; /* millicelsius */
729 temperature = <95000>; /* millicelsius */
730 hysteresis = <2000>; /* millicelsius */
737 trip = <&cpu_alert0>;
739 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
742 trip = <&cpu_alert1>;
744 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
745 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
751 polling-delay-passive = <100>; /* milliseconds */
752 polling-delay = <1000>; /* milliseconds */
754 thermal-sensors = <&tsadc 1>;
757 gpu_alert0: gpu_alert0 {
758 temperature = <75000>; /* millicelsius */
759 hysteresis = <2000>; /* millicelsius */
763 temperature = <95000>; /* millicelsius */
764 hysteresis = <2000>; /* millicelsius */
771 trip = <&gpu_alert0>;
773 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
779 tsadc: tsadc@ff260000 {
780 compatible = "rockchip,rk3399-tsadc";
781 reg = <0x0 0xff260000 0x0 0x100>;
782 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
783 rockchip,grf = <&grf>;
784 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
785 clock-names = "tsadc", "apb_pclk";
786 assigned-clocks = <&cru SCLK_TSADC>;
787 assigned-clock-rates = <750000>;
788 resets = <&cru SRST_TSADC>;
789 reset-names = "tsadc-apb";
790 pinctrl-names = "init", "default", "sleep";
791 pinctrl-0 = <&otp_gpio>;
792 pinctrl-1 = <&otp_out>;
793 pinctrl-2 = <&otp_gpio>;
794 #thermal-sensor-cells = <1>;
795 rockchip,hw-tshut-temp = <95000>;
799 qos_gpu: qos_gpu@0xffae0000 {
800 compatible ="syscon";
801 reg = <0x0 0xffae0000 0x0 0x20>;
803 qos_video_m0: qos_video_m0@0xffab8000 {
804 compatible ="syscon";
805 reg = <0x0 0xffab8000 0x0 0x20>;
807 qos_video_m1_r: qos_video_m1_r@0xffac0000 {
808 compatible ="syscon";
809 reg = <0x0 0xffac0000 0x0 0x20>;
811 qos_video_m1_w: qos_video_m1_w@0xffac0080 {
812 compatible ="syscon";
813 reg = <0x0 0xffac0080 0x0 0x20>;
815 qos_rga_r: qos_rga_r@0xffab0000 {
816 compatible ="syscon";
817 reg = <0x0 0xffab0000 0x0 0x20>;
819 qos_rga_w: qos_rga_w@0xffab0080 {
820 compatible ="syscon";
821 reg = <0x0 0xffab0000 0x0 0x20>;
823 qos_iep: qos_iep@0xffa98000 {
824 compatible ="syscon";
825 reg = <0x0 0xffa98000 0x0 0x20>;
827 qos_vop_big_r: qos_vop_big_r@0xffac8000 {
828 compatible ="syscon";
829 reg = <0x0 0xffac8000 0x0 0x20>;
831 qos_vop_big_w: qos_vop_big_w@0xffac8080 {
832 compatible ="syscon";
833 reg = <0x0 0xffac8080 0x0 0x20>;
835 qos_vop_little: qos_vop_little@0xffad0000 {
836 compatible ="syscon";
837 reg = <0x0 0xffad0000 0x0 0x20>;
839 qos_isp0_m0: qos_isp0_m0@0xffaa0000 {
840 compatible ="syscon";
841 reg = <0x0 0xffaa0000 0x0 0x20>;
843 qos_isp0_m1: qos_isp0_m1@0xffaa0080 {
844 compatible ="syscon";
845 reg = <0x0 0xffaa0080 0x0 0x20>;
847 qos_isp1_m0: qos_isp1_m0@0xffaa8000 {
848 compatible ="syscon";
849 reg = <0x0 0xffaa8000 0x0 0x20>;
851 qos_isp1_m1: qos_isp1_m1@0xffaa8080 {
852 compatible ="syscon";
853 reg = <0x0 0xffaa8080 0x0 0x20>;
855 qos_hdcp: qos_hdcp@0xffa90000 {
856 compatible ="syscon";
857 reg = <0x0 0xffa90000 0x0 0x20>;
860 pmu: power-management@ff310000 {
861 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
862 reg = <0x0 0xff310000 0x0 0x1000>;
864 power: power-controller {
866 compatible = "rockchip,rk3399-power-controller";
867 #power-domain-cells = <1>;
868 #address-cells = <1>;
872 reg = <RK3399_PD_CENTER>;
873 #address-cells = <1>;
877 reg = <RK3399_PD_VDU>;
878 pm_qos = <&qos_video_m1_r>,
882 reg = <RK3399_PD_VCODEC>;
883 pm_qos = <&qos_video_m0>;
886 reg = <RK3399_PD_IEP>;
890 reg = <RK3399_PD_RGA>;
891 pm_qos = <&qos_rga_r>,
896 reg = <RK3399_PD_VIO>;
897 #address-cells = <1>;
901 reg = <RK3399_PD_ISP0>;
902 pm_qos = <&qos_isp0_m0>,
906 reg = <RK3399_PD_ISP1>;
907 pm_qos = <&qos_isp1_m0>,
911 reg = <RK3399_PD_HDCP>;
912 pm_qos = <&qos_hdcp>;
915 reg = <RK3399_PD_VO>;
916 #address-cells = <1>;
920 reg = <RK3399_PD_VOPB>;
921 pm_qos = <&qos_vop_big_r>,
925 reg = <RK3399_PD_VOPL>;
926 pm_qos = <&qos_vop_little>;
931 reg = <RK3399_PD_GPU>;
937 pmugrf: syscon@ff320000 {
938 compatible = "rockchip,rk3399-pmugrf", "syscon";
939 reg = <0x0 0xff320000 0x0 0x1000>;
943 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
944 reg = <0x0 0xff350000 0x0 0x1000>;
945 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
946 clock-names = "spiclk", "apb_pclk";
947 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
948 pinctrl-names = "default";
949 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
950 #address-cells = <1>;
955 uart4: serial@ff370000 {
956 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
957 reg = <0x0 0xff370000 0x0 0x100>;
958 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
959 clock-names = "baudclk", "apb_pclk";
960 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
963 pinctrl-names = "default";
964 pinctrl-0 = <&uart4_xfer>;
969 compatible = "rockchip,rk3399-i2c";
970 reg = <0x0 0xff3d0000 0x0 0x1000>;
971 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
972 clock-names = "i2c", "pclk";
973 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
974 pinctrl-names = "default";
975 pinctrl-0 = <&i2c4_xfer>;
976 #address-cells = <1>;
982 compatible = "rockchip,rk3399-i2c";
983 reg = <0x0 0xff3e0000 0x0 0x1000>;
984 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
985 clock-names = "i2c", "pclk";
986 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
987 pinctrl-names = "default";
988 pinctrl-0 = <&i2c8_xfer>;
989 #address-cells = <1>;
995 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
996 reg = <0x0 0xff420000 0x0 0x10>;
998 pinctrl-names = "default";
999 pinctrl-0 = <&pwm0_pin>;
1000 clocks = <&pmucru PCLK_RKPWM_PMU>;
1001 clock-names = "pwm";
1002 status = "disabled";
1005 pwm1: pwm@ff420010 {
1006 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1007 reg = <0x0 0xff420010 0x0 0x10>;
1009 pinctrl-names = "default";
1010 pinctrl-0 = <&pwm1_pin>;
1011 clocks = <&pmucru PCLK_RKPWM_PMU>;
1012 clock-names = "pwm";
1013 status = "disabled";
1016 pwm2: pwm@ff420020 {
1017 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1018 reg = <0x0 0xff420020 0x0 0x10>;
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&pwm2_pin>;
1022 clocks = <&pmucru PCLK_RKPWM_PMU>;
1023 clock-names = "pwm";
1024 status = "disabled";
1027 pwm3: pwm@ff420030 {
1028 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1029 reg = <0x0 0xff420030 0x0 0x10>;
1031 pinctrl-names = "default";
1032 pinctrl-0 = <&pwm3a_pin>;
1033 clocks = <&pmucru PCLK_RKPWM_PMU>;
1034 clock-names = "pwm";
1035 status = "disabled";
1039 compatible = "rockchip,rk3399-rga";
1040 reg = <0x0 0xff680000 0x0 0x10000>;
1041 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1042 interrupt-names = "rga";
1043 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1044 clock-names = "aclk", "hclk", "sclk";
1045 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1046 reset-names = "core", "axi", "ahb";
1047 status = "disabled";
1050 pmucru: pmu-clock-controller@ff750000 {
1051 compatible = "rockchip,rk3399-pmucru";
1052 reg = <0x0 0xff750000 0x0 0x1000>;
1055 assigned-clocks = <&pmucru PLL_PPLL>;
1056 assigned-clock-rates = <676000000>;
1059 cru: clock-controller@ff760000 {
1060 compatible = "rockchip,rk3399-cru";
1061 reg = <0x0 0xff760000 0x0 0x1000>;
1065 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1066 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1067 <&cru ARMCLKL>, <&cru ARMCLKB>,
1068 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1070 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1072 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1073 <&cru PCLK_PERILP0>,
1074 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1075 assigned-clock-rates =
1076 <400000000>, <200000000>,
1077 <400000000>, <200000000>,
1078 <816000000>, <1008000000>,
1079 <594000000>, <800000000>,
1081 <150000000>, <75000000>,
1083 <100000000>, <100000000>,
1085 <100000000>, <50000000>;
1088 grf: syscon@ff770000 {
1089 compatible = "rockchip,rk3399-grf", "syscon";
1090 reg = <0x0 0xff770000 0x0 0x10000>;
1094 compatible = "snps,dw-wdt";
1095 reg = <0x0 0xff840000 0x0 0x100>;
1096 clocks = <&cru PCLK_WDT>;
1097 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1100 spdif: spdif@ff870000 {
1101 compatible = "rockchip,rk3399-spdif";
1102 reg = <0x0 0xff870000 0x0 0x1000>;
1103 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1104 dmas = <&dmac_bus 7>;
1106 clock-names = "mclk", "hclk";
1107 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1108 pinctrl-names = "default";
1109 pinctrl-0 = <&spdif_bus>;
1110 status = "disabled";
1113 i2s0: i2s@ff880000 {
1114 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1115 reg = <0x0 0xff880000 0x0 0x1000>;
1116 rockchip,grf = <&grf>;
1117 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1118 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1119 dma-names = "tx", "rx";
1120 clock-names = "i2s_clk", "i2s_hclk";
1121 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1122 pinctrl-names = "default";
1123 pinctrl-0 = <&i2s0_8ch_bus>;
1124 status = "disabled";
1127 i2s1: i2s@ff890000 {
1128 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1129 reg = <0x0 0xff890000 0x0 0x1000>;
1130 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1131 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1132 dma-names = "tx", "rx";
1133 clock-names = "i2s_clk", "i2s_hclk";
1134 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1135 pinctrl-names = "default";
1136 pinctrl-0 = <&i2s1_2ch_bus>;
1137 status = "disabled";
1140 i2s2: i2s@ff8a0000 {
1141 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1142 reg = <0x0 0xff8a0000 0x0 0x1000>;
1143 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1144 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1145 dma-names = "tx", "rx";
1146 clock-names = "i2s_clk", "i2s_hclk";
1147 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1148 status = "disabled";
1152 compatible = "arm,malit860",
1157 reg = <0x0 0xff9a0000 0x0 0x10000>;
1159 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1160 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1162 interrupt-names = "GPU", "JOB", "MMU";
1164 clocks = <&cru ACLK_GPU>;
1165 clock-names = "clk_mali";
1166 #cooling-cells = <2>; /* min followed by max */
1167 operating-points-v2 = <&gpu_opp_table>;
1169 status = "disabled";
1172 compatible = "arm,mali-simple-power-model";
1175 static-power = <500>;
1176 dynamic-power = <1500>;
1177 ts = <20000 2000 (-20) 2>;
1178 thermal-zone = "gpu";
1182 gpu_opp_table: gpu_opp_table {
1183 compatible = "operating-points-v2";
1187 opp-hz = /bits/ 64 <200000000>;
1188 opp-microvolt = <900000>;
1191 opp-hz = /bits/ 64 <300000000>;
1192 opp-microvolt = <900000>;
1195 opp-hz = /bits/ 64 <400000000>;
1196 opp-microvolt = <900000>;
1201 vopl: vop@ff8f0000 {
1202 compatible = "rockchip,rk3399-vop-lit";
1203 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1204 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1206 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1207 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1208 reset-names = "axi", "ahb", "dclk";
1209 iommus = <&vopl_mmu>;
1210 status = "disabled";
1213 #address-cells = <1>;
1216 vopl_out_mipi: endpoint@0 {
1218 remote-endpoint = <&mipi_in_vopl>;
1221 vopl_out_edp: endpoint@1 {
1223 remote-endpoint = <&edp_in_vopl>;
1228 vopl_mmu: iommu@ff8f3f00 {
1229 compatible = "rockchip,iommu";
1230 reg = <0x0 0xff8f3f00 0x0 0x100>;
1231 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1232 interrupt-names = "vopl_mmu";
1234 status = "disabled";
1237 vopb: vop@ff900000 {
1238 compatible = "rockchip,rk3399-vop-big";
1239 reg = <0x0 0xff900000 0x0 0x3efc>;
1240 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1242 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1243 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1244 reset-names = "axi", "ahb", "dclk";
1245 iommus = <&vopb_mmu>;
1246 status = "disabled";
1249 #address-cells = <1>;
1252 vopb_out_edp: endpoint@0 {
1254 remote-endpoint = <&edp_in_vopb>;
1257 vopb_out_mipi: endpoint@1 {
1259 remote-endpoint = <&mipi_in_vopb>;
1264 vopb_mmu: iommu@ff903f00 {
1265 compatible = "rockchip,iommu";
1266 reg = <0x0 0xff903f00 0x0 0x100>;
1267 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1268 interrupt-names = "vopb_mmu";
1270 status = "disabled";
1273 mipi_dsi: mipi@ff960000 {
1274 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1275 reg = <0x0 0xff960000 0x0 0x8000>;
1276 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1277 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1278 <&cru SCLK_DPHY_TX0_CFG>;
1279 clock-names = "ref", "pclk", "phy_cfg";
1280 rockchip,grf = <&grf>;
1281 #address-cells = <1>;
1283 status = "disabled";
1286 #address-cells = <1>;
1291 #address-cells = <1>;
1294 mipi_in_vopb: endpoint@0 {
1296 remote-endpoint = <&vopb_out_mipi>;
1298 mipi_in_vopl: endpoint@1 {
1300 remote-endpoint = <&vopl_out_mipi>;
1307 compatible = "rockchip,rk3399-edp";
1308 reg = <0x0 0xff970000 0x0 0x8000>;
1309 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1310 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1311 clock-names = "dp", "pclk";
1312 resets = <&cru SRST_P_EDP_CTRL>;
1314 rockchip,grf = <&grf>;
1315 status = "disabled";
1316 pinctrl-names = "default";
1317 pinctrl-0 = <&edp_hpd>;
1320 #address-cells = <1>;
1325 #address-cells = <1>;
1328 edp_in_vopb: endpoint@0 {
1330 remote-endpoint = <&vopb_out_edp>;
1333 edp_in_vopl: endpoint@1 {
1335 remote-endpoint = <&vopl_out_edp>;
1341 display_subsystem: display-subsystem {
1342 compatible = "rockchip,display-subsystem";
1343 ports = <&vopl_out>, <&vopb_out>;
1344 status = "disabled";
1348 compatible = "rockchip,rk3399-pinctrl";
1349 rockchip,grf = <&grf>;
1350 rockchip,pmu = <&pmugrf>;
1351 #address-cells = <0x2>;
1352 #size-cells = <0x2>;
1355 gpio0: gpio0@ff720000 {
1356 compatible = "rockchip,gpio-bank";
1357 reg = <0x0 0xff720000 0x0 0x100>;
1358 clocks = <&pmucru PCLK_GPIO0_PMU>;
1359 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1362 #gpio-cells = <0x2>;
1364 interrupt-controller;
1365 #interrupt-cells = <0x2>;
1368 gpio1: gpio1@ff730000 {
1369 compatible = "rockchip,gpio-bank";
1370 reg = <0x0 0xff730000 0x0 0x100>;
1371 clocks = <&pmucru PCLK_GPIO1_PMU>;
1372 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1375 #gpio-cells = <0x2>;
1377 interrupt-controller;
1378 #interrupt-cells = <0x2>;
1381 gpio2: gpio2@ff780000 {
1382 compatible = "rockchip,gpio-bank";
1383 reg = <0x0 0xff780000 0x0 0x100>;
1384 clocks = <&cru PCLK_GPIO2>;
1385 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1388 #gpio-cells = <0x2>;
1390 interrupt-controller;
1391 #interrupt-cells = <0x2>;
1394 gpio3: gpio3@ff788000 {
1395 compatible = "rockchip,gpio-bank";
1396 reg = <0x0 0xff788000 0x0 0x100>;
1397 clocks = <&cru PCLK_GPIO3>;
1398 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1401 #gpio-cells = <0x2>;
1403 interrupt-controller;
1404 #interrupt-cells = <0x2>;
1407 gpio4: gpio4@ff790000 {
1408 compatible = "rockchip,gpio-bank";
1409 reg = <0x0 0xff790000 0x0 0x100>;
1410 clocks = <&cru PCLK_GPIO4>;
1411 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1414 #gpio-cells = <0x2>;
1416 interrupt-controller;
1417 #interrupt-cells = <0x2>;
1420 pcfg_pull_up: pcfg-pull-up {
1424 pcfg_pull_down: pcfg-pull-down {
1428 pcfg_pull_none: pcfg-pull-none {
1432 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1434 drive-strength = <12>;
1437 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1439 drive-strength = <8>;
1442 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1444 drive-strength = <4>;
1447 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1449 drive-strength = <2>;
1452 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1454 drive-strength = <12>;
1457 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1459 drive-strength = <13>;
1463 emmc_pwr: emmc-pwr {
1465 <0 5 RK_FUNC_1 &pcfg_pull_up>;
1470 rgmii_pins: rgmii-pins {
1473 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1475 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1477 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1479 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1481 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1483 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1485 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1487 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1489 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1491 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1493 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1495 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1497 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1499 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1501 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1504 rmii_pins: rmii-pins {
1507 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1509 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1511 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1513 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1515 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1517 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1519 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1521 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1523 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1525 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1530 i2c0_xfer: i2c0-xfer {
1532 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1533 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1538 i2c1_xfer: i2c1-xfer {
1540 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1541 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1546 i2c2_xfer: i2c2-xfer {
1548 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1549 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1554 i2c3_xfer: i2c3-xfer {
1556 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1557 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1560 i2c3_gpio: i2c3_gpio {
1562 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1563 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1569 i2c4_xfer: i2c4-xfer {
1571 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1572 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1577 i2c5_xfer: i2c5-xfer {
1579 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1580 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1585 i2c6_xfer: i2c6-xfer {
1587 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1588 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1593 i2c7_xfer: i2c7-xfer {
1595 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1596 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1601 i2c8_xfer: i2c8-xfer {
1603 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1604 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1609 i2s0_8ch_bus: i2s0-8ch-bus {
1611 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1612 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1613 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1614 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1615 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1616 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1617 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1618 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1619 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1624 i2s1_2ch_bus: i2s1-2ch-bus {
1626 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1627 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1628 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1629 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1630 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1635 sdio0_bus1: sdio0-bus1 {
1637 <2 20 RK_FUNC_1 &pcfg_pull_up>;
1640 sdio0_bus4: sdio0-bus4 {
1642 <2 20 RK_FUNC_1 &pcfg_pull_up>,
1643 <2 21 RK_FUNC_1 &pcfg_pull_up>,
1644 <2 22 RK_FUNC_1 &pcfg_pull_up>,
1645 <2 23 RK_FUNC_1 &pcfg_pull_up>;
1648 sdio0_cmd: sdio0-cmd {
1650 <2 24 RK_FUNC_1 &pcfg_pull_up>;
1653 sdio0_clk: sdio0-clk {
1655 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1658 sdio0_cd: sdio0-cd {
1660 <2 26 RK_FUNC_1 &pcfg_pull_up>;
1663 sdio0_pwr: sdio0-pwr {
1665 <2 27 RK_FUNC_1 &pcfg_pull_up>;
1668 sdio0_bkpwr: sdio0-bkpwr {
1670 <2 28 RK_FUNC_1 &pcfg_pull_up>;
1673 sdio0_wp: sdio0-wp {
1675 <0 3 RK_FUNC_1 &pcfg_pull_up>;
1678 sdio0_int: sdio0-int {
1680 <0 4 RK_FUNC_1 &pcfg_pull_up>;
1685 sdmmc_bus1: sdmmc-bus1 {
1687 <4 8 RK_FUNC_1 &pcfg_pull_up>;
1690 sdmmc_bus4: sdmmc-bus4 {
1692 <4 8 RK_FUNC_1 &pcfg_pull_up>,
1693 <4 9 RK_FUNC_1 &pcfg_pull_up>,
1694 <4 10 RK_FUNC_1 &pcfg_pull_up>,
1695 <4 11 RK_FUNC_1 &pcfg_pull_up>;
1698 sdmmc_clk: sdmmc-clk {
1700 <4 12 RK_FUNC_1 &pcfg_pull_none>;
1703 sdmmc_cmd: sdmmc-cmd {
1705 <4 13 RK_FUNC_1 &pcfg_pull_up>;
1708 sdmmc_cd: sdmcc-cd {
1710 <0 7 RK_FUNC_1 &pcfg_pull_up>;
1713 sdmmc_wp: sdmmc-wp {
1715 <0 8 RK_FUNC_1 &pcfg_pull_up>;
1720 spdif_bus: spdif-bus {
1722 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1727 spi0_clk: spi0-clk {
1729 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1731 spi0_cs0: spi0-cs0 {
1733 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1735 spi0_cs1: spi0-cs1 {
1737 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1741 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1745 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1750 spi1_clk: spi1-clk {
1752 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1754 spi1_cs0: spi1-cs0 {
1756 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1760 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1764 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1769 spi2_clk: spi2-clk {
1771 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1773 spi2_cs0: spi2-cs0 {
1775 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1779 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1783 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1788 spi3_clk: spi3-clk {
1790 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1792 spi3_cs0: spi3-cs0 {
1794 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1798 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1802 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1807 spi4_clk: spi4-clk {
1809 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1811 spi4_cs0: spi4-cs0 {
1813 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1817 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1821 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1826 spi5_clk: spi5-clk {
1828 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1830 spi5_cs0: spi5-cs0 {
1832 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1836 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1840 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1845 otp_gpio: otp-gpio {
1846 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1850 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1855 uart0_xfer: uart0-xfer {
1857 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1858 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1861 uart0_cts: uart0-cts {
1863 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1866 uart0_rts: uart0-rts {
1868 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1873 uart1_xfer: uart1-xfer {
1875 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1876 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1881 uart2a_xfer: uart2a-xfer {
1883 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1884 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1889 uart2b_xfer: uart2b-xfer {
1891 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1892 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1897 uart2c_xfer: uart2c-xfer {
1899 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1900 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1905 uart3_xfer: uart3-xfer {
1907 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1908 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1911 uart3_cts: uart3-cts {
1913 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1916 uart3_rts: uart3-rts {
1918 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1923 uart4_xfer: uart4-xfer {
1925 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1926 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1931 uarthdcp_xfer: uarthdcp-xfer {
1933 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1934 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1939 pwm0_pin: pwm0-pin {
1941 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1944 vop0_pwm_pin: vop0-pwm-pin {
1946 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1951 pwm1_pin: pwm1-pin {
1953 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1956 vop1_pwm_pin: vop1-pwm-pin {
1958 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1963 pwm2_pin: pwm2-pin {
1965 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1970 pwm3a_pin: pwm3a-pin {
1972 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1977 pwm3b_pin: pwm3b-pin {
1979 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1986 <4 23 RK_FUNC_2 &pcfg_pull_none>;
1991 hdmi_i2c_xfer: hdmi-i2c-xfer {
1993 <4 17 RK_FUNC_3 &pcfg_pull_none>,
1994 <4 16 RK_FUNC_3 &pcfg_pull_none>;
1997 hdmi_cec: hdmi-cec {
1999 <4 23 RK_FUNC_1 &pcfg_pull_none>;