2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/suspend/rockchip-rk3399.h>
51 #include <dt-bindings/thermal/thermal.h>
53 #include "rk3399-dram-default-timing.dtsi"
56 compatible = "rockchip,rk3399";
58 interrupt-parent = <&gic>;
113 compatible = "arm,cortex-a53", "arm,armv8";
115 enable-method = "psci";
116 #cooling-cells = <2>; /* min followed by max */
117 dynamic-power-coefficient = <100>;
118 clocks = <&cru ARMCLKL>;
119 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
124 compatible = "arm,cortex-a53", "arm,armv8";
126 enable-method = "psci";
127 clocks = <&cru ARMCLKL>;
128 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
133 compatible = "arm,cortex-a53", "arm,armv8";
135 enable-method = "psci";
136 clocks = <&cru ARMCLKL>;
137 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
142 compatible = "arm,cortex-a53", "arm,armv8";
144 enable-method = "psci";
145 clocks = <&cru ARMCLKL>;
146 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
151 compatible = "arm,cortex-a72", "arm,armv8";
153 enable-method = "psci";
154 #cooling-cells = <2>; /* min followed by max */
155 dynamic-power-coefficient = <436>;
156 clocks = <&cru ARMCLKB>;
157 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
162 compatible = "arm,cortex-a72", "arm,armv8";
164 enable-method = "psci";
165 clocks = <&cru ARMCLKB>;
166 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
170 entry-method = "psci";
172 CPU_SLEEP: cpu-sleep {
173 compatible = "arm,idle-state";
175 arm,psci-suspend-param = <0x0010000>;
176 entry-latency-us = <120>;
177 exit-latency-us = <250>;
178 min-residency-us = <900>;
181 CLUSTER_SLEEP: cluster-sleep {
182 compatible = "arm,idle-state";
184 arm,psci-suspend-param = <0x1010000>;
185 entry-latency-us = <400>;
186 exit-latency-us = <500>;
187 min-residency-us = <2000>;
193 compatible = "arm,cortex-a53-pmu";
194 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
198 compatible = "arm,cortex-a72-pmu";
199 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
203 compatible = "arm,psci-1.0";
208 compatible = "rockchip,cpuinfo";
209 nvmem-cells = <&efuse_id>;
210 nvmem-cell-names = "id";
214 compatible = "arm,armv8-timer";
215 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
216 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
217 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
218 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
222 compatible = "fixed-clock";
223 clock-frequency = <24000000>;
224 clock-output-names = "xin24m";
228 dummy_cpll: dummy_cpll {
229 compatible = "fixed-clock";
230 clock-frequency = <0>;
231 clock-output-names = "dummy_cpll";
235 dummy_vpll: dummy_vpll {
236 compatible = "fixed-clock";
237 clock-frequency = <0>;
238 clock-output-names = "dummy_vpll";
243 compatible = "arm,amba-bus";
244 #address-cells = <2>;
248 dmac_bus: dma-controller@ff6d0000 {
249 compatible = "arm,pl330", "arm,primecell";
250 reg = <0x0 0xff6d0000 0x0 0x4000>;
251 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
252 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
254 clocks = <&cru ACLK_DMAC0_PERILP>;
255 clock-names = "apb_pclk";
256 peripherals-req-type-burst;
259 dmac_peri: dma-controller@ff6e0000 {
260 compatible = "arm,pl330", "arm,primecell";
261 reg = <0x0 0xff6e0000 0x0 0x4000>;
262 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
263 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
265 clocks = <&cru ACLK_DMAC1_PERILP>;
266 clock-names = "apb_pclk";
267 peripherals-req-type-burst;
271 gmac: ethernet@fe300000 {
272 compatible = "rockchip,rk3399-gmac";
273 reg = <0x0 0xfe300000 0x0 0x10000>;
274 rockchip,grf = <&grf>;
275 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
276 interrupt-names = "macirq";
277 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
278 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
279 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
281 clock-names = "stmmaceth", "mac_clk_rx",
282 "mac_clk_tx", "clk_mac_ref",
283 "clk_mac_refout", "aclk_mac",
285 resets = <&cru SRST_A_GMAC>;
286 reset-names = "stmmaceth";
287 power-domains = <&power RK3399_PD_GMAC>;
291 sdio0: dwmmc@fe310000 {
292 compatible = "rockchip,rk3399-dw-mshc",
293 "rockchip,rk3288-dw-mshc";
294 reg = <0x0 0xfe310000 0x0 0x4000>;
295 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
296 clock-freq-min-max = <400000 150000000>;
297 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
298 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
299 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
300 fifo-depth = <0x100>;
301 power-domains = <&power RK3399_PD_SDIOAUDIO>;
305 sdmmc: dwmmc@fe320000 {
306 compatible = "rockchip,rk3399-dw-mshc",
307 "rockchip,rk3288-dw-mshc";
308 reg = <0x0 0xfe320000 0x0 0x4000>;
309 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
310 clock-freq-min-max = <400000 150000000>;
311 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
312 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
313 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
314 fifo-depth = <0x100>;
315 power-domains = <&power RK3399_PD_SD>;
319 sdhci: sdhci@fe330000 {
320 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
321 reg = <0x0 0xfe330000 0x0 0x10000>;
322 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
323 arasan,soc-ctl-syscon = <&grf>;
324 assigned-clocks = <&cru SCLK_EMMC>;
325 assigned-clock-rates = <200000000>;
326 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
327 clock-names = "clk_xin", "clk_ahb";
328 clock-output-names = "emmc_cardclock";
331 phy-names = "phy_arasan";
332 power-domains = <&power RK3399_PD_EMMC>;
336 usb_host0_ehci: usb@fe380000 {
337 compatible = "generic-ehci";
338 reg = <0x0 0xfe380000 0x0 0x20000>;
339 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
340 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
341 <&cru SCLK_USBPHY0_480M_SRC>;
342 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
343 phys = <&u2phy0_host>;
345 power-domains = <&power RK3399_PD_PERIHP>;
349 usb_host0_ohci: usb@fe3a0000 {
350 compatible = "generic-ohci";
351 reg = <0x0 0xfe3a0000 0x0 0x20000>;
352 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
353 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
354 <&cru SCLK_USBPHY0_480M_SRC>;
355 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
356 phys = <&u2phy0_host>;
358 power-domains = <&power RK3399_PD_PERIHP>;
362 usb_host1_ehci: usb@fe3c0000 {
363 compatible = "generic-ehci";
364 reg = <0x0 0xfe3c0000 0x0 0x20000>;
365 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
366 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
367 <&cru SCLK_USBPHY1_480M_SRC>;
368 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
369 phys = <&u2phy1_host>;
371 power-domains = <&power RK3399_PD_PERIHP>;
375 usb_host1_ohci: usb@fe3e0000 {
376 compatible = "generic-ohci";
377 reg = <0x0 0xfe3e0000 0x0 0x20000>;
378 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
379 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
380 <&cru SCLK_USBPHY1_480M_SRC>;
381 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
382 phys = <&u2phy1_host>;
384 power-domains = <&power RK3399_PD_PERIHP>;
388 usbdrd3_0: usb@fe800000 {
389 compatible = "rockchip,rk3399-dwc3";
390 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
391 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
392 clock-names = "ref_clk", "suspend_clk",
393 "bus_clk", "grf_clk";
394 power-domains = <&power RK3399_PD_USB3>;
395 resets = <&cru SRST_A_USB3_OTG0>;
396 reset-names = "usb3-otg";
397 #address-cells = <2>;
401 usbdrd_dwc3_0: dwc3@fe800000 {
402 compatible = "snps,dwc3";
403 reg = <0x0 0xfe800000 0x0 0x100000>;
404 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
406 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
407 phy-names = "usb2-phy", "usb3-phy";
408 phy_type = "utmi_wide";
409 snps,dis_enblslpm_quirk;
410 snps,dis-u2-freeclk-exists-quirk;
411 snps,dis_u2_susphy_quirk;
412 snps,dis-del-phy-power-chg-quirk;
413 snps,tx-ipgap-linecheck-dis-quirk;
414 snps,xhci-slow-suspend-quirk;
415 snps,usb3-warm-reset-on-resume-quirk;
420 usbdrd3_1: usb@fe900000 {
421 compatible = "rockchip,rk3399-dwc3";
422 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
423 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
424 clock-names = "ref_clk", "suspend_clk",
425 "bus_clk", "grf_clk";
426 power-domains = <&power RK3399_PD_USB3>;
427 resets = <&cru SRST_A_USB3_OTG1>;
428 reset-names = "usb3-otg";
429 #address-cells = <2>;
433 usbdrd_dwc3_1: dwc3@fe900000 {
434 compatible = "snps,dwc3";
435 reg = <0x0 0xfe900000 0x0 0x100000>;
436 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
438 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
439 phy-names = "usb2-phy", "usb3-phy";
440 phy_type = "utmi_wide";
441 snps,dis_enblslpm_quirk;
442 snps,dis-u2-freeclk-exists-quirk;
443 snps,dis_u2_susphy_quirk;
444 snps,dis-del-phy-power-chg-quirk;
445 snps,tx-ipgap-linecheck-dis-quirk;
446 snps,xhci-slow-suspend-quirk;
447 snps,usb3-warm-reset-on-resume-quirk;
452 cdn_dp: dp@fec00000 {
453 compatible = "rockchip,rk3399-cdn-dp";
454 reg = <0x0 0xfec00000 0x0 0x100000>;
455 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
457 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
458 clock-names = "core-clk", "pclk", "spdif", "grf";
459 assigned-clocks = <&cru SCLK_DP_CORE>;
460 assigned-clock-rates = <100000000>;
461 power-domains = <&power RK3399_PD_HDCP>;
462 phys = <&tcphy0_dp>, <&tcphy1_dp>;
463 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
464 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
465 reset-names = "spdif", "dptx", "apb", "core";
466 rockchip,grf = <&grf>;
467 #address-cells = <1>;
469 #sound-dai-cells = <1>;
473 #address-cells = <1>;
477 #address-cells = <1>;
479 dp_in_vopb: endpoint@0 {
481 remote-endpoint = <&vopb_out_dp>;
484 dp_in_vopl: endpoint@1 {
486 remote-endpoint = <&vopl_out_dp>;
492 gic: interrupt-controller@fee00000 {
493 compatible = "arm,gic-v3";
494 #interrupt-cells = <4>;
495 #address-cells = <2>;
498 interrupt-controller;
500 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
501 <0x0 0xfef00000 0 0xc0000>, /* GICR */
502 <0x0 0xfff00000 0 0x10000>, /* GICC */
503 <0x0 0xfff10000 0 0x10000>, /* GICH */
504 <0x0 0xfff20000 0 0x10000>; /* GICV */
505 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
506 its: interrupt-controller@fee20000 {
507 compatible = "arm,gic-v3-its";
509 reg = <0x0 0xfee20000 0x0 0x20000>;
513 ppi_cluster0: interrupt-partition-0 {
514 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
517 ppi_cluster1: interrupt-partition-1 {
518 affinity = <&cpu_b0 &cpu_b1>;
523 saradc: saradc@ff100000 {
524 compatible = "rockchip,rk3399-saradc";
525 reg = <0x0 0xff100000 0x0 0x100>;
526 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
527 #io-channel-cells = <1>;
528 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
529 clock-names = "saradc", "apb_pclk";
530 resets = <&cru SRST_P_SARADC>;
531 reset-names = "saradc-apb";
536 compatible = "rockchip,rk3399-i2c";
537 reg = <0x0 0xff3c0000 0x0 0x1000>;
538 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
539 clock-names = "i2c", "pclk";
540 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
541 pinctrl-names = "default";
542 pinctrl-0 = <&i2c0_xfer>;
543 #address-cells = <1>;
549 compatible = "rockchip,rk3399-i2c";
550 reg = <0x0 0xff110000 0x0 0x1000>;
551 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
552 clock-names = "i2c", "pclk";
553 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c1_xfer>;
556 #address-cells = <1>;
562 compatible = "rockchip,rk3399-i2c";
563 reg = <0x0 0xff120000 0x0 0x1000>;
564 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
565 clock-names = "i2c", "pclk";
566 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&i2c2_xfer>;
569 #address-cells = <1>;
575 compatible = "rockchip,rk3399-i2c";
576 reg = <0x0 0xff130000 0x0 0x1000>;
577 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
578 clock-names = "i2c", "pclk";
579 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
580 pinctrl-names = "default";
581 pinctrl-0 = <&i2c3_xfer>;
582 #address-cells = <1>;
588 compatible = "rockchip,rk3399-i2c";
589 reg = <0x0 0xff140000 0x0 0x1000>;
590 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
591 clock-names = "i2c", "pclk";
592 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&i2c5_xfer>;
595 #address-cells = <1>;
601 compatible = "rockchip,rk3399-i2c";
602 reg = <0x0 0xff150000 0x0 0x1000>;
603 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
604 clock-names = "i2c", "pclk";
605 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&i2c6_xfer>;
608 #address-cells = <1>;
614 compatible = "rockchip,rk3399-i2c";
615 reg = <0x0 0xff160000 0x0 0x1000>;
616 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
617 clock-names = "i2c", "pclk";
618 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
619 pinctrl-names = "default";
620 pinctrl-0 = <&i2c7_xfer>;
621 #address-cells = <1>;
626 uart0: serial@ff180000 {
627 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
628 reg = <0x0 0xff180000 0x0 0x100>;
629 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
630 clock-names = "baudclk", "apb_pclk";
631 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
634 pinctrl-names = "default";
635 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
639 uart1: serial@ff190000 {
640 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
641 reg = <0x0 0xff190000 0x0 0x100>;
642 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
643 clock-names = "baudclk", "apb_pclk";
644 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&uart1_xfer>;
652 uart2: serial@ff1a0000 {
653 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
654 reg = <0x0 0xff1a0000 0x0 0x100>;
655 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
656 clock-names = "baudclk", "apb_pclk";
657 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&uart2c_xfer>;
665 uart3: serial@ff1b0000 {
666 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
667 reg = <0x0 0xff1b0000 0x0 0x100>;
668 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
669 clock-names = "baudclk", "apb_pclk";
670 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
673 pinctrl-names = "default";
674 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
679 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
680 reg = <0x0 0xff1c0000 0x0 0x1000>;
681 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
682 clock-names = "spiclk", "apb_pclk";
683 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
684 pinctrl-names = "default";
685 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
686 #address-cells = <1>;
692 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
693 reg = <0x0 0xff1d0000 0x0 0x1000>;
694 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
695 clock-names = "spiclk", "apb_pclk";
696 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
697 pinctrl-names = "default";
698 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
699 #address-cells = <1>;
705 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
706 reg = <0x0 0xff1e0000 0x0 0x1000>;
707 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
708 clock-names = "spiclk", "apb_pclk";
709 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
710 pinctrl-names = "default";
711 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
712 #address-cells = <1>;
718 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
719 reg = <0x0 0xff1f0000 0x0 0x1000>;
720 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
721 clock-names = "spiclk", "apb_pclk";
722 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
723 pinctrl-names = "default";
724 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
725 #address-cells = <1>;
731 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
732 reg = <0x0 0xff200000 0x0 0x1000>;
733 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
734 clock-names = "spiclk", "apb_pclk";
735 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
736 pinctrl-names = "default";
737 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
738 #address-cells = <1>;
743 thermal_zones: thermal-zones {
744 soc_thermal: soc-thermal {
745 polling-delay-passive = <20>; /* milliseconds */
746 polling-delay = <1000>; /* milliseconds */
747 sustainable-power = <1000>; /* milliwatts */
749 thermal-sensors = <&tsadc 0>;
752 threshold: trip-point@0 {
753 temperature = <70000>; /* millicelsius */
754 hysteresis = <2000>; /* millicelsius */
757 target: trip-point@1 {
758 temperature = <85000>; /* millicelsius */
759 hysteresis = <2000>; /* millicelsius */
763 temperature = <95000>; /* millicelsius */
764 hysteresis = <2000>; /* millicelsius */
773 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
774 contribution = <4096>;
779 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
780 contribution = <1024>;
785 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
786 contribution = <4096>;
791 gpu_thermal: gpu-thermal {
792 polling-delay-passive = <100>; /* milliseconds */
793 polling-delay = <1000>; /* milliseconds */
795 thermal-sensors = <&tsadc 1>;
799 tsadc: tsadc@ff260000 {
800 compatible = "rockchip,rk3399-tsadc";
801 reg = <0x0 0xff260000 0x0 0x100>;
802 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
803 rockchip,grf = <&grf>;
804 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
805 clock-names = "tsadc", "apb_pclk";
806 assigned-clocks = <&cru SCLK_TSADC>;
807 assigned-clock-rates = <750000>;
808 resets = <&cru SRST_TSADC>;
809 reset-names = "tsadc-apb";
810 pinctrl-names = "init", "default", "sleep";
811 pinctrl-0 = <&otp_gpio>;
812 pinctrl-1 = <&otp_out>;
813 pinctrl-2 = <&otp_gpio>;
814 #thermal-sensor-cells = <1>;
815 rockchip,hw-tshut-temp = <95000>;
819 qos_emmc: qos@ffa58000 {
820 compatible = "syscon";
821 reg = <0x0 0xffa58000 0x0 0x20>;
824 qos_gmac: qos@ffa5c000 {
825 compatible = "syscon";
826 reg = <0x0 0xffa5c000 0x0 0x20>;
829 qos_pcie: qos@ffa60080 {
830 compatible = "syscon";
831 reg = <0x0 0xffa60080 0x0 0x20>;
834 qos_usb_host0: qos@ffa60100 {
835 compatible = "syscon";
836 reg = <0x0 0xffa60100 0x0 0x20>;
839 qos_usb_host1: qos@ffa60180 {
840 compatible = "syscon";
841 reg = <0x0 0xffa60180 0x0 0x20>;
844 qos_usb_otg0: qos@ffa70000 {
845 compatible = "syscon";
846 reg = <0x0 0xffa70000 0x0 0x20>;
849 qos_usb_otg1: qos@ffa70080 {
850 compatible = "syscon";
851 reg = <0x0 0xffa70080 0x0 0x20>;
854 qos_sd: qos@ffa74000 {
855 compatible = "syscon";
856 reg = <0x0 0xffa74000 0x0 0x20>;
859 qos_sdioaudio: qos@ffa76000 {
860 compatible = "syscon";
861 reg = <0x0 0xffa76000 0x0 0x20>;
864 qos_hdcp: qos@ffa90000 {
865 compatible = "syscon";
866 reg = <0x0 0xffa90000 0x0 0x20>;
869 qos_iep: qos@ffa98000 {
870 compatible = "syscon";
871 reg = <0x0 0xffa98000 0x0 0x20>;
874 qos_isp0_m0: qos@ffaa0000 {
875 compatible = "syscon";
876 reg = <0x0 0xffaa0000 0x0 0x20>;
879 qos_isp0_m1: qos@ffaa0080 {
880 compatible = "syscon";
881 reg = <0x0 0xffaa0080 0x0 0x20>;
884 qos_isp1_m0: qos@ffaa8000 {
885 compatible = "syscon";
886 reg = <0x0 0xffaa8000 0x0 0x20>;
889 qos_isp1_m1: qos@ffaa8080 {
890 compatible = "syscon";
891 reg = <0x0 0xffaa8080 0x0 0x20>;
894 qos_rga_r: qos@ffab0000 {
895 compatible = "syscon";
896 reg = <0x0 0xffab0000 0x0 0x20>;
899 qos_rga_w: qos@ffab0080 {
900 compatible = "syscon";
901 reg = <0x0 0xffab0080 0x0 0x20>;
904 qos_video_m0: qos@ffab8000 {
905 compatible = "syscon";
906 reg = <0x0 0xffab8000 0x0 0x20>;
909 qos_video_m1_r: qos@ffac0000 {
910 compatible = "syscon";
911 reg = <0x0 0xffac0000 0x0 0x20>;
914 qos_video_m1_w: qos@ffac0080 {
915 compatible = "syscon";
916 reg = <0x0 0xffac0080 0x0 0x20>;
919 qos_vop_big_r: qos@ffac8000 {
920 compatible = "syscon";
921 reg = <0x0 0xffac8000 0x0 0x20>;
924 qos_vop_big_w: qos@ffac8080 {
925 compatible = "syscon";
926 reg = <0x0 0xffac8080 0x0 0x20>;
929 qos_vop_little: qos@ffad0000 {
930 compatible = "syscon";
931 reg = <0x0 0xffad0000 0x0 0x20>;
934 qos_perihp: qos@ffad8080 {
935 compatible = "syscon";
936 reg = <0x0 0xffad8080 0x0 0x20>;
939 qos_gpu: qos@ffae0000 {
940 compatible = "syscon";
941 reg = <0x0 0xffae0000 0x0 0x20>;
944 pmu: power-management@ff310000 {
945 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
946 reg = <0x0 0xff310000 0x0 0x1000>;
949 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
950 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
951 * Some of the power domains are grouped together for every
953 * The detail contents as below.
955 power: power-controller {
956 compatible = "rockchip,rk3399-power-controller";
957 #power-domain-cells = <1>;
958 #address-cells = <1>;
961 /* These power domains are grouped by VD_CENTER */
962 pd_iep@RK3399_PD_IEP {
963 reg = <RK3399_PD_IEP>;
964 clocks = <&cru ACLK_IEP>,
968 pd_rga@RK3399_PD_RGA {
969 reg = <RK3399_PD_RGA>;
970 clocks = <&cru ACLK_RGA>,
972 pm_qos = <&qos_rga_r>,
975 pd_vcodec@RK3399_PD_VCODEC {
976 reg = <RK3399_PD_VCODEC>;
977 clocks = <&cru ACLK_VCODEC>,
979 pm_qos = <&qos_video_m0>;
981 pd_vdu@RK3399_PD_VDU {
982 reg = <RK3399_PD_VDU>;
983 clocks = <&cru ACLK_VDU>,
985 pm_qos = <&qos_video_m1_r>,
989 /* These power domains are grouped by VD_GPU */
990 pd_gpu@RK3399_PD_GPU {
991 reg = <RK3399_PD_GPU>;
992 clocks = <&cru ACLK_GPU>;
996 /* These power domains are grouped by VD_LOGIC */
997 pd_edp@RK3399_PD_EDP {
998 reg = <RK3399_PD_EDP>;
999 clocks = <&cru PCLK_EDP_CTRL>;
1001 pd_emmc@RK3399_PD_EMMC {
1002 reg = <RK3399_PD_EMMC>;
1003 clocks = <&cru ACLK_EMMC>;
1004 pm_qos = <&qos_emmc>;
1006 pd_gmac@RK3399_PD_GMAC {
1007 reg = <RK3399_PD_GMAC>;
1008 clocks = <&cru ACLK_GMAC>,
1010 pm_qos = <&qos_gmac>;
1012 pd_perihp@RK3399_PD_PERIHP {
1013 reg = <RK3399_PD_PERIHP>;
1014 #address-cells = <1>;
1016 clocks = <&cru ACLK_PERIHP>;
1017 pm_qos = <&qos_perihp>,
1022 pd_sd@RK3399_PD_SD {
1023 reg = <RK3399_PD_SD>;
1024 clocks = <&cru HCLK_SDMMC>,
1029 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1030 reg = <RK3399_PD_SDIOAUDIO>;
1031 clocks = <&cru HCLK_SDIO>;
1032 pm_qos = <&qos_sdioaudio>;
1034 pd_usb3@RK3399_PD_USB3 {
1035 reg = <RK3399_PD_USB3>;
1036 clocks = <&cru ACLK_USB3>;
1037 pm_qos = <&qos_usb_otg0>,
1040 pd_vio@RK3399_PD_VIO {
1041 reg = <RK3399_PD_VIO>;
1042 #address-cells = <1>;
1045 pd_hdcp@RK3399_PD_HDCP {
1046 reg = <RK3399_PD_HDCP>;
1047 clocks = <&cru ACLK_HDCP>,
1050 pm_qos = <&qos_hdcp>;
1052 pd_isp0@RK3399_PD_ISP0 {
1053 reg = <RK3399_PD_ISP0>;
1054 clocks = <&cru ACLK_ISP0>,
1056 pm_qos = <&qos_isp0_m0>,
1059 pd_isp1@RK3399_PD_ISP1 {
1060 reg = <RK3399_PD_ISP1>;
1061 clocks = <&cru ACLK_ISP1>,
1063 pm_qos = <&qos_isp1_m0>,
1066 pd_tcpc0@RK3399_PD_TCPC0 {
1067 reg = <RK3399_PD_TCPD0>;
1068 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1069 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1071 pd_tcpc1@RK3399_PD_TCPC1 {
1072 reg = <RK3399_PD_TCPD1>;
1073 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1074 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1076 pd_vo@RK3399_PD_VO {
1077 reg = <RK3399_PD_VO>;
1078 #address-cells = <1>;
1081 pd_vopb@RK3399_PD_VOPB {
1082 reg = <RK3399_PD_VOPB>;
1083 clocks = <&cru ACLK_VOP0>,
1085 pm_qos = <&qos_vop_big_r>,
1088 pd_vopl@RK3399_PD_VOPL {
1089 reg = <RK3399_PD_VOPL>;
1090 clocks = <&cru ACLK_VOP1>,
1092 pm_qos = <&qos_vop_little>;
1099 pmugrf: syscon@ff320000 {
1100 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1101 reg = <0x0 0xff320000 0x0 0x1000>;
1102 #address-cells = <1>;
1105 pmu_io_domains: io-domains {
1106 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1107 status = "disabled";
1111 compatible = "syscon-reboot-mode";
1113 mode-bootloader = <BOOT_BL_DOWNLOAD>;
1114 mode-charge = <BOOT_CHARGING>;
1115 mode-fastboot = <BOOT_FASTBOOT>;
1116 mode-loader = <BOOT_BL_DOWNLOAD>;
1117 mode-normal = <BOOT_NORMAL>;
1118 mode-recovery = <BOOT_RECOVERY>;
1119 mode-ums = <BOOT_UMS>;
1122 pmu_pvtm: pmu-pvtm {
1123 compatible = "rockchip,rk3399-pmu-pvtm";
1124 clocks = <&pmucru SCLK_PVTM_PMU>;
1125 clock-names = "pmu";
1126 status = "disabled";
1130 spi3: spi@ff350000 {
1131 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1132 reg = <0x0 0xff350000 0x0 0x1000>;
1133 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1134 clock-names = "spiclk", "apb_pclk";
1135 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1136 pinctrl-names = "default";
1137 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1138 #address-cells = <1>;
1140 status = "disabled";
1143 uart4: serial@ff370000 {
1144 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1145 reg = <0x0 0xff370000 0x0 0x100>;
1146 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1147 clock-names = "baudclk", "apb_pclk";
1148 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1151 pinctrl-names = "default";
1152 pinctrl-0 = <&uart4_xfer>;
1153 status = "disabled";
1156 i2c4: i2c@ff3d0000 {
1157 compatible = "rockchip,rk3399-i2c";
1158 reg = <0x0 0xff3d0000 0x0 0x1000>;
1159 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1160 clock-names = "i2c", "pclk";
1161 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&i2c4_xfer>;
1164 #address-cells = <1>;
1166 status = "disabled";
1169 i2c8: i2c@ff3e0000 {
1170 compatible = "rockchip,rk3399-i2c";
1171 reg = <0x0 0xff3e0000 0x0 0x1000>;
1172 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1173 clock-names = "i2c", "pclk";
1174 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1175 pinctrl-names = "default";
1176 pinctrl-0 = <&i2c8_xfer>;
1177 #address-cells = <1>;
1179 status = "disabled";
1182 pcie_phy: phy@e220 {
1183 compatible = "rockchip,rk3399-pcie-phy";
1185 rockchip,grf = <&grf>;
1186 clocks = <&cru SCLK_PCIEPHY_REF>;
1187 clock-names = "refclk";
1188 resets = <&cru SRST_PCIEPHY>;
1189 reset-names = "phy";
1190 status = "disabled";
1193 pcie0: pcie@f8000000 {
1194 compatible = "rockchip,rk3399-pcie";
1195 #address-cells = <3>;
1198 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1199 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1200 clock-names = "aclk", "aclk-perf",
1202 bus-range = <0x0 0x1>;
1203 max-link-speed = <1>;
1204 linux,pci-domain = <0>;
1205 msi-map = <0x0 &its 0x0 0x1000>;
1206 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1207 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1208 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1209 interrupt-names = "sys", "legacy", "client";
1210 #interrupt-cells = <1>;
1211 interrupt-map-mask = <0 0 0 7>;
1212 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1213 <0 0 0 2 &pcie0_intc 1>,
1214 <0 0 0 3 &pcie0_intc 2>,
1215 <0 0 0 4 &pcie0_intc 3>;
1217 phy-names = "pcie-phy";
1218 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1219 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1220 reg = <0x0 0xf8000000 0x0 0x2000000>,
1221 <0x0 0xfd000000 0x0 0x1000000>;
1222 reg-names = "axi-base", "apb-base";
1223 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1224 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1225 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1227 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1228 "pm", "pclk", "aclk";
1229 status = "disabled";
1230 pcie0_intc: interrupt-controller {
1231 interrupt-controller;
1232 #address-cells = <0>;
1233 #interrupt-cells = <1>;
1237 pwm0: pwm@ff420000 {
1238 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1239 reg = <0x0 0xff420000 0x0 0x10>;
1241 pinctrl-names = "default";
1242 pinctrl-0 = <&pwm0_pin>;
1243 clocks = <&pmucru PCLK_RKPWM_PMU>;
1244 clock-names = "pwm";
1245 status = "disabled";
1248 pwm1: pwm@ff420010 {
1249 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1250 reg = <0x0 0xff420010 0x0 0x10>;
1252 pinctrl-names = "default";
1253 pinctrl-0 = <&pwm1_pin>;
1254 clocks = <&pmucru PCLK_RKPWM_PMU>;
1255 clock-names = "pwm";
1256 status = "disabled";
1259 pwm2: pwm@ff420020 {
1260 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1261 reg = <0x0 0xff420020 0x0 0x10>;
1263 pinctrl-names = "default";
1264 pinctrl-0 = <&pwm2_pin>;
1265 clocks = <&pmucru PCLK_RKPWM_PMU>;
1266 clock-names = "pwm";
1267 status = "disabled";
1270 pwm3: pwm@ff420030 {
1271 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1272 reg = <0x0 0xff420030 0x0 0x10>;
1274 pinctrl-names = "default";
1275 pinctrl-0 = <&pwm3a_pin>;
1276 clocks = <&pmucru PCLK_RKPWM_PMU>;
1277 clock-names = "pwm";
1278 status = "disabled";
1282 reg = <0x00 0xff630000 0x00 0x4000>;
1283 compatible = "rockchip,rk3399-dfi";
1284 rockchip,pmu = <&pmugrf>;
1285 clocks = <&cru PCLK_DDR_MON>;
1286 clock-names = "pclk_ddr_mon";
1287 status = "disabled";
1291 compatible = "rockchip,rk3399-dmc";
1292 devfreq-events = <&dfi>;
1293 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1294 clocks = <&cru SCLK_DDRCLK>;
1295 clock-names = "dmc_clk";
1296 ddr_timing = <&ddr_timing>;
1297 status = "disabled";
1300 vpu: vpu_service@ff650000 {
1301 compatible = "rockchip,vpu_service";
1302 rockchip,grf = <&grf>;
1303 iommus = <&vpu_mmu>;
1304 iommu_enabled = <1>;
1305 reg = <0x0 0xff650000 0x0 0x800>;
1306 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
1307 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1308 interrupt-names = "irq_dec", "irq_enc";
1309 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1310 clock-names = "aclk_vcodec", "hclk_vcodec";
1311 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1312 reset-names = "video_h", "video_a";
1313 power-domains = <&power RK3399_PD_VCODEC>;
1314 name = "vpu_service";
1316 /* 0 means ion, 1 means drm */
1318 status = "disabled";
1321 vpu_mmu: iommu@ff650800 {
1322 compatible = "rockchip,iommu";
1323 reg = <0x0 0xff650800 0x0 0x40>;
1324 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1325 interrupt-names = "vpu_mmu";
1326 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1327 clock-names = "aclk", "hclk";
1328 power-domains = <&power RK3399_PD_VCODEC>;
1332 rkvdec: rkvdec@ff660000 {
1333 compatible = "rockchip,rkvdec";
1334 rockchip,grf = <&grf>;
1335 iommus = <&vdec_mmu>;
1336 iommu_enabled = <1>;
1337 reg = <0x0 0xff660000 0x0 0x400>;
1338 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1339 interrupt-names = "irq_dec";
1340 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1341 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1342 clock-names = "aclk_vcodec", "hclk_vcodec",
1343 "clk_cabac", "clk_core";
1344 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
1345 <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>,
1346 <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>;
1347 reset-names = "video_h", "video_a", "video_core", "video_cabac",
1349 power-domains = <&power RK3399_PD_VDU>;
1352 /* 0 means ion, 1 means drm */
1354 status = "disabled";
1357 vdec_mmu: iommu@ff660480 {
1358 compatible = "rockchip,iommu";
1359 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1360 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1361 interrupt-names = "vdec_mmu";
1362 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1363 clock-names = "aclk", "hclk";
1364 power-domains = <&power RK3399_PD_VDU>;
1369 compatible = "rockchip,iep";
1370 iommu_enabled = <1>;
1371 iommus = <&iep_mmu>;
1372 reg = <0x0 0xff670000 0x0 0x800>;
1373 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1374 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1375 clock-names = "aclk_iep", "hclk_iep";
1376 power-domains = <&power RK3399_PD_IEP>;
1379 status = "disabled";
1382 iep_mmu: iommu@ff670800 {
1383 compatible = "rockchip,iommu";
1384 reg = <0x0 0xff670800 0x0 0x40>;
1385 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1386 interrupt-names = "iep_mmu";
1388 status = "disabled";
1392 compatible = "rockchip,rk3399-rga";
1393 reg = <0x0 0xff680000 0x0 0x10000>;
1394 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1395 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1396 clock-names = "aclk", "hclk", "sclk";
1397 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1398 reset-names = "core", "axi", "ahb";
1399 power-domains = <&power RK3399_PD_RGA>;
1400 status = "disabled";
1403 efuse0: efuse@ff690000 {
1404 compatible = "rockchip,rk3399-efuse";
1405 reg = <0x0 0xff690000 0x0 0x80>;
1406 #address-cells = <1>;
1408 clocks = <&cru PCLK_EFUSE1024NS>;
1409 clock-names = "pclk_efuse";
1415 cpul_leakage: cpul-leakage {
1418 cpub_leakage: cpub-leakage {
1421 gpu_leakage: gpu-leakage {
1424 center_leakage: center-leakage {
1427 logic_leakage: logic-leakage {
1430 wafer_info: wafer-info {
1435 pmucru: pmu-clock-controller@ff750000 {
1436 compatible = "rockchip,rk3399-pmucru";
1437 reg = <0x0 0xff750000 0x0 0x1000>;
1440 assigned-clocks = <&pmucru PLL_PPLL>;
1441 assigned-clock-rates = <676000000>;
1444 cru: clock-controller@ff760000 {
1445 compatible = "rockchip,rk3399-cru";
1446 reg = <0x0 0xff760000 0x0 0x1000>;
1450 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1451 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1452 <&cru ARMCLKL>, <&cru ARMCLKB>,
1453 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1454 <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1455 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1457 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1458 <&cru PCLK_PERILP0>,
1459 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1460 assigned-clock-rates =
1461 <400000000>, <200000000>,
1462 <400000000>, <200000000>,
1463 <816000000>, <816000000>,
1464 <594000000>, <800000000>,
1465 <200000000>, <1000000000>,
1466 <150000000>, <75000000>,
1468 <100000000>, <100000000>,
1470 <100000000>, <50000000>;
1473 grf: syscon@ff770000 {
1474 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1475 reg = <0x0 0xff770000 0x0 0x10000>;
1476 #address-cells = <1>;
1479 io_domains: io-domains {
1480 compatible = "rockchip,rk3399-io-voltage-domain";
1481 status = "disabled";
1484 emmc_phy: phy@f780 {
1485 compatible = "rockchip,rk3399-emmc-phy";
1486 reg = <0xf780 0x24>;
1488 clock-names = "emmcclk";
1490 status = "disabled";
1493 u2phy0: usb2-phy@e450 {
1494 compatible = "rockchip,rk3399-usb2phy";
1495 reg = <0xe450 0x10>;
1496 clocks = <&cru SCLK_USB2PHY0_REF>;
1497 clock-names = "phyclk";
1499 clock-output-names = "clk_usbphy0_480m";
1500 status = "disabled";
1502 u2phy0_otg: otg-port {
1504 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1505 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1506 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1507 interrupt-names = "otg-bvalid", "otg-id",
1509 status = "disabled";
1512 u2phy0_host: host-port {
1514 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1515 interrupt-names = "linestate";
1516 status = "disabled";
1520 u2phy1: usb2-phy@e460 {
1521 compatible = "rockchip,rk3399-usb2phy";
1522 reg = <0xe460 0x10>;
1523 clocks = <&cru SCLK_USB2PHY1_REF>;
1524 clock-names = "phyclk";
1526 clock-output-names = "clk_usbphy1_480m";
1527 status = "disabled";
1529 u2phy1_otg: otg-port {
1531 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1532 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1533 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1534 interrupt-names = "otg-bvalid", "otg-id",
1536 status = "disabled";
1539 u2phy1_host: host-port {
1541 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1542 interrupt-names = "linestate";
1543 status = "disabled";
1548 compatible = "rockchip,rk3399-pvtm";
1549 clocks = <&cru SCLK_PVTM_CORE_L>,
1550 <&cru SCLK_PVTM_CORE_B>,
1551 <&cru SCLK_PVTM_GPU>,
1552 <&cru SCLK_PVTM_DDR>;
1553 clock-names = "core_l", "core_b", "gpu", "ddr";
1554 status = "disabled";
1558 tcphy0: phy@ff7c0000 {
1559 compatible = "rockchip,rk3399-typec-phy";
1560 reg = <0x0 0xff7c0000 0x0 0x40000>;
1561 rockchip,grf = <&grf>;
1563 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1564 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1565 clock-names = "tcpdcore", "tcpdphy-ref";
1566 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1567 assigned-clock-rates = <50000000>;
1568 power-domains = <&power RK3399_PD_TCPD0>;
1569 resets = <&cru SRST_UPHY0>,
1570 <&cru SRST_UPHY0_PIPE_L00>,
1571 <&cru SRST_P_UPHY0_TCPHY>;
1572 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1573 rockchip,typec-conn-dir = <0xe580 0 16>;
1574 rockchip,usb3tousb2-en = <0xe580 3 19>;
1575 rockchip,usb3-host-disable = <0x2434 0 16>;
1576 rockchip,usb3-host-port = <0x2434 12 28>;
1577 rockchip,external-psm = <0xe588 14 30>;
1578 rockchip,pipe-status = <0xe5c0 0 0>;
1579 rockchip,uphy-dp-sel = <0x6268 19 19>;
1580 status = "disabled";
1582 tcphy0_dp: dp-port {
1586 tcphy0_usb3: usb3-port {
1591 tcphy1: phy@ff800000 {
1592 compatible = "rockchip,rk3399-typec-phy";
1593 reg = <0x0 0xff800000 0x0 0x40000>;
1594 rockchip,grf = <&grf>;
1596 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1597 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1598 clock-names = "tcpdcore", "tcpdphy-ref";
1599 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1600 assigned-clock-rates = <50000000>;
1601 power-domains = <&power RK3399_PD_TCPD1>;
1602 resets = <&cru SRST_UPHY1>,
1603 <&cru SRST_UPHY1_PIPE_L00>,
1604 <&cru SRST_P_UPHY1_TCPHY>;
1605 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1606 rockchip,typec-conn-dir = <0xe58c 0 16>;
1607 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1608 rockchip,usb3-host-disable = <0x2444 0 16>;
1609 rockchip,usb3-host-port = <0x2444 12 28>;
1610 rockchip,external-psm = <0xe594 14 30>;
1611 rockchip,pipe-status = <0xe5c0 16 16>;
1612 rockchip,uphy-dp-sel = <0x6268 3 19>;
1613 status = "disabled";
1615 tcphy1_dp: dp-port {
1619 tcphy1_usb3: usb3-port {
1625 compatible = "snps,dw-wdt";
1626 reg = <0x0 0xff848000 0x0 0x100>;
1627 clocks = <&cru PCLK_WDT>;
1628 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1631 rktimer: rktimer@ff850000 {
1632 compatible = "rockchip,rk3399-timer";
1633 reg = <0x0 0xff850000 0x0 0x1000>;
1634 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1635 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1636 clock-names = "pclk", "timer";
1639 spdif: spdif@ff870000 {
1640 compatible = "rockchip,rk3399-spdif";
1641 reg = <0x0 0xff870000 0x0 0x1000>;
1642 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1643 dmas = <&dmac_bus 7>;
1645 clock-names = "mclk", "hclk";
1646 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1647 pinctrl-names = "default";
1648 pinctrl-0 = <&spdif_bus>;
1649 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1650 status = "disabled";
1653 i2s0: i2s@ff880000 {
1654 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1655 reg = <0x0 0xff880000 0x0 0x1000>;
1656 rockchip,grf = <&grf>;
1657 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1658 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1659 dma-names = "tx", "rx";
1660 clock-names = "i2s_clk", "i2s_hclk";
1661 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1662 pinctrl-names = "default";
1663 pinctrl-0 = <&i2s0_8ch_bus>;
1664 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1665 status = "disabled";
1668 i2s1: i2s@ff890000 {
1669 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1670 reg = <0x0 0xff890000 0x0 0x1000>;
1671 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1672 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1673 dma-names = "tx", "rx";
1674 clock-names = "i2s_clk", "i2s_hclk";
1675 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1676 pinctrl-names = "default";
1677 pinctrl-0 = <&i2s1_2ch_bus>;
1678 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1679 status = "disabled";
1682 i2s2: i2s@ff8a0000 {
1683 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1684 reg = <0x0 0xff8a0000 0x0 0x1000>;
1685 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1686 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1687 dma-names = "tx", "rx";
1688 clock-names = "i2s_clk", "i2s_hclk";
1689 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1690 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1691 status = "disabled";
1695 compatible = "arm,malit860",
1700 reg = <0x0 0xff9a0000 0x0 0x10000>;
1702 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1703 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1704 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1705 interrupt-names = "GPU", "JOB", "MMU";
1707 clocks = <&cru ACLK_GPU>;
1708 clock-names = "clk_mali";
1709 #cooling-cells = <2>; /* min followed by max */
1710 power-domains = <&power RK3399_PD_GPU>;
1711 power-off-delay-ms = <200>;
1712 status = "disabled";
1714 gpu_power_model: power_model {
1715 compatible = "arm,mali-simple-power-model";
1718 static-power = <300>;
1719 dynamic-power = <396>;
1720 ts = <32000 4700 (-80) 2>;
1721 thermal-zone = "gpu-thermal";
1725 vopl: vop@ff8f0000 {
1726 compatible = "rockchip,rk3399-vop-lit";
1727 reg = <0x0 0xff8f0000 0x0 0x600>,
1728 <0x0 0xff8f1c00 0x0 0x200>,
1729 <0x0 0xff8f2000 0x0 0x400>;
1730 reg-names = "regs", "cabc_lut", "gamma_lut";
1731 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1732 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>, <&cru DCLK_VOP1_DIV>;
1733 clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
1734 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1735 reset-names = "axi", "ahb", "dclk";
1736 power-domains = <&power RK3399_PD_VOPL>;
1737 iommus = <&vopl_mmu>;
1738 status = "disabled";
1741 #address-cells = <1>;
1744 vopl_out_dsi: endpoint@0 {
1746 remote-endpoint = <&dsi_in_vopl>;
1749 vopl_out_edp: endpoint@1 {
1751 remote-endpoint = <&edp_in_vopl>;
1754 vopl_out_hdmi: endpoint@2 {
1756 remote-endpoint = <&hdmi_in_vopl>;
1759 vopl_out_dp: endpoint@3 {
1761 remote-endpoint = <&dp_in_vopl>;
1764 vopl_out_dsi1: endpoint@4 {
1766 remote-endpoint = <&dsi1_in_vopl>;
1771 vop1_pwm: voppwm@ff8f01a0 {
1772 compatible = "rockchip,vop-pwm";
1773 reg = <0x0 0xff8f01a0 0x0 0x10>;
1775 pinctrl-names = "default";
1776 pinctrl-0 = <&vop1_pwm_pin>;
1777 clocks = <&cru SCLK_VOP1_PWM>;
1778 clock-names = "pwm";
1779 status = "disabled";
1782 vopl_mmu: iommu@ff8f3f00 {
1783 compatible = "rockchip,iommu";
1784 reg = <0x0 0xff8f3f00 0x0 0x100>;
1785 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1786 interrupt-names = "vopl_mmu";
1787 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1788 clock-names = "aclk", "hclk";
1789 power-domains = <&power RK3399_PD_VOPL>;
1791 status = "disabled";
1794 vopb: vop@ff900000 {
1795 compatible = "rockchip,rk3399-vop-big";
1796 reg = <0x0 0xff900000 0x0 0x600>,
1797 <0x0 0xff901c00 0x0 0x200>,
1798 <0x0 0xff902000 0x0 0x1000>;
1799 reg-names = "regs", "cabc_lut", "gamma_lut";
1800 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1801 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>, <&cru DCLK_VOP0_DIV>;
1802 clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
1803 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1804 reset-names = "axi", "ahb", "dclk";
1805 power-domains = <&power RK3399_PD_VOPB>;
1806 iommus = <&vopb_mmu>;
1807 status = "disabled";
1810 #address-cells = <1>;
1813 vopb_out_edp: endpoint@0 {
1815 remote-endpoint = <&edp_in_vopb>;
1818 vopb_out_dsi: endpoint@1 {
1820 remote-endpoint = <&dsi_in_vopb>;
1823 vopb_out_hdmi: endpoint@2 {
1825 remote-endpoint = <&hdmi_in_vopb>;
1828 vopb_out_dp: endpoint@3 {
1830 remote-endpoint = <&dp_in_vopb>;
1833 vopb_out_dsi1: endpoint@4 {
1835 remote-endpoint = <&dsi1_in_vopb>;
1840 vop0_pwm: voppwm@ff9001a0 {
1841 compatible = "rockchip,vop-pwm";
1842 reg = <0x0 0xff9001a0 0x0 0x10>;
1844 pinctrl-names = "default";
1845 pinctrl-0 = <&vop0_pwm_pin>;
1846 clocks = <&cru SCLK_VOP0_PWM>;
1847 clock-names = "pwm";
1848 status = "disabled";
1851 vopb_mmu: iommu@ff903f00 {
1852 compatible = "rockchip,iommu";
1853 reg = <0x0 0xff903f00 0x0 0x100>;
1854 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1855 interrupt-names = "vopb_mmu";
1856 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1857 clock-names = "aclk", "hclk";
1858 power-domains = <&power RK3399_PD_VOPB>;
1860 status = "disabled";
1863 isp0_mmu: iommu@ff914000 {
1864 compatible = "rockchip,iommu";
1865 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1866 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1867 interrupt-names = "isp0_mmu";
1869 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1870 clock-names = "aclk", "hclk";
1871 power-domains = <&power RK3399_PD_ISP0>;
1872 rk_iommu,disable_reset_quirk;
1873 status = "disabled";
1876 isp1_mmu: iommu@ff924000 {
1877 compatible = "rockchip,iommu";
1878 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1879 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1880 interrupt-names = "isp1_mmu";
1882 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1883 clock-names = "aclk", "hclk";
1884 power-domains = <&power RK3399_PD_ISP1>;
1885 rk_iommu,disable_reset_quirk;
1886 status = "disabled";
1889 hdmi: hdmi@ff940000 {
1890 compatible = "rockchip,rk3399-dw-hdmi";
1891 reg = <0x0 0xff940000 0x0 0x20000>;
1893 rockchip,grf = <&grf>;
1894 pinctrl-names = "default";
1895 pinctrl-0 = <&hdmi_i2c_xfer>;
1896 power-domains = <&power RK3399_PD_HDCP>;
1897 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1898 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1899 clock-names = "iahb", "isfr", "vpll", "grf";
1900 status = "disabled";
1904 #address-cells = <1>;
1906 hdmi_in_vopb: endpoint@0 {
1908 remote-endpoint = <&vopb_out_hdmi>;
1910 hdmi_in_vopl: endpoint@1 {
1912 remote-endpoint = <&vopl_out_hdmi>;
1919 compatible = "rockchip,rk3399-mipi-dsi";
1920 reg = <0x0 0xff960000 0x0 0x8000>;
1921 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1922 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1923 <&cru SCLK_DPHY_TX0_CFG>;
1924 clock-names = "ref", "pclk", "phy_cfg";
1925 resets = <&cru SRST_P_MIPI_DSI0>;
1926 reset-names = "apb";
1927 power-domains = <&power RK3399_PD_VIO>;
1928 rockchip,grf = <&grf>;
1929 #address-cells = <1>;
1931 status = "disabled";
1935 #address-cells = <1>;
1938 dsi_in_vopb: endpoint@0 {
1940 remote-endpoint = <&vopb_out_dsi>;
1943 dsi_in_vopl: endpoint@1 {
1945 remote-endpoint = <&vopl_out_dsi>;
1951 dsi1: dsi@ff968000 {
1952 compatible = "rockchip,rk3399-mipi-dsi";
1953 reg = <0x0 0xff968000 0x0 0x8000>;
1954 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1955 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1956 <&cru SCLK_DPHY_TX1RX1_CFG>;
1957 clock-names = "ref", "pclk", "phy_cfg";
1958 resets = <&cru SRST_P_MIPI_DSI1>;
1959 reset-names = "apb";
1960 power-domains = <&power RK3399_PD_VIO>;
1961 rockchip,grf = <&grf>;
1962 #address-cells = <1>;
1964 status = "disabled";
1968 #address-cells = <1>;
1971 dsi1_in_vopb: endpoint@0 {
1973 remote-endpoint = <&vopb_out_dsi1>;
1976 dsi1_in_vopl: endpoint@1 {
1978 remote-endpoint = <&vopl_out_dsi1>;
1985 compatible = "rockchip,rk3399-edp";
1986 reg = <0x0 0xff970000 0x0 0x8000>;
1987 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1988 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1989 clock-names = "dp", "pclk";
1990 power-domains = <&power RK3399_PD_EDP>;
1991 resets = <&cru SRST_P_EDP_CTRL>;
1993 rockchip,grf = <&grf>;
1994 status = "disabled";
1995 pinctrl-names = "default";
1996 pinctrl-0 = <&edp_hpd>;
1999 #address-cells = <1>;
2004 #address-cells = <1>;
2007 edp_in_vopb: endpoint@0 {
2009 remote-endpoint = <&vopb_out_edp>;
2012 edp_in_vopl: endpoint@1 {
2014 remote-endpoint = <&vopl_out_edp>;
2020 display_subsystem: display-subsystem {
2021 compatible = "rockchip,display-subsystem";
2022 ports = <&vopl_out>, <&vopb_out>;
2023 clocks = <&cru PLL_VPLL>, <&cru PLL_CPLL>;
2024 clock-names = "hdmi-tmds-pll", "default-vop-pll";
2025 status = "disabled";
2029 compatible = "rockchip,rk3399-pinctrl";
2030 rockchip,grf = <&grf>;
2031 rockchip,pmu = <&pmugrf>;
2032 #address-cells = <0x2>;
2033 #size-cells = <0x2>;
2036 gpio0: gpio0@ff720000 {
2037 compatible = "rockchip,gpio-bank";
2038 reg = <0x0 0xff720000 0x0 0x100>;
2039 clocks = <&pmucru PCLK_GPIO0_PMU>;
2040 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
2043 #gpio-cells = <0x2>;
2045 interrupt-controller;
2046 #interrupt-cells = <0x2>;
2049 gpio1: gpio1@ff730000 {
2050 compatible = "rockchip,gpio-bank";
2051 reg = <0x0 0xff730000 0x0 0x100>;
2052 clocks = <&pmucru PCLK_GPIO1_PMU>;
2053 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
2056 #gpio-cells = <0x2>;
2058 interrupt-controller;
2059 #interrupt-cells = <0x2>;
2062 gpio2: gpio2@ff780000 {
2063 compatible = "rockchip,gpio-bank";
2064 reg = <0x0 0xff780000 0x0 0x100>;
2065 clocks = <&cru PCLK_GPIO2>;
2066 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
2069 #gpio-cells = <0x2>;
2071 interrupt-controller;
2072 #interrupt-cells = <0x2>;
2075 gpio3: gpio3@ff788000 {
2076 compatible = "rockchip,gpio-bank";
2077 reg = <0x0 0xff788000 0x0 0x100>;
2078 clocks = <&cru PCLK_GPIO3>;
2079 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
2082 #gpio-cells = <0x2>;
2084 interrupt-controller;
2085 #interrupt-cells = <0x2>;
2088 gpio4: gpio4@ff790000 {
2089 compatible = "rockchip,gpio-bank";
2090 reg = <0x0 0xff790000 0x0 0x100>;
2091 clocks = <&cru PCLK_GPIO4>;
2092 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2095 #gpio-cells = <0x2>;
2097 interrupt-controller;
2098 #interrupt-cells = <0x2>;
2101 pcfg_pull_up: pcfg-pull-up {
2105 pcfg_pull_down: pcfg-pull-down {
2109 pcfg_pull_none: pcfg-pull-none {
2113 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2115 drive-strength = <20>;
2118 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2120 drive-strength = <20>;
2123 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2125 drive-strength = <18>;
2128 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2130 drive-strength = <12>;
2133 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2135 drive-strength = <8>;
2138 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2140 drive-strength = <4>;
2143 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2145 drive-strength = <2>;
2148 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2150 drive-strength = <12>;
2153 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2155 drive-strength = <13>;
2158 pcfg_output_high: pcfg-output-high {
2162 pcfg_output_low: pcfg-output-low {
2166 pcfg_input: pcfg-input {
2171 emmc_pwr: emmc-pwr {
2173 <0 5 RK_FUNC_1 &pcfg_pull_up>;
2178 rgmii_pins: rgmii-pins {
2181 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2183 <3 14 RK_FUNC_1 &pcfg_pull_none>,
2185 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2187 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2189 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2191 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2193 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2195 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2197 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2199 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2201 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2203 <3 3 RK_FUNC_1 &pcfg_pull_none>,
2205 <3 2 RK_FUNC_1 &pcfg_pull_none>,
2207 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2209 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2212 rmii_pins: rmii-pins {
2215 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2217 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2219 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2221 <3 10 RK_FUNC_1 &pcfg_pull_none>,
2223 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2225 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2227 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2229 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2231 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2233 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2238 i2c0_xfer: i2c0-xfer {
2240 <1 15 RK_FUNC_2 &pcfg_pull_none>,
2241 <1 16 RK_FUNC_2 &pcfg_pull_none>;
2246 i2c1_xfer: i2c1-xfer {
2248 <4 2 RK_FUNC_1 &pcfg_pull_none>,
2249 <4 1 RK_FUNC_1 &pcfg_pull_none>;
2254 i2c2_xfer: i2c2-xfer {
2256 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2257 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2262 i2c3_xfer: i2c3-xfer {
2264 <4 17 RK_FUNC_1 &pcfg_pull_none>,
2265 <4 16 RK_FUNC_1 &pcfg_pull_none>;
2268 i2c3_gpio: i2c3_gpio {
2270 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2271 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2277 i2c4_xfer: i2c4-xfer {
2279 <1 12 RK_FUNC_1 &pcfg_pull_none>,
2280 <1 11 RK_FUNC_1 &pcfg_pull_none>;
2285 i2c5_xfer: i2c5-xfer {
2287 <3 11 RK_FUNC_2 &pcfg_pull_none>,
2288 <3 10 RK_FUNC_2 &pcfg_pull_none>;
2293 i2c6_xfer: i2c6-xfer {
2295 <2 10 RK_FUNC_2 &pcfg_pull_none>,
2296 <2 9 RK_FUNC_2 &pcfg_pull_none>;
2301 i2c7_xfer: i2c7-xfer {
2303 <2 8 RK_FUNC_2 &pcfg_pull_none>,
2304 <2 7 RK_FUNC_2 &pcfg_pull_none>;
2309 i2c8_xfer: i2c8-xfer {
2311 <1 21 RK_FUNC_1 &pcfg_pull_none>,
2312 <1 20 RK_FUNC_1 &pcfg_pull_none>;
2317 i2s0_8ch_bus: i2s0-8ch-bus {
2319 <3 24 RK_FUNC_1 &pcfg_pull_none>,
2320 <3 25 RK_FUNC_1 &pcfg_pull_none>,
2321 <3 26 RK_FUNC_1 &pcfg_pull_none>,
2322 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2323 <3 28 RK_FUNC_1 &pcfg_pull_none>,
2324 <3 29 RK_FUNC_1 &pcfg_pull_none>,
2325 <3 30 RK_FUNC_1 &pcfg_pull_none>,
2326 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2327 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2332 i2s1_2ch_bus: i2s1-2ch-bus {
2334 <4 3 RK_FUNC_1 &pcfg_pull_none>,
2335 <4 4 RK_FUNC_1 &pcfg_pull_none>,
2336 <4 5 RK_FUNC_1 &pcfg_pull_none>,
2337 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2338 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2343 sdio0_bus1: sdio0-bus1 {
2345 <2 20 RK_FUNC_1 &pcfg_pull_up>;
2348 sdio0_bus4: sdio0-bus4 {
2350 <2 20 RK_FUNC_1 &pcfg_pull_up>,
2351 <2 21 RK_FUNC_1 &pcfg_pull_up>,
2352 <2 22 RK_FUNC_1 &pcfg_pull_up>,
2353 <2 23 RK_FUNC_1 &pcfg_pull_up>;
2356 sdio0_cmd: sdio0-cmd {
2358 <2 24 RK_FUNC_1 &pcfg_pull_up>;
2361 sdio0_clk: sdio0-clk {
2363 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2366 sdio0_cd: sdio0-cd {
2368 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2371 sdio0_pwr: sdio0-pwr {
2373 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2376 sdio0_bkpwr: sdio0-bkpwr {
2378 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2381 sdio0_wp: sdio0-wp {
2383 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2386 sdio0_int: sdio0-int {
2388 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2393 sdmmc_bus1: sdmmc-bus1 {
2395 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2398 sdmmc_bus4: sdmmc-bus4 {
2400 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2401 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2402 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2403 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2406 sdmmc_clk: sdmmc-clk {
2408 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2411 sdmmc_cmd: sdmmc-cmd {
2413 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2416 sdmmc_cd: sdmcc-cd {
2418 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2421 sdmmc_wp: sdmmc-wp {
2423 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2428 spdif_bus: spdif-bus {
2430 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2433 spdif_bus_1: spdif-bus-1 {
2435 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2440 spi0_clk: spi0-clk {
2442 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2444 spi0_cs0: spi0-cs0 {
2446 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2448 spi0_cs1: spi0-cs1 {
2450 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2454 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2458 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2463 spi1_clk: spi1-clk {
2465 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2467 spi1_cs0: spi1-cs0 {
2469 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2473 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2477 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2482 spi2_clk: spi2-clk {
2484 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2486 spi2_cs0: spi2-cs0 {
2488 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2492 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2496 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2501 spi3_clk: spi3-clk {
2503 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2505 spi3_cs0: spi3-cs0 {
2507 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2511 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2515 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2520 spi4_clk: spi4-clk {
2522 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2524 spi4_cs0: spi4-cs0 {
2526 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2530 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2534 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2539 spi5_clk: spi5-clk {
2541 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2543 spi5_cs0: spi5-cs0 {
2545 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2549 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2553 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2558 otp_gpio: otp-gpio {
2559 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2563 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2568 uart0_xfer: uart0-xfer {
2570 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2571 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2574 uart0_cts: uart0-cts {
2576 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2579 uart0_rts: uart0-rts {
2581 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2586 uart1_xfer: uart1-xfer {
2588 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2589 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2594 uart2a_xfer: uart2a-xfer {
2596 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2597 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2602 uart2b_xfer: uart2b-xfer {
2604 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2605 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2610 uart2c_xfer: uart2c-xfer {
2612 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2613 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2618 uart3_xfer: uart3-xfer {
2620 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2621 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2624 uart3_cts: uart3-cts {
2626 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2629 uart3_rts: uart3-rts {
2631 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2636 uart4_xfer: uart4-xfer {
2638 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2639 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2644 uarthdcp_xfer: uarthdcp-xfer {
2646 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2647 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2652 pwm0_pin: pwm0-pin {
2654 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2657 vop0_pwm_pin: vop0-pwm-pin {
2659 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2664 pwm1_pin: pwm1-pin {
2666 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2669 vop1_pwm_pin: vop1-pwm-pin {
2671 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2676 pwm2_pin: pwm2-pin {
2678 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2683 pwm3a_pin: pwm3a-pin {
2685 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2690 pwm3b_pin: pwm3b-pin {
2692 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2699 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2704 hdmi_i2c_xfer: hdmi-i2c-xfer {
2706 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2707 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2710 hdmi_cec: hdmi-cec {
2712 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2717 pcie_clkreqn: pci-clkreqn {
2719 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2722 pcie_clkreqnb: pci-clkreqnb {
2724 <4 24 RK_FUNC_1 &pcfg_pull_none>;
2727 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2729 * Since our pcie doesn't support
2730 * ClockPM(CPM), we want to hack this as
2731 * gpio, so the EP could be able to
2732 * de-assert it along and make ClockPM(CPM)
2736 <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
2739 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2741 <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
2746 rockchip_suspend: rockchip-suspend {
2747 compatible = "rockchip,pm-rk3399";
2748 status = "disabled";
2749 rockchip,sleep-debug-en = <0>;
2750 rockchip,virtual-poweroff = <0>;
2751 rockchip,sleep-mode-config = <
2758 | RKPM_SLP_CENTER_PD
2759 | RKPM_SLP_AP_PWROFF
2762 rockchip,wakeup-config = <